drivers/phy/phy-rockchip-usb.c

   1 /*
   2  * Rockchip usb PHY driver
   3  *
   4  * Copyright (C) 2014 Yunzhi Li <lyz@rock-chips.com>
   5  * Copyright (C) 2014 ROCKCHIP, Inc.
   6  *
   7  * This program is free software; you can redistribute it and/or modify
   8  * it under the terms of the GNU General Public License as published by
   9  * the Free Software Foundation; either version 2 of the License.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/clk.h>
  18 #include <linux/clk-provider.h>
  19 #include <linux/io.h>
  20 #include <linux/gpio/consumer.h>
  21 #include <linux/kernel.h>
  22 #include <linux/module.h>
  23 #include <linux/mutex.h>
  24 #include <linux/of.h>
  25 #include <linux/of_address.h>
  26 #include <linux/of_platform.h>
  27 #include <linux/phy/phy.h>
  28 #include <linux/platform_device.h>
  29 #include <linux/regulator/consumer.h>
  30 #include <linux/reset.h>
  31 #include <linux/regmap.h>
  32 #include <linux/mfd/syscon.h>
  33 #include <linux/delay.h>
  34
  35 /*
  36  * The higher 16-bit of this register is used for write protection
  37  * only if BIT(13 + 16) set to 1 the BIT(13) can be written.
  38  */
  39 #define SIDDQ_WRITE_ENA BIT(29)
  40 #define SIDDQ_ON                BIT(13)
  41 #define SIDDQ_OFF               (0 << 13)
  42
  43 #define USB2_PHY_WRITE_ENA      (0xffff << 16)
  44 #define USB2_PHY_SUSPEND        (0x5 << 0 | 0xd << 4 | 0x1 << 8)
  45 #define USB2_PHY_RESUME (0)
  46
  47 #define UTMI_SEL_GRF_WR_ENA     (0x3 << 16)
  48 #define UTMI_SEL_GRF_SUSPEND    (0x1 << 0)
  49 #define UTMI_SEL_GRF_RESUME     (0x2 << 0)
  50
  51 struct rockchip_usb_phys {
  52         int reg;
  53         const char *pll_name;
  54 };
  55
  56 struct rockchip_usb_phy_pdata {
  57         struct rockchip_usb_phys *phys;
  58         unsigned int phy_pw_on;
  59         unsigned int phy_pw_off;
  60         bool siddq_ctl;
  61 };
  62
  63 struct rockchip_usb_phy_base {
  64         struct device *dev;
  65         struct regmap *reg_base;
  66         struct gpio_desc *vbus_drv_gpio;
  67         const struct rockchip_usb_phy_pdata *pdata;
  68 };
  69
  70 struct rockchip_usb_phy {
  71         struct rockchip_usb_phy_base *base;
  72         struct device_node *np;
  73         unsigned int    reg_offset;
  74         struct clk      *clk;
  75         struct clk      *clk480m;
  76         struct clk_hw   clk480m_hw;
  77         struct phy      *phy;
  78         struct reset_control *reset;
  79 };
  80
  81 static int rockchip_usb_phy_power(struct rockchip_usb_phy *phy,
  82                                            bool off)
  83 {
  84         unsigned int val;
  85
  86         val = !off ? phy->base->pdata->phy_pw_on : phy->base->pdata->phy_pw_off;
  87         return regmap_write(phy->base->reg_base, phy->reg_offset, val);
  88 }
  89
  90 static unsigned long rockchip_usb_phy480m_recalc_rate(struct clk_hw *hw,
  91                                                 unsigned long parent_rate)
  92 {
  93         return 480000000;
  94 }
  95
  96 static void rockchip_usb_phy480m_disable(struct clk_hw *hw)
  97 {
  98         struct rockchip_usb_phy *phy = container_of(hw,
  99                                                     struct rockchip_usb_phy,
 100                                                     clk480m_hw);
 101
 102         /* Power down usb phy analog blocks by set siddq 1 */
 103         if (phy->base->pdata->siddq_ctl)
 104                 rockchip_usb_phy_power(phy, 1);
 105 }
 106
 107 static int rockchip_usb_phy480m_enable(struct clk_hw *hw)
 108 {
 109         int ret = 0;
 110         struct rockchip_usb_phy *phy = container_of(hw,
 111                                                     struct rockchip_usb_phy,
 112                                                     clk480m_hw);
 113
 114         /* Power up usb phy analog blocks by set siddq 0 */
 115         if (phy->base->pdata->siddq_ctl)
 116                 ret = rockchip_usb_phy_power(phy, 0);
 117
 118         return ret;
 119 }
 120
 121 static int rockchip_usb_phy480m_is_enabled(struct clk_hw *hw)
 122 {
 123         struct rockchip_usb_phy *phy = container_of(hw,
 124                                                     struct rockchip_usb_phy,
 125                                                     clk480m_hw);
 126         int ret = 1;
 127         u32 val;
 128
 129         if (phy->base->pdata->siddq_ctl) {
 130                 ret = regmap_read(phy->base->reg_base, phy->reg_offset, &val);
 131                 if (ret < 0)
 132                         return ret;
 133
 134                 ret = (val & SIDDQ_ON) ? 0 : 1;
 135         }
 136
 137         return ret;
 138 }
 139
 140 static const struct clk_ops rockchip_usb_phy480m_ops = {
 141         .enable = rockchip_usb_phy480m_enable,
 142         .disable = rockchip_usb_phy480m_disable,
 143         .is_enabled = rockchip_usb_phy480m_is_enabled,
 144         .recalc_rate = rockchip_usb_phy480m_recalc_rate,
 145 };
 146
 147 static int rockchip_usb_phy_power_off(struct phy *_phy)
 148 {
 149         int ret = 0;
 150         struct rockchip_usb_phy *phy = phy_get_drvdata(_phy);
 151
 152         if (!phy->base->pdata->siddq_ctl) {
 153                 ret = rockchip_usb_phy_power(phy, 1);
 154                 if (ret)
 155                         return ret;
 156         }
 157
 158         clk_disable_unprepare(phy->clk480m);
 159         return 0;
 160 }
 161
 162 static int rockchip_usb_phy_power_on(struct phy *_phy)
 163 {
 164         int ret = 0;
 165         struct rockchip_usb_phy *phy = phy_get_drvdata(_phy);
 166
 167         ret = clk_prepare_enable(phy->clk480m);
 168         if (ret)
 169                 return ret;
 170
 171         if (!phy->base->pdata->siddq_ctl)
 172                 ret = rockchip_usb_phy_power(phy, 0);
 173
 174         return ret;
 175 }
 176
 177 static int rockchip_usb_phy_reset(struct phy *_phy)
 178 {
 179         struct rockchip_usb_phy *phy = phy_get_drvdata(_phy);
 180
 181         if (phy->reset) {
 182                 reset_control_assert(phy->reset);
 183                 udelay(10);
 184                 reset_control_deassert(phy->reset);
 185         }
 186
 187         return 0;
 188 }
 189
 190 static const struct phy_ops ops = {
 191         .power_on       = rockchip_usb_phy_power_on,
 192         .power_off      = rockchip_usb_phy_power_off,
 193         .reset          = rockchip_usb_phy_reset,
 194         .owner          = THIS_MODULE,
 195 };
 196
 197 static void rockchip_usb_phy_action(void *data)
 198 {
 199         struct rockchip_usb_phy *rk_phy = data;
 200
 201         of_clk_del_provider(rk_phy->np);
 202         clk_unregister(rk_phy->clk480m);
 203
 204         if (rk_phy->clk)
 205                 clk_put(rk_phy->clk);
 206 }
 207
 208 static int rockchip_usb_phy_init(struct rockchip_usb_phy_base *base,
 209                                  struct device_node *child)
 210 {
 211         struct rockchip_usb_phy *rk_phy;
 212         unsigned int reg_offset;
 213         const char *clk_name;
 214         struct clk_init_data init;
 215         int err, i;
 216
 217         rk_phy = devm_kzalloc(base->dev, sizeof(*rk_phy), GFP_KERNEL);
 218         if (!rk_phy)
 219                 return -ENOMEM;
 220
 221         rk_phy->base = base;
 222         rk_phy->np = child;
 223
 224         if (of_property_read_u32(child, "reg", &reg_offset)) {
 225                 dev_err(base->dev, "missing reg property in node %s\n",
 226                         child->name);
 227                 return -EINVAL;
 228         }
 229
 230         rk_phy->reset = of_reset_control_get(child, "phy-reset");
 231         if (IS_ERR(rk_phy->reset))
 232                 rk_phy->reset = NULL;
 233
 234         rk_phy->reg_offset = reg_offset;
 235
 236         rk_phy->clk = of_clk_get_by_name(child, "phyclk");
 237         if (IS_ERR(rk_phy->clk))
 238                 rk_phy->clk = NULL;
 239
 240         i = 0;
 241         init.name = NULL;
 242         while (base->pdata->phys[i].reg) {
 243                 if (base->pdata->phys[i].reg == reg_offset) {
 244                         init.name = base->pdata->phys[i].pll_name;
 245                         break;
 246                 }
 247                 i++;
 248         }
 249
 250         if (!init.name) {
 251                 dev_err(base->dev, "phy data not found\n");
 252                 return -EINVAL;
 253         }
 254
 255         if (rk_phy->clk) {
 256                 clk_name = __clk_get_name(rk_phy->clk);
 257                 init.flags = 0;
 258                 init.parent_names = &clk_name;
 259                 init.num_parents = 1;
 260         } else {
 261                 init.flags = CLK_IS_ROOT;
 262                 init.parent_names = NULL;
 263                 init.num_parents = 0;
 264         }
 265
 266         init.ops = &rockchip_usb_phy480m_ops;
 267         rk_phy->clk480m_hw.init = &init;
 268
 269         rk_phy->clk480m = clk_register(base->dev, &rk_phy->clk480m_hw);
 270         if (IS_ERR(rk_phy->clk480m)) {
 271                 err = PTR_ERR(rk_phy->clk480m);
 272                 goto err_clk;
 273         }
 274
 275         err = of_clk_add_provider(child, of_clk_src_simple_get,
 276                                   rk_phy->clk480m);
 277         if (err < 0)
 278                 goto err_clk_prov;
 279
 280         err = devm_add_action(base->dev, rockchip_usb_phy_action, rk_phy);
 281         if (err)
 282                 goto err_devm_action;
 283
 284         rk_phy->phy = devm_phy_create(base->dev, child, &ops);
 285         if (IS_ERR(rk_phy->phy)) {
 286                 dev_err(base->dev, "failed to create PHY\n");
 287                 return PTR_ERR(rk_phy->phy);
 288         }
 289         phy_set_drvdata(rk_phy->phy, rk_phy);
 290
 291         /* only power up usb phy when it use, so disable it when init*/
 292         return rockchip_usb_phy_power(rk_phy, 1);
 293
 294 err_devm_action:
 295         of_clk_del_provider(child);
 296 err_clk_prov:
 297         clk_unregister(rk_phy->clk480m);
 298 err_clk:
 299         if (rk_phy->clk)
 300                 clk_put(rk_phy->clk);
 301         return err;
 302 }
 303
 304 static const struct rockchip_usb_phy_pdata rk3066a_pdata = {
 305         .phys = (struct rockchip_usb_phys[]){
 306                 { .reg = 0x17c, .pll_name = "sclk_otgphy0_480m" },
 307                 { .reg = 0x188, .pll_name = "sclk_otgphy1_480m" },
 308                 { /* sentinel */ }
 309         },
 310         .phy_pw_on  = SIDDQ_WRITE_ENA | SIDDQ_OFF,
 311         .phy_pw_off = SIDDQ_WRITE_ENA | SIDDQ_ON,
 312         .siddq_ctl  = true,
 313 };
 314
 315 static const struct rockchip_usb_phy_pdata rk3188_pdata = {
 316         .phys = (struct rockchip_usb_phys[]){
 317                 { .reg = 0x10c, .pll_name = "sclk_otgphy0_480m" },
 318                 { .reg = 0x11c, .pll_name = "sclk_otgphy1_480m" },
 319                 { /* sentinel */ }
 320         },
 321         .phy_pw_on  = SIDDQ_WRITE_ENA | SIDDQ_OFF,
 322         .phy_pw_off = SIDDQ_WRITE_ENA | SIDDQ_ON,
 323         .siddq_ctl  = true,
 324 };
 325
 326 static const struct rockchip_usb_phy_pdata rk3288_pdata = {
 327         .phys = (struct rockchip_usb_phys[]){
 328                 { .reg = 0x320, .pll_name = "sclk_otgphy0_480m" },
 329                 { .reg = 0x334, .pll_name = "sclk_otgphy1_480m" },
 330                 { .reg = 0x348, .pll_name = "sclk_otgphy2_480m" },
 331                 { /* sentinel */ }
 332         },
 333         .phy_pw_on  = SIDDQ_WRITE_ENA | SIDDQ_OFF,
 334         .phy_pw_off = SIDDQ_WRITE_ENA | SIDDQ_ON,
 335         .siddq_ctl  = true,
 336 };
 337
 338 static const struct rockchip_usb_phy_pdata rk336x_pdata = {
 339         .phys = (struct rockchip_usb_phys[]){
 340                 { .reg = 0x700, .pll_name = "sclk_otgphy0_480m" },
 341                 { .reg = 0x728, .pll_name = "sclk_otgphy1_480m" },
 342                 { /* sentinel */ }
 343         },
 344         .phy_pw_on  = USB2_PHY_WRITE_ENA | USB2_PHY_RESUME,
 345         .phy_pw_off = USB2_PHY_WRITE_ENA | USB2_PHY_SUSPEND,
 346         .siddq_ctl  = false,
 347 };
 348
 349 static const struct rockchip_usb_phy_pdata rk3399_pdata = {
 350         .phys = (struct rockchip_usb_phys[]){
 351                 { .reg = 0xe458, .pll_name = "sclk_otgphy0_480m" },
 352                 { .reg = 0xe468, .pll_name = "sclk_otgphy1_480m" },
 353                 { /* sentinel */ }
 354         },
 355         .phy_pw_on  = UTMI_SEL_GRF_WR_ENA | UTMI_SEL_GRF_RESUME,
 356         .phy_pw_off = UTMI_SEL_GRF_WR_ENA | UTMI_SEL_GRF_SUSPEND,
 357         .siddq_ctl  = false,
 358 };
 359
 360 static int rockchip_usb_phy_probe(struct platform_device *pdev)
 361 {
 362         struct device *dev = &pdev->dev;
 363         struct rockchip_usb_phy_base *phy_base;
 364         struct phy_provider *phy_provider;
 365         const struct of_device_id *match;
 366         struct device_node *child;
 367         int err;
 368
 369         phy_base = devm_kzalloc(dev, sizeof(*phy_base), GFP_KERNEL);
 370         if (!phy_base)
 371                 return -ENOMEM;
 372
 373         match = of_match_device(dev->driver->of_match_table, dev);
 374         if (!match || !match->data) {
 375                 dev_err(dev, "missing phy data\n");
 376                 return -EINVAL;
 377         }
 378
 379         phy_base->pdata = match->data;
 380
 381         phy_base->dev = dev;
 382         phy_base->reg_base = ERR_PTR(-ENODEV);
 383         if (dev->parent && dev->parent->of_node)
 384                 phy_base->reg_base = syscon_node_to_regmap(
 385                                                 dev->parent->of_node);
 386         if (IS_ERR(phy_base->reg_base))
 387                 phy_base->reg_base = syscon_regmap_lookup_by_phandle(
 388                                                 dev->of_node, "rockchip,grf");
 389         if (IS_ERR(phy_base->reg_base)) {
 390                 dev_err(&pdev->dev, "Missing rockchip,grf property\n");
 391                 return PTR_ERR(phy_base->reg_base);
 392         }
 393
 394         /* Request the vbus_drv GPIO asserted */
 395         phy_base->vbus_drv_gpio =
 396                 devm_gpiod_get_optional(dev, "vbus_drv", GPIOD_OUT_HIGH);
 397         if (!phy_base->vbus_drv_gpio)
 398                 dev_info(&pdev->dev, "vbus_drv is not assigned!\n");
 399         else if (IS_ERR(phy_base->vbus_drv_gpio))
 400                 return PTR_ERR(phy_base->vbus_drv_gpio);
 401
 402         for_each_available_child_of_node(dev->of_node, child) {
 403                 err = rockchip_usb_phy_init(phy_base, child);
 404                 if (err) {
 405                         of_node_put(child);
 406                         return err;
 407                 }
 408         }
 409
 410         phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
 411         return PTR_ERR_OR_ZERO(phy_provider);
 412 }
 413
 414 static const struct of_device_id rockchip_usb_phy_dt_ids[] = {
 415         { .compatible = "rockchip,rk3066a-usb-phy", .data = &rk3066a_pdata },
 416         { .compatible = "rockchip,rk3188-usb-phy", .data = &rk3188_pdata },
 417         { .compatible = "rockchip,rk3288-usb-phy", .data = &rk3288_pdata },
 418         {}
 419 };
 420
 421 MODULE_DEVICE_TABLE(of, rockchip_usb_phy_dt_ids);
 422
 423 static struct platform_driver rockchip_usb_driver = {
 424         .probe          = rockchip_usb_phy_probe,
 425         .driver         = {
 426                 .name   = "rockchip-usb-phy",
 427                 .of_match_table = rockchip_usb_phy_dt_ids,
 428         },
 429 };
 430
 431 module_platform_driver(rockchip_usb_driver);
 432
 433 MODULE_AUTHOR("Yunzhi Li <lyz@rock-chips.com>");
 434 MODULE_DESCRIPTION("Rockchip USB 2.0 PHY driver");
 435 MODULE_LICENSE("GPL v2");