2 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
3 * Author: Chris Zhong <zyw@rock-chips.com>
4 * Kever Yang <kever.yang@rock-chips.com>
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
16 #include <linux/clk.h>
17 #include <linux/clk-provider.h>
18 #include <linux/delay.h>
19 #include <linux/extcon.h>
21 #include <linux/iopoll.h>
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/mutex.h>
26 #include <linux/of_address.h>
27 #include <linux/of_platform.h>
28 #include <linux/platform_device.h>
29 #include <linux/regmap.h>
30 #include <linux/reset.h>
32 #include <linux/mfd/syscon.h>
33 #include <linux/phy/phy.h>
35 #define CMN_SSM_BANDGAP (0x21 << 2)
36 #define CMN_SSM_BIAS (0x22 << 2)
37 #define CMN_PLLSM0_PLLEN (0x29 << 2)
38 #define CMN_PLLSM0_PLLPRE (0x2a << 2)
39 #define CMN_PLLSM0_PLLVREF (0x2b << 2)
40 #define CMN_PLLSM0_PLLLOCK (0x2c << 2)
41 #define CMN_PLLSM1_PLLEN (0x31 << 2)
42 #define CMN_PLLSM1_PLLPRE (0x32 << 2)
43 #define CMN_PLLSM1_PLLVREF (0x33 << 2)
44 #define CMN_PLLSM1_PLLLOCK (0x34 << 2)
45 #define CMN_PLLSM1_USER_DEF_CTRL (0x37 << 2)
46 #define CMN_ICAL_OVRD (0xc1 << 2)
47 #define CMN_PLL0_VCOCAL_OVRD (0x83 << 2)
48 #define CMN_PLL0_VCOCAL_INIT (0x84 << 2)
49 #define CMN_PLL0_VCOCAL_ITER (0x85 << 2)
50 #define CMN_PLL0_LOCK_REFCNT_START (0x90 << 2)
51 #define CMN_PLL0_LOCK_PLLCNT_START (0x92 << 2)
52 #define CMN_PLL0_LOCK_PLLCNT_THR (0x93 << 2)
53 #define CMN_PLL0_INTDIV (0x94 << 2)
54 #define CMN_PLL0_FRACDIV (0x95 << 2)
55 #define CMN_PLL0_HIGH_THR (0x96 << 2)
56 #define CMN_PLL0_DSM_DIAG (0x97 << 2)
57 #define CMN_PLL0_SS_CTRL1 (0x98 << 2)
58 #define CMN_PLL0_SS_CTRL2 (0x99 << 2)
59 #define CMN_PLL1_VCOCAL_START (0xa1 << 2)
60 #define CMN_PLL1_VCOCAL_OVRD (0xa3 << 2)
61 #define CMN_PLL1_VCOCAL_INIT (0xa4 << 2)
62 #define CMN_PLL1_VCOCAL_ITER (0xa5 << 2)
63 #define CMN_PLL1_LOCK_REFCNT_START (0xb0 << 2)
64 #define CMN_PLL1_LOCK_PLLCNT_START (0xb2 << 2)
65 #define CMN_PLL1_LOCK_PLLCNT_THR (0xb3 << 2)
66 #define CMN_PLL1_INTDIV (0xb4 << 2)
67 #define CMN_PLL1_FRACDIV (0xb5 << 2)
68 #define CMN_PLL1_HIGH_THR (0xb6 << 2)
69 #define CMN_PLL1_DSM_DIAG (0xb7 << 2)
70 #define CMN_PLL1_SS_CTRL1 (0xb8 << 2)
71 #define CMN_PLL1_SS_CTRL2 (0xb9 << 2)
72 #define CMN_RXCAL_OVRD (0xd1 << 2)
73 #define CMN_TXPUCAL_CTRL (0xe0 << 2)
74 #define CMN_TXPUCAL_OVRD (0xe1 << 2)
75 #define CMN_TXPDCAL_OVRD (0xf1 << 2)
76 #define CMN_DIAG_PLL0_FBH_OVRD (0x1c0 << 2)
77 #define CMN_DIAG_PLL0_FBL_OVRD (0x1c1 << 2)
78 #define CMN_DIAG_PLL0_OVRD (0x1c2 << 2)
79 #define CMN_DIAG_PLL0_V2I_TUNE (0x1c5 << 2)
80 #define CMN_DIAG_PLL0_CP_TUNE (0x1c6 << 2)
81 #define CMN_DIAG_PLL0_LF_PROG (0x1c7 << 2)
82 #define CMN_DIAG_PLL1_FBH_OVRD (0x1d0 << 2)
83 #define CMN_DIAG_PLL1_FBL_OVRD (0x1d1 << 2)
84 #define CMN_DIAG_PLL1_OVRD (0x1d2 << 2)
85 #define CMN_DIAG_PLL1_V2I_TUNE (0x1d5 << 2)
86 #define CMN_DIAG_PLL1_CP_TUNE (0x1d6 << 2)
87 #define CMN_DIAG_PLL1_LF_PROG (0x1d7 << 2)
88 #define CMN_DIAG_PLL1_PTATIS_TUNE1 (0x1d8 << 2)
89 #define CMN_DIAG_PLL1_PTATIS_TUNE2 (0x1d9 << 2)
90 #define CMN_DIAG_PLL1_INCLK_CTRL (0x1da << 2)
91 #define CMN_DIAG_HSCLK_SEL (0x1e0 << 2)
93 #define XCVR_PSM_RCTRL(n) ((0x4001 | ((n) << 9)) << 2)
94 #define XCVR_PSM_CAL_TMR(n) ((0x4002 | ((n) << 9)) << 2)
95 #define XCVR_PSM_A0IN_TMR(n) ((0x4003 | ((n) << 9)) << 2)
96 #define TX_TXCC_CAL_SCLR_MULT(n) ((0x4047 | ((n) << 9)) << 2)
97 #define TX_TXCC_CPOST_MULT_00(n) ((0x404c | ((n) << 9)) << 2)
98 #define TX_TXCC_CPOST_MULT_01(n) ((0x404d | ((n) << 9)) << 2)
99 #define TX_TXCC_CPOST_MULT_10(n) ((0x404e | ((n) << 9)) << 2)
100 #define TX_TXCC_CPOST_MULT_11(n) ((0x404f | ((n) << 9)) << 2)
101 #define TX_TXCC_MGNFS_MULT_000(n) ((0x4050 | ((n) << 9)) << 2)
102 #define TX_TXCC_MGNFS_MULT_001(n) ((0x4051 | ((n) << 9)) << 2)
103 #define TX_TXCC_MGNFS_MULT_010(n) ((0x4052 | ((n) << 9)) << 2)
104 #define TX_TXCC_MGNFS_MULT_011(n) ((0x4053 | ((n) << 9)) << 2)
105 #define TX_TXCC_MGNFS_MULT_100(n) ((0x4054 | ((n) << 9)) << 2)
106 #define TX_TXCC_MGNFS_MULT_101(n) ((0x4055 | ((n) << 9)) << 2)
107 #define TX_TXCC_MGNFS_MULT_110(n) ((0x4056 | ((n) << 9)) << 2)
108 #define TX_TXCC_MGNFS_MULT_111(n) ((0x4057 | ((n) << 9)) << 2)
109 #define XCVR_DIAG_PLLDRC_CTRL(n) ((0x40e0 | ((n) << 9)) << 2)
110 #define XCVR_DIAG_BIDI_CTRL(n) ((0x40e8 | ((n) << 9)) << 2)
111 #define XCVR_DIAG_LANE_FCM_EN_MGN(n) ((0x40f2 | ((n) << 9)) << 2)
112 #define TX_PSC_A0(n) ((0x4100 | ((n) << 9)) << 2)
113 #define TX_PSC_A1(n) ((0x4101 | ((n) << 9)) << 2)
114 #define TX_PSC_A2(n) ((0x4102 | ((n) << 9)) << 2)
115 #define TX_PSC_A3(n) ((0x4103 | ((n) << 9)) << 2)
116 #define TX_RCVDET_CTRL(n) ((0x4120 | ((n) << 9)) << 2)
117 #define TX_RCVDET_EN_TMR(n) ((0x4122 | ((n) << 9)) << 2)
118 #define TX_RCVDET_ST_TMR(n) ((0x4123 | ((n) << 9)) << 2)
119 #define TX_DIAG_TX_DRV(n) ((0x41e1 | ((n) << 9)) << 2)
120 #define TX_DIAG_BGREF_PREDRV_DELAY (0x41e7 << 2)
121 #define TX_ANA_CTRL_REG_1 (0x5020 << 2)
122 #define TX_ANA_CTRL_REG_2 (0x5021 << 2)
123 #define TXDA_COEFF_CALC_CTRL (0x5022 << 2)
124 #define TX_DIG_CTRL_REG_2 (0x5024 << 2)
125 #define TXDA_CYA_AUXDA_CYA (0x5025 << 2)
126 #define TX_ANA_CTRL_REG_3 (0x5026 << 2)
127 #define TX_ANA_CTRL_REG_4 (0x5027 << 2)
128 #define TX_ANA_CTRL_REG_5 (0x5029 << 2)
130 #define RX_PSC_A0(n) ((0x8000 | ((n) << 9)) << 2)
131 #define RX_PSC_A1(n) ((0x8001 | ((n) << 9)) << 2)
132 #define RX_PSC_A2(n) ((0x8002 | ((n) << 9)) << 2)
133 #define RX_PSC_A3(n) ((0x8003 | ((n) << 9)) << 2)
134 #define RX_PSC_CAL(n) ((0x8006 | ((n) << 9)) << 2)
135 #define RX_PSC_RDY(n) ((0x8007 | ((n) << 9)) << 2)
136 #define RX_IQPI_ILL_CAL_OVRD (0x8023 << 2)
137 #define RX_EPI_ILL_CAL_OVRD (0x8033 << 2)
138 #define RX_SDCAL0_OVRD (0x8041 << 2)
139 #define RX_SDCAL1_OVRD (0x8049 << 2)
140 #define RX_SLC_INIT (0x806d << 2)
141 #define RX_SLC_RUN (0x806e << 2)
142 #define RX_CDRLF_CNFG2 (0x8081 << 2)
143 #define RX_SIGDET_HL_FILT_TMR(n) ((0x8090 | ((n) << 9)) << 2)
144 #define RX_SLC_IOP0_OVRD (0x8101 << 2)
145 #define RX_SLC_IOP1_OVRD (0x8105 << 2)
146 #define RX_SLC_QOP0_OVRD (0x8109 << 2)
147 #define RX_SLC_QOP1_OVRD (0x810d << 2)
148 #define RX_SLC_EOP0_OVRD (0x8111 << 2)
149 #define RX_SLC_EOP1_OVRD (0x8115 << 2)
150 #define RX_SLC_ION0_OVRD (0x8119 << 2)
151 #define RX_SLC_ION1_OVRD (0x811d << 2)
152 #define RX_SLC_QON0_OVRD (0x8121 << 2)
153 #define RX_SLC_QON1_OVRD (0x8125 << 2)
154 #define RX_SLC_EON0_OVRD (0x8129 << 2)
155 #define RX_SLC_EON1_OVRD (0x812d << 2)
156 #define RX_SLC_IEP0_OVRD (0x8131 << 2)
157 #define RX_SLC_IEP1_OVRD (0x8135 << 2)
158 #define RX_SLC_QEP0_OVRD (0x8139 << 2)
159 #define RX_SLC_QEP1_OVRD (0x813d << 2)
160 #define RX_SLC_EEP0_OVRD (0x8141 << 2)
161 #define RX_SLC_EEP1_OVRD (0x8145 << 2)
162 #define RX_SLC_IEN0_OVRD (0x8149 << 2)
163 #define RX_SLC_IEN1_OVRD (0x814d << 2)
164 #define RX_SLC_QEN0_OVRD (0x8151 << 2)
165 #define RX_SLC_QEN1_OVRD (0x8155 << 2)
166 #define RX_SLC_EEN0_OVRD (0x8159 << 2)
167 #define RX_SLC_EEN1_OVRD (0x815d << 2)
168 #define RX_REE_CTRL_DATA_MASK(n) ((0x81bb | ((n) << 9)) << 2)
169 #define RX_DIAG_SIGDET_TUNE(n) ((0x81dc | ((n) << 9)) << 2)
170 #define RX_DIAG_SC2C_DELAY (0x81e1 << 2)
172 #define PMA_LANE_CFG (0xc000 << 2)
173 #define PIPE_CMN_CTRL1 (0xc001 << 2)
174 #define PIPE_CMN_CTRL2 (0xc002 << 2)
175 #define PIPE_COM_LOCK_CFG1 (0xc003 << 2)
176 #define PIPE_COM_LOCK_CFG2 (0xc004 << 2)
177 #define PIPE_RCV_DET_INH (0xc005 << 2)
178 #define DP_MODE_CTL (0xc008 << 2)
179 #define DP_CLK_CTL (0xc009 << 2)
180 #define STS (0xc00F << 2)
181 #define PHY_ISO_CMN_CTRL (0xc010 << 2)
182 #define PHY_DP_TX_CTL (0xc408 << 2)
183 #define PMA_CMN_CTRL1 (0xc800 << 2)
184 #define PHY_PMA_ISO_CMN_CTRL (0xc810 << 2)
185 #define PHY_ISOLATION_CTRL (0xc81f << 2)
186 #define PHY_PMA_ISO_XCVR_CTRL(n) ((0xcc11 | ((n) << 6)) << 2)
187 #define PHY_PMA_ISO_LINK_MODE(n) ((0xcc12 | ((n) << 6)) << 2)
188 #define PHY_PMA_ISO_PWRST_CTRL(n) ((0xcc13 | ((n) << 6)) << 2)
189 #define PHY_PMA_ISO_TX_DATA_LO(n) ((0xcc14 | ((n) << 6)) << 2)
190 #define PHY_PMA_ISO_TX_DATA_HI(n) ((0xcc15 | ((n) << 6)) << 2)
191 #define PHY_PMA_ISO_RX_DATA_LO(n) ((0xcc16 | ((n) << 6)) << 2)
192 #define PHY_PMA_ISO_RX_DATA_HI(n) ((0xcc17 | ((n) << 6)) << 2)
193 #define TX_BIST_CTRL(n) ((0x4140 | ((n) << 9)) << 2)
194 #define TX_BIST_UDDWR(n) ((0x4141 | ((n) << 9)) << 2)
197 * Selects which PLL clock will be driven on the analog high speed
198 * clock 0: PLL 0 div 1
199 * clock 1: PLL 1 div 2
201 #define CLK_PLL_CONFIG 0X30
202 #define CLK_PLL_MASK 0x33
204 #define CMN_READY BIT(0)
206 #define DP_PLL_CLOCK_ENABLE BIT(2)
207 #define DP_PLL_ENABLE BIT(0)
208 #define DP_PLL_DATA_RATE_RBR ((2 << 12) | (4 << 8))
209 #define DP_PLL_DATA_RATE_HBR ((2 << 12) | (4 << 8))
210 #define DP_PLL_DATA_RATE_HBR2 ((1 << 12) | (2 << 8))
212 #define GRF_SOC_CON26 0x6268
213 #define UPHY_DP_SEL BIT(3)
214 #define UPHY_DP_SEL_MASK BIT(19)
215 #define DPTX_HPD_SEL (3 << 12)
216 #define DPTX_HPD_DEL (2 << 12)
217 #define DPTX_HPD_SEL_MASK (3 << 28)
219 #define DP_MODE_A0 BIT(4)
220 #define DP_MODE_A2 BIT(6)
221 #define DP_MODE_ENTER_A0 0xc101
222 #define DP_MODE_ENTER_A2 0xc104
224 #define PHY_MODE_SET_TIMEOUT 100000
226 #define PIN_ASSIGN_C_E 0x51d9
227 #define PIN_ASSIGN_D_F 0x5100
229 #define MODE_DISCONNECT 0
230 #define MODE_UFP_USB BIT(0)
231 #define MODE_DFP_USB BIT(1)
232 #define MODE_DFP_DP BIT(2)
240 struct rockchip_usb3phy_port_cfg {
241 struct usb3phy_reg typec_conn_dir;
242 struct usb3phy_reg usb3tousb2_en;
243 struct usb3phy_reg external_psm;
244 struct usb3phy_reg pipe_status;
245 struct usb3phy_reg uphy_dp_sel;
248 struct rockchip_typec_phy {
251 struct extcon_dev *extcon;
253 struct regmap *grf_regs;
254 struct clk *clk_core;
256 struct reset_control *uphy_rst;
257 struct reset_control *pipe_rst;
258 struct reset_control *tcphy_rst;
259 struct rockchip_usb3phy_port_cfg port_cfgs;
260 /* mutex to protect access to individual PHYs */
272 struct phy_reg usb_pll_cfg[] = {
273 { 0xf0, CMN_PLL0_VCOCAL_INIT },
274 { 0x18, CMN_PLL0_VCOCAL_ITER },
275 { 0xd0, CMN_PLL0_INTDIV },
276 { 0x4a4a, CMN_PLL0_FRACDIV },
277 { 0x34, CMN_PLL0_HIGH_THR },
278 { 0x1ee, CMN_PLL0_SS_CTRL1 },
279 { 0x7f03, CMN_PLL0_SS_CTRL2 },
280 { 0x20, CMN_PLL0_DSM_DIAG },
281 { 0, CMN_DIAG_PLL0_OVRD },
282 { 0, CMN_DIAG_PLL0_FBH_OVRD },
283 { 0, CMN_DIAG_PLL0_FBL_OVRD },
284 { 0x7, CMN_DIAG_PLL0_V2I_TUNE },
285 { 0x45, CMN_DIAG_PLL0_CP_TUNE },
286 { 0x8, CMN_DIAG_PLL0_LF_PROG },
289 struct phy_reg dp_pll_cfg[] = {
290 { 0xf0, CMN_PLL1_VCOCAL_INIT },
291 { 0x18, CMN_PLL1_VCOCAL_ITER },
292 { 0x30b9, CMN_PLL1_VCOCAL_START },
293 { 0x21c, CMN_PLL1_INTDIV },
294 { 0, CMN_PLL1_FRACDIV },
295 { 0x5, CMN_PLL1_HIGH_THR },
296 { 0x35, CMN_PLL1_SS_CTRL1 },
297 { 0x7f1e, CMN_PLL1_SS_CTRL2 },
298 { 0x20, CMN_PLL1_DSM_DIAG },
299 { 0, CMN_PLLSM1_USER_DEF_CTRL },
300 { 0, CMN_DIAG_PLL1_OVRD },
301 { 0, CMN_DIAG_PLL1_FBH_OVRD },
302 { 0, CMN_DIAG_PLL1_FBL_OVRD },
303 { 0x6, CMN_DIAG_PLL1_V2I_TUNE },
304 { 0x45, CMN_DIAG_PLL1_CP_TUNE },
305 { 0x8, CMN_DIAG_PLL1_LF_PROG },
306 { 0x100, CMN_DIAG_PLL1_PTATIS_TUNE1 },
307 { 0x7, CMN_DIAG_PLL1_PTATIS_TUNE2 },
308 { 0x4, CMN_DIAG_PLL1_INCLK_CTRL },
311 static void tcphy_cfg_24m(struct rockchip_typec_phy *tcphy)
316 * cmn_ref_clk_sel = 3, select the 24Mhz for clk parent
317 * cmn_psm_clk_dig_div = 2, set the clk division to 2
319 writel(0x830, tcphy->base + PMA_CMN_CTRL1);
320 for (i = 0; i < 4; i++) {
322 * The following PHY configuration assumes a 24 MHz reference
325 writel(0x90, tcphy->base + XCVR_DIAG_LANE_FCM_EN_MGN(i));
326 writel(0x960, tcphy->base + TX_RCVDET_EN_TMR(i));
327 writel(0x30, tcphy->base + TX_RCVDET_ST_TMR(i));
330 rdata = readl(tcphy->base + CMN_DIAG_HSCLK_SEL);
331 rdata &= ~CLK_PLL_MASK;
332 rdata |= CLK_PLL_CONFIG;
333 writel(rdata, tcphy->base + CMN_DIAG_HSCLK_SEL);
336 static void tcphy_cfg_usb_pll(struct rockchip_typec_phy *tcphy)
340 /* load the configuration of PLL0 */
341 for (i = 0; i < ARRAY_SIZE(usb_pll_cfg); i++)
342 writel(usb_pll_cfg[i].value, tcphy->base + usb_pll_cfg[i].addr);
345 static void tcphy_cfg_dp_pll(struct rockchip_typec_phy *tcphy)
349 /* set the default mode to RBR */
350 writel(DP_PLL_CLOCK_ENABLE | DP_PLL_ENABLE | DP_PLL_DATA_RATE_RBR,
351 tcphy->base + DP_CLK_CTL);
353 /* load the configuration of PLL1 */
354 for (i = 0; i < ARRAY_SIZE(dp_pll_cfg); i++)
355 writel(dp_pll_cfg[i].value, tcphy->base + dp_pll_cfg[i].addr);
358 static void tcphy_tx_usb_cfg_lane(struct rockchip_typec_phy *tcphy, u32 lane)
360 writel(0x7799, tcphy->base + TX_PSC_A0(lane));
361 writel(0x7798, tcphy->base + TX_PSC_A1(lane));
362 writel(0x5098, tcphy->base + TX_PSC_A2(lane));
363 writel(0x5098, tcphy->base + TX_PSC_A3(lane));
364 writel(0, tcphy->base + TX_TXCC_MGNFS_MULT_000(lane));
365 writel(0xbf, tcphy->base + XCVR_DIAG_BIDI_CTRL(lane));
368 static void tcphy_rx_usb_cfg_lane(struct rockchip_typec_phy *tcphy, u32 lane)
370 writel(0xa6fd, tcphy->base + RX_PSC_A0(lane));
371 writel(0xa6fd, tcphy->base + RX_PSC_A1(lane));
372 writel(0xa410, tcphy->base + RX_PSC_A2(lane));
373 writel(0x2410, tcphy->base + RX_PSC_A3(lane));
374 writel(0x23ff, tcphy->base + RX_PSC_CAL(lane));
375 writel(0x13, tcphy->base + RX_SIGDET_HL_FILT_TMR(lane));
376 writel(0x03e7, tcphy->base + RX_REE_CTRL_DATA_MASK(lane));
377 writel(0x1004, tcphy->base + RX_DIAG_SIGDET_TUNE(lane));
378 writel(0x2010, tcphy->base + RX_PSC_RDY(lane));
379 writel(0xfb, tcphy->base + XCVR_DIAG_BIDI_CTRL(lane));
382 static void tcphy_dp_cfg_lane(struct rockchip_typec_phy *tcphy, u32 lane)
386 writel(0xbefc, tcphy->base + XCVR_PSM_RCTRL(lane));
387 writel(0x6799, tcphy->base + TX_PSC_A0(lane));
388 writel(0x6798, tcphy->base + TX_PSC_A1(lane));
389 writel(0x98, tcphy->base + TX_PSC_A2(lane));
390 writel(0x98, tcphy->base + TX_PSC_A3(lane));
392 writel(0, tcphy->base + TX_TXCC_MGNFS_MULT_000(lane));
393 writel(0, tcphy->base + TX_TXCC_MGNFS_MULT_001(lane));
394 writel(0, tcphy->base + TX_TXCC_MGNFS_MULT_010(lane));
395 writel(0, tcphy->base + TX_TXCC_MGNFS_MULT_011(lane));
396 writel(0, tcphy->base + TX_TXCC_MGNFS_MULT_100(lane));
397 writel(0, tcphy->base + TX_TXCC_MGNFS_MULT_101(lane));
398 writel(0, tcphy->base + TX_TXCC_MGNFS_MULT_110(lane));
399 writel(0, tcphy->base + TX_TXCC_MGNFS_MULT_111(lane));
400 writel(0, tcphy->base + TX_TXCC_CPOST_MULT_10(lane));
401 writel(0, tcphy->base + TX_TXCC_CPOST_MULT_01(lane));
402 writel(0, tcphy->base + TX_TXCC_CPOST_MULT_00(lane));
403 writel(0, tcphy->base + TX_TXCC_CPOST_MULT_11(lane));
405 writel(0x128, tcphy->base + TX_TXCC_CAL_SCLR_MULT(lane));
406 writel(0x400, tcphy->base + TX_DIAG_TX_DRV(lane));
408 rdata = readl(tcphy->base + XCVR_DIAG_PLLDRC_CTRL(lane));
409 rdata = (rdata & 0x8fff) | 0x6000;
410 writel(rdata, tcphy->base + XCVR_DIAG_PLLDRC_CTRL(lane));
413 static inline int property_enable(struct rockchip_typec_phy *tcphy,
414 const struct usb3phy_reg *reg, bool en)
416 u32 mask = 1 << reg->write_enable;
417 u32 val = en << reg->enable_bit;
419 return regmap_write(tcphy->grf_regs, reg->offset, val | mask);
422 static void tcphy_dp_aux_calibration(struct rockchip_typec_phy *tcphy)
424 u16 rdata, rdata2, val;
426 /* disable txda_cal_latch_en for rewrite the calibration values */
427 rdata = readl(tcphy->base + TX_ANA_CTRL_REG_1);
428 val = rdata & 0xdfff;
429 writel(val, tcphy->base + TX_ANA_CTRL_REG_1);
432 * read a resistor calibration code from CMN_TXPUCAL_CTRL[6:0] and
433 * write it to TX_DIG_CTRL_REG_2[6:0], and delay 1ms to make sure it
436 rdata = readl(tcphy->base + TX_DIG_CTRL_REG_2);
437 rdata = rdata & 0xffc0;
439 rdata2 = readl(tcphy->base + CMN_TXPUCAL_CTRL);
440 rdata2 = rdata2 & 0x3f;
442 val = rdata | rdata2;
443 writel(val, tcphy->base + TX_DIG_CTRL_REG_2);
444 usleep_range(1000, 1050);
447 * Enable signal for latch that sample and holds calibration values.
448 * Activate this signal for 1 clock cycle to sample new calibration
451 rdata = readl(tcphy->base + TX_ANA_CTRL_REG_1);
452 val = rdata | 0x2000;
453 writel(val, tcphy->base + TX_ANA_CTRL_REG_1);
454 usleep_range(150, 200);
456 /* set TX Voltage Level and TX Deemphasis to 0 */
457 writel(0, tcphy->base + PHY_DP_TX_CTL);
458 /* re-enable decap */
459 writel(0x100, tcphy->base + TX_ANA_CTRL_REG_2);
460 writel(0x300, tcphy->base + TX_ANA_CTRL_REG_2);
461 writel(0x2008, tcphy->base + TX_ANA_CTRL_REG_1);
462 writel(0x2018, tcphy->base + TX_ANA_CTRL_REG_1);
464 writel(0, tcphy->base + TX_ANA_CTRL_REG_5);
467 * Programs txda_drv_ldo_prog[15:0], Sets driver LDO
468 * voltage 16'h1001 for DP-AUX-TX and RX
470 writel(0x1001, tcphy->base + TX_ANA_CTRL_REG_4);
472 /* re-enables Bandgap reference for LDO */
473 writel(0x2098, tcphy->base + TX_ANA_CTRL_REG_1);
474 writel(0x2198, tcphy->base + TX_ANA_CTRL_REG_1);
477 * re-enables the transmitter pre-driver, driver data selection MUX,
478 * and receiver detect circuits.
480 writel(0x301, tcphy->base + TX_ANA_CTRL_REG_2);
481 writel(0x303, tcphy->base + TX_ANA_CTRL_REG_2);
484 * BIT 12: Controls auxda_polarity, which selects the polarity of the
486 * 1, Reverses the polarity (If TYPEC, Pulls ups aux_p and pull
488 * 0, Normal polarity (if TYPE_C, pulls up aux_m and pulls down
494 writel(val, tcphy->base + TX_ANA_CTRL_REG_1);
496 writel(0, tcphy->base + TX_ANA_CTRL_REG_3);
497 writel(0, tcphy->base + TX_ANA_CTRL_REG_4);
498 writel(0, tcphy->base + TX_ANA_CTRL_REG_5);
501 * Controls low_power_swing_en, set the voltage swing of the driver
502 * to 400mv. The values below are peak to peak (differential) values.
504 writel(4, tcphy->base + TXDA_COEFF_CALC_CTRL);
505 writel(0, tcphy->base + TXDA_CYA_AUXDA_CYA);
507 /* Controls tx_high_z_tm_en */
508 val = readl(tcphy->base + TX_DIG_CTRL_REG_2);
510 writel(val, tcphy->base + TX_DIG_CTRL_REG_2);
513 static int tcphy_phy_init(struct rockchip_typec_phy *tcphy, u8 mode)
515 struct rockchip_usb3phy_port_cfg *cfg = &tcphy->port_cfgs;
519 ret = clk_prepare_enable(tcphy->clk_core);
521 dev_err(tcphy->dev, "Failed to prepare_enable core clock\n");
525 ret = clk_prepare_enable(tcphy->clk_ref);
527 dev_err(tcphy->dev, "Failed to prepare_enable ref clock\n");
531 reset_control_deassert(tcphy->tcphy_rst);
533 property_enable(tcphy, &cfg->typec_conn_dir, tcphy->flip);
535 tcphy_cfg_24m(tcphy);
537 if (mode == MODE_DFP_DP) {
538 tcphy_cfg_dp_pll(tcphy);
539 for (i = 0; i < 4; i++)
540 tcphy_dp_cfg_lane(tcphy, i);
542 writel(PIN_ASSIGN_C_E, tcphy->base + PMA_LANE_CFG);
544 tcphy_cfg_usb_pll(tcphy);
545 tcphy_cfg_dp_pll(tcphy);
547 tcphy_tx_usb_cfg_lane(tcphy, 3);
548 tcphy_rx_usb_cfg_lane(tcphy, 2);
549 tcphy_dp_cfg_lane(tcphy, 0);
550 tcphy_dp_cfg_lane(tcphy, 1);
552 tcphy_tx_usb_cfg_lane(tcphy, 0);
553 tcphy_rx_usb_cfg_lane(tcphy, 1);
554 tcphy_dp_cfg_lane(tcphy, 2);
555 tcphy_dp_cfg_lane(tcphy, 3);
558 writel(PIN_ASSIGN_D_F, tcphy->base + PMA_LANE_CFG);
561 writel(DP_MODE_ENTER_A2, tcphy->base + DP_MODE_CTL);
563 reset_control_deassert(tcphy->uphy_rst);
565 ret = readx_poll_timeout(readl, tcphy->base + PMA_CMN_CTRL1,
566 val, val & CMN_READY, 10,
567 PHY_MODE_SET_TIMEOUT);
569 dev_err(tcphy->dev, "wait pma ready timeout\n");
574 reset_control_deassert(tcphy->pipe_rst);
579 reset_control_assert(tcphy->uphy_rst);
580 reset_control_assert(tcphy->tcphy_rst);
581 clk_disable_unprepare(tcphy->clk_ref);
583 clk_disable_unprepare(tcphy->clk_core);
587 static void tcphy_phy_deinit(struct rockchip_typec_phy *tcphy)
589 reset_control_assert(tcphy->tcphy_rst);
590 reset_control_assert(tcphy->uphy_rst);
591 reset_control_assert(tcphy->pipe_rst);
592 clk_disable_unprepare(tcphy->clk_core);
593 clk_disable_unprepare(tcphy->clk_ref);
596 static int tcphy_get_mode(struct rockchip_typec_phy *tcphy)
598 struct extcon_dev *edev = tcphy->extcon;
599 union extcon_property_value property;
607 id = EXTCON_USB_HOST;
612 ufp = extcon_get_state(edev, EXTCON_USB);
613 dfp = extcon_get_state(edev, EXTCON_USB_HOST);
614 dp = extcon_get_state(edev, EXTCON_DISP_DP);
617 id = EXTCON_USB_HOST;
622 } else if (dfp && dp) {
623 mode = MODE_DFP_USB | MODE_DFP_DP;
629 ret = extcon_get_property(edev, id, EXTCON_PROP_USB_TYPEC_POLARITY,
632 dev_err(tcphy->dev, "get property failed\n");
636 tcphy->flip = property.intval ? 1 : 0;
641 static int rockchip_usb3_phy_power_on(struct phy *phy)
643 struct rockchip_typec_phy *tcphy = phy_get_drvdata(phy);
644 struct rockchip_usb3phy_port_cfg *cfg = &tcphy->port_cfgs;
645 const struct usb3phy_reg *reg = &cfg->pipe_status;
646 int timeout, new_mode, ret = 0;
649 mutex_lock(&tcphy->lock);
651 new_mode = tcphy_get_mode(tcphy);
657 if (!(new_mode & (MODE_DFP_USB | MODE_UFP_USB))) {
662 if (tcphy->mode == new_mode)
665 if (tcphy->mode == MODE_DISCONNECT)
666 tcphy_phy_init(tcphy, new_mode);
668 /* wait TCPHY for pipe ready */
669 for (timeout = 0; timeout < 100; timeout++) {
670 regmap_read(tcphy->grf_regs, reg->offset, &val);
671 if (!(val & BIT(reg->enable_bit))) {
672 tcphy->mode |= new_mode & (MODE_DFP_USB | MODE_UFP_USB);
675 usleep_range(10, 20);
678 if (tcphy->mode == MODE_DISCONNECT)
679 tcphy_phy_deinit(tcphy);
684 mutex_unlock(&tcphy->lock);
688 static int rockchip_usb3_phy_power_off(struct phy *phy)
690 struct rockchip_typec_phy *tcphy = phy_get_drvdata(phy);
692 mutex_lock(&tcphy->lock);
694 if (tcphy->mode == MODE_DISCONNECT)
697 tcphy->mode &= ~(MODE_UFP_USB | MODE_DFP_USB);
698 if (tcphy->mode == MODE_DISCONNECT)
699 tcphy_phy_deinit(tcphy);
702 mutex_unlock(&tcphy->lock);
706 static const struct phy_ops rockchip_usb3_phy_ops = {
707 .power_on = rockchip_usb3_phy_power_on,
708 .power_off = rockchip_usb3_phy_power_off,
709 .owner = THIS_MODULE,
712 static int rockchip_dp_phy_power_on(struct phy *phy)
714 struct rockchip_typec_phy *tcphy = phy_get_drvdata(phy);
715 struct rockchip_usb3phy_port_cfg *cfg = &tcphy->port_cfgs;
716 int new_mode, ret = 0;
719 mutex_lock(&tcphy->lock);
721 new_mode = tcphy_get_mode(tcphy);
727 if (!(new_mode & MODE_DFP_DP)) {
732 if (tcphy->mode == new_mode)
736 * If the PHY has been power on, but the mode is not DP only mode,
737 * re-init the PHY for setting all of 4 lanes to DP.
739 if (new_mode == MODE_DFP_DP && tcphy->mode != MODE_DISCONNECT) {
740 tcphy_phy_deinit(tcphy);
741 tcphy_phy_init(tcphy, new_mode);
742 } else if (tcphy->mode == MODE_DISCONNECT) {
743 tcphy_phy_init(tcphy, new_mode);
746 property_enable(tcphy, &cfg->uphy_dp_sel, 1);
748 ret = readx_poll_timeout(readl, tcphy->base + DP_MODE_CTL,
749 val, val & DP_MODE_A2, 1000,
750 PHY_MODE_SET_TIMEOUT);
752 dev_err(tcphy->dev, "failed to wait TCPHY enter A2\n");
753 goto power_on_finish;
756 tcphy_dp_aux_calibration(tcphy);
758 writel(DP_MODE_ENTER_A0, tcphy->base + DP_MODE_CTL);
760 ret = readx_poll_timeout(readl, tcphy->base + DP_MODE_CTL,
761 val, val & DP_MODE_A0, 1000,
762 PHY_MODE_SET_TIMEOUT);
764 writel(DP_MODE_ENTER_A2, tcphy->base + DP_MODE_CTL);
765 dev_err(tcphy->dev, "failed to wait TCPHY enter A0\n");
766 goto power_on_finish;
769 regmap_write(tcphy->grf_regs, GRF_SOC_CON26,
770 DPTX_HPD_SEL_MASK | DPTX_HPD_SEL);
772 tcphy->mode |= MODE_DFP_DP;
775 if (tcphy->mode == MODE_DISCONNECT)
776 tcphy_phy_deinit(tcphy);
778 mutex_unlock(&tcphy->lock);
782 static int rockchip_dp_phy_power_off(struct phy *phy)
784 struct rockchip_typec_phy *tcphy = phy_get_drvdata(phy);
786 mutex_lock(&tcphy->lock);
788 if (tcphy->mode == MODE_DISCONNECT)
791 tcphy->mode &= ~MODE_DFP_DP;
792 regmap_write(tcphy->grf_regs, GRF_SOC_CON26,
793 DPTX_HPD_SEL_MASK | DPTX_HPD_DEL);
795 writel(DP_MODE_ENTER_A2, tcphy->base + DP_MODE_CTL);
797 if (tcphy->mode == MODE_DISCONNECT)
798 tcphy_phy_deinit(tcphy);
801 mutex_unlock(&tcphy->lock);
805 static const struct phy_ops rockchip_dp_phy_ops = {
806 .power_on = rockchip_dp_phy_power_on,
807 .power_off = rockchip_dp_phy_power_off,
808 .owner = THIS_MODULE,
811 static int tcphy_get_param(struct device *dev,
812 struct usb3phy_reg *reg,
818 ret = of_property_read_u32_array(dev->of_node, name, buffer, 3);
820 dev_err(dev, "Can not parse %s\n", name);
824 reg->offset = buffer[0];
825 reg->enable_bit = buffer[1];
826 reg->write_enable = buffer[2];
830 static int tcphy_parse_dt(struct rockchip_typec_phy *tcphy,
833 struct rockchip_usb3phy_port_cfg *cfg = &tcphy->port_cfgs;
836 ret = tcphy_get_param(dev, &cfg->typec_conn_dir,
837 "rockchip,typec-conn-dir");
841 ret = tcphy_get_param(dev, &cfg->usb3tousb2_en,
842 "rockchip,usb3tousb2-en");
846 ret = tcphy_get_param(dev, &cfg->external_psm,
847 "rockchip,external-psm");
851 ret = tcphy_get_param(dev, &cfg->pipe_status,
852 "rockchip,pipe-status");
856 ret = tcphy_get_param(dev, &cfg->uphy_dp_sel,
857 "rockchip,uphy-dp-sel");
861 tcphy->grf_regs = syscon_regmap_lookup_by_phandle(dev->of_node,
863 if (IS_ERR(tcphy->grf_regs)) {
864 dev_err(dev, "could not find grf dt node\n");
865 return PTR_ERR(tcphy->grf_regs);
868 tcphy->clk_core = devm_clk_get(dev, "tcpdcore");
869 if (IS_ERR(tcphy->clk_core)) {
870 dev_err(dev, "could not get uphy core clock\n");
871 return PTR_ERR(tcphy->clk_core);
874 tcphy->clk_ref = devm_clk_get(dev, "tcpdphy-ref");
875 if (IS_ERR(tcphy->clk_ref)) {
876 dev_err(dev, "could not get uphy ref clock\n");
877 return PTR_ERR(tcphy->clk_ref);
880 tcphy->uphy_rst = devm_reset_control_get(dev, "uphy");
881 if (IS_ERR(tcphy->uphy_rst)) {
882 dev_err(dev, "no uphy_rst reset control found\n");
883 return PTR_ERR(tcphy->uphy_rst);
886 tcphy->pipe_rst = devm_reset_control_get(dev, "uphy-pipe");
887 if (IS_ERR(tcphy->pipe_rst)) {
888 dev_err(dev, "no pipe_rst reset control found\n");
889 return PTR_ERR(tcphy->pipe_rst);
892 tcphy->tcphy_rst = devm_reset_control_get(dev, "uphy-tcphy");
893 if (IS_ERR(tcphy->tcphy_rst)) {
894 dev_err(dev, "no tcphy_rst reset control found\n");
895 return PTR_ERR(tcphy->tcphy_rst);
901 static void typec_phy_pre_init(struct rockchip_typec_phy *tcphy)
903 struct rockchip_usb3phy_port_cfg *cfg = &tcphy->port_cfgs;
905 reset_control_assert(tcphy->tcphy_rst);
906 reset_control_assert(tcphy->uphy_rst);
907 reset_control_assert(tcphy->pipe_rst);
909 /* select external psm clock */
910 property_enable(tcphy, &cfg->external_psm, 1);
911 property_enable(tcphy, &cfg->usb3tousb2_en, 0);
913 tcphy->mode = MODE_DISCONNECT;
916 static struct phy *tcphy_phy_xlate(struct device *dev,
917 struct of_phandle_args *args)
919 struct rockchip_typec_phy *tcphy = dev_get_drvdata(dev);
922 if (WARN_ON(args->args[0] >= 2))
923 return ERR_PTR(-ENODEV);
925 for (i = 0; i < 2; i++) {
926 if (i == args->args[0])
927 return tcphy->phy[i];
930 return ERR_PTR(-ENODEV);
933 static int rockchip_typec_phy_probe(struct platform_device *pdev)
935 struct device *dev = &pdev->dev;
936 struct rockchip_typec_phy *tcphy;
937 struct phy_provider *phy_provider;
938 struct resource *res;
941 tcphy = devm_kzalloc(dev, sizeof(*tcphy), GFP_KERNEL);
945 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
946 tcphy->base = devm_ioremap_resource(dev, res);
947 if (IS_ERR(tcphy->base))
948 return PTR_ERR(tcphy->base);
950 ret = tcphy_parse_dt(tcphy, dev);
955 platform_set_drvdata(pdev, tcphy);
956 mutex_init(&tcphy->lock);
958 typec_phy_pre_init(tcphy);
960 if (device_property_read_bool(dev, "extcon")) {
961 tcphy->extcon = extcon_get_edev_by_phandle(dev, 0);
962 if (IS_ERR(tcphy->extcon)) {
963 if (PTR_ERR(tcphy->extcon) != -EPROBE_DEFER)
964 dev_err(dev, "Invalid or missing extcon\n");
965 return PTR_ERR(tcphy->extcon);
969 tcphy->phy[0] = devm_phy_create(dev, NULL, &rockchip_dp_phy_ops);
970 if (IS_ERR(tcphy->phy[0])) {
971 dev_err(dev, "failed to create DP phy\n");
972 return PTR_ERR(tcphy->phy[0]);
975 tcphy->phy[1] = devm_phy_create(dev, NULL, &rockchip_usb3_phy_ops);
976 if (IS_ERR(tcphy->phy[1])) {
977 dev_err(dev, "failed to create USB3 phy\n");
978 return PTR_ERR(tcphy->phy[1]);
981 phy_set_drvdata(tcphy->phy[0], tcphy);
982 phy_set_drvdata(tcphy->phy[1], tcphy);
984 phy_provider = devm_of_phy_provider_register(dev, tcphy_phy_xlate);
985 if (IS_ERR(phy_provider)) {
986 dev_err(dev, "Failed to register phy provider\n");
987 return PTR_ERR(phy_provider);
993 static const struct of_device_id rockchip_typec_phy_dt_ids[] = {
994 { .compatible = "rockchip,rk3399-typec-phy" },
998 MODULE_DEVICE_TABLE(of, rockchip_typec_phy_dt_ids);
1000 static struct platform_driver rockchip_typec_phy_driver = {
1001 .probe = rockchip_typec_phy_probe,
1003 .name = "rockchip-typec-phy",
1004 .of_match_table = rockchip_typec_phy_dt_ids,
1008 module_platform_driver(rockchip_typec_phy_driver);
1010 MODULE_AUTHOR("Chris Zhong <zyw@rock-chips.com>");
1011 MODULE_AUTHOR("Kever Yang <kever.yang@rock-chips.com>");
1012 MODULE_DESCRIPTION("Rockchip USB TYPE-C PHY driver");
1013 MODULE_LICENSE("GPL v2");