2 * Rockchip USB 3.0 PHY with Innosilicon IP block driver
4 * Copyright (C) 2016 Fuzhou Rockchip Electronics Co., Ltd
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/clk.h>
18 #include <linux/delay.h>
19 #include <linux/debugfs.h>
20 #include <linux/gpio/consumer.h>
21 #include <linux/interrupt.h>
23 #include <linux/kernel.h>
24 #include <linux/mfd/syscon.h>
25 #include <linux/module.h>
27 #include <linux/of_address.h>
28 #include <linux/of_irq.h>
29 #include <linux/of_platform.h>
30 #include <linux/phy/phy.h>
31 #include <linux/platform_device.h>
32 #include <linux/regmap.h>
33 #include <linux/reset.h>
34 #include <linux/usb/phy.h>
35 #include <linux/uaccess.h>
37 #define U3PHY_PORT_NUM 2
38 #define U3PHY_MAX_CLKS 4
39 #define BIT_WRITEABLE_SHIFT 16
40 #define SCHEDULE_DELAY (60 * HZ)
42 #define U3PHY_APB_RST BIT(0)
43 #define U3PHY_POR_RST BIT(1)
44 #define U3PHY_MAC_RST BIT(2)
46 struct rockchip_u3phy;
47 struct rockchip_u3phy_port;
49 enum rockchip_u3phy_type {
54 enum rockchip_u3phy_pipe_pwr {
62 enum rockchip_u3phy_rest_req {
72 enum rockchip_u3phy_utmi_state {
73 PHY_UTMI_HS_ONLINE = 0,
74 PHY_UTMI_DISCONNECT = 1,
76 PHY_UTMI_FS_LS_ONLINE = 4,
80 * @rvalue: reset value
81 * @dvalue: desired value
86 unsigned int bitstart;
91 struct rockchip_u3phy_grfcfg {
92 struct u3phy_reg um_suspend;
93 struct u3phy_reg ls_det_en;
94 struct u3phy_reg ls_det_st;
95 struct u3phy_reg um_ls;
96 struct u3phy_reg um_hstdct;
97 struct u3phy_reg u2_only_ctrl;
98 struct u3phy_reg u3_disable;
99 struct u3phy_reg pp_pwr_st;
100 struct u3phy_reg pp_pwr_en[PIPE_PWR_MAX];
104 * struct rockchip_u3phy_apbcfg: usb3-phy apb configuration.
105 * @u2_pre_emp: usb2-phy pre-emphasis tuning.
106 * @u2_pre_emp_sth: usb2-phy pre-emphasis strength tuning.
107 * @u2_odt_tuning: usb2-phy odt 45ohm tuning.
109 struct rockchip_u3phy_apbcfg {
110 unsigned int u2_pre_emp;
111 unsigned int u2_pre_emp_sth;
112 unsigned int u2_odt_tuning;
115 struct rockchip_u3phy_cfg {
117 const struct rockchip_u3phy_grfcfg grfcfg;
119 int (*phy_pipe_power)(struct rockchip_u3phy *,
120 struct rockchip_u3phy_port *,
122 int (*phy_tuning)(struct rockchip_u3phy *,
123 struct rockchip_u3phy_port *,
124 struct device_node *);
125 int (*phy_cp_test)(struct rockchip_u3phy *,
126 struct rockchip_u3phy_port *);
129 struct rockchip_u3phy_port {
135 bool refclk_25m_quirk;
136 struct mutex mutex; /* mutex for updating register */
137 struct delayed_work um_sm_work;
140 struct rockchip_u3phy {
142 struct regmap *u3phy_grf;
145 struct clk *clks[U3PHY_MAX_CLKS];
147 struct gpio_desc *vbus_drv_gpio;
148 struct reset_control *rsts[U3PHY_RESET_MAX];
149 struct rockchip_u3phy_apbcfg apbcfg;
150 const struct rockchip_u3phy_cfg *cfgs;
151 struct rockchip_u3phy_port ports[U3PHY_PORT_NUM];
152 struct usb_phy usb_phy;
155 static inline int param_write(void __iomem *base,
156 const struct u3phy_reg *reg, bool desired)
158 unsigned int val, mask;
159 unsigned int tmp = desired ? reg->dvalue : reg->rvalue;
162 mask = GENMASK(reg->bitend, reg->bitstart);
163 val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT);
164 ret = regmap_write(base, reg->offset, val);
169 static inline bool param_exped(void __iomem *base,
170 const struct u3phy_reg *reg,
174 unsigned int tmp, orig;
175 unsigned int mask = GENMASK(reg->bitend, reg->bitstart);
177 ret = regmap_read(base, reg->offset, &orig);
181 tmp = (orig & mask) >> reg->bitstart;
185 static int rockchip_u3phy_usb2_only_show(struct seq_file *s, void *unused)
187 struct rockchip_u3phy *u3phy = s->private;
189 if (param_exped(u3phy->u3phy_grf, &u3phy->cfgs->grfcfg.u2_only_ctrl, 1))
190 dev_info(u3phy->dev, "u2\n");
192 dev_info(u3phy->dev, "u3\n");
197 static int rockchip_u3phy_usb2_only_open(struct inode *inode,
200 return single_open(file, rockchip_u3phy_usb2_only_show,
204 static ssize_t rockchip_u3phy_usb2_only_write(struct file *file,
205 const char __user *ubuf,
206 size_t count, loff_t *ppos)
208 struct seq_file *s = file->private_data;
209 struct rockchip_u3phy *u3phy = s->private;
210 struct rockchip_u3phy_port *u3phy_port;
214 if (copy_from_user(&buf, ubuf, min_t(size_t, sizeof(buf) - 1, count)))
217 if (!strncmp(buf, "u3", 2) &&
218 param_exped(u3phy->u3phy_grf,
219 &u3phy->cfgs->grfcfg.u2_only_ctrl, 1)) {
220 dev_info(u3phy->dev, "Set usb3.0 and usb2.0 mode successfully\n");
222 gpiod_set_value_cansleep(u3phy->vbus_drv_gpio, 0);
224 param_write(u3phy->grf,
225 &u3phy->cfgs->grfcfg.u3_disable, false);
226 param_write(u3phy->u3phy_grf,
227 &u3phy->cfgs->grfcfg.u2_only_ctrl, false);
229 for (index = 0; index < U3PHY_PORT_NUM; index++) {
230 u3phy_port = &u3phy->ports[index];
231 /* enable u3 rx termimation */
232 if (u3phy_port->type == U3PHY_TYPE_PIPE)
233 writel(0x30, u3phy_port->base + 0xd8);
236 atomic_notifier_call_chain(&u3phy->usb_phy.notifier, 0, NULL);
238 gpiod_set_value_cansleep(u3phy->vbus_drv_gpio, 1);
239 } else if (!strncmp(buf, "u2", 2) &&
240 param_exped(u3phy->u3phy_grf,
241 &u3phy->cfgs->grfcfg.u2_only_ctrl, 0)) {
242 dev_info(u3phy->dev, "Set usb2.0 only mode successfully\n");
244 gpiod_set_value_cansleep(u3phy->vbus_drv_gpio, 0);
246 param_write(u3phy->grf,
247 &u3phy->cfgs->grfcfg.u3_disable, true);
248 param_write(u3phy->u3phy_grf,
249 &u3phy->cfgs->grfcfg.u2_only_ctrl, true);
251 for (index = 0; index < U3PHY_PORT_NUM; index++) {
252 u3phy_port = &u3phy->ports[index];
253 /* disable u3 rx termimation */
254 if (u3phy_port->type == U3PHY_TYPE_PIPE)
255 writel(0x20, u3phy_port->base + 0xd8);
258 atomic_notifier_call_chain(&u3phy->usb_phy.notifier, 0, NULL);
260 gpiod_set_value_cansleep(u3phy->vbus_drv_gpio, 1);
262 dev_info(u3phy->dev, "Same or illegal mode\n");
268 static const struct file_operations rockchip_u3phy_usb2_only_fops = {
269 .open = rockchip_u3phy_usb2_only_open,
270 .write = rockchip_u3phy_usb2_only_write,
273 .release = single_release,
276 int rockchip_u3phy_debugfs_init(struct rockchip_u3phy *u3phy)
282 root = debugfs_create_dir(dev_name(u3phy->dev), NULL);
290 file = debugfs_create_file("u3phy_mode", 0644, root,
291 u3phy, &rockchip_u3phy_usb2_only_fops);
299 debugfs_remove_recursive(root);
304 static const char *get_rest_name(enum rockchip_u3phy_rest_req rst)
308 return "u3phy-u2-por";
310 return "u3phy-u3-por";
312 return "u3phy-pipe-mac";
314 return "u3phy-utmi-mac";
316 return "u3phy-utmi-apb";
318 return "u3phy-pipe-apb";
324 static void rockchip_u3phy_rest_deassert(struct rockchip_u3phy *u3phy,
329 if (flag & U3PHY_APB_RST) {
330 dev_dbg(u3phy->dev, "deassert APB bus interface reset\n");
331 for (rst = UTMI_APB_RSTN; rst <= PIPE_APB_RSTN; rst++) {
332 if (u3phy->rsts[rst])
333 reset_control_deassert(u3phy->rsts[rst]);
337 if (flag & U3PHY_POR_RST) {
338 usleep_range(15, 20);
339 dev_dbg(u3phy->dev, "deassert u2 and u3 phy power on reset\n");
340 for (rst = U2_POR_RSTN; rst <= U3_POR_RSTN; rst++) {
341 if (u3phy->rsts[rst])
342 reset_control_deassert(u3phy->rsts[rst]);
346 if (flag & U3PHY_MAC_RST) {
347 usleep_range(2000, 2100);
348 dev_dbg(u3phy->dev, "deassert pipe and utmi MAC reset\n");
349 for (rst = PIPE_MAC_RSTN; rst <= UTMI_MAC_RSTN; rst++)
350 if (u3phy->rsts[rst])
351 reset_control_deassert(u3phy->rsts[rst]);
355 static void rockchip_u3phy_rest_assert(struct rockchip_u3phy *u3phy)
359 dev_dbg(u3phy->dev, "assert u3phy reset\n");
360 for (rst = 0; rst < U3PHY_RESET_MAX; rst++)
361 if (u3phy->rsts[rst])
362 reset_control_assert(u3phy->rsts[rst]);
365 static int rockchip_u3phy_clk_enable(struct rockchip_u3phy *u3phy)
369 for (clk = 0; clk < U3PHY_MAX_CLKS && u3phy->clks[clk]; clk++) {
370 ret = clk_prepare_enable(u3phy->clks[clk]);
372 goto err_disable_clks;
378 clk_disable_unprepare(u3phy->clks[clk]);
382 static void rockchip_u3phy_clk_disable(struct rockchip_u3phy *u3phy)
386 for (clk = U3PHY_MAX_CLKS - 1; clk >= 0; clk--)
387 if (u3phy->clks[clk])
388 clk_disable_unprepare(u3phy->clks[clk]);
391 static int rockchip_u3phy_init(struct phy *phy)
396 static int rockchip_u3phy_exit(struct phy *phy)
401 static int rockchip_u3phy_power_on(struct phy *phy)
403 struct rockchip_u3phy_port *u3phy_port = phy_get_drvdata(phy);
404 struct rockchip_u3phy *u3phy = dev_get_drvdata(phy->dev.parent);
407 dev_info(&u3phy_port->phy->dev, "u3phy %s power on\n",
408 (u3phy_port->type == U3PHY_TYPE_UTMI) ? "u2" : "u3");
410 if (!u3phy_port->suspended)
413 ret = rockchip_u3phy_clk_enable(u3phy);
417 if (u3phy_port->type == U3PHY_TYPE_UTMI) {
418 param_write(u3phy->u3phy_grf,
419 &u3phy->cfgs->grfcfg.um_suspend, false);
421 /* current in p2 ? */
422 if (param_exped(u3phy->u3phy_grf,
423 &u3phy->cfgs->grfcfg.pp_pwr_st, PIPE_PWR_P2))
426 if (u3phy->cfgs->phy_pipe_power) {
427 dev_dbg(u3phy->dev, "do pipe power up\n");
428 u3phy->cfgs->phy_pipe_power(u3phy, u3phy_port, true);
432 param_write(u3phy->u3phy_grf,
433 &u3phy->cfgs->grfcfg.pp_pwr_en[PIPE_PWR_P0], true);
434 usleep_range(90, 100);
436 /* enter to p2 from p0 */
437 param_write(u3phy->u3phy_grf,
438 &u3phy->cfgs->grfcfg.pp_pwr_en[PIPE_PWR_P2],
444 u3phy_port->suspended = false;
448 static int rockchip_u3phy_power_off(struct phy *phy)
450 struct rockchip_u3phy_port *u3phy_port = phy_get_drvdata(phy);
451 struct rockchip_u3phy *u3phy = dev_get_drvdata(phy->dev.parent);
453 dev_info(&u3phy_port->phy->dev, "u3phy %s power off\n",
454 (u3phy_port->type == U3PHY_TYPE_UTMI) ? "u2" : "u3");
456 if (u3phy_port->suspended)
459 if (u3phy_port->type == U3PHY_TYPE_UTMI) {
460 param_write(u3phy->u3phy_grf,
461 &u3phy->cfgs->grfcfg.um_suspend, true);
463 /* current in p3 ? */
464 if (param_exped(u3phy->u3phy_grf,
465 &u3phy->cfgs->grfcfg.pp_pwr_st, PIPE_PWR_P3))
469 param_write(u3phy->u3phy_grf,
470 &u3phy->cfgs->grfcfg.pp_pwr_en[PIPE_PWR_P0], true);
473 /* enter to p3 from p0 */
474 param_write(u3phy->u3phy_grf,
475 &u3phy->cfgs->grfcfg.pp_pwr_en[PIPE_PWR_P3], true);
478 if (u3phy->cfgs->phy_pipe_power) {
479 dev_dbg(u3phy->dev, "do pipe power down\n");
480 u3phy->cfgs->phy_pipe_power(u3phy, u3phy_port, false);
485 rockchip_u3phy_clk_disable(u3phy);
486 u3phy_port->suspended = true;
490 static int rockchip_u3phy_cp_test(struct phy *phy)
492 struct rockchip_u3phy_port *u3phy_port = phy_get_drvdata(phy);
493 struct rockchip_u3phy *u3phy = dev_get_drvdata(phy->dev.parent);
496 if (u3phy->cfgs->phy_cp_test) {
498 * When do USB3 compliance test, we may connect the oscilloscope
499 * front panel Aux Out to the DUT SSRX+, the Aux Out of the
500 * oscilloscope outputs a negative pulse whose width is between
501 * 300- 400 ns which may trigger some DUTs to change the CP test
504 * The Inno USB3 PHY disable the function to detect the negative
505 * pulse in SSRX+ by default, so we need to enable the function
506 * to toggle the CP test pattern before do USB3 compliance test.
508 dev_dbg(u3phy->dev, "prepare for u3phy compliance test\n");
509 ret = u3phy->cfgs->phy_cp_test(u3phy, u3phy_port);
517 static __maybe_unused
518 struct phy *rockchip_u3phy_xlate(struct device *dev,
519 struct of_phandle_args *args)
521 struct rockchip_u3phy *u3phy = dev_get_drvdata(dev);
522 struct rockchip_u3phy_port *u3phy_port = NULL;
523 struct device_node *phy_np = args->np;
526 if (args->args_count != 1) {
527 dev_err(dev, "invalid number of cells in 'phy' property\n");
528 return ERR_PTR(-EINVAL);
531 for (index = 0; index < U3PHY_PORT_NUM; index++) {
532 if (phy_np == u3phy->ports[index].phy->dev.of_node) {
533 u3phy_port = &u3phy->ports[index];
539 dev_err(dev, "failed to find appropriate phy\n");
540 return ERR_PTR(-EINVAL);
543 return u3phy_port->phy;
546 static struct phy_ops rockchip_u3phy_ops = {
547 .init = rockchip_u3phy_init,
548 .exit = rockchip_u3phy_exit,
549 .power_on = rockchip_u3phy_power_on,
550 .power_off = rockchip_u3phy_power_off,
551 .cp_test = rockchip_u3phy_cp_test,
552 .owner = THIS_MODULE,
556 * The function manage host-phy port state and suspend/resume phy port
557 * to save power automatically.
559 * we rely on utmi_linestate and utmi_hostdisconnect to identify whether
560 * devices is disconnect or not. Besides, we do not need care it is FS/LS
561 * disconnected or HS disconnected, actually, we just only need get the
562 * device is disconnected at last through rearm the delayed work,
563 * to suspend the phy port in _PHY_STATE_DISCONNECT_ case.
565 static void rockchip_u3phy_um_sm_work(struct work_struct *work)
567 struct rockchip_u3phy_port *u3phy_port =
568 container_of(work, struct rockchip_u3phy_port, um_sm_work.work);
569 struct rockchip_u3phy *u3phy =
570 dev_get_drvdata(u3phy_port->phy->dev.parent);
571 unsigned int sh = u3phy->cfgs->grfcfg.um_hstdct.bitend -
572 u3phy->cfgs->grfcfg.um_hstdct.bitstart + 1;
573 unsigned int ul, uhd, state;
574 unsigned int ul_mask, uhd_mask;
577 mutex_lock(&u3phy_port->mutex);
579 ret = regmap_read(u3phy->u3phy_grf,
580 u3phy->cfgs->grfcfg.um_ls.offset, &ul);
584 ret = regmap_read(u3phy->u3phy_grf,
585 u3phy->cfgs->grfcfg.um_hstdct.offset, &uhd);
589 uhd_mask = GENMASK(u3phy->cfgs->grfcfg.um_hstdct.bitend,
590 u3phy->cfgs->grfcfg.um_hstdct.bitstart);
591 ul_mask = GENMASK(u3phy->cfgs->grfcfg.um_ls.bitend,
592 u3phy->cfgs->grfcfg.um_ls.bitstart);
594 /* stitch on um_ls and um_hstdct as phy state */
595 state = ((uhd & uhd_mask) >> u3phy->cfgs->grfcfg.um_hstdct.bitstart) |
596 (((ul & ul_mask) >> u3phy->cfgs->grfcfg.um_ls.bitstart) << sh);
599 case PHY_UTMI_HS_ONLINE:
600 dev_dbg(&u3phy_port->phy->dev, "HS online\n");
602 case PHY_UTMI_FS_LS_ONLINE:
604 * For FS/LS device, the online state share with connect state
605 * from um_ls and um_hstdct register, so we distinguish
606 * them via suspended flag.
608 * Plus, there are two cases, one is D- Line pull-up, and D+
609 * line pull-down, the state is 4; another is D+ line pull-up,
610 * and D- line pull-down, the state is 2.
612 if (!u3phy_port->suspended) {
613 /* D- line pull-up, D+ line pull-down */
614 dev_dbg(&u3phy_port->phy->dev, "FS/LS online\n");
618 case PHY_UTMI_CONNECT:
619 if (u3phy_port->suspended) {
620 dev_dbg(&u3phy_port->phy->dev, "Connected\n");
621 rockchip_u3phy_power_on(u3phy_port->phy);
622 u3phy_port->suspended = false;
624 /* D+ line pull-up, D- line pull-down */
625 dev_dbg(&u3phy_port->phy->dev, "FS/LS online\n");
628 case PHY_UTMI_DISCONNECT:
629 if (!u3phy_port->suspended) {
630 dev_dbg(&u3phy_port->phy->dev, "Disconnected\n");
631 rockchip_u3phy_power_off(u3phy_port->phy);
632 u3phy_port->suspended = true;
636 * activate the linestate detection to get the next device
639 param_write(u3phy->u3phy_grf,
640 &u3phy->cfgs->grfcfg.ls_det_st, true);
641 param_write(u3phy->u3phy_grf,
642 &u3phy->cfgs->grfcfg.ls_det_en, true);
645 * we don't need to rearm the delayed work when the phy port
648 mutex_unlock(&u3phy_port->mutex);
651 dev_dbg(&u3phy_port->phy->dev, "unknown phy state\n");
656 mutex_unlock(&u3phy_port->mutex);
657 schedule_delayed_work(&u3phy_port->um_sm_work, SCHEDULE_DELAY);
660 static irqreturn_t rockchip_u3phy_um_ls_irq(int irq, void *data)
662 struct rockchip_u3phy_port *u3phy_port = data;
663 struct rockchip_u3phy *u3phy =
664 dev_get_drvdata(u3phy_port->phy->dev.parent);
666 if (!param_exped(u3phy->u3phy_grf,
667 &u3phy->cfgs->grfcfg.ls_det_st,
668 u3phy->cfgs->grfcfg.ls_det_st.dvalue))
671 dev_dbg(u3phy->dev, "utmi linestate interrupt\n");
672 mutex_lock(&u3phy_port->mutex);
674 /* disable linestate detect irq and clear its status */
675 param_write(u3phy->u3phy_grf, &u3phy->cfgs->grfcfg.ls_det_en, false);
676 param_write(u3phy->u3phy_grf, &u3phy->cfgs->grfcfg.ls_det_st, true);
678 mutex_unlock(&u3phy_port->mutex);
681 * In this case for host phy, a new device is plugged in, meanwhile,
682 * if the phy port is suspended, we need rearm the work to resume it
683 * and mange its states; otherwise, we just return irq handled.
685 if (u3phy_port->suspended) {
686 dev_dbg(u3phy->dev, "schedule utmi sm work\n");
687 rockchip_u3phy_um_sm_work(&u3phy_port->um_sm_work.work);
693 static int rockchip_u3phy_parse_dt(struct rockchip_u3phy *u3phy,
694 struct platform_device *pdev)
697 struct device *dev = &pdev->dev;
698 struct device_node *np = dev->of_node;
701 u3phy->um_ls_irq = platform_get_irq_byname(pdev, "linestate");
702 if (u3phy->um_ls_irq < 0) {
703 dev_err(dev, "get utmi linestate irq failed\n");
707 u3phy->vbus_drv_gpio = devm_gpiod_get_optional(dev, "vbus-drv",
710 if (!u3phy->vbus_drv_gpio) {
711 dev_warn(&pdev->dev, "vbus_drv is not assigned\n");
712 } else if (IS_ERR(u3phy->vbus_drv_gpio)) {
713 dev_err(&pdev->dev, "failed to get vbus_drv\n");
714 return PTR_ERR(u3phy->vbus_drv_gpio);
717 for (clk = 0; clk < U3PHY_MAX_CLKS; clk++) {
718 u3phy->clks[clk] = of_clk_get(np, clk);
719 if (IS_ERR(u3phy->clks[clk])) {
720 ret = PTR_ERR(u3phy->clks[clk]);
721 if (ret == -EPROBE_DEFER)
723 u3phy->clks[clk] = NULL;
728 for (i = 0; i < U3PHY_RESET_MAX; i++) {
729 u3phy->rsts[i] = devm_reset_control_get(dev, get_rest_name(i));
730 if (IS_ERR(u3phy->rsts[i])) {
731 dev_info(dev, "no %s reset control specified\n",
733 u3phy->rsts[i] = NULL;
741 clk_put(u3phy->clks[clk]);
745 static int rockchip_u3phy_port_init(struct rockchip_u3phy *u3phy,
746 struct rockchip_u3phy_port *u3phy_port,
747 struct device_node *child_np)
753 dev_dbg(u3phy->dev, "u3phy port initialize\n");
755 mutex_init(&u3phy_port->mutex);
756 u3phy_port->suspended = true; /* initial status */
758 phy = devm_phy_create(u3phy->dev, child_np, &rockchip_u3phy_ops);
760 dev_err(u3phy->dev, "failed to create phy\n");
764 u3phy_port->phy = phy;
766 ret = of_address_to_resource(child_np, 0, &res);
768 dev_err(u3phy->dev, "failed to get address resource(np-%s)\n",
773 u3phy_port->base = devm_ioremap_resource(&u3phy_port->phy->dev, &res);
774 if (IS_ERR(u3phy_port->base)) {
775 dev_err(u3phy->dev, "failed to remap phy regs\n");
776 return PTR_ERR(u3phy_port->base);
779 if (!of_node_cmp(child_np->name, "pipe")) {
780 u3phy_port->type = U3PHY_TYPE_PIPE;
781 u3phy_port->refclk_25m_quirk =
782 of_property_read_bool(child_np,
783 "rockchip,refclk-25m-quirk");
785 u3phy_port->type = U3PHY_TYPE_UTMI;
786 INIT_DELAYED_WORK(&u3phy_port->um_sm_work,
787 rockchip_u3phy_um_sm_work);
789 ret = devm_request_threaded_irq(u3phy->dev, u3phy->um_ls_irq,
790 NULL, rockchip_u3phy_um_ls_irq,
791 IRQF_ONESHOT, "rockchip_u3phy",
794 dev_err(u3phy->dev, "failed to request utmi linestate irq handle\n");
799 if (u3phy->cfgs->phy_tuning) {
800 dev_dbg(u3phy->dev, "do u3phy tuning\n");
801 ret = u3phy->cfgs->phy_tuning(u3phy, u3phy_port, child_np);
806 phy_set_drvdata(u3phy_port->phy, u3phy_port);
810 static int rockchip_u3phy_on_init(struct usb_phy *usb_phy)
812 struct rockchip_u3phy *u3phy =
813 container_of(usb_phy, struct rockchip_u3phy, usb_phy);
815 reset_control_deassert(u3phy->rsts[U3_POR_RSTN]);
816 usleep_range(250, 300);
817 reset_control_deassert(u3phy->rsts[PIPE_MAC_RSTN]);
822 static void rockchip_u3phy_on_shutdown(struct usb_phy *usb_phy)
824 struct rockchip_u3phy *u3phy =
825 container_of(usb_phy, struct rockchip_u3phy, usb_phy);
827 reset_control_assert(u3phy->rsts[U3_POR_RSTN]);
828 reset_control_assert(u3phy->rsts[PIPE_MAC_RSTN]);
829 usleep_range(15, 20);
832 static int rockchip_u3phy_on_disconnect(struct usb_phy *usb_phy,
833 enum usb_device_speed speed)
835 struct rockchip_u3phy *u3phy =
836 container_of(usb_phy, struct rockchip_u3phy, usb_phy);
838 dev_info(u3phy->dev, "%s device has disconnected\n",
839 (speed == USB_SPEED_SUPER) ? "U3" : "UW/U2/U1.1/U1");
841 if (speed == USB_SPEED_SUPER)
842 atomic_notifier_call_chain(&usb_phy->notifier, 0, NULL);
847 static int rockchip_u3phy_probe(struct platform_device *pdev)
849 struct device *dev = &pdev->dev;
850 struct device_node *np = dev->of_node;
851 struct device_node *child_np;
852 struct phy_provider *provider;
853 struct rockchip_u3phy *u3phy;
854 const struct rockchip_u3phy_cfg *phy_cfgs;
855 const struct of_device_id *match;
859 match = of_match_device(dev->driver->of_match_table, dev);
860 if (!match || !match->data) {
861 dev_err(dev, "phy-cfgs are not assigned!\n");
865 u3phy = devm_kzalloc(dev, sizeof(*u3phy), GFP_KERNEL);
870 syscon_regmap_lookup_by_phandle(np, "rockchip,u3phygrf");
871 if (IS_ERR(u3phy->u3phy_grf))
872 return PTR_ERR(u3phy->u3phy_grf);
875 syscon_regmap_lookup_by_phandle(np, "rockchip,grf");
876 if (IS_ERR(u3phy->grf)) {
877 dev_err(dev, "Missing rockchip,grf property\n");
878 return PTR_ERR(u3phy->grf);
881 if (of_property_read_u32_array(np, "reg", reg, 2)) {
882 dev_err(dev, "the reg property is not assigned in %s node\n",
888 phy_cfgs = match->data;
889 platform_set_drvdata(pdev, u3phy);
891 /* find out a proper config which can be matched with dt. */
893 while (phy_cfgs[index].reg) {
894 if (phy_cfgs[index].reg == reg[1]) {
895 u3phy->cfgs = &phy_cfgs[index];
903 dev_err(dev, "no phy-cfgs can be matched with %s node\n",
908 ret = rockchip_u3phy_parse_dt(u3phy, pdev);
910 dev_err(dev, "parse dt failed, ret(%d)\n", ret);
914 ret = rockchip_u3phy_clk_enable(u3phy);
916 dev_err(dev, "clk enable failed, ret(%d)\n", ret);
920 rockchip_u3phy_rest_assert(u3phy);
921 rockchip_u3phy_rest_deassert(u3phy, U3PHY_APB_RST | U3PHY_POR_RST);
924 for_each_available_child_of_node(np, child_np) {
925 struct rockchip_u3phy_port *u3phy_port = &u3phy->ports[index];
927 u3phy_port->index = index;
928 ret = rockchip_u3phy_port_init(u3phy, u3phy_port, child_np);
930 dev_err(dev, "u3phy port init failed,ret(%d)\n", ret);
934 /* to prevent out of boundary */
935 if (++index >= U3PHY_PORT_NUM)
939 provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
940 if (IS_ERR_OR_NULL(provider))
943 rockchip_u3phy_rest_deassert(u3phy, U3PHY_MAC_RST);
944 rockchip_u3phy_clk_disable(u3phy);
946 u3phy->usb_phy.dev = dev;
947 u3phy->usb_phy.init = rockchip_u3phy_on_init;
948 u3phy->usb_phy.shutdown = rockchip_u3phy_on_shutdown;
949 u3phy->usb_phy.notify_disconnect = rockchip_u3phy_on_disconnect;
950 usb_add_phy(&u3phy->usb_phy, USB_PHY_TYPE_USB3);
951 ATOMIC_INIT_NOTIFIER_HEAD(&u3phy->usb_phy.notifier);
953 rockchip_u3phy_debugfs_init(u3phy);
955 dev_info(dev, "Rockchip u3phy initialized successfully\n");
959 of_node_put(child_np);
963 static int rk3328_u3phy_pipe_power(struct rockchip_u3phy *u3phy,
964 struct rockchip_u3phy_port *u3phy_port,
970 reg = readl(u3phy_port->base + 0x1a8);
971 reg &= ~BIT(4); /* ldo power up */
972 writel(reg, u3phy_port->base + 0x1a8);
974 reg = readl(u3phy_port->base + 0x044);
975 reg &= ~BIT(4); /* bg power on */
976 writel(reg, u3phy_port->base + 0x044);
978 reg = readl(u3phy_port->base + 0x150);
979 reg |= BIT(6); /* tx bias enable */
980 writel(reg, u3phy_port->base + 0x150);
982 reg = readl(u3phy_port->base + 0x080);
983 reg &= ~BIT(2); /* tx cm power up */
984 writel(reg, u3phy_port->base + 0x080);
986 reg = readl(u3phy_port->base + 0x0c0);
987 /* tx obs enable and rx cm enable */
988 reg |= (BIT(3) | BIT(4));
989 writel(reg, u3phy_port->base + 0x0c0);
993 reg = readl(u3phy_port->base + 0x1a8);
994 reg |= BIT(4); /* ldo power down */
995 writel(reg, u3phy_port->base + 0x1a8);
997 reg = readl(u3phy_port->base + 0x044);
998 reg |= BIT(4); /* bg power down */
999 writel(reg, u3phy_port->base + 0x044);
1001 reg = readl(u3phy_port->base + 0x150);
1002 reg &= ~BIT(6); /* tx bias disable */
1003 writel(reg, u3phy_port->base + 0x150);
1005 reg = readl(u3phy_port->base + 0x080);
1006 reg |= BIT(2); /* tx cm power down */
1007 writel(reg, u3phy_port->base + 0x080);
1009 reg = readl(u3phy_port->base + 0x0c0);
1010 /* tx obs disable and rx cm disable */
1011 reg &= ~(BIT(3) | BIT(4));
1012 writel(reg, u3phy_port->base + 0x0c0);
1018 static int rk3328_u3phy_tuning(struct rockchip_u3phy *u3phy,
1019 struct rockchip_u3phy_port *u3phy_port,
1020 struct device_node *child_np)
1022 if (u3phy_port->type == U3PHY_TYPE_UTMI) {
1024 * For rk3328 SoC, pre-emphasis and pre-emphasis strength must
1025 * be written as one fixed value as below.
1027 * Dissimilarly, the odt 45ohm value should be flexibly tuninged
1028 * for the different boards to adjust HS eye height, so its
1029 * value can be assigned in DT in code design.
1032 /* {bits[2:0]=111}: always enable pre-emphasis */
1033 u3phy->apbcfg.u2_pre_emp = 0x0f;
1035 /* {bits[5:3]=000}: pre-emphasis strength as the weakest */
1036 u3phy->apbcfg.u2_pre_emp_sth = 0x41;
1038 /* {bits[4:0]=10101}: odt 45ohm tuning */
1039 u3phy->apbcfg.u2_odt_tuning = 0xb5;
1040 /* optional override of the odt 45ohm tuning */
1041 of_property_read_u32(child_np, "rockchip,odt-val-tuning",
1042 &u3phy->apbcfg.u2_odt_tuning);
1044 writel(u3phy->apbcfg.u2_pre_emp, u3phy_port->base + 0x030);
1045 writel(u3phy->apbcfg.u2_pre_emp_sth, u3phy_port->base + 0x040);
1046 writel(u3phy->apbcfg.u2_odt_tuning, u3phy_port->base + 0x11c);
1047 } else if (u3phy_port->type == U3PHY_TYPE_PIPE) {
1048 if (u3phy_port->refclk_25m_quirk) {
1049 dev_dbg(u3phy->dev, "switch to 25m refclk\n");
1050 /* ref clk switch to 25M */
1051 writel(0x64, u3phy_port->base + 0x11c);
1052 writel(0x64, u3phy_port->base + 0x028);
1053 writel(0x01, u3phy_port->base + 0x020);
1054 writel(0x21, u3phy_port->base + 0x030);
1055 writel(0x06, u3phy_port->base + 0x108);
1056 writel(0x00, u3phy_port->base + 0x118);
1058 /* configure for 24M ref clk */
1059 writel(0x80, u3phy_port->base + 0x10c);
1060 writel(0x01, u3phy_port->base + 0x118);
1061 writel(0x38, u3phy_port->base + 0x11c);
1062 writel(0x83, u3phy_port->base + 0x020);
1063 writel(0x02, u3phy_port->base + 0x108);
1068 writel(0x08, u3phy_port->base + 0x000);
1069 writel(0x0c, u3phy_port->base + 0x120);
1071 /* Tuning Rx for compliance RJTL test */
1072 writel(0x70, u3phy_port->base + 0x150);
1073 writel(0x12, u3phy_port->base + 0x0c8);
1074 writel(0x05, u3phy_port->base + 0x148);
1075 writel(0x08, u3phy_port->base + 0x068);
1076 writel(0xf0, u3phy_port->base + 0x1c4);
1077 writel(0xff, u3phy_port->base + 0x070);
1078 writel(0x0f, u3phy_port->base + 0x06c);
1079 writel(0xe0, u3phy_port->base + 0x060);
1082 * Tuning Tx to increase the bias current
1083 * used in TX driver and RX EQ, it can
1084 * also increase the voltage of LFPS.
1086 writel(0x08, u3phy_port->base + 0x180);
1088 dev_err(u3phy->dev, "invalid u3phy port type\n");
1095 static int rk322xh_u3phy_cp_test_enable(struct rockchip_u3phy *u3phy,
1096 struct rockchip_u3phy_port *u3phy_port)
1098 if (u3phy_port->type == U3PHY_TYPE_PIPE) {
1099 writel(0x0c, u3phy_port->base + 0x408);
1101 dev_err(u3phy->dev, "The u3phy type is not pipe\n");
1108 static const struct rockchip_u3phy_cfg rk3328_u3phy_cfgs[] = {
1112 .um_suspend = { 0x0004, 15, 0, 0x1452, 0x15d1 },
1113 .u2_only_ctrl = { 0x0020, 15, 15, 0, 1 },
1114 .um_ls = { 0x0030, 5, 4, 0, 1 },
1115 .um_hstdct = { 0x0030, 7, 7, 0, 1 },
1116 .ls_det_en = { 0x0040, 0, 0, 0, 1 },
1117 .ls_det_st = { 0x0044, 0, 0, 0, 1 },
1118 .pp_pwr_st = { 0x0034, 14, 13, 0, 0},
1119 .pp_pwr_en = { {0x0020, 14, 0, 0x0014, 0x0005},
1120 {0x0020, 14, 0, 0x0014, 0x000d},
1121 {0x0020, 14, 0, 0x0014, 0x0015},
1122 {0x0020, 14, 0, 0x0014, 0x001d} },
1123 .u3_disable = { 0x04c4, 15, 0, 0x1100, 0x101},
1125 .phy_pipe_power = rk3328_u3phy_pipe_power,
1126 .phy_tuning = rk3328_u3phy_tuning,
1127 .phy_cp_test = rk322xh_u3phy_cp_test_enable,
1132 static const struct of_device_id rockchip_u3phy_dt_match[] = {
1133 { .compatible = "rockchip,rk3328-u3phy", .data = &rk3328_u3phy_cfgs },
1136 MODULE_DEVICE_TABLE(of, rockchip_u3phy_dt_match);
1138 static struct platform_driver rockchip_u3phy_driver = {
1139 .probe = rockchip_u3phy_probe,
1141 .name = "rockchip-u3phy",
1142 .of_match_table = rockchip_u3phy_dt_match,
1145 module_platform_driver(rockchip_u3phy_driver);
1147 MODULE_AUTHOR("Frank Wang <frank.wang@rock-chips.com>");
1148 MODULE_AUTHOR("William Wu <william.wu@rock-chips.com>");
1149 MODULE_DESCRIPTION("Rockchip USB 3.0 PHY driver");
1150 MODULE_LICENSE("GPL v2");