2 * Rockchip USB2.0 PHY with Innosilicon IP block driver
4 * Copyright (C) 2016 Fuzhou Rockchip Electronics Co., Ltd
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/clk.h>
18 #include <linux/clk-provider.h>
19 #include <linux/delay.h>
20 #include <linux/extcon.h>
21 #include <linux/interrupt.h>
23 #include <linux/gpio/consumer.h>
24 #include <linux/jiffies.h>
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/mutex.h>
29 #include <linux/of_address.h>
30 #include <linux/of_irq.h>
31 #include <linux/of_platform.h>
32 #include <linux/phy/phy.h>
33 #include <linux/platform_device.h>
34 #include <linux/power_supply.h>
35 #include <linux/regmap.h>
36 #include <linux/mfd/syscon.h>
37 #include <linux/usb/of.h>
38 #include <linux/usb/otg.h>
39 #include <linux/wakelock.h>
41 #define BIT_WRITEABLE_SHIFT 16
42 #define SCHEDULE_DELAY (60 * HZ)
43 #define OTG_SCHEDULE_DELAY (2 * HZ)
45 struct rockchip_usb2phy;
47 enum rockchip_usb2phy_port_id {
53 enum rockchip_usb2phy_host_state {
54 PHY_STATE_HS_ONLINE = 0,
55 PHY_STATE_DISCONNECT = 1,
56 PHY_STATE_CONNECT = 2,
57 PHY_STATE_FS_LS_ONLINE = 4,
61 * Different states involved in USB charger detection.
62 * USB_CHG_STATE_UNDEFINED USB charger is not connected or detection
63 * process is not yet started.
64 * USB_CHG_STATE_WAIT_FOR_DCD Waiting for Data pins contact.
65 * USB_CHG_STATE_DCD_DONE Data pin contact is detected.
66 * USB_CHG_STATE_PRIMARY_DONE Primary detection is completed (Detects
67 * between SDP and DCP/CDP).
68 * USB_CHG_STATE_SECONDARY_DONE Secondary detection is completed (Detects
69 * between DCP and CDP).
70 * USB_CHG_STATE_DETECTED USB charger type is determined.
73 USB_CHG_STATE_UNDEFINED = 0,
74 USB_CHG_STATE_WAIT_FOR_DCD,
75 USB_CHG_STATE_DCD_DONE,
76 USB_CHG_STATE_PRIMARY_DONE,
77 USB_CHG_STATE_SECONDARY_DONE,
78 USB_CHG_STATE_DETECTED,
81 static const unsigned int rockchip_usb2phy_extcon_cable[] = {
95 unsigned int bitstart;
101 * struct rockchip_chg_det_reg: usb charger detect registers
102 * @cp_det: charging port detected successfully.
103 * @dcp_det: dedicated charging port detected successfully.
104 * @dp_det: assert data pin connect successfully.
105 * @idm_sink_en: open dm sink curren.
106 * @idp_sink_en: open dp sink current.
107 * @idp_src_en: open dm source current.
108 * @rdm_pdwn_en: open dm pull down resistor.
109 * @vdm_src_en: open dm voltage source.
110 * @vdp_src_en: open dp voltage source.
111 * @opmode: utmi operational mode.
113 struct rockchip_chg_det_reg {
114 struct usb2phy_reg cp_det;
115 struct usb2phy_reg dcp_det;
116 struct usb2phy_reg dp_det;
117 struct usb2phy_reg idm_sink_en;
118 struct usb2phy_reg idp_sink_en;
119 struct usb2phy_reg idp_src_en;
120 struct usb2phy_reg rdm_pdwn_en;
121 struct usb2phy_reg vdm_src_en;
122 struct usb2phy_reg vdp_src_en;
123 struct usb2phy_reg opmode;
127 * struct rockchip_usb2phy_port_cfg: usb-phy port configuration.
128 * @phy_sus: phy suspend register.
129 * @bvalid_det_en: vbus valid rise detection enable register.
130 * @bvalid_det_st: vbus valid rise detection status register.
131 * @bvalid_det_clr: vbus valid rise detection clear register.
132 * @ls_det_en: linestate detection enable register.
133 * @ls_det_st: linestate detection state register.
134 * @ls_det_clr: linestate detection clear register.
135 * @idfall_det_en: id fall detection enable register.
136 * @idfall_det_st: id fall detection state register.
137 * @idfall_det_clr: id fall detection clear register.
138 * @idrise_det_en: id rise detection enable register.
139 * @idrise_det_st: id rise detection state register.
140 * @idrise_det_clr: id rise detection clear register.
141 * @utmi_avalid: utmi vbus avalid status register.
142 * @utmi_bvalid: utmi vbus bvalid status register.
143 * @utmi_iddig: otg port id pin status register.
144 * @utmi_ls: utmi linestate state register.
145 * @utmi_hstdet: utmi host disconnect register.
147 struct rockchip_usb2phy_port_cfg {
148 struct usb2phy_reg phy_sus;
149 struct usb2phy_reg bvalid_det_en;
150 struct usb2phy_reg bvalid_det_st;
151 struct usb2phy_reg bvalid_det_clr;
152 struct usb2phy_reg ls_det_en;
153 struct usb2phy_reg ls_det_st;
154 struct usb2phy_reg ls_det_clr;
155 struct usb2phy_reg idfall_det_en;
156 struct usb2phy_reg idfall_det_st;
157 struct usb2phy_reg idfall_det_clr;
158 struct usb2phy_reg idrise_det_en;
159 struct usb2phy_reg idrise_det_st;
160 struct usb2phy_reg idrise_det_clr;
161 struct usb2phy_reg utmi_avalid;
162 struct usb2phy_reg utmi_bvalid;
163 struct usb2phy_reg utmi_iddig;
164 struct usb2phy_reg utmi_ls;
165 struct usb2phy_reg utmi_hstdet;
169 * struct rockchip_usb2phy_cfg: usb-phy configuration.
170 * @reg: the address offset of grf for usb-phy config.
171 * @num_ports: specify how many ports that the phy has.
172 * @phy_tuning: phy default parameters tunning.
173 * @clkout_ctl: keep on/turn off output clk of phy.
174 * @chg_det: charger detection registers.
176 struct rockchip_usb2phy_cfg {
178 unsigned int num_ports;
179 int (*phy_tuning)(struct rockchip_usb2phy *);
180 struct usb2phy_reg clkout_ctl;
181 const struct rockchip_usb2phy_port_cfg port_cfgs[USB2PHY_NUM_PORTS];
182 const struct rockchip_chg_det_reg chg_det;
186 * struct rockchip_usb2phy_port: usb-phy port data.
187 * @port_id: flag for otg port or host port.
188 * @perip_connected: flag for periphyeral connect status.
189 * @suspended: phy suspended flag.
190 * @utmi_avalid: utmi avalid status usage flag.
191 * true - use avalid to get vbus status
192 * flase - use bvalid to get vbus status
193 * @vbus_attached: otg device vbus status.
194 * @bvalid_irq: IRQ number assigned for vbus valid rise detection.
195 * @ls_irq: IRQ number assigned for linestate detection.
196 * @id_irq: IRQ number assigned for id fall or rise detection.
197 * @mutex: for register updating in sm_work.
198 * @chg_work: charge detect work.
199 * @otg_sm_work: OTG state machine work.
200 * @sm_work: HOST state machine work.
201 * @phy_cfg: port register configuration, assigned by driver data.
202 * @event_nb: hold event notification callback.
203 * @wakelock: wake lock struct to prevent system suspend
204 * when USB is active.
205 * @state: define OTG enumeration states before device reset.
206 * @mode: the dr_mode of the controller.
208 struct rockchip_usb2phy_port {
210 unsigned int port_id;
211 bool perip_connected;
219 struct delayed_work chg_work;
220 struct delayed_work otg_sm_work;
221 struct delayed_work sm_work;
222 const struct rockchip_usb2phy_port_cfg *port_cfg;
223 struct notifier_block event_nb;
224 struct wake_lock wakelock;
225 enum usb_otg_state state;
226 enum usb_dr_mode mode;
230 * struct rockchip_usb2phy: usb2.0 phy driver data.
231 * @grf: General Register Files regmap.
232 * @clk: clock struct of phy input clk.
233 * @clk480m: clock struct of phy output clk.
234 * @clk_hw: clock struct of phy output clk management.
235 * @chg_state: states involved in USB charger detection.
236 * @chg_type: USB charger types.
237 * @dcd_retries: The retry count used to track Data contact
239 * @edev_self: represent the source of extcon.
240 * @edev: extcon device for notification registration
241 * @phy_cfg: phy register configuration, assigned by driver data.
242 * @ports: phy port instance.
244 struct rockchip_usb2phy {
249 struct clk_hw clk480m_hw;
250 enum usb_chg_state chg_state;
251 enum power_supply_type chg_type;
255 struct extcon_dev *edev;
256 const struct rockchip_usb2phy_cfg *phy_cfg;
257 struct rockchip_usb2phy_port ports[USB2PHY_NUM_PORTS];
260 static inline int property_enable(struct rockchip_usb2phy *rphy,
261 const struct usb2phy_reg *reg, bool en)
263 unsigned int val, mask, tmp;
265 tmp = en ? reg->enable : reg->disable;
266 mask = GENMASK(reg->bitend, reg->bitstart);
267 val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT);
269 return regmap_write(rphy->grf, reg->offset, val);
272 static inline bool property_enabled(struct rockchip_usb2phy *rphy,
273 const struct usb2phy_reg *reg)
276 unsigned int tmp, orig;
277 unsigned int mask = GENMASK(reg->bitend, reg->bitstart);
279 ret = regmap_read(rphy->grf, reg->offset, &orig);
283 tmp = (orig & mask) >> reg->bitstart;
284 return tmp == reg->enable;
287 static int rockchip_usb2phy_clk480m_enable(struct clk_hw *hw)
289 struct rockchip_usb2phy *rphy =
290 container_of(hw, struct rockchip_usb2phy, clk480m_hw);
293 /* turn on 480m clk output if it is off */
294 if (!property_enabled(rphy, &rphy->phy_cfg->clkout_ctl)) {
295 ret = property_enable(rphy, &rphy->phy_cfg->clkout_ctl, true);
299 /* waitting for the clk become stable */
306 static void rockchip_usb2phy_clk480m_disable(struct clk_hw *hw)
308 struct rockchip_usb2phy *rphy =
309 container_of(hw, struct rockchip_usb2phy, clk480m_hw);
311 /* turn off 480m clk output */
312 property_enable(rphy, &rphy->phy_cfg->clkout_ctl, false);
315 static int rockchip_usb2phy_clk480m_enabled(struct clk_hw *hw)
317 struct rockchip_usb2phy *rphy =
318 container_of(hw, struct rockchip_usb2phy, clk480m_hw);
320 return property_enabled(rphy, &rphy->phy_cfg->clkout_ctl);
324 rockchip_usb2phy_clk480m_recalc_rate(struct clk_hw *hw,
325 unsigned long parent_rate)
330 static const struct clk_ops rockchip_usb2phy_clkout_ops = {
331 .enable = rockchip_usb2phy_clk480m_enable,
332 .disable = rockchip_usb2phy_clk480m_disable,
333 .is_enabled = rockchip_usb2phy_clk480m_enabled,
334 .recalc_rate = rockchip_usb2phy_clk480m_recalc_rate,
337 static void rockchip_usb2phy_clk480m_unregister(void *data)
339 struct rockchip_usb2phy *rphy = data;
341 of_clk_del_provider(rphy->dev->of_node);
342 clk_unregister(rphy->clk480m);
346 rockchip_usb2phy_clk480m_register(struct rockchip_usb2phy *rphy)
348 struct device_node *node = rphy->dev->of_node;
349 struct clk_init_data init;
350 const char *clk_name;
354 init.name = "clk_usbphy_480m";
355 init.ops = &rockchip_usb2phy_clkout_ops;
357 /* optional override of the clockname */
358 of_property_read_string(node, "clock-output-names", &init.name);
361 clk_name = __clk_get_name(rphy->clk);
362 init.parent_names = &clk_name;
363 init.num_parents = 1;
365 init.parent_names = NULL;
366 init.num_parents = 0;
369 rphy->clk480m_hw.init = &init;
371 /* register the clock */
372 rphy->clk480m = clk_register(rphy->dev, &rphy->clk480m_hw);
373 if (IS_ERR(rphy->clk480m)) {
374 ret = PTR_ERR(rphy->clk480m);
378 ret = of_clk_add_provider(node, of_clk_src_simple_get, rphy->clk480m);
380 goto err_clk_provider;
382 ret = devm_add_action(rphy->dev, rockchip_usb2phy_clk480m_unregister,
385 goto err_unreg_action;
390 of_clk_del_provider(node);
392 clk_unregister(rphy->clk480m);
397 static int rockchip_usb2phy_extcon_register(struct rockchip_usb2phy *rphy)
400 struct device_node *node = rphy->dev->of_node;
401 struct extcon_dev *edev;
403 if (of_property_read_bool(node, "extcon")) {
404 edev = extcon_get_edev_by_phandle(rphy->dev, 0);
406 if (PTR_ERR(edev) != -EPROBE_DEFER)
407 dev_err(rphy->dev, "Invalid or missing extcon\n");
408 return PTR_ERR(edev);
411 /* Initialize extcon device */
412 edev = devm_extcon_dev_allocate(rphy->dev,
413 rockchip_usb2phy_extcon_cable);
418 ret = devm_extcon_dev_register(rphy->dev, edev);
420 dev_err(rphy->dev, "failed to register extcon device\n");
424 rphy->edev_self = true;
432 static int rockchip_usb2phy_init(struct phy *phy)
434 struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
435 struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
438 mutex_lock(&rport->mutex);
440 if (rport->port_id == USB2PHY_PORT_OTG) {
441 if (rport->mode != USB_DR_MODE_HOST) {
442 /* clear bvalid status and enable bvalid detect irq */
443 ret = property_enable(rphy,
450 ret = property_enable(rphy,
457 if (rphy->edev_self) {
458 ret = property_enable(rphy,
465 ret = property_enable(rphy,
472 ret = property_enable(rphy,
479 ret = property_enable(rphy,
487 schedule_delayed_work(&rport->otg_sm_work,
490 /* If OTG works in host only mode, do nothing. */
491 dev_dbg(&rport->phy->dev, "mode %d\n", rport->mode);
493 } else if (rport->port_id == USB2PHY_PORT_HOST) {
494 /* clear linestate and enable linestate detect irq */
495 ret = property_enable(rphy, &rport->port_cfg->ls_det_clr, true);
499 ret = property_enable(rphy, &rport->port_cfg->ls_det_en, true);
503 schedule_delayed_work(&rport->sm_work, SCHEDULE_DELAY);
507 mutex_unlock(&rport->mutex);
511 static int rockchip_usb2phy_power_on(struct phy *phy)
513 struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
514 struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
517 dev_dbg(&rport->phy->dev, "port power on\n");
519 if (!rport->suspended)
522 ret = clk_prepare_enable(rphy->clk480m);
526 ret = property_enable(rphy, &rport->port_cfg->phy_sus, false);
530 rport->suspended = false;
534 static int rockchip_usb2phy_power_off(struct phy *phy)
536 struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
537 struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
540 dev_dbg(&rport->phy->dev, "port power off\n");
542 if (rport->suspended)
545 ret = property_enable(rphy, &rport->port_cfg->phy_sus, true);
549 rport->suspended = true;
550 clk_disable_unprepare(rphy->clk480m);
555 static int rockchip_usb2phy_exit(struct phy *phy)
557 struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
559 if (rport->port_id == USB2PHY_PORT_OTG &&
560 rport->mode != USB_DR_MODE_HOST)
561 cancel_delayed_work_sync(&rport->chg_work);
562 else if (rport->port_id == USB2PHY_PORT_HOST)
563 cancel_delayed_work_sync(&rport->sm_work);
568 static const struct phy_ops rockchip_usb2phy_ops = {
569 .init = rockchip_usb2phy_init,
570 .exit = rockchip_usb2phy_exit,
571 .power_on = rockchip_usb2phy_power_on,
572 .power_off = rockchip_usb2phy_power_off,
573 .owner = THIS_MODULE,
576 static void rockchip_usb2phy_otg_sm_work(struct work_struct *work)
578 struct rockchip_usb2phy_port *rport =
579 container_of(work, struct rockchip_usb2phy_port,
581 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
582 static unsigned int cable;
586 if (rport->utmi_avalid)
587 rport->vbus_attached =
588 property_enabled(rphy, &rport->port_cfg->utmi_avalid);
590 rport->vbus_attached =
591 property_enabled(rphy, &rport->port_cfg->utmi_bvalid);
594 delay = OTG_SCHEDULE_DELAY;
596 dev_dbg(&rport->phy->dev, "%s otg sm work\n",
597 usb_otg_state_string(rport->state));
599 switch (rport->state) {
600 case OTG_STATE_UNDEFINED:
601 rport->state = OTG_STATE_B_IDLE;
602 if (!rport->vbus_attached)
603 rockchip_usb2phy_power_off(rport->phy);
605 case OTG_STATE_B_IDLE:
606 if (extcon_get_cable_state_(rphy->edev, EXTCON_USB_HOST) > 0) {
607 dev_dbg(&rport->phy->dev, "usb otg host connect\n");
608 rport->state = OTG_STATE_A_HOST;
609 rockchip_usb2phy_power_on(rport->phy);
611 } else if (rport->vbus_attached) {
612 dev_dbg(&rport->phy->dev, "vbus_attach\n");
613 switch (rphy->chg_state) {
614 case USB_CHG_STATE_UNDEFINED:
615 schedule_delayed_work(&rport->chg_work, 0);
617 case USB_CHG_STATE_DETECTED:
618 switch (rphy->chg_type) {
619 case POWER_SUPPLY_TYPE_USB:
620 dev_dbg(&rport->phy->dev,
621 "sdp cable is connecetd\n");
622 wake_lock(&rport->wakelock);
623 cable = EXTCON_CHG_USB_SDP;
624 rockchip_usb2phy_power_on(rport->phy);
625 rport->state = OTG_STATE_B_PERIPHERAL;
626 rport->perip_connected = true;
629 case POWER_SUPPLY_TYPE_USB_DCP:
630 dev_dbg(&rport->phy->dev,
631 "dcp cable is connecetd\n");
632 cable = EXTCON_CHG_USB_DCP;
633 rockchip_usb2phy_power_off(rport->phy);
636 case POWER_SUPPLY_TYPE_USB_CDP:
637 dev_dbg(&rport->phy->dev,
638 "cdp cable is connecetd\n");
639 wake_lock(&rport->wakelock);
640 cable = EXTCON_CHG_USB_CDP;
641 rockchip_usb2phy_power_on(rport->phy);
642 rport->state = OTG_STATE_B_PERIPHERAL;
643 rport->perip_connected = true;
646 case POWER_SUPPLY_TYPE_USB_FLOATING:
647 dev_dbg(&rport->phy->dev,
648 "floating cable is connecetd\n");
649 cable = EXTCON_CHG_USB_SLOW;
650 rockchip_usb2phy_power_off(rport->phy);
661 rphy->chg_state = USB_CHG_STATE_UNDEFINED;
662 rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
665 case OTG_STATE_B_PERIPHERAL:
666 if (!rport->vbus_attached) {
667 dev_dbg(&rport->phy->dev, "usb disconnect\n");
668 rphy->chg_state = USB_CHG_STATE_UNDEFINED;
669 rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
670 rport->state = OTG_STATE_B_IDLE;
671 rport->perip_connected = false;
673 rockchip_usb2phy_power_off(rport->phy);
674 wake_unlock(&rport->wakelock);
679 case OTG_STATE_A_HOST:
680 if (extcon_get_cable_state_(rphy->edev, EXTCON_USB_HOST) == 0) {
681 dev_dbg(&rport->phy->dev, "usb otg host disconnect\n");
682 rport->state = OTG_STATE_B_IDLE;
683 rockchip_usb2phy_power_off(rport->phy);
690 if (extcon_get_state(rphy->edev, cable) != rport->vbus_attached)
691 extcon_set_cable_state_(rphy->edev,
692 cable, rport->vbus_attached);
694 if (rphy->edev_self &&
695 (extcon_get_state(rphy->edev, EXTCON_USB) !=
696 rport->perip_connected))
697 extcon_set_cable_state_(rphy->edev,
699 rport->perip_connected);
702 schedule_delayed_work(&rport->otg_sm_work, delay);
705 static const char *chg_to_string(enum power_supply_type chg_type)
708 case POWER_SUPPLY_TYPE_USB:
709 return "USB_SDP_CHARGER";
710 case POWER_SUPPLY_TYPE_USB_DCP:
711 return "USB_DCP_CHARGER";
712 case POWER_SUPPLY_TYPE_USB_CDP:
713 return "USB_CDP_CHARGER";
714 case POWER_SUPPLY_TYPE_USB_FLOATING:
715 return "USB_FLOATING_CHARGER";
717 return "INVALID_CHARGER";
721 static void rockchip_chg_enable_dcd(struct rockchip_usb2phy *rphy,
724 property_enable(rphy, &rphy->phy_cfg->chg_det.rdm_pdwn_en, en);
725 property_enable(rphy, &rphy->phy_cfg->chg_det.idp_src_en, en);
728 static void rockchip_chg_enable_primary_det(struct rockchip_usb2phy *rphy,
731 property_enable(rphy, &rphy->phy_cfg->chg_det.vdp_src_en, en);
732 property_enable(rphy, &rphy->phy_cfg->chg_det.idm_sink_en, en);
735 static void rockchip_chg_enable_secondary_det(struct rockchip_usb2phy *rphy,
738 property_enable(rphy, &rphy->phy_cfg->chg_det.vdm_src_en, en);
739 property_enable(rphy, &rphy->phy_cfg->chg_det.idp_sink_en, en);
742 #define CHG_DCD_POLL_TIME (100 * HZ / 1000)
743 #define CHG_DCD_MAX_RETRIES 6
744 #define CHG_PRIMARY_DET_TIME (40 * HZ / 1000)
745 #define CHG_SECONDARY_DET_TIME (40 * HZ / 1000)
746 static void rockchip_chg_detect_work(struct work_struct *work)
748 struct rockchip_usb2phy_port *rport =
749 container_of(work, struct rockchip_usb2phy_port, chg_work.work);
750 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
751 bool is_dcd, tmout, vout;
754 dev_dbg(&rport->phy->dev, "chg detection work state = %d\n",
756 switch (rphy->chg_state) {
757 case USB_CHG_STATE_UNDEFINED:
758 if (!rport->suspended)
759 rockchip_usb2phy_power_off(rport->phy);
760 /* put the controller in non-driving mode */
761 property_enable(rphy, &rphy->phy_cfg->chg_det.opmode, false);
762 /* Start DCD processing stage 1 */
763 rockchip_chg_enable_dcd(rphy, true);
764 rphy->chg_state = USB_CHG_STATE_WAIT_FOR_DCD;
765 rphy->dcd_retries = 0;
766 rphy->primary_retries = 0;
767 delay = CHG_DCD_POLL_TIME;
769 case USB_CHG_STATE_WAIT_FOR_DCD:
770 /* get data contact detection status */
771 is_dcd = property_enabled(rphy, &rphy->phy_cfg->chg_det.dp_det);
772 tmout = ++rphy->dcd_retries == CHG_DCD_MAX_RETRIES;
774 if (is_dcd || tmout) {
776 /* Turn off DCD circuitry */
777 rockchip_chg_enable_dcd(rphy, false);
778 /* Voltage Source on DP, Probe on DM */
779 rockchip_chg_enable_primary_det(rphy, true);
780 delay = CHG_PRIMARY_DET_TIME;
781 rphy->chg_state = USB_CHG_STATE_DCD_DONE;
784 delay = CHG_DCD_POLL_TIME;
787 case USB_CHG_STATE_DCD_DONE:
788 vout = property_enabled(rphy, &rphy->phy_cfg->chg_det.cp_det);
789 rockchip_chg_enable_primary_det(rphy, false);
791 /* Voltage Source on DM, Probe on DP */
792 rockchip_chg_enable_secondary_det(rphy, true);
793 delay = CHG_SECONDARY_DET_TIME;
794 rphy->chg_state = USB_CHG_STATE_PRIMARY_DONE;
797 /* floating charger found */
798 rphy->chg_type = POWER_SUPPLY_TYPE_USB_FLOATING;
799 rphy->chg_state = USB_CHG_STATE_DETECTED;
802 if (rphy->primary_retries < 2) {
803 /* Turn off DCD circuitry */
804 rockchip_chg_enable_dcd(rphy, false);
805 /* Voltage Source on DP, Probe on DM */
806 rockchip_chg_enable_primary_det(rphy,
808 delay = CHG_PRIMARY_DET_TIME;
810 USB_CHG_STATE_DCD_DONE;
811 rphy->primary_retries++;
812 /* break USB_CHG_STATE_DCD_DONE */
815 rphy->chg_type = POWER_SUPPLY_TYPE_USB;
816 rphy->chg_state = USB_CHG_STATE_DETECTED;
821 case USB_CHG_STATE_PRIMARY_DONE:
822 vout = property_enabled(rphy, &rphy->phy_cfg->chg_det.dcp_det);
823 /* Turn off voltage source */
824 rockchip_chg_enable_secondary_det(rphy, false);
826 rphy->chg_type = POWER_SUPPLY_TYPE_USB_DCP;
828 rphy->chg_type = POWER_SUPPLY_TYPE_USB_CDP;
830 case USB_CHG_STATE_SECONDARY_DONE:
831 rphy->chg_state = USB_CHG_STATE_DETECTED;
834 case USB_CHG_STATE_DETECTED:
835 /* put the controller in normal mode */
836 property_enable(rphy, &rphy->phy_cfg->chg_det.opmode, true);
837 rockchip_usb2phy_otg_sm_work(&rport->otg_sm_work.work);
838 dev_info(&rport->phy->dev, "charger = %s\n",
839 chg_to_string(rphy->chg_type));
845 schedule_delayed_work(&rport->chg_work, delay);
849 * The function manage host-phy port state and suspend/resume phy port
852 * we rely on utmi_linestate and utmi_hostdisconnect to identify whether
853 * devices is disconnect or not. Besides, we do not need care it is FS/LS
854 * disconnected or HS disconnected, actually, we just only need get the
855 * device is disconnected at last through rearm the delayed work,
856 * to suspend the phy port in _PHY_STATE_DISCONNECT_ case.
858 * NOTE: It may invoke *phy_powr_off or *phy_power_on which will invoke
859 * some clk related APIs, so do not invoke it from interrupt context directly.
861 static void rockchip_usb2phy_sm_work(struct work_struct *work)
863 struct rockchip_usb2phy_port *rport =
864 container_of(work, struct rockchip_usb2phy_port, sm_work.work);
865 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
866 unsigned int sh = rport->port_cfg->utmi_hstdet.bitend -
867 rport->port_cfg->utmi_hstdet.bitstart + 1;
868 unsigned int ul, uhd, state;
869 unsigned int ul_mask, uhd_mask;
872 mutex_lock(&rport->mutex);
874 ret = regmap_read(rphy->grf, rport->port_cfg->utmi_ls.offset, &ul);
878 ret = regmap_read(rphy->grf, rport->port_cfg->utmi_hstdet.offset,
883 uhd_mask = GENMASK(rport->port_cfg->utmi_hstdet.bitend,
884 rport->port_cfg->utmi_hstdet.bitstart);
885 ul_mask = GENMASK(rport->port_cfg->utmi_ls.bitend,
886 rport->port_cfg->utmi_ls.bitstart);
888 /* stitch on utmi_ls and utmi_hstdet as phy state */
889 state = ((uhd & uhd_mask) >> rport->port_cfg->utmi_hstdet.bitstart) |
890 (((ul & ul_mask) >> rport->port_cfg->utmi_ls.bitstart) << sh);
893 case PHY_STATE_HS_ONLINE:
894 dev_dbg(&rport->phy->dev, "HS online\n");
896 case PHY_STATE_FS_LS_ONLINE:
898 * For FS/LS device, the online state share with connect state
899 * from utmi_ls and utmi_hstdet register, so we distinguish
900 * them via suspended flag.
902 * Plus, there are two cases, one is D- Line pull-up, and D+
903 * line pull-down, the state is 4; another is D+ line pull-up,
904 * and D- line pull-down, the state is 2.
906 if (!rport->suspended) {
907 /* D- line pull-up, D+ line pull-down */
908 dev_dbg(&rport->phy->dev, "FS/LS online\n");
912 case PHY_STATE_CONNECT:
913 if (rport->suspended) {
914 dev_dbg(&rport->phy->dev, "Connected\n");
915 rockchip_usb2phy_power_on(rport->phy);
916 rport->suspended = false;
918 /* D+ line pull-up, D- line pull-down */
919 dev_dbg(&rport->phy->dev, "FS/LS online\n");
922 case PHY_STATE_DISCONNECT:
923 if (!rport->suspended) {
924 dev_dbg(&rport->phy->dev, "Disconnected\n");
925 rockchip_usb2phy_power_off(rport->phy);
926 rport->suspended = true;
930 * activate the linestate detection to get the next device
933 property_enable(rphy, &rport->port_cfg->ls_det_clr, true);
934 property_enable(rphy, &rport->port_cfg->ls_det_en, true);
937 * we don't need to rearm the delayed work when the phy port
940 mutex_unlock(&rport->mutex);
943 dev_dbg(&rport->phy->dev, "unknown phy state\n");
948 mutex_unlock(&rport->mutex);
949 schedule_delayed_work(&rport->sm_work, SCHEDULE_DELAY);
952 static irqreturn_t rockchip_usb2phy_linestate_irq(int irq, void *data)
954 struct rockchip_usb2phy_port *rport = data;
955 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
957 if (!property_enabled(rphy, &rport->port_cfg->ls_det_st))
960 mutex_lock(&rport->mutex);
962 /* disable linestate detect irq and clear its status */
963 property_enable(rphy, &rport->port_cfg->ls_det_en, false);
964 property_enable(rphy, &rport->port_cfg->ls_det_clr, true);
966 mutex_unlock(&rport->mutex);
969 * In this case for host phy port, a new device is plugged in,
970 * meanwhile, if the phy port is suspended, we need rearm the work to
971 * resume it and mange its states; otherwise, we do nothing about that.
973 if (rport->suspended && rport->port_id == USB2PHY_PORT_HOST)
974 rockchip_usb2phy_sm_work(&rport->sm_work.work);
979 static irqreturn_t rockchip_usb2phy_bvalid_irq(int irq, void *data)
981 struct rockchip_usb2phy_port *rport = data;
982 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
984 if (!property_enabled(rphy, &rport->port_cfg->bvalid_det_st))
987 mutex_lock(&rport->mutex);
989 /* clear bvalid detect irq pending status */
990 property_enable(rphy, &rport->port_cfg->bvalid_det_clr, true);
992 mutex_unlock(&rport->mutex);
994 rockchip_usb2phy_otg_sm_work(&rport->otg_sm_work.work);
999 static irqreturn_t rockchip_usb2phy_id_irq(int irq, void *data)
1001 struct rockchip_usb2phy_port *rport = data;
1002 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
1004 if (!property_enabled(rphy, &rport->port_cfg->idfall_det_st) &&
1005 !property_enabled(rphy, &rport->port_cfg->idrise_det_st))
1008 mutex_lock(&rport->mutex);
1010 /* clear id fall or rise detect irq pending status */
1011 if (property_enabled(rphy, &rport->port_cfg->idfall_det_st)) {
1012 property_enable(rphy, &rport->port_cfg->idfall_det_clr,
1014 extcon_set_state(rphy->edev, EXTCON_USB_HOST, true);
1015 extcon_set_state(rphy->edev, EXTCON_USB_VBUS_EN, true);
1016 } else if (property_enabled(rphy, &rport->port_cfg->idrise_det_st)) {
1017 property_enable(rphy, &rport->port_cfg->idrise_det_clr,
1019 extcon_set_state(rphy->edev, EXTCON_USB_HOST, false);
1020 extcon_set_state(rphy->edev, EXTCON_USB_VBUS_EN, false);
1023 extcon_sync(rphy->edev, EXTCON_USB_HOST);
1024 extcon_sync(rphy->edev, EXTCON_USB_VBUS_EN);
1026 mutex_unlock(&rport->mutex);
1031 static int rockchip_usb2phy_host_port_init(struct rockchip_usb2phy *rphy,
1032 struct rockchip_usb2phy_port *rport,
1033 struct device_node *child_np)
1037 rport->port_id = USB2PHY_PORT_HOST;
1038 rport->port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_HOST];
1039 rport->suspended = true;
1041 mutex_init(&rport->mutex);
1042 INIT_DELAYED_WORK(&rport->sm_work, rockchip_usb2phy_sm_work);
1044 rport->ls_irq = of_irq_get_byname(child_np, "linestate");
1045 if (rport->ls_irq < 0) {
1046 dev_err(rphy->dev, "no linestate irq provided\n");
1047 return rport->ls_irq;
1050 ret = devm_request_threaded_irq(rphy->dev, rport->ls_irq, NULL,
1051 rockchip_usb2phy_linestate_irq,
1053 "rockchip_usb2phy", rport);
1055 dev_err(rphy->dev, "failed to request linestate irq handle\n");
1062 static int rockchip_otg_event(struct notifier_block *nb,
1063 unsigned long event, void *ptr)
1065 struct rockchip_usb2phy_port *rport =
1066 container_of(nb, struct rockchip_usb2phy_port, event_nb);
1068 schedule_delayed_work(&rport->otg_sm_work, OTG_SCHEDULE_DELAY);
1073 static int rockchip_usb2phy_otg_port_init(struct rockchip_usb2phy *rphy,
1074 struct rockchip_usb2phy_port *rport,
1075 struct device_node *child_np)
1080 rport->port_id = USB2PHY_PORT_OTG;
1081 rport->port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG];
1082 rport->state = OTG_STATE_UNDEFINED;
1085 * set suspended flag to true, but actually don't
1086 * put phy in suspend mode, it aims to enable usb
1087 * phy and clock in power_on() called by usb controller
1088 * driver during probe.
1090 rport->suspended = true;
1091 rport->vbus_attached = false;
1092 rport->perip_connected = false;
1094 mutex_init(&rport->mutex);
1096 rport->mode = of_usb_get_dr_mode_by_phy(child_np, -1);
1097 if (rport->mode == USB_DR_MODE_HOST)
1100 wake_lock_init(&rport->wakelock, WAKE_LOCK_SUSPEND, "rockchip_otg");
1101 INIT_DELAYED_WORK(&rport->chg_work, rockchip_chg_detect_work);
1102 INIT_DELAYED_WORK(&rport->otg_sm_work, rockchip_usb2phy_otg_sm_work);
1104 rport->utmi_avalid =
1105 of_property_read_bool(child_np, "rockchip,utmi-avalid");
1107 rport->bvalid_irq = of_irq_get_byname(child_np, "otg-bvalid");
1108 if (rport->bvalid_irq < 0) {
1109 dev_err(rphy->dev, "no vbus valid irq provided\n");
1110 return rport->bvalid_irq;
1113 ret = devm_request_threaded_irq(rphy->dev, rport->bvalid_irq, NULL,
1114 rockchip_usb2phy_bvalid_irq,
1116 "rockchip_usb2phy_bvalid", rport);
1118 dev_err(rphy->dev, "failed to request otg-bvalid irq handle\n");
1122 if (rphy->edev_self) {
1123 rport->id_irq = of_irq_get_byname(child_np, "otg-id");
1124 if (rport->id_irq < 0) {
1125 dev_err(rphy->dev, "no otg id irq provided\n");
1126 return rport->id_irq;
1129 ret = devm_request_threaded_irq(rphy->dev, rport->id_irq, NULL,
1130 rockchip_usb2phy_id_irq,
1132 "rockchip_usb2phy_id", rport);
1134 dev_err(rphy->dev, "failed to request otg-id irq handle\n");
1138 iddig = property_enabled(rphy, &rport->port_cfg->utmi_iddig);
1140 extcon_set_state(rphy->edev, EXTCON_USB, false);
1141 extcon_set_state(rphy->edev, EXTCON_USB_HOST, true);
1142 extcon_set_state(rphy->edev, EXTCON_USB_VBUS_EN, true);
1144 extcon_set_state(rphy->edev, EXTCON_USB_HOST, false);
1145 extcon_set_state(rphy->edev, EXTCON_USB_VBUS_EN, false);
1149 if (!IS_ERR(rphy->edev)) {
1150 rport->event_nb.notifier_call = rockchip_otg_event;
1152 ret = extcon_register_notifier(rphy->edev, EXTCON_USB_HOST,
1155 dev_err(rphy->dev, "register USB HOST notifier failed\n");
1163 static int rockchip_usb2phy_probe(struct platform_device *pdev)
1165 struct device *dev = &pdev->dev;
1166 struct device_node *np = dev->of_node;
1167 struct device_node *child_np;
1168 struct phy_provider *provider;
1169 struct rockchip_usb2phy *rphy;
1170 const struct rockchip_usb2phy_cfg *phy_cfgs;
1171 const struct of_device_id *match;
1175 rphy = devm_kzalloc(dev, sizeof(*rphy), GFP_KERNEL);
1179 match = of_match_device(dev->driver->of_match_table, dev);
1180 if (!match || !match->data) {
1181 dev_err(dev, "phy configs are not assigned!\n");
1185 if (!dev->parent || !dev->parent->of_node)
1188 rphy->grf = syscon_node_to_regmap(dev->parent->of_node);
1189 if (IS_ERR(rphy->grf))
1190 return PTR_ERR(rphy->grf);
1192 if (of_property_read_u32(np, "reg", ®)) {
1193 dev_err(dev, "the reg property is not assigned in %s node\n",
1199 phy_cfgs = match->data;
1200 rphy->chg_state = USB_CHG_STATE_UNDEFINED;
1201 rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
1202 rphy->edev_self = false;
1203 platform_set_drvdata(pdev, rphy);
1205 ret = rockchip_usb2phy_extcon_register(rphy);
1209 /* find out a proper config which can be matched with dt. */
1211 while (phy_cfgs[index].reg) {
1212 if (phy_cfgs[index].reg == reg) {
1213 rphy->phy_cfg = &phy_cfgs[index];
1220 if (!rphy->phy_cfg) {
1221 dev_err(dev, "no phy-config can be matched with %s node\n",
1226 rphy->clk = of_clk_get_by_name(np, "phyclk");
1227 if (!IS_ERR(rphy->clk)) {
1228 clk_prepare_enable(rphy->clk);
1230 dev_info(&pdev->dev, "no phyclk specified\n");
1234 ret = rockchip_usb2phy_clk480m_register(rphy);
1236 dev_err(dev, "failed to register 480m output clock\n");
1240 if (rphy->phy_cfg->phy_tuning) {
1241 ret = rphy->phy_cfg->phy_tuning(rphy);
1247 for_each_available_child_of_node(np, child_np) {
1248 struct rockchip_usb2phy_port *rport = &rphy->ports[index];
1251 /* This driver aims to support both otg-port and host-port */
1252 if (of_node_cmp(child_np->name, "host-port") &&
1253 of_node_cmp(child_np->name, "otg-port"))
1256 phy = devm_phy_create(dev, child_np, &rockchip_usb2phy_ops);
1258 dev_err(dev, "failed to create phy\n");
1264 phy_set_drvdata(rport->phy, rport);
1266 /* initialize otg/host port separately */
1267 if (!of_node_cmp(child_np->name, "host-port")) {
1268 ret = rockchip_usb2phy_host_port_init(rphy, rport,
1273 ret = rockchip_usb2phy_otg_port_init(rphy, rport,
1280 /* to prevent out of boundary */
1281 if (++index >= rphy->phy_cfg->num_ports)
1285 provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
1286 return PTR_ERR_OR_ZERO(provider);
1289 of_node_put(child_np);
1292 clk_disable_unprepare(rphy->clk);
1298 static int rk3366_usb2phy_tuning(struct rockchip_usb2phy *rphy)
1300 unsigned int open_pre_emphasize = 0xffff851f;
1301 unsigned int eye_height_tuning = 0xffff68c8;
1302 unsigned int compensation_tuning = 0xffff026e;
1305 /* open HS pre-emphasize to expand HS slew rate for each port. */
1306 ret |= regmap_write(rphy->grf, 0x0780, open_pre_emphasize);
1307 ret |= regmap_write(rphy->grf, 0x079c, eye_height_tuning);
1308 ret |= regmap_write(rphy->grf, 0x07b0, open_pre_emphasize);
1309 ret |= regmap_write(rphy->grf, 0x07cc, eye_height_tuning);
1311 /* compensate default tuning reference relate to ODT and etc. */
1312 ret |= regmap_write(rphy->grf, 0x078c, compensation_tuning);
1317 static const struct rockchip_usb2phy_cfg rk3366_phy_cfgs[] = {
1321 .phy_tuning = rk3366_usb2phy_tuning,
1322 .clkout_ctl = { 0x0724, 15, 15, 1, 0 },
1324 [USB2PHY_PORT_HOST] = {
1325 .phy_sus = { 0x0728, 15, 0, 0, 0x1d1 },
1326 .ls_det_en = { 0x0680, 4, 4, 0, 1 },
1327 .ls_det_st = { 0x0690, 4, 4, 0, 1 },
1328 .ls_det_clr = { 0x06a0, 4, 4, 0, 1 },
1329 .utmi_ls = { 0x049c, 14, 13, 0, 1 },
1330 .utmi_hstdet = { 0x049c, 12, 12, 0, 1 }
1337 static const struct rockchip_usb2phy_cfg rk3399_phy_cfgs[] = {
1341 .clkout_ctl = { 0xe450, 4, 4, 1, 0 },
1343 [USB2PHY_PORT_OTG] = {
1344 .phy_sus = { 0xe454, 1, 0, 2, 1 },
1345 .bvalid_det_en = { 0xe3c0, 3, 3, 0, 1 },
1346 .bvalid_det_st = { 0xe3e0, 3, 3, 0, 1 },
1347 .bvalid_det_clr = { 0xe3d0, 3, 3, 0, 1 },
1348 .idfall_det_en = { 0xe3c0, 5, 5, 0, 1 },
1349 .idfall_det_st = { 0xe3e0, 5, 5, 0, 1 },
1350 .idfall_det_clr = { 0xe3d0, 5, 5, 0, 1 },
1351 .idrise_det_en = { 0xe3c0, 4, 4, 0, 1 },
1352 .idrise_det_st = { 0xe3e0, 4, 4, 0, 1 },
1353 .idrise_det_clr = { 0xe3d0, 4, 4, 0, 1 },
1354 .utmi_avalid = { 0xe2ac, 7, 7, 0, 1 },
1355 .utmi_bvalid = { 0xe2ac, 12, 12, 0, 1 },
1356 .utmi_iddig = { 0xe2ac, 8, 8, 0, 1 },
1358 [USB2PHY_PORT_HOST] = {
1359 .phy_sus = { 0xe458, 1, 0, 0x2, 0x1 },
1360 .ls_det_en = { 0xe3c0, 6, 6, 0, 1 },
1361 .ls_det_st = { 0xe3e0, 6, 6, 0, 1 },
1362 .ls_det_clr = { 0xe3d0, 6, 6, 0, 1 },
1363 .utmi_ls = { 0xe2ac, 22, 21, 0, 1 },
1364 .utmi_hstdet = { 0xe2ac, 23, 23, 0, 1 }
1368 .opmode = { 0xe454, 3, 0, 5, 1 },
1369 .cp_det = { 0xe2ac, 2, 2, 0, 1 },
1370 .dcp_det = { 0xe2ac, 1, 1, 0, 1 },
1371 .dp_det = { 0xe2ac, 0, 0, 0, 1 },
1372 .idm_sink_en = { 0xe450, 8, 8, 0, 1 },
1373 .idp_sink_en = { 0xe450, 7, 7, 0, 1 },
1374 .idp_src_en = { 0xe450, 9, 9, 0, 1 },
1375 .rdm_pdwn_en = { 0xe450, 10, 10, 0, 1 },
1376 .vdm_src_en = { 0xe450, 12, 12, 0, 1 },
1377 .vdp_src_en = { 0xe450, 11, 11, 0, 1 },
1383 .clkout_ctl = { 0xe460, 4, 4, 1, 0 },
1385 [USB2PHY_PORT_OTG] = {
1386 .phy_sus = { 0xe464, 1, 0, 2, 1 },
1387 .bvalid_det_en = { 0xe3c0, 8, 8, 0, 1 },
1388 .bvalid_det_st = { 0xe3e0, 8, 8, 0, 1 },
1389 .bvalid_det_clr = { 0xe3d0, 8, 8, 0, 1 },
1390 .idfall_det_en = { 0xe3c0, 10, 10, 0, 1 },
1391 .idfall_det_st = { 0xe3e0, 10, 10, 0, 1 },
1392 .idfall_det_clr = { 0xe3d0, 10, 10, 0, 1 },
1393 .idrise_det_en = { 0xe3c0, 9, 9, 0, 1 },
1394 .idrise_det_st = { 0xe3e0, 9, 9, 0, 1 },
1395 .idrise_det_clr = { 0xe3d0, 9, 9, 0, 1 },
1396 .utmi_avalid = { 0xe2ac, 10, 10, 0, 1 },
1397 .utmi_bvalid = { 0xe2ac, 16, 16, 0, 1 },
1398 .utmi_iddig = { 0xe2ac, 11, 11, 0, 1 },
1400 [USB2PHY_PORT_HOST] = {
1401 .phy_sus = { 0xe468, 1, 0, 0x2, 0x1 },
1402 .ls_det_en = { 0xe3c0, 11, 11, 0, 1 },
1403 .ls_det_st = { 0xe3e0, 11, 11, 0, 1 },
1404 .ls_det_clr = { 0xe3d0, 11, 11, 0, 1 },
1405 .utmi_ls = { 0xe2ac, 26, 25, 0, 1 },
1406 .utmi_hstdet = { 0xe2ac, 27, 27, 0, 1 }
1413 static const struct of_device_id rockchip_usb2phy_dt_match[] = {
1414 { .compatible = "rockchip,rk3366-usb2phy", .data = &rk3366_phy_cfgs },
1415 { .compatible = "rockchip,rk3399-usb2phy", .data = &rk3399_phy_cfgs },
1418 MODULE_DEVICE_TABLE(of, rockchip_usb2phy_dt_match);
1420 static struct platform_driver rockchip_usb2phy_driver = {
1421 .probe = rockchip_usb2phy_probe,
1423 .name = "rockchip-usb2phy",
1424 .of_match_table = rockchip_usb2phy_dt_match,
1427 module_platform_driver(rockchip_usb2phy_driver);
1429 MODULE_AUTHOR("Frank Wang <frank.wang@rock-chips.com>");
1430 MODULE_DESCRIPTION("Rockchip USB2.0 PHY driver");
1431 MODULE_LICENSE("GPL v2");