drivers/phy/phy-rockchip-inno-usb2.c

   1 /*
   2  * Rockchip USB2.0 PHY with Innosilicon IP block driver
   3  *
   4  * Copyright (C) 2016 Fuzhou Rockchip Electronics Co., Ltd
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/clk.h>
  18 #include <linux/clk-provider.h>
  19 #include <linux/delay.h>
  20 #include <linux/extcon.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/io.h>
  23 #include <linux/gpio/consumer.h>
  24 #include <linux/jiffies.h>
  25 #include <linux/kernel.h>
  26 #include <linux/module.h>
  27 #include <linux/mutex.h>
  28 #include <linux/of.h>
  29 #include <linux/of_address.h>
  30 #include <linux/of_irq.h>
  31 #include <linux/of_platform.h>
  32 #include <linux/phy/phy.h>
  33 #include <linux/platform_device.h>
  34 #include <linux/power_supply.h>
  35 #include <linux/regmap.h>
  36 #include <linux/mfd/syscon.h>
  37 #include <linux/usb/otg.h>
  38 #include <linux/wakelock.h>
  39
  40 #define BIT_WRITEABLE_SHIFT     16
  41 #define SCHEDULE_DELAY          (60 * HZ)
  42 #define OTG_SCHEDULE_DELAY      (2 * HZ)
  43
  44 struct rockchip_usb2phy;
  45
  46 enum rockchip_usb2phy_port_id {
  47         USB2PHY_PORT_OTG,
  48         USB2PHY_PORT_HOST,
  49         USB2PHY_NUM_PORTS,
  50 };
  51
  52 enum rockchip_usb2phy_host_state {
  53         PHY_STATE_HS_ONLINE     = 0,
  54         PHY_STATE_DISCONNECT    = 1,
  55         PHY_STATE_HS_CONNECT    = 2,
  56         PHY_STATE_FS_CONNECT    = 4,
  57 };
  58
  59 /**
  60  * Different states involved in USB charger detection.
  61  * USB_CHG_STATE_UNDEFINED      USB charger is not connected or detection
  62  *                              process is not yet started.
  63  * USB_CHG_STATE_WAIT_FOR_DCD   Waiting for Data pins contact.
  64  * USB_CHG_STATE_DCD_DONE       Data pin contact is detected.
  65  * USB_CHG_STATE_PRIMARY_DONE   Primary detection is completed (Detects
  66  *                              between SDP and DCP/CDP).
  67  * USB_CHG_STATE_SECONDARY_DONE Secondary detection is completed (Detects
  68  *                              between DCP and CDP).
  69  * USB_CHG_STATE_DETECTED       USB charger type is determined.
  70  */
  71 enum usb_chg_state {
  72         USB_CHG_STATE_UNDEFINED = 0,
  73         USB_CHG_STATE_WAIT_FOR_DCD,
  74         USB_CHG_STATE_DCD_DONE,
  75         USB_CHG_STATE_PRIMARY_DONE,
  76         USB_CHG_STATE_SECONDARY_DONE,
  77         USB_CHG_STATE_DETECTED,
  78 };
  79
  80 static const unsigned int rockchip_usb2phy_extcon_cable[] = {
  81         EXTCON_USB,
  82         EXTCON_USB_HOST,
  83         EXTCON_CHG_USB_SDP,
  84         EXTCON_CHG_USB_CDP,
  85         EXTCON_CHG_USB_DCP,
  86         EXTCON_CHG_USB_SLOW,
  87         EXTCON_NONE,
  88 };
  89
  90 struct usb2phy_reg {
  91         unsigned int    offset;
  92         unsigned int    bitend;
  93         unsigned int    bitstart;
  94         unsigned int    disable;
  95         unsigned int    enable;
  96 };
  97
  98 /**
  99  * struct rockchip_chg_det_reg: usb charger detect registers
 100  * @cp_det: charging port detected successfully.
 101  * @dcp_det: dedicated charging port detected successfully.
 102  * @dp_det: assert data pin connect successfully.
 103  * @idm_sink_en: open dm sink curren.
 104  * @idp_sink_en: open dp sink current.
 105  * @idp_src_en: open dm source current.
 106  * @rdm_pdwn_en: open dm pull down resistor.
 107  * @vdm_src_en: open dm voltage source.
 108  * @vdp_src_en: open dp voltage source.
 109  * @opmode: utmi operational mode.
 110  */
 111 struct rockchip_chg_det_reg {
 112         struct usb2phy_reg      cp_det;
 113         struct usb2phy_reg      dcp_det;
 114         struct usb2phy_reg      dp_det;
 115         struct usb2phy_reg      idm_sink_en;
 116         struct usb2phy_reg      idp_sink_en;
 117         struct usb2phy_reg      idp_src_en;
 118         struct usb2phy_reg      rdm_pdwn_en;
 119         struct usb2phy_reg      vdm_src_en;
 120         struct usb2phy_reg      vdp_src_en;
 121         struct usb2phy_reg      opmode;
 122 };
 123
 124 /**
 125  * struct rockchip_usb2phy_port_cfg: usb-phy port configuration.
 126  * @phy_sus: phy suspend register.
 127  * @bvalid_det_en: vbus valid rise detection enable register.
 128  * @bvalid_det_st: vbus valid rise detection status register.
 129  * @bvalid_det_clr: vbus valid rise detection clear register.
 130  * @ls_det_en: linestate detection enable register.
 131  * @ls_det_st: linestate detection state register.
 132  * @ls_det_clr: linestate detection clear register.
 133  * @utmi_bvalid: utmi vbus valid status register.
 134  * @utmi_ls: utmi linestate state register.
 135  * @utmi_hstdet: utmi host disconnect register.
 136  */
 137 struct rockchip_usb2phy_port_cfg {
 138         struct usb2phy_reg      phy_sus;
 139         struct usb2phy_reg      bvalid_det_en;
 140         struct usb2phy_reg      bvalid_det_st;
 141         struct usb2phy_reg      bvalid_det_clr;
 142         struct usb2phy_reg      ls_det_en;
 143         struct usb2phy_reg      ls_det_st;
 144         struct usb2phy_reg      ls_det_clr;
 145         struct usb2phy_reg      utmi_bvalid;
 146         struct usb2phy_reg      utmi_ls;
 147         struct usb2phy_reg      utmi_hstdet;
 148 };
 149
 150 /**
 151  * struct rockchip_usb2phy_cfg: usb-phy configuration.
 152  * @reg: the address offset of grf for usb-phy config.
 153  * @num_ports: specify how many ports that the phy has.
 154  * @phy_tuning: phy default parameters tunning.
 155  * @clkout_ctl: keep on/turn off output clk of phy.
 156  * @chg_det: charger detection registers.
 157  */
 158 struct rockchip_usb2phy_cfg {
 159         unsigned int    reg;
 160         unsigned int    num_ports;
 161         int (*phy_tuning)(struct rockchip_usb2phy *);
 162         struct usb2phy_reg      clkout_ctl;
 163         const struct rockchip_usb2phy_port_cfg  port_cfgs[USB2PHY_NUM_PORTS];
 164         const struct rockchip_chg_det_reg       chg_det;
 165 };
 166
 167 /**
 168  * struct rockchip_usb2phy_port: usb-phy port data.
 169  * @port_id: flag for otg port or host port.
 170  * @suspended: phy suspended flag.
 171  * @vbus_attached: otg device vbus status.
 172  * @bvalid_irq: IRQ number assigned for vbus valid rise detection.
 173  * @ls_irq: IRQ number assigned for linestate detection.
 174  * @mutex: for register updating in sm_work.
 175  * @chg_work: charge detect work.
 176  * @otg_sm_work: OTG state machine work.
 177  * @sm_work: HOST state machine work.
 178  * @phy_cfg: port register configuration, assigned by driver data.
 179  * @event_nb: hold event notification callback.
 180  * @wakelock: wake lock struct to prevent system suspend
 181  *            when USB is active.
 182  * @state: define OTG enumeration states before device reset.
 183  */
 184 struct rockchip_usb2phy_port {
 185         struct phy      *phy;
 186         unsigned int    port_id;
 187         bool            suspended;
 188         bool            vbus_attached;
 189         int             bvalid_irq;
 190         int             ls_irq;
 191         struct mutex    mutex;
 192         struct          delayed_work chg_work;
 193         struct          delayed_work otg_sm_work;
 194         struct          delayed_work sm_work;
 195         const struct    rockchip_usb2phy_port_cfg *port_cfg;
 196         struct notifier_block   event_nb;
 197         struct wake_lock        wakelock;
 198         enum usb_otg_state      state;
 199 };
 200
 201 /**
 202  * struct rockchip_usb2phy: usb2.0 phy driver data.
 203  * @grf: General Register Files regmap.
 204  * @clk: clock struct of phy input clk.
 205  * @clk480m: clock struct of phy output clk.
 206  * @clk_hw: clock struct of phy output clk management.
 207  * @chg_state: states involved in USB charger detection.
 208  * @chg_type: USB charger types.
 209  * @dcd_retries: The retry count used to track Data contact
 210  *               detection process.
 211  * @edev: extcon device for notification registration
 212  * @phy_cfg: phy register configuration, assigned by driver data.
 213  * @ports: phy port instance.
 214  */
 215 struct rockchip_usb2phy {
 216         struct device   *dev;
 217         struct regmap   *grf;
 218         struct clk      *clk;
 219         struct clk      *clk480m;
 220         struct clk_hw   clk480m_hw;
 221         enum usb_chg_state      chg_state;
 222         enum power_supply_type  chg_type;
 223         u8                      dcd_retries;
 224         struct extcon_dev       *edev;
 225         const struct rockchip_usb2phy_cfg       *phy_cfg;
 226         struct rockchip_usb2phy_port    ports[USB2PHY_NUM_PORTS];
 227 };
 228
 229 static inline int property_enable(struct rockchip_usb2phy *rphy,
 230                                   const struct usb2phy_reg *reg, bool en)
 231 {
 232         unsigned int val, mask, tmp;
 233
 234         tmp = en ? reg->enable : reg->disable;
 235         mask = GENMASK(reg->bitend, reg->bitstart);
 236         val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT);
 237
 238         return regmap_write(rphy->grf, reg->offset, val);
 239 }
 240
 241 static inline bool property_enabled(struct rockchip_usb2phy *rphy,
 242                                     const struct usb2phy_reg *reg)
 243 {
 244         int ret;
 245         unsigned int tmp, orig;
 246         unsigned int mask = GENMASK(reg->bitend, reg->bitstart);
 247
 248         ret = regmap_read(rphy->grf, reg->offset, &orig);
 249         if (ret)
 250                 return false;
 251
 252         tmp = (orig & mask) >> reg->bitstart;
 253         return tmp == reg->enable;
 254 }
 255
 256 static int rockchip_usb2phy_clk480m_enable(struct clk_hw *hw)
 257 {
 258         struct rockchip_usb2phy *rphy =
 259                 container_of(hw, struct rockchip_usb2phy, clk480m_hw);
 260         int ret;
 261
 262         /* turn on 480m clk output if it is off */
 263         if (!property_enabled(rphy, &rphy->phy_cfg->clkout_ctl)) {
 264                 ret = property_enable(rphy, &rphy->phy_cfg->clkout_ctl, true);
 265                 if (ret)
 266                         return ret;
 267
 268                 /* waitting for the clk become stable */
 269                 mdelay(1);
 270         }
 271
 272         return 0;
 273 }
 274
 275 static void rockchip_usb2phy_clk480m_disable(struct clk_hw *hw)
 276 {
 277         struct rockchip_usb2phy *rphy =
 278                 container_of(hw, struct rockchip_usb2phy, clk480m_hw);
 279
 280         /* turn off 480m clk output */
 281         property_enable(rphy, &rphy->phy_cfg->clkout_ctl, false);
 282 }
 283
 284 static int rockchip_usb2phy_clk480m_enabled(struct clk_hw *hw)
 285 {
 286         struct rockchip_usb2phy *rphy =
 287                 container_of(hw, struct rockchip_usb2phy, clk480m_hw);
 288
 289         return property_enabled(rphy, &rphy->phy_cfg->clkout_ctl);
 290 }
 291
 292 static unsigned long
 293 rockchip_usb2phy_clk480m_recalc_rate(struct clk_hw *hw,
 294                                      unsigned long parent_rate)
 295 {
 296         return 480000000;
 297 }
 298
 299 static const struct clk_ops rockchip_usb2phy_clkout_ops = {
 300         .enable = rockchip_usb2phy_clk480m_enable,
 301         .disable = rockchip_usb2phy_clk480m_disable,
 302         .is_enabled = rockchip_usb2phy_clk480m_enabled,
 303         .recalc_rate = rockchip_usb2phy_clk480m_recalc_rate,
 304 };
 305
 306 static void rockchip_usb2phy_clk480m_unregister(void *data)
 307 {
 308         struct rockchip_usb2phy *rphy = data;
 309
 310         of_clk_del_provider(rphy->dev->of_node);
 311         clk_unregister(rphy->clk480m);
 312
 313         if (rphy->clk)
 314                 clk_put(rphy->clk);
 315 }
 316
 317 static int
 318 rockchip_usb2phy_clk480m_register(struct rockchip_usb2phy *rphy)
 319 {
 320         struct device_node *node = rphy->dev->of_node;
 321         struct clk_init_data init;
 322         const char *clk_name;
 323         int ret;
 324
 325         init.flags = 0;
 326         init.name = "clk_usbphy_480m";
 327         init.ops = &rockchip_usb2phy_clkout_ops;
 328
 329         /* optional override of the clockname */
 330         of_property_read_string(node, "clock-output-names", &init.name);
 331
 332         rphy->clk = of_clk_get_by_name(node, "phyclk");
 333         if (IS_ERR(rphy->clk)) {
 334                 rphy->clk = NULL;
 335                 init.parent_names = NULL;
 336                 init.num_parents = 0;
 337         } else {
 338                 clk_name = __clk_get_name(rphy->clk);
 339                 init.parent_names = &clk_name;
 340                 init.num_parents = 1;
 341                 clk_prepare_enable(rphy->clk);
 342         }
 343
 344         rphy->clk480m_hw.init = &init;
 345
 346         /* register the clock */
 347         rphy->clk480m = clk_register(rphy->dev, &rphy->clk480m_hw);
 348         if (IS_ERR(rphy->clk480m)) {
 349                 ret = PTR_ERR(rphy->clk480m);
 350                 goto err_register;
 351         }
 352
 353         ret = of_clk_add_provider(node, of_clk_src_simple_get, rphy->clk480m);
 354         if (ret < 0)
 355                 goto err_clk_provider;
 356
 357         ret = devm_add_action(rphy->dev, rockchip_usb2phy_clk480m_unregister,
 358                               rphy);
 359         if (ret < 0)
 360                 goto err_unreg_action;
 361
 362         return 0;
 363
 364 err_unreg_action:
 365         of_clk_del_provider(node);
 366 err_clk_provider:
 367         clk_unregister(rphy->clk480m);
 368 err_register:
 369         if (rphy->clk)
 370                 clk_put(rphy->clk);
 371         return ret;
 372 }
 373
 374 static int rockchip_usb2phy_extcon_register(struct rockchip_usb2phy *rphy)
 375 {
 376         int ret;
 377         struct device_node *node = rphy->dev->of_node;
 378         struct extcon_dev *edev;
 379
 380         if (of_property_read_bool(node, "extcon")) {
 381                 edev = extcon_get_edev_by_phandle(rphy->dev, 0);
 382                 if (IS_ERR(edev)) {
 383                         if (PTR_ERR(edev) != -EPROBE_DEFER)
 384                                 dev_err(rphy->dev, "Invalid or missing extcon\n");
 385                         return PTR_ERR(edev);
 386                 }
 387         } else {
 388                 /* Initialize extcon device */
 389                 edev = devm_extcon_dev_allocate(rphy->dev,
 390                                                 rockchip_usb2phy_extcon_cable);
 391
 392                 if (IS_ERR(edev))
 393                         return -ENOMEM;
 394
 395                 ret = devm_extcon_dev_register(rphy->dev, edev);
 396                 if (ret) {
 397                         dev_err(rphy->dev, "failed to register extcon device\n");
 398                         return ret;
 399                 }
 400         }
 401
 402         rphy->edev = edev;
 403
 404         return 0;
 405 }
 406
 407 static int rockchip_usb2phy_init(struct phy *phy)
 408 {
 409         struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
 410         struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
 411         int ret;
 412
 413         mutex_lock(&rport->mutex);
 414
 415         if (rport->port_id == USB2PHY_PORT_OTG) {
 416                 /* clear bvalid status and enable bvalid detect irq */
 417                 ret = property_enable(rphy,
 418                                       &rport->port_cfg->bvalid_det_clr, true);
 419                 if (ret) {
 420                         mutex_unlock(&rport->mutex);
 421                         return ret;
 422                 }
 423
 424                 ret = property_enable(rphy,
 425                                       &rport->port_cfg->bvalid_det_en, true);
 426                 if (ret) {
 427                         mutex_unlock(&rport->mutex);
 428                         return ret;
 429                 }
 430
 431                 mutex_unlock(&rport->mutex);
 432                 schedule_delayed_work(&rport->otg_sm_work, OTG_SCHEDULE_DELAY);
 433
 434         } else if (rport->port_id == USB2PHY_PORT_HOST) {
 435                 /* clear linestate and enable linestate detect irq */
 436                 ret = property_enable(rphy, &rport->port_cfg->ls_det_clr, true);
 437                 if (ret) {
 438                         mutex_unlock(&rport->mutex);
 439                         return ret;
 440                 }
 441
 442                 ret = property_enable(rphy, &rport->port_cfg->ls_det_en, true);
 443                 if (ret) {
 444                         mutex_unlock(&rport->mutex);
 445                         return ret;
 446                 }
 447
 448                 mutex_unlock(&rport->mutex);
 449                 schedule_delayed_work(&rport->sm_work, SCHEDULE_DELAY);
 450         }
 451
 452         return 0;
 453 }
 454
 455 static int rockchip_usb2phy_power_on(struct phy *phy)
 456 {
 457         struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
 458         struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
 459         int ret;
 460
 461         dev_dbg(&rport->phy->dev, "port power on\n");
 462
 463         if (!rport->suspended)
 464                 return 0;
 465
 466         ret = clk_prepare_enable(rphy->clk480m);
 467         if (ret)
 468                 return ret;
 469
 470         ret = property_enable(rphy, &rport->port_cfg->phy_sus, false);
 471         if (ret)
 472                 return ret;
 473
 474         rport->suspended = false;
 475
 476         return 0;
 477 }
 478
 479 static int rockchip_usb2phy_power_off(struct phy *phy)
 480 {
 481         struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
 482         struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
 483         int ret;
 484
 485         dev_dbg(&rport->phy->dev, "port power off\n");
 486
 487         if (rport->suspended)
 488                 return 0;
 489
 490         ret = property_enable(rphy, &rport->port_cfg->phy_sus, true);
 491         if (ret)
 492                 return ret;
 493
 494         rport->suspended = true;
 495         clk_disable_unprepare(rphy->clk480m);
 496
 497         return 0;
 498 }
 499
 500 static int rockchip_usb2phy_exit(struct phy *phy)
 501 {
 502         struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
 503
 504         if (rport->port_id == USB2PHY_PORT_OTG) {
 505                 cancel_delayed_work_sync(&rport->chg_work);
 506                 cancel_delayed_work_sync(&rport->otg_sm_work);
 507         } else if (rport->port_id == USB2PHY_PORT_HOST)
 508                 cancel_delayed_work_sync(&rport->sm_work);
 509
 510         return 0;
 511 }
 512
 513 static const struct phy_ops rockchip_usb2phy_ops = {
 514         .init           = rockchip_usb2phy_init,
 515         .exit           = rockchip_usb2phy_exit,
 516         .power_on       = rockchip_usb2phy_power_on,
 517         .power_off      = rockchip_usb2phy_power_off,
 518         .owner          = THIS_MODULE,
 519 };
 520
 521 static void rockchip_usb2phy_otg_sm_work(struct work_struct *work)
 522 {
 523         struct rockchip_usb2phy_port *rport =
 524                 container_of(work, struct rockchip_usb2phy_port,
 525                              otg_sm_work.work);
 526         struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
 527         static unsigned int cable;
 528         unsigned long delay;
 529         bool vbus_attach, sch_work, notify_charger;
 530
 531         vbus_attach = property_enabled(rphy, &rport->port_cfg->utmi_bvalid);
 532         sch_work = false;
 533         notify_charger = false;
 534         delay = OTG_SCHEDULE_DELAY;
 535         dev_dbg(&rport->phy->dev, "%s otg sm work\n",
 536                 usb_otg_state_string(rport->state));
 537
 538         switch (rport->state) {
 539         case OTG_STATE_UNDEFINED:
 540                 rport->state = OTG_STATE_B_IDLE;
 541                 if (!vbus_attach)
 542                         rockchip_usb2phy_power_off(rport->phy);
 543                 /* fall through */
 544         case OTG_STATE_B_IDLE:
 545                 if (extcon_get_cable_state_(rphy->edev, EXTCON_USB_HOST) > 0) {
 546                         dev_dbg(&rport->phy->dev, "usb otg host connect\n");
 547                         rport->state = OTG_STATE_A_HOST;
 548                         rockchip_usb2phy_power_on(rport->phy);
 549                         return;
 550                 } else if (vbus_attach) {
 551                         dev_dbg(&rport->phy->dev, "vbus_attach\n");
 552                         switch (rphy->chg_state) {
 553                         case USB_CHG_STATE_UNDEFINED:
 554                                 schedule_delayed_work(&rport->chg_work, 0);
 555                                 return;
 556                         case USB_CHG_STATE_DETECTED:
 557                                 switch (rphy->chg_type) {
 558                                 case POWER_SUPPLY_TYPE_USB:
 559                                         dev_dbg(&rport->phy->dev,
 560                                                 "sdp cable is connecetd\n");
 561                                         wake_lock(&rport->wakelock);
 562                                         rockchip_usb2phy_power_on(rport->phy);
 563                                         rport->state = OTG_STATE_B_PERIPHERAL;
 564                                         notify_charger = true;
 565                                         sch_work = true;
 566                                         cable = EXTCON_CHG_USB_SDP;
 567                                         break;
 568                                 case POWER_SUPPLY_TYPE_USB_DCP:
 569                                         dev_dbg(&rport->phy->dev,
 570                                                 "dcp cable is connecetd\n");
 571                                         rockchip_usb2phy_power_off(rport->phy);
 572                                         notify_charger = true;
 573                                         sch_work = true;
 574                                         cable = EXTCON_CHG_USB_DCP;
 575                                         break;
 576                                 case POWER_SUPPLY_TYPE_USB_CDP:
 577                                         dev_dbg(&rport->phy->dev,
 578                                                 "cdp cable is connecetd\n");
 579                                         wake_lock(&rport->wakelock);
 580                                         rockchip_usb2phy_power_on(rport->phy);
 581                                         rport->state = OTG_STATE_B_PERIPHERAL;
 582                                         notify_charger = true;
 583                                         sch_work = true;
 584                                         cable = EXTCON_CHG_USB_CDP;
 585                                         break;
 586                                 case POWER_SUPPLY_TYPE_USB_FLOATING:
 587                                         dev_dbg(&rport->phy->dev,
 588                                                 "floating cable is connecetd\n");
 589                                         rockchip_usb2phy_power_off(rport->phy);
 590                                         notify_charger = true;
 591                                         sch_work = true;
 592                                         cable = EXTCON_CHG_USB_SLOW;
 593                                         break;
 594                                 default:
 595                                         break;
 596                                 }
 597                                 break;
 598                         default:
 599                                 break;
 600                         }
 601                 } else {
 602                         notify_charger = true;
 603                         rphy->chg_state = USB_CHG_STATE_UNDEFINED;
 604                         rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
 605                 }
 606
 607                 if (rport->vbus_attached != vbus_attach) {
 608                         rport->vbus_attached = vbus_attach;
 609
 610                         if (notify_charger && rphy->edev)
 611                                 extcon_set_cable_state_(rphy->edev,
 612                                                         cable, vbus_attach);
 613                 }
 614                 break;
 615         case OTG_STATE_B_PERIPHERAL:
 616                 if (!vbus_attach) {
 617                         dev_dbg(&rport->phy->dev, "usb disconnect\n");
 618                         rphy->chg_state = USB_CHG_STATE_UNDEFINED;
 619                         rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
 620                         rport->state = OTG_STATE_B_IDLE;
 621                         delay = 0;
 622                         rockchip_usb2phy_power_off(rport->phy);
 623                         wake_unlock(&rport->wakelock);
 624                 }
 625                 sch_work = true;
 626                 break;
 627         case OTG_STATE_A_HOST:
 628                 if (extcon_get_cable_state_(rphy->edev, EXTCON_USB_HOST) == 0) {
 629                         dev_dbg(&rport->phy->dev, "usb otg host disconnect\n");
 630                         rport->state = OTG_STATE_B_IDLE;
 631                         rockchip_usb2phy_power_off(rport->phy);
 632                 }
 633                 break;
 634         default:
 635                 break;
 636         }
 637
 638         if (sch_work)
 639                 schedule_delayed_work(&rport->otg_sm_work, delay);
 640 }
 641
 642 static const char *chg_to_string(enum power_supply_type chg_type)
 643 {
 644         switch (chg_type) {
 645         case POWER_SUPPLY_TYPE_USB:
 646                 return "USB_SDP_CHARGER";
 647         case POWER_SUPPLY_TYPE_USB_DCP:
 648                 return "USB_DCP_CHARGER";
 649         case POWER_SUPPLY_TYPE_USB_CDP:
 650                 return "USB_CDP_CHARGER";
 651         case POWER_SUPPLY_TYPE_USB_FLOATING:
 652                 return "USB_FLOATING_CHARGER";
 653         default:
 654                 return "INVALID_CHARGER";
 655         }
 656 }
 657
 658 static void rockchip_chg_enable_dcd(struct rockchip_usb2phy *rphy,
 659                                     bool en)
 660 {
 661         property_enable(rphy, &rphy->phy_cfg->chg_det.rdm_pdwn_en, en);
 662         property_enable(rphy, &rphy->phy_cfg->chg_det.idp_src_en, en);
 663 }
 664
 665 static void rockchip_chg_enable_primary_det(struct rockchip_usb2phy *rphy,
 666                                             bool en)
 667 {
 668         property_enable(rphy, &rphy->phy_cfg->chg_det.vdp_src_en, en);
 669         property_enable(rphy, &rphy->phy_cfg->chg_det.idm_sink_en, en);
 670 }
 671
 672 static void rockchip_chg_enable_secondary_det(struct rockchip_usb2phy *rphy,
 673                                               bool en)
 674 {
 675         property_enable(rphy, &rphy->phy_cfg->chg_det.vdm_src_en, en);
 676         property_enable(rphy, &rphy->phy_cfg->chg_det.idp_sink_en, en);
 677 }
 678
 679 #define CHG_DCD_POLL_TIME       (100 * HZ / 1000)
 680 #define CHG_DCD_MAX_RETRIES     6
 681 #define CHG_PRIMARY_DET_TIME    (40 * HZ / 1000)
 682 #define CHG_SECONDARY_DET_TIME  (40 * HZ / 1000)
 683 static void rockchip_chg_detect_work(struct work_struct *work)
 684 {
 685         struct rockchip_usb2phy_port *rport =
 686                 container_of(work, struct rockchip_usb2phy_port, chg_work.work);
 687         struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
 688         bool is_dcd, tmout, vout;
 689         unsigned long delay;
 690
 691         dev_dbg(&rport->phy->dev, "chg detection work state = %d\n",
 692                 rphy->chg_state);
 693         switch (rphy->chg_state) {
 694         case USB_CHG_STATE_UNDEFINED:
 695                 if (!rport->suspended)
 696                         rockchip_usb2phy_power_off(rport->phy);
 697                 /* put the controller in non-driving mode */
 698                 property_enable(rphy, &rphy->phy_cfg->chg_det.opmode, false);
 699                 /* Start DCD processing stage 1 */
 700                 rockchip_chg_enable_dcd(rphy, true);
 701                 rphy->chg_state = USB_CHG_STATE_WAIT_FOR_DCD;
 702                 rphy->dcd_retries = 0;
 703                 delay = CHG_DCD_POLL_TIME;
 704                 break;
 705         case USB_CHG_STATE_WAIT_FOR_DCD:
 706                 /* get data contact detection status */
 707                 is_dcd = property_enabled(rphy, &rphy->phy_cfg->chg_det.dp_det);
 708                 tmout = ++rphy->dcd_retries == CHG_DCD_MAX_RETRIES;
 709                 /* stage 2 */
 710                 if (is_dcd || tmout) {
 711                         /* stage 4 */
 712                         /* Turn off DCD circuitry */
 713                         rockchip_chg_enable_dcd(rphy, false);
 714                         /* Voltage Source on DP, Probe on DM */
 715                         rockchip_chg_enable_primary_det(rphy, true);
 716                         delay = CHG_PRIMARY_DET_TIME;
 717                         rphy->chg_state = USB_CHG_STATE_DCD_DONE;
 718                 } else {
 719                         /* stage 3 */
 720                         delay = CHG_DCD_POLL_TIME;
 721                 }
 722                 break;
 723         case USB_CHG_STATE_DCD_DONE:
 724                 vout = property_enabled(rphy, &rphy->phy_cfg->chg_det.cp_det);
 725                 rockchip_chg_enable_primary_det(rphy, false);
 726                 if (vout) {
 727                         /* Voltage Source on DM, Probe on DP  */
 728                         rockchip_chg_enable_secondary_det(rphy, true);
 729                         delay = CHG_SECONDARY_DET_TIME;
 730                         rphy->chg_state = USB_CHG_STATE_PRIMARY_DONE;
 731                 } else {
 732                         if (tmout) {
 733                                 /* floating charger found */
 734                                 rphy->chg_type = POWER_SUPPLY_TYPE_USB_FLOATING;
 735                                 rphy->chg_state = USB_CHG_STATE_DETECTED;
 736                                 delay = 0;
 737                         } else {
 738                                 rphy->chg_type = POWER_SUPPLY_TYPE_USB;
 739                                 rphy->chg_state = USB_CHG_STATE_DETECTED;
 740                                 delay = 0;
 741                         }
 742                 }
 743                 break;
 744         case USB_CHG_STATE_PRIMARY_DONE:
 745                 vout = property_enabled(rphy, &rphy->phy_cfg->chg_det.dcp_det);
 746                 /* Turn off voltage source */
 747                 rockchip_chg_enable_secondary_det(rphy, false);
 748                 if (vout)
 749                         rphy->chg_type = POWER_SUPPLY_TYPE_USB_DCP;
 750                 else
 751                         rphy->chg_type = POWER_SUPPLY_TYPE_USB_CDP;
 752                 /* fall through */
 753         case USB_CHG_STATE_SECONDARY_DONE:
 754                 rphy->chg_state = USB_CHG_STATE_DETECTED;
 755                 delay = 0;
 756                 /* fall through */
 757         case USB_CHG_STATE_DETECTED:
 758                 /* put the controller in normal mode */
 759                 property_enable(rphy, &rphy->phy_cfg->chg_det.opmode, true);
 760                 rockchip_usb2phy_otg_sm_work(&rport->otg_sm_work.work);
 761                 dev_info(&rport->phy->dev, "charger = %s\n",
 762                          chg_to_string(rphy->chg_type));
 763                 return;
 764         default:
 765                 return;
 766         }
 767
 768         schedule_delayed_work(&rport->chg_work, delay);
 769 }
 770
 771 /*
 772  * The function manage host-phy port state and suspend/resume phy port
 773  * to save power.
 774  *
 775  * we rely on utmi_linestate and utmi_hostdisconnect to identify whether
 776  * FS/HS is disconnect or not. Besides, we do not need care it is FS
 777  * disconnected or HS disconnected, actually, we just only need get the
 778  * device is disconnected at last through rearm the delayed work,
 779  * to suspend the phy port in _PHY_STATE_DISCONNECT_ case.
 780  *
 781  * NOTE: It may invoke *phy_powr_off or *phy_power_on which will invoke
 782  * some clk related APIs, so do not invoke it from interrupt context directly.
 783  */
 784 static void rockchip_usb2phy_sm_work(struct work_struct *work)
 785 {
 786         struct rockchip_usb2phy_port *rport =
 787                 container_of(work, struct rockchip_usb2phy_port, sm_work.work);
 788         struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
 789         unsigned int sh = rport->port_cfg->utmi_hstdet.bitend -
 790                           rport->port_cfg->utmi_hstdet.bitstart + 1;
 791         unsigned int ul, uhd, state;
 792         unsigned int ul_mask, uhd_mask;
 793         int ret;
 794
 795         mutex_lock(&rport->mutex);
 796
 797         ret = regmap_read(rphy->grf, rport->port_cfg->utmi_ls.offset, &ul);
 798         if (ret < 0)
 799                 goto next_schedule;
 800
 801         ret = regmap_read(rphy->grf, rport->port_cfg->utmi_hstdet.offset,
 802                           &uhd);
 803         if (ret < 0)
 804                 goto next_schedule;
 805
 806         uhd_mask = GENMASK(rport->port_cfg->utmi_hstdet.bitend,
 807                            rport->port_cfg->utmi_hstdet.bitstart);
 808         ul_mask = GENMASK(rport->port_cfg->utmi_ls.bitend,
 809                           rport->port_cfg->utmi_ls.bitstart);
 810
 811         /* stitch on utmi_ls and utmi_hstdet as phy state */
 812         state = ((uhd & uhd_mask) >> rport->port_cfg->utmi_hstdet.bitstart) |
 813                 (((ul & ul_mask) >> rport->port_cfg->utmi_ls.bitstart) << sh);
 814
 815         switch (state) {
 816         case PHY_STATE_HS_ONLINE:
 817                 dev_dbg(&rport->phy->dev, "HS online\n");
 818                 break;
 819         case PHY_STATE_FS_CONNECT:
 820                 /*
 821                  * For FS device, the online state share with connect state
 822                  * from utmi_ls and utmi_hstdet register, so we distinguish
 823                  * them via suspended flag.
 824                  */
 825                 if (!rport->suspended) {
 826                         dev_dbg(&rport->phy->dev, "FS online\n");
 827                         break;
 828                 }
 829                 /* fall through */
 830         case PHY_STATE_HS_CONNECT:
 831                 if (rport->suspended) {
 832                         dev_dbg(&rport->phy->dev, "HS/FS connected\n");
 833                         rockchip_usb2phy_power_on(rport->phy);
 834                         rport->suspended = false;
 835                 }
 836                 break;
 837         case PHY_STATE_DISCONNECT:
 838                 if (!rport->suspended) {
 839                         dev_dbg(&rport->phy->dev, "HS/FS disconnected\n");
 840                         rockchip_usb2phy_power_off(rport->phy);
 841                         rport->suspended = true;
 842                 }
 843
 844                 /*
 845                  * activate the linestate detection to get the next device
 846                  * plug-in irq.
 847                  */
 848                 property_enable(rphy, &rport->port_cfg->ls_det_clr, true);
 849                 property_enable(rphy, &rport->port_cfg->ls_det_en, true);
 850
 851                 /*
 852                  * we don't need to rearm the delayed work when the phy port
 853                  * is suspended.
 854                  */
 855                 mutex_unlock(&rport->mutex);
 856                 return;
 857         default:
 858                 dev_dbg(&rport->phy->dev, "unknown phy state\n");
 859                 break;
 860         }
 861
 862 next_schedule:
 863         mutex_unlock(&rport->mutex);
 864         schedule_delayed_work(&rport->sm_work, SCHEDULE_DELAY);
 865 }
 866
 867 static irqreturn_t rockchip_usb2phy_linestate_irq(int irq, void *data)
 868 {
 869         struct rockchip_usb2phy_port *rport = data;
 870         struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
 871
 872         if (!property_enabled(rphy, &rport->port_cfg->ls_det_st))
 873                 return IRQ_NONE;
 874
 875         mutex_lock(&rport->mutex);
 876
 877         /* disable linestate detect irq and clear its status */
 878         property_enable(rphy, &rport->port_cfg->ls_det_en, false);
 879         property_enable(rphy, &rport->port_cfg->ls_det_clr, true);
 880
 881         mutex_unlock(&rport->mutex);
 882
 883         /*
 884          * In this case for host phy port, a new device is plugged in,
 885          * meanwhile, if the phy port is suspended, we need rearm the work to
 886          * resume it and mange its states; otherwise, we do nothing about that.
 887          */
 888         if (rport->suspended && rport->port_id == USB2PHY_PORT_HOST)
 889                 rockchip_usb2phy_sm_work(&rport->sm_work.work);
 890
 891         return IRQ_HANDLED;
 892 }
 893
 894 static irqreturn_t rockchip_usb2phy_bvalid_irq(int irq, void *data)
 895 {
 896         struct rockchip_usb2phy_port *rport = data;
 897         struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
 898
 899         if (!property_enabled(rphy, &rport->port_cfg->bvalid_det_st))
 900                 return IRQ_NONE;
 901
 902         mutex_lock(&rport->mutex);
 903
 904         /* clear bvalid detect irq pending status */
 905         property_enable(rphy, &rport->port_cfg->bvalid_det_clr, true);
 906
 907         mutex_unlock(&rport->mutex);
 908
 909         rockchip_usb2phy_otg_sm_work(&rport->otg_sm_work.work);
 910
 911         return IRQ_HANDLED;
 912 }
 913
 914 static int rockchip_usb2phy_host_port_init(struct rockchip_usb2phy *rphy,
 915                                            struct rockchip_usb2phy_port *rport,
 916                                            struct device_node *child_np)
 917 {
 918         int ret;
 919
 920         rport->port_id = USB2PHY_PORT_HOST;
 921         rport->port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_HOST];
 922         rport->suspended = true;
 923
 924         mutex_init(&rport->mutex);
 925         INIT_DELAYED_WORK(&rport->sm_work, rockchip_usb2phy_sm_work);
 926
 927         rport->ls_irq = of_irq_get_byname(child_np, "linestate");
 928         if (rport->ls_irq < 0) {
 929                 dev_err(rphy->dev, "no linestate irq provided\n");
 930                 return rport->ls_irq;
 931         }
 932
 933         ret = devm_request_threaded_irq(rphy->dev, rport->ls_irq, NULL,
 934                                         rockchip_usb2phy_linestate_irq,
 935                                         IRQF_ONESHOT,
 936                                         "rockchip_usb2phy", rport);
 937         if (ret) {
 938                 dev_err(rphy->dev, "failed to request linestate irq handle\n");
 939                 return ret;
 940         }
 941
 942         return 0;
 943 }
 944
 945 static int rockchip_otg_event(struct notifier_block *nb,
 946                               unsigned long event, void *ptr)
 947 {
 948         struct rockchip_usb2phy_port *rport =
 949                 container_of(nb, struct rockchip_usb2phy_port, event_nb);
 950
 951         schedule_delayed_work(&rport->otg_sm_work, OTG_SCHEDULE_DELAY);
 952
 953         return NOTIFY_DONE;
 954 }
 955
 956 static int rockchip_usb2phy_otg_port_init(struct rockchip_usb2phy *rphy,
 957                                           struct rockchip_usb2phy_port *rport,
 958                                           struct device_node *child_np)
 959 {
 960         int ret;
 961
 962         rport->port_id = USB2PHY_PORT_OTG;
 963         rport->port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG];
 964         rport->state = OTG_STATE_UNDEFINED;
 965         /*
 966          * set suspended flag to true, but actually don't
 967          * put phy in suspend mode, it aims to enable usb
 968          * phy and clock in power_on() called by usb controller
 969          * driver during probe.
 970          */
 971         rport->suspended = true;
 972         rport->vbus_attached = false;
 973
 974         mutex_init(&rport->mutex);
 975         wake_lock_init(&rport->wakelock, WAKE_LOCK_SUSPEND, "rockchip_otg");
 976         INIT_DELAYED_WORK(&rport->chg_work, rockchip_chg_detect_work);
 977         INIT_DELAYED_WORK(&rport->otg_sm_work, rockchip_usb2phy_otg_sm_work);
 978
 979         rport->bvalid_irq = of_irq_get_byname(child_np, "otg-bvalid");
 980         if (rport->bvalid_irq < 0) {
 981                 dev_err(rphy->dev, "no vbus valid irq provided\n");
 982                 return rport->bvalid_irq;
 983         }
 984
 985         ret = devm_request_threaded_irq(rphy->dev, rport->bvalid_irq, NULL,
 986                                         rockchip_usb2phy_bvalid_irq,
 987                                         IRQF_ONESHOT,
 988                                         "rockchip_usb2phy_bvalid", rport);
 989         if (ret) {
 990                 dev_err(rphy->dev, "failed to request otg-bvalid irq handle\n");
 991                 return ret;
 992         }
 993
 994         if (!IS_ERR(rphy->edev)) {
 995                 rport->event_nb.notifier_call = rockchip_otg_event;
 996
 997                 ret = extcon_register_notifier(rphy->edev, EXTCON_USB_HOST,
 998                                                &rport->event_nb);
 999                 if (ret < 0) {
1000                         dev_err(rphy->dev, "register USB HOST notifier failed\n");
1001                         return ret;
1002                 }
1003         }
1004
1005         return 0;
1006 }
1007
1008 static int rockchip_usb2phy_probe(struct platform_device *pdev)
1009 {
1010         struct device *dev = &pdev->dev;
1011         struct device_node *np = dev->of_node;
1012         struct device_node *child_np;
1013         struct phy_provider *provider;
1014         struct rockchip_usb2phy *rphy;
1015         const struct rockchip_usb2phy_cfg *phy_cfgs;
1016         const struct of_device_id *match;
1017         unsigned int reg;
1018         int index, ret;
1019
1020         rphy = devm_kzalloc(dev, sizeof(*rphy), GFP_KERNEL);
1021         if (!rphy)
1022                 return -ENOMEM;
1023
1024         match = of_match_device(dev->driver->of_match_table, dev);
1025         if (!match || !match->data) {
1026                 dev_err(dev, "phy configs are not assigned!\n");
1027                 return -EINVAL;
1028         }
1029
1030         if (!dev->parent || !dev->parent->of_node)
1031                 return -EINVAL;
1032
1033         rphy->grf = syscon_node_to_regmap(dev->parent->of_node);
1034         if (IS_ERR(rphy->grf))
1035                 return PTR_ERR(rphy->grf);
1036
1037         if (of_property_read_u32(np, "reg", &reg)) {
1038                 dev_err(dev, "the reg property is not assigned in %s node\n",
1039                         np->name);
1040                 return -EINVAL;
1041         }
1042
1043         rphy->dev = dev;
1044         phy_cfgs = match->data;
1045         rphy->chg_state = USB_CHG_STATE_UNDEFINED;
1046         rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
1047         platform_set_drvdata(pdev, rphy);
1048
1049         ret = rockchip_usb2phy_extcon_register(rphy);
1050         if (ret)
1051                 return ret;
1052
1053         /* find out a proper config which can be matched with dt. */
1054         index = 0;
1055         while (phy_cfgs[index].reg) {
1056                 if (phy_cfgs[index].reg == reg) {
1057                         rphy->phy_cfg = &phy_cfgs[index];
1058                         break;
1059                 }
1060
1061                 ++index;
1062         }
1063
1064         if (!rphy->phy_cfg) {
1065                 dev_err(dev, "no phy-config can be matched with %s node\n",
1066                         np->name);
1067                 return -EINVAL;
1068         }
1069
1070         ret = rockchip_usb2phy_clk480m_register(rphy);
1071         if (ret) {
1072                 dev_err(dev, "failed to register 480m output clock\n");
1073                 return ret;
1074         }
1075
1076         if (rphy->phy_cfg->phy_tuning) {
1077                 ret = rphy->phy_cfg->phy_tuning(rphy);
1078                 if (ret)
1079                         return ret;
1080         }
1081
1082         index = 0;
1083         for_each_available_child_of_node(np, child_np) {
1084                 struct rockchip_usb2phy_port *rport = &rphy->ports[index];
1085                 struct phy *phy;
1086
1087                 /* This driver aims to support both otg-port and host-port */
1088                 if (of_node_cmp(child_np->name, "host-port") &&
1089                     of_node_cmp(child_np->name, "otg-port"))
1090                         goto next_child;
1091
1092                 phy = devm_phy_create(dev, child_np, &rockchip_usb2phy_ops);
1093                 if (IS_ERR(phy)) {
1094                         dev_err(dev, "failed to create phy\n");
1095                         ret = PTR_ERR(phy);
1096                         goto put_child;
1097                 }
1098
1099                 rport->phy = phy;
1100                 phy_set_drvdata(rport->phy, rport);
1101
1102                 /* initialize otg/host port separately */
1103                 if (!of_node_cmp(child_np->name, "host-port")) {
1104                         ret = rockchip_usb2phy_host_port_init(rphy, rport,
1105                                                               child_np);
1106                         if (ret)
1107                                 goto put_child;
1108                 } else {
1109                         ret = rockchip_usb2phy_otg_port_init(rphy, rport,
1110                                                              child_np);
1111                         if (ret)
1112                                 goto put_child;
1113                 }
1114
1115 next_child:
1116                 /* to prevent out of boundary */
1117                 if (++index >= rphy->phy_cfg->num_ports)
1118                         break;
1119         }
1120
1121         provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
1122         return PTR_ERR_OR_ZERO(provider);
1123
1124 put_child:
1125         of_node_put(child_np);
1126         return ret;
1127 }
1128
1129 static int rk3366_usb2phy_tuning(struct rockchip_usb2phy *rphy)
1130 {
1131         unsigned int open_pre_emphasize = 0xffff851f;
1132         unsigned int eye_height_tuning = 0xffff68c8;
1133         unsigned int compensation_tuning = 0xffff026e;
1134         int ret = 0;
1135
1136         /* open HS pre-emphasize to expand HS slew rate for each port. */
1137         ret |= regmap_write(rphy->grf, 0x0780, open_pre_emphasize);
1138         ret |= regmap_write(rphy->grf, 0x079c, eye_height_tuning);
1139         ret |= regmap_write(rphy->grf, 0x07b0, open_pre_emphasize);
1140         ret |= regmap_write(rphy->grf, 0x07cc, eye_height_tuning);
1141
1142         /* compensate default tuning reference relate to ODT and etc. */
1143         ret |= regmap_write(rphy->grf, 0x078c, compensation_tuning);
1144
1145         return ret;
1146 }
1147
1148 static const struct rockchip_usb2phy_cfg rk3366_phy_cfgs[] = {
1149         {
1150                 .reg = 0x700,
1151                 .num_ports      = 2,
1152                 .phy_tuning     = rk3366_usb2phy_tuning,
1153                 .clkout_ctl     = { 0x0724, 15, 15, 1, 0 },
1154                 .port_cfgs      = {
1155                         [USB2PHY_PORT_HOST] = {
1156                                 .phy_sus        = { 0x0728, 15, 0, 0, 0x1d1 },
1157                                 .ls_det_en      = { 0x0680, 4, 4, 0, 1 },
1158                                 .ls_det_st      = { 0x0690, 4, 4, 0, 1 },
1159                                 .ls_det_clr     = { 0x06a0, 4, 4, 0, 1 },
1160                                 .utmi_ls        = { 0x049c, 14, 13, 0, 1 },
1161                                 .utmi_hstdet    = { 0x049c, 12, 12, 0, 1 }
1162                         }
1163                 },
1164         },
1165         { /* sentinel */ }
1166 };
1167
1168 static const struct rockchip_usb2phy_cfg rk3399_phy_cfgs[] = {
1169         {
1170                 .reg            = 0xe450,
1171                 .num_ports      = 2,
1172                 .clkout_ctl     = { 0xe450, 4, 4, 1, 0 },
1173                 .port_cfgs      = {
1174                         [USB2PHY_PORT_OTG] = {
1175                                 .phy_sus        = { 0xe454, 1, 0, 2, 1 },
1176                                 .bvalid_det_en  = { 0xe3c0, 3, 3, 0, 1 },
1177                                 .bvalid_det_st  = { 0xe3e0, 3, 3, 0, 1 },
1178                                 .bvalid_det_clr = { 0xe3d0, 3, 3, 0, 1 },
1179                                 .utmi_bvalid    = { 0xe2ac, 7, 7, 0, 1 },
1180                         },
1181                 },
1182                 .chg_det = {
1183                         .opmode         = { 0xe454, 3, 0, 5, 1 },
1184                         .cp_det         = { 0xe2ac, 2, 2, 0, 1 },
1185                         .dcp_det        = { 0xe2ac, 1, 1, 0, 1 },
1186                         .dp_det         = { 0xe2ac, 0, 0, 0, 1 },
1187                         .idm_sink_en    = { 0xe450, 8, 8, 0, 1 },
1188                         .idp_sink_en    = { 0xe450, 7, 7, 0, 1 },
1189                         .idp_src_en     = { 0xe450, 9, 9, 0, 1 },
1190                         .rdm_pdwn_en    = { 0xe450, 10, 10, 0, 1 },
1191                         .vdm_src_en     = { 0xe450, 12, 12, 0, 1 },
1192                         .vdp_src_en     = { 0xe450, 11, 11, 0, 1 },
1193                 },
1194         },
1195         { /* sentinel */ }
1196 };
1197
1198 static const struct of_device_id rockchip_usb2phy_dt_match[] = {
1199         { .compatible = "rockchip,rk3366-usb2phy", .data = &rk3366_phy_cfgs },
1200         { .compatible = "rockchip,rk3399-usb2phy", .data = &rk3399_phy_cfgs },
1201         {}
1202 };
1203 MODULE_DEVICE_TABLE(of, rockchip_usb2phy_dt_match);
1204
1205 static struct platform_driver rockchip_usb2phy_driver = {
1206         .probe          = rockchip_usb2phy_probe,
1207         .driver         = {
1208                 .name   = "rockchip-usb2phy",
1209                 .of_match_table = rockchip_usb2phy_dt_match,
1210         },
1211 };
1212 module_platform_driver(rockchip_usb2phy_driver);
1213
1214 MODULE_AUTHOR("Frank Wang <frank.wang@rock-chips.com>");
1215 MODULE_DESCRIPTION("Rockchip USB2.0 PHY driver");
1216 MODULE_LICENSE("GPL v2");