drivers/phy/phy-rockchip-inno-usb2.c

   1 /*
   2  * Rockchip USB2.0 PHY with Innosilicon IP block driver
   3  *
   4  * Copyright (C) 2016 Fuzhou Rockchip Electronics Co., Ltd
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  */
  16
  17 #include <linux/clk.h>
  18 #include <linux/clk-provider.h>
  19 #include <linux/delay.h>
  20 #include <linux/extcon.h>
  21 #include <linux/interrupt.h>
  22 #include <linux/io.h>
  23 #include <linux/gpio/consumer.h>
  24 #include <linux/jiffies.h>
  25 #include <linux/kernel.h>
  26 #include <linux/module.h>
  27 #include <linux/mutex.h>
  28 #include <linux/of.h>
  29 #include <linux/of_address.h>
  30 #include <linux/of_irq.h>
  31 #include <linux/of_platform.h>
  32 #include <linux/phy/phy.h>
  33 #include <linux/platform_device.h>
  34 #include <linux/power_supply.h>
  35 #include <linux/regmap.h>
  36 #include <linux/mfd/syscon.h>
  37 #include <linux/usb/otg.h>
  38 #include <linux/wakelock.h>
  39
  40 #define BIT_WRITEABLE_SHIFT     16
  41 #define SCHEDULE_DELAY          (60 * HZ)
  42 #define OTG_SCHEDULE_DELAY      (2 * HZ)
  43
  44 struct rockchip_usb2phy;
  45
  46 enum rockchip_usb2phy_port_id {
  47         USB2PHY_PORT_OTG,
  48         USB2PHY_PORT_HOST,
  49         USB2PHY_NUM_PORTS,
  50 };
  51
  52 enum rockchip_usb2phy_host_state {
  53         PHY_STATE_HS_ONLINE     = 0,
  54         PHY_STATE_DISCONNECT    = 1,
  55         PHY_STATE_CONNECT       = 2,
  56         PHY_STATE_FS_LS_ONLINE  = 4,
  57 };
  58
  59 /**
  60  * Different states involved in USB charger detection.
  61  * USB_CHG_STATE_UNDEFINED      USB charger is not connected or detection
  62  *                              process is not yet started.
  63  * USB_CHG_STATE_WAIT_FOR_DCD   Waiting for Data pins contact.
  64  * USB_CHG_STATE_DCD_DONE       Data pin contact is detected.
  65  * USB_CHG_STATE_PRIMARY_DONE   Primary detection is completed (Detects
  66  *                              between SDP and DCP/CDP).
  67  * USB_CHG_STATE_SECONDARY_DONE Secondary detection is completed (Detects
  68  *                              between DCP and CDP).
  69  * USB_CHG_STATE_DETECTED       USB charger type is determined.
  70  */
  71 enum usb_chg_state {
  72         USB_CHG_STATE_UNDEFINED = 0,
  73         USB_CHG_STATE_WAIT_FOR_DCD,
  74         USB_CHG_STATE_DCD_DONE,
  75         USB_CHG_STATE_PRIMARY_DONE,
  76         USB_CHG_STATE_SECONDARY_DONE,
  77         USB_CHG_STATE_DETECTED,
  78 };
  79
  80 static const unsigned int rockchip_usb2phy_extcon_cable[] = {
  81         EXTCON_USB,
  82         EXTCON_USB_HOST,
  83         EXTCON_CHG_USB_SDP,
  84         EXTCON_CHG_USB_CDP,
  85         EXTCON_CHG_USB_DCP,
  86         EXTCON_CHG_USB_SLOW,
  87         EXTCON_NONE,
  88 };
  89
  90 struct usb2phy_reg {
  91         unsigned int    offset;
  92         unsigned int    bitend;
  93         unsigned int    bitstart;
  94         unsigned int    disable;
  95         unsigned int    enable;
  96 };
  97
  98 /**
  99  * struct rockchip_chg_det_reg: usb charger detect registers
 100  * @cp_det: charging port detected successfully.
 101  * @dcp_det: dedicated charging port detected successfully.
 102  * @dp_det: assert data pin connect successfully.
 103  * @idm_sink_en: open dm sink curren.
 104  * @idp_sink_en: open dp sink current.
 105  * @idp_src_en: open dm source current.
 106  * @rdm_pdwn_en: open dm pull down resistor.
 107  * @vdm_src_en: open dm voltage source.
 108  * @vdp_src_en: open dp voltage source.
 109  * @opmode: utmi operational mode.
 110  */
 111 struct rockchip_chg_det_reg {
 112         struct usb2phy_reg      cp_det;
 113         struct usb2phy_reg      dcp_det;
 114         struct usb2phy_reg      dp_det;
 115         struct usb2phy_reg      idm_sink_en;
 116         struct usb2phy_reg      idp_sink_en;
 117         struct usb2phy_reg      idp_src_en;
 118         struct usb2phy_reg      rdm_pdwn_en;
 119         struct usb2phy_reg      vdm_src_en;
 120         struct usb2phy_reg      vdp_src_en;
 121         struct usb2phy_reg      opmode;
 122 };
 123
 124 /**
 125  * struct rockchip_usb2phy_port_cfg: usb-phy port configuration.
 126  * @phy_sus: phy suspend register.
 127  * @bvalid_det_en: vbus valid rise detection enable register.
 128  * @bvalid_det_st: vbus valid rise detection status register.
 129  * @bvalid_det_clr: vbus valid rise detection clear register.
 130  * @ls_det_en: linestate detection enable register.
 131  * @ls_det_st: linestate detection state register.
 132  * @ls_det_clr: linestate detection clear register.
 133  * @utmi_avalid: utmi vbus avalid status register.
 134  * @utmi_bvalid: utmi vbus bvalid status register.
 135  * @utmi_ls: utmi linestate state register.
 136  * @utmi_hstdet: utmi host disconnect register.
 137  */
 138 struct rockchip_usb2phy_port_cfg {
 139         struct usb2phy_reg      phy_sus;
 140         struct usb2phy_reg      bvalid_det_en;
 141         struct usb2phy_reg      bvalid_det_st;
 142         struct usb2phy_reg      bvalid_det_clr;
 143         struct usb2phy_reg      ls_det_en;
 144         struct usb2phy_reg      ls_det_st;
 145         struct usb2phy_reg      ls_det_clr;
 146         struct usb2phy_reg      utmi_avalid;
 147         struct usb2phy_reg      utmi_bvalid;
 148         struct usb2phy_reg      utmi_ls;
 149         struct usb2phy_reg      utmi_hstdet;
 150 };
 151
 152 /**
 153  * struct rockchip_usb2phy_cfg: usb-phy configuration.
 154  * @reg: the address offset of grf for usb-phy config.
 155  * @num_ports: specify how many ports that the phy has.
 156  * @phy_tuning: phy default parameters tunning.
 157  * @clkout_ctl: keep on/turn off output clk of phy.
 158  * @chg_det: charger detection registers.
 159  */
 160 struct rockchip_usb2phy_cfg {
 161         unsigned int    reg;
 162         unsigned int    num_ports;
 163         int (*phy_tuning)(struct rockchip_usb2phy *);
 164         struct usb2phy_reg      clkout_ctl;
 165         const struct rockchip_usb2phy_port_cfg  port_cfgs[USB2PHY_NUM_PORTS];
 166         const struct rockchip_chg_det_reg       chg_det;
 167 };
 168
 169 /**
 170  * struct rockchip_usb2phy_port: usb-phy port data.
 171  * @port_id: flag for otg port or host port.
 172  * @suspended: phy suspended flag.
 173  * @utmi_avalid: utmi avalid status usage flag.
 174  *      true    - use avalid to get vbus status
 175  *      flase   - use bvalid to get vbus status
 176  * @vbus_attached: otg device vbus status.
 177  * @bvalid_irq: IRQ number assigned for vbus valid rise detection.
 178  * @ls_irq: IRQ number assigned for linestate detection.
 179  * @mutex: for register updating in sm_work.
 180  * @chg_work: charge detect work.
 181  * @otg_sm_work: OTG state machine work.
 182  * @sm_work: HOST state machine work.
 183  * @phy_cfg: port register configuration, assigned by driver data.
 184  * @event_nb: hold event notification callback.
 185  * @wakelock: wake lock struct to prevent system suspend
 186  *            when USB is active.
 187  * @state: define OTG enumeration states before device reset.
 188  */
 189 struct rockchip_usb2phy_port {
 190         struct phy      *phy;
 191         unsigned int    port_id;
 192         bool            suspended;
 193         bool            utmi_avalid;
 194         bool            vbus_attached;
 195         int             bvalid_irq;
 196         int             ls_irq;
 197         struct mutex    mutex;
 198         struct          delayed_work chg_work;
 199         struct          delayed_work otg_sm_work;
 200         struct          delayed_work sm_work;
 201         const struct    rockchip_usb2phy_port_cfg *port_cfg;
 202         struct notifier_block   event_nb;
 203         struct wake_lock        wakelock;
 204         enum usb_otg_state      state;
 205 };
 206
 207 /**
 208  * struct rockchip_usb2phy: usb2.0 phy driver data.
 209  * @grf: General Register Files regmap.
 210  * @clk: clock struct of phy input clk.
 211  * @clk480m: clock struct of phy output clk.
 212  * @clk_hw: clock struct of phy output clk management.
 213  * @chg_state: states involved in USB charger detection.
 214  * @chg_type: USB charger types.
 215  * @dcd_retries: The retry count used to track Data contact
 216  *               detection process.
 217  * @edev: extcon device for notification registration
 218  * @phy_cfg: phy register configuration, assigned by driver data.
 219  * @ports: phy port instance.
 220  */
 221 struct rockchip_usb2phy {
 222         struct device   *dev;
 223         struct regmap   *grf;
 224         struct clk      *clk;
 225         struct clk      *clk480m;
 226         struct clk_hw   clk480m_hw;
 227         enum usb_chg_state      chg_state;
 228         enum power_supply_type  chg_type;
 229         u8                      dcd_retries;
 230         struct extcon_dev       *edev;
 231         const struct rockchip_usb2phy_cfg       *phy_cfg;
 232         struct rockchip_usb2phy_port    ports[USB2PHY_NUM_PORTS];
 233 };
 234
 235 static inline int property_enable(struct rockchip_usb2phy *rphy,
 236                                   const struct usb2phy_reg *reg, bool en)
 237 {
 238         unsigned int val, mask, tmp;
 239
 240         tmp = en ? reg->enable : reg->disable;
 241         mask = GENMASK(reg->bitend, reg->bitstart);
 242         val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT);
 243
 244         return regmap_write(rphy->grf, reg->offset, val);
 245 }
 246
 247 static inline bool property_enabled(struct rockchip_usb2phy *rphy,
 248                                     const struct usb2phy_reg *reg)
 249 {
 250         int ret;
 251         unsigned int tmp, orig;
 252         unsigned int mask = GENMASK(reg->bitend, reg->bitstart);
 253
 254         ret = regmap_read(rphy->grf, reg->offset, &orig);
 255         if (ret)
 256                 return false;
 257
 258         tmp = (orig & mask) >> reg->bitstart;
 259         return tmp == reg->enable;
 260 }
 261
 262 static int rockchip_usb2phy_clk480m_enable(struct clk_hw *hw)
 263 {
 264         struct rockchip_usb2phy *rphy =
 265                 container_of(hw, struct rockchip_usb2phy, clk480m_hw);
 266         int ret;
 267
 268         /* turn on 480m clk output if it is off */
 269         if (!property_enabled(rphy, &rphy->phy_cfg->clkout_ctl)) {
 270                 ret = property_enable(rphy, &rphy->phy_cfg->clkout_ctl, true);
 271                 if (ret)
 272                         return ret;
 273
 274                 /* waitting for the clk become stable */
 275                 mdelay(1);
 276         }
 277
 278         return 0;
 279 }
 280
 281 static void rockchip_usb2phy_clk480m_disable(struct clk_hw *hw)
 282 {
 283         struct rockchip_usb2phy *rphy =
 284                 container_of(hw, struct rockchip_usb2phy, clk480m_hw);
 285
 286         /* turn off 480m clk output */
 287         property_enable(rphy, &rphy->phy_cfg->clkout_ctl, false);
 288 }
 289
 290 static int rockchip_usb2phy_clk480m_enabled(struct clk_hw *hw)
 291 {
 292         struct rockchip_usb2phy *rphy =
 293                 container_of(hw, struct rockchip_usb2phy, clk480m_hw);
 294
 295         return property_enabled(rphy, &rphy->phy_cfg->clkout_ctl);
 296 }
 297
 298 static unsigned long
 299 rockchip_usb2phy_clk480m_recalc_rate(struct clk_hw *hw,
 300                                      unsigned long parent_rate)
 301 {
 302         return 480000000;
 303 }
 304
 305 static const struct clk_ops rockchip_usb2phy_clkout_ops = {
 306         .enable = rockchip_usb2phy_clk480m_enable,
 307         .disable = rockchip_usb2phy_clk480m_disable,
 308         .is_enabled = rockchip_usb2phy_clk480m_enabled,
 309         .recalc_rate = rockchip_usb2phy_clk480m_recalc_rate,
 310 };
 311
 312 static void rockchip_usb2phy_clk480m_unregister(void *data)
 313 {
 314         struct rockchip_usb2phy *rphy = data;
 315
 316         of_clk_del_provider(rphy->dev->of_node);
 317         clk_unregister(rphy->clk480m);
 318 }
 319
 320 static int
 321 rockchip_usb2phy_clk480m_register(struct rockchip_usb2phy *rphy)
 322 {
 323         struct device_node *node = rphy->dev->of_node;
 324         struct clk_init_data init;
 325         const char *clk_name;
 326         int ret;
 327
 328         init.flags = 0;
 329         init.name = "clk_usbphy_480m";
 330         init.ops = &rockchip_usb2phy_clkout_ops;
 331
 332         /* optional override of the clockname */
 333         of_property_read_string(node, "clock-output-names", &init.name);
 334
 335         if (rphy->clk) {
 336                 clk_name = __clk_get_name(rphy->clk);
 337                 init.parent_names = &clk_name;
 338                 init.num_parents = 1;
 339         } else {
 340                 init.parent_names = NULL;
 341                 init.num_parents = 0;
 342         }
 343
 344         rphy->clk480m_hw.init = &init;
 345
 346         /* register the clock */
 347         rphy->clk480m = clk_register(rphy->dev, &rphy->clk480m_hw);
 348         if (IS_ERR(rphy->clk480m)) {
 349                 ret = PTR_ERR(rphy->clk480m);
 350                 goto err_ret;
 351         }
 352
 353         ret = of_clk_add_provider(node, of_clk_src_simple_get, rphy->clk480m);
 354         if (ret < 0)
 355                 goto err_clk_provider;
 356
 357         ret = devm_add_action(rphy->dev, rockchip_usb2phy_clk480m_unregister,
 358                               rphy);
 359         if (ret < 0)
 360                 goto err_unreg_action;
 361
 362         return 0;
 363
 364 err_unreg_action:
 365         of_clk_del_provider(node);
 366 err_clk_provider:
 367         clk_unregister(rphy->clk480m);
 368 err_ret:
 369         return ret;
 370 }
 371
 372 static int rockchip_usb2phy_extcon_register(struct rockchip_usb2phy *rphy)
 373 {
 374         int ret;
 375         struct device_node *node = rphy->dev->of_node;
 376         struct extcon_dev *edev;
 377
 378         if (of_property_read_bool(node, "extcon")) {
 379                 edev = extcon_get_edev_by_phandle(rphy->dev, 0);
 380                 if (IS_ERR(edev)) {
 381                         if (PTR_ERR(edev) != -EPROBE_DEFER)
 382                                 dev_err(rphy->dev, "Invalid or missing extcon\n");
 383                         return PTR_ERR(edev);
 384                 }
 385         } else {
 386                 /* Initialize extcon device */
 387                 edev = devm_extcon_dev_allocate(rphy->dev,
 388                                                 rockchip_usb2phy_extcon_cable);
 389
 390                 if (IS_ERR(edev))
 391                         return -ENOMEM;
 392
 393                 ret = devm_extcon_dev_register(rphy->dev, edev);
 394                 if (ret) {
 395                         dev_err(rphy->dev, "failed to register extcon device\n");
 396                         return ret;
 397                 }
 398         }
 399
 400         rphy->edev = edev;
 401
 402         return 0;
 403 }
 404
 405 static int rockchip_usb2phy_init(struct phy *phy)
 406 {
 407         struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
 408         struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
 409         int ret;
 410
 411         mutex_lock(&rport->mutex);
 412
 413         if (rport->port_id == USB2PHY_PORT_OTG) {
 414                 /* clear bvalid status and enable bvalid detect irq */
 415                 ret = property_enable(rphy,
 416                                       &rport->port_cfg->bvalid_det_clr, true);
 417                 if (ret) {
 418                         mutex_unlock(&rport->mutex);
 419                         return ret;
 420                 }
 421
 422                 ret = property_enable(rphy,
 423                                       &rport->port_cfg->bvalid_det_en, true);
 424                 if (ret) {
 425                         mutex_unlock(&rport->mutex);
 426                         return ret;
 427                 }
 428
 429                 mutex_unlock(&rport->mutex);
 430                 schedule_delayed_work(&rport->otg_sm_work, OTG_SCHEDULE_DELAY);
 431
 432         } else if (rport->port_id == USB2PHY_PORT_HOST) {
 433                 /* clear linestate and enable linestate detect irq */
 434                 ret = property_enable(rphy, &rport->port_cfg->ls_det_clr, true);
 435                 if (ret) {
 436                         mutex_unlock(&rport->mutex);
 437                         return ret;
 438                 }
 439
 440                 ret = property_enable(rphy, &rport->port_cfg->ls_det_en, true);
 441                 if (ret) {
 442                         mutex_unlock(&rport->mutex);
 443                         return ret;
 444                 }
 445
 446                 mutex_unlock(&rport->mutex);
 447                 schedule_delayed_work(&rport->sm_work, SCHEDULE_DELAY);
 448         }
 449
 450         return 0;
 451 }
 452
 453 static int rockchip_usb2phy_power_on(struct phy *phy)
 454 {
 455         struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
 456         struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
 457         int ret;
 458
 459         dev_dbg(&rport->phy->dev, "port power on\n");
 460
 461         if (!rport->suspended)
 462                 return 0;
 463
 464         ret = clk_prepare_enable(rphy->clk480m);
 465         if (ret)
 466                 return ret;
 467
 468         ret = property_enable(rphy, &rport->port_cfg->phy_sus, false);
 469         if (ret)
 470                 return ret;
 471
 472         rport->suspended = false;
 473         return 0;
 474 }
 475
 476 static int rockchip_usb2phy_power_off(struct phy *phy)
 477 {
 478         struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
 479         struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
 480         int ret;
 481
 482         dev_dbg(&rport->phy->dev, "port power off\n");
 483
 484         if (rport->suspended)
 485                 return 0;
 486
 487         ret = property_enable(rphy, &rport->port_cfg->phy_sus, true);
 488         if (ret)
 489                 return ret;
 490
 491         rport->suspended = true;
 492         clk_disable_unprepare(rphy->clk480m);
 493
 494         return 0;
 495 }
 496
 497 static int rockchip_usb2phy_exit(struct phy *phy)
 498 {
 499         struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
 500
 501         if (rport->port_id == USB2PHY_PORT_OTG) {
 502                 cancel_delayed_work_sync(&rport->chg_work);
 503                 cancel_delayed_work_sync(&rport->otg_sm_work);
 504         } else if (rport->port_id == USB2PHY_PORT_HOST)
 505                 cancel_delayed_work_sync(&rport->sm_work);
 506
 507         return 0;
 508 }
 509
 510 static const struct phy_ops rockchip_usb2phy_ops = {
 511         .init           = rockchip_usb2phy_init,
 512         .exit           = rockchip_usb2phy_exit,
 513         .power_on       = rockchip_usb2phy_power_on,
 514         .power_off      = rockchip_usb2phy_power_off,
 515         .owner          = THIS_MODULE,
 516 };
 517
 518 static void rockchip_usb2phy_otg_sm_work(struct work_struct *work)
 519 {
 520         struct rockchip_usb2phy_port *rport =
 521                 container_of(work, struct rockchip_usb2phy_port,
 522                              otg_sm_work.work);
 523         struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
 524         static unsigned int cable;
 525         unsigned long delay;
 526         bool vbus_attach, sch_work, notify_charger;
 527
 528         if (rport->utmi_avalid)
 529                 vbus_attach =
 530                         property_enabled(rphy, &rport->port_cfg->utmi_avalid);
 531         else
 532                 vbus_attach =
 533                         property_enabled(rphy, &rport->port_cfg->utmi_bvalid);
 534
 535         sch_work = false;
 536         notify_charger = false;
 537         delay = OTG_SCHEDULE_DELAY;
 538         dev_dbg(&rport->phy->dev, "%s otg sm work\n",
 539                 usb_otg_state_string(rport->state));
 540
 541         switch (rport->state) {
 542         case OTG_STATE_UNDEFINED:
 543                 rport->state = OTG_STATE_B_IDLE;
 544                 if (!vbus_attach)
 545                         rockchip_usb2phy_power_off(rport->phy);
 546                 /* fall through */
 547         case OTG_STATE_B_IDLE:
 548                 if (extcon_get_cable_state_(rphy->edev, EXTCON_USB_HOST) > 0) {
 549                         dev_dbg(&rport->phy->dev, "usb otg host connect\n");
 550                         rport->state = OTG_STATE_A_HOST;
 551                         rockchip_usb2phy_power_on(rport->phy);
 552                         return;
 553                 } else if (vbus_attach) {
 554                         dev_dbg(&rport->phy->dev, "vbus_attach\n");
 555                         switch (rphy->chg_state) {
 556                         case USB_CHG_STATE_UNDEFINED:
 557                                 schedule_delayed_work(&rport->chg_work, 0);
 558                                 return;
 559                         case USB_CHG_STATE_DETECTED:
 560                                 switch (rphy->chg_type) {
 561                                 case POWER_SUPPLY_TYPE_USB:
 562                                         dev_dbg(&rport->phy->dev,
 563                                                 "sdp cable is connecetd\n");
 564                                         wake_lock(&rport->wakelock);
 565                                         rockchip_usb2phy_power_on(rport->phy);
 566                                         rport->state = OTG_STATE_B_PERIPHERAL;
 567                                         notify_charger = true;
 568                                         sch_work = true;
 569                                         cable = EXTCON_CHG_USB_SDP;
 570                                         break;
 571                                 case POWER_SUPPLY_TYPE_USB_DCP:
 572                                         dev_dbg(&rport->phy->dev,
 573                                                 "dcp cable is connecetd\n");
 574                                         rockchip_usb2phy_power_off(rport->phy);
 575                                         notify_charger = true;
 576                                         sch_work = true;
 577                                         cable = EXTCON_CHG_USB_DCP;
 578                                         break;
 579                                 case POWER_SUPPLY_TYPE_USB_CDP:
 580                                         dev_dbg(&rport->phy->dev,
 581                                                 "cdp cable is connecetd\n");
 582                                         wake_lock(&rport->wakelock);
 583                                         rockchip_usb2phy_power_on(rport->phy);
 584                                         rport->state = OTG_STATE_B_PERIPHERAL;
 585                                         notify_charger = true;
 586                                         sch_work = true;
 587                                         cable = EXTCON_CHG_USB_CDP;
 588                                         break;
 589                                 case POWER_SUPPLY_TYPE_USB_FLOATING:
 590                                         dev_dbg(&rport->phy->dev,
 591                                                 "floating cable is connecetd\n");
 592                                         rockchip_usb2phy_power_off(rport->phy);
 593                                         notify_charger = true;
 594                                         sch_work = true;
 595                                         cable = EXTCON_CHG_USB_SLOW;
 596                                         break;
 597                                 default:
 598                                         break;
 599                                 }
 600                                 break;
 601                         default:
 602                                 break;
 603                         }
 604                 } else {
 605                         notify_charger = true;
 606                         rphy->chg_state = USB_CHG_STATE_UNDEFINED;
 607                         rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
 608                 }
 609
 610                 if (rport->vbus_attached != vbus_attach) {
 611                         rport->vbus_attached = vbus_attach;
 612
 613                         if (notify_charger && rphy->edev)
 614                                 extcon_set_cable_state_(rphy->edev,
 615                                                         cable, vbus_attach);
 616                 }
 617                 break;
 618         case OTG_STATE_B_PERIPHERAL:
 619                 if (!vbus_attach) {
 620                         dev_dbg(&rport->phy->dev, "usb disconnect\n");
 621                         rphy->chg_state = USB_CHG_STATE_UNDEFINED;
 622                         rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
 623                         rport->state = OTG_STATE_B_IDLE;
 624                         delay = 0;
 625                         rockchip_usb2phy_power_off(rport->phy);
 626                         wake_unlock(&rport->wakelock);
 627                 }
 628                 sch_work = true;
 629                 break;
 630         case OTG_STATE_A_HOST:
 631                 if (extcon_get_cable_state_(rphy->edev, EXTCON_USB_HOST) == 0) {
 632                         dev_dbg(&rport->phy->dev, "usb otg host disconnect\n");
 633                         rport->state = OTG_STATE_B_IDLE;
 634                         rockchip_usb2phy_power_off(rport->phy);
 635                 }
 636                 break;
 637         default:
 638                 break;
 639         }
 640
 641         if (sch_work)
 642                 schedule_delayed_work(&rport->otg_sm_work, delay);
 643 }
 644
 645 static const char *chg_to_string(enum power_supply_type chg_type)
 646 {
 647         switch (chg_type) {
 648         case POWER_SUPPLY_TYPE_USB:
 649                 return "USB_SDP_CHARGER";
 650         case POWER_SUPPLY_TYPE_USB_DCP:
 651                 return "USB_DCP_CHARGER";
 652         case POWER_SUPPLY_TYPE_USB_CDP:
 653                 return "USB_CDP_CHARGER";
 654         case POWER_SUPPLY_TYPE_USB_FLOATING:
 655                 return "USB_FLOATING_CHARGER";
 656         default:
 657                 return "INVALID_CHARGER";
 658         }
 659 }
 660
 661 static void rockchip_chg_enable_dcd(struct rockchip_usb2phy *rphy,
 662                                     bool en)
 663 {
 664         property_enable(rphy, &rphy->phy_cfg->chg_det.rdm_pdwn_en, en);
 665         property_enable(rphy, &rphy->phy_cfg->chg_det.idp_src_en, en);
 666 }
 667
 668 static void rockchip_chg_enable_primary_det(struct rockchip_usb2phy *rphy,
 669                                             bool en)
 670 {
 671         property_enable(rphy, &rphy->phy_cfg->chg_det.vdp_src_en, en);
 672         property_enable(rphy, &rphy->phy_cfg->chg_det.idm_sink_en, en);
 673 }
 674
 675 static void rockchip_chg_enable_secondary_det(struct rockchip_usb2phy *rphy,
 676                                               bool en)
 677 {
 678         property_enable(rphy, &rphy->phy_cfg->chg_det.vdm_src_en, en);
 679         property_enable(rphy, &rphy->phy_cfg->chg_det.idp_sink_en, en);
 680 }
 681
 682 #define CHG_DCD_POLL_TIME       (100 * HZ / 1000)
 683 #define CHG_DCD_MAX_RETRIES     6
 684 #define CHG_PRIMARY_DET_TIME    (40 * HZ / 1000)
 685 #define CHG_SECONDARY_DET_TIME  (40 * HZ / 1000)
 686 static void rockchip_chg_detect_work(struct work_struct *work)
 687 {
 688         struct rockchip_usb2phy_port *rport =
 689                 container_of(work, struct rockchip_usb2phy_port, chg_work.work);
 690         struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
 691         bool is_dcd, tmout, vout;
 692         unsigned long delay;
 693
 694         dev_dbg(&rport->phy->dev, "chg detection work state = %d\n",
 695                 rphy->chg_state);
 696         switch (rphy->chg_state) {
 697         case USB_CHG_STATE_UNDEFINED:
 698                 if (!rport->suspended)
 699                         rockchip_usb2phy_power_off(rport->phy);
 700                 /* put the controller in non-driving mode */
 701                 property_enable(rphy, &rphy->phy_cfg->chg_det.opmode, false);
 702                 /* Start DCD processing stage 1 */
 703                 rockchip_chg_enable_dcd(rphy, true);
 704                 rphy->chg_state = USB_CHG_STATE_WAIT_FOR_DCD;
 705                 rphy->dcd_retries = 0;
 706                 delay = CHG_DCD_POLL_TIME;
 707                 break;
 708         case USB_CHG_STATE_WAIT_FOR_DCD:
 709                 /* get data contact detection status */
 710                 is_dcd = property_enabled(rphy, &rphy->phy_cfg->chg_det.dp_det);
 711                 tmout = ++rphy->dcd_retries == CHG_DCD_MAX_RETRIES;
 712                 /* stage 2 */
 713                 if (is_dcd || tmout) {
 714                         /* stage 4 */
 715                         /* Turn off DCD circuitry */
 716                         rockchip_chg_enable_dcd(rphy, false);
 717                         /* Voltage Source on DP, Probe on DM */
 718                         rockchip_chg_enable_primary_det(rphy, true);
 719                         delay = CHG_PRIMARY_DET_TIME;
 720                         rphy->chg_state = USB_CHG_STATE_DCD_DONE;
 721                 } else {
 722                         /* stage 3 */
 723                         delay = CHG_DCD_POLL_TIME;
 724                 }
 725                 break;
 726         case USB_CHG_STATE_DCD_DONE:
 727                 vout = property_enabled(rphy, &rphy->phy_cfg->chg_det.cp_det);
 728                 rockchip_chg_enable_primary_det(rphy, false);
 729                 if (vout) {
 730                         /* Voltage Source on DM, Probe on DP  */
 731                         rockchip_chg_enable_secondary_det(rphy, true);
 732                         delay = CHG_SECONDARY_DET_TIME;
 733                         rphy->chg_state = USB_CHG_STATE_PRIMARY_DONE;
 734                 } else {
 735                         if (tmout) {
 736                                 /* floating charger found */
 737                                 rphy->chg_type = POWER_SUPPLY_TYPE_USB_FLOATING;
 738                                 rphy->chg_state = USB_CHG_STATE_DETECTED;
 739                                 delay = 0;
 740                         } else {
 741                                 rphy->chg_type = POWER_SUPPLY_TYPE_USB;
 742                                 rphy->chg_state = USB_CHG_STATE_DETECTED;
 743                                 delay = 0;
 744                         }
 745                 }
 746                 break;
 747         case USB_CHG_STATE_PRIMARY_DONE:
 748                 vout = property_enabled(rphy, &rphy->phy_cfg->chg_det.dcp_det);
 749                 /* Turn off voltage source */
 750                 rockchip_chg_enable_secondary_det(rphy, false);
 751                 if (vout)
 752                         rphy->chg_type = POWER_SUPPLY_TYPE_USB_DCP;
 753                 else
 754                         rphy->chg_type = POWER_SUPPLY_TYPE_USB_CDP;
 755                 /* fall through */
 756         case USB_CHG_STATE_SECONDARY_DONE:
 757                 rphy->chg_state = USB_CHG_STATE_DETECTED;
 758                 delay = 0;
 759                 /* fall through */
 760         case USB_CHG_STATE_DETECTED:
 761                 /* put the controller in normal mode */
 762                 property_enable(rphy, &rphy->phy_cfg->chg_det.opmode, true);
 763                 rockchip_usb2phy_otg_sm_work(&rport->otg_sm_work.work);
 764                 dev_info(&rport->phy->dev, "charger = %s\n",
 765                          chg_to_string(rphy->chg_type));
 766                 return;
 767         default:
 768                 return;
 769         }
 770
 771         schedule_delayed_work(&rport->chg_work, delay);
 772 }
 773
 774 /*
 775  * The function manage host-phy port state and suspend/resume phy port
 776  * to save power.
 777  *
 778  * we rely on utmi_linestate and utmi_hostdisconnect to identify whether
 779  * devices is disconnect or not. Besides, we do not need care it is FS/LS
 780  * disconnected or HS disconnected, actually, we just only need get the
 781  * device is disconnected at last through rearm the delayed work,
 782  * to suspend the phy port in _PHY_STATE_DISCONNECT_ case.
 783  *
 784  * NOTE: It may invoke *phy_powr_off or *phy_power_on which will invoke
 785  * some clk related APIs, so do not invoke it from interrupt context directly.
 786  */
 787 static void rockchip_usb2phy_sm_work(struct work_struct *work)
 788 {
 789         struct rockchip_usb2phy_port *rport =
 790                 container_of(work, struct rockchip_usb2phy_port, sm_work.work);
 791         struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
 792         unsigned int sh = rport->port_cfg->utmi_hstdet.bitend -
 793                           rport->port_cfg->utmi_hstdet.bitstart + 1;
 794         unsigned int ul, uhd, state;
 795         unsigned int ul_mask, uhd_mask;
 796         int ret;
 797
 798         mutex_lock(&rport->mutex);
 799
 800         ret = regmap_read(rphy->grf, rport->port_cfg->utmi_ls.offset, &ul);
 801         if (ret < 0)
 802                 goto next_schedule;
 803
 804         ret = regmap_read(rphy->grf, rport->port_cfg->utmi_hstdet.offset,
 805                           &uhd);
 806         if (ret < 0)
 807                 goto next_schedule;
 808
 809         uhd_mask = GENMASK(rport->port_cfg->utmi_hstdet.bitend,
 810                            rport->port_cfg->utmi_hstdet.bitstart);
 811         ul_mask = GENMASK(rport->port_cfg->utmi_ls.bitend,
 812                           rport->port_cfg->utmi_ls.bitstart);
 813
 814         /* stitch on utmi_ls and utmi_hstdet as phy state */
 815         state = ((uhd & uhd_mask) >> rport->port_cfg->utmi_hstdet.bitstart) |
 816                 (((ul & ul_mask) >> rport->port_cfg->utmi_ls.bitstart) << sh);
 817
 818         switch (state) {
 819         case PHY_STATE_HS_ONLINE:
 820                 dev_dbg(&rport->phy->dev, "HS online\n");
 821                 break;
 822         case PHY_STATE_FS_LS_ONLINE:
 823                 /*
 824                  * For FS/LS device, the online state share with connect state
 825                  * from utmi_ls and utmi_hstdet register, so we distinguish
 826                  * them via suspended flag.
 827                  *
 828                  * Plus, there are two cases, one is D- Line pull-up, and D+
 829                  * line pull-down, the state is 4; another is D+ line pull-up,
 830                  * and D- line pull-down, the state is 2.
 831                  */
 832                 if (!rport->suspended) {
 833                         /* D- line pull-up, D+ line pull-down */
 834                         dev_dbg(&rport->phy->dev, "FS/LS online\n");
 835                         break;
 836                 }
 837                 /* fall through */
 838         case PHY_STATE_CONNECT:
 839                 if (rport->suspended) {
 840                         dev_dbg(&rport->phy->dev, "Connected\n");
 841                         rockchip_usb2phy_power_on(rport->phy);
 842                         rport->suspended = false;
 843                 } else {
 844                         /* D+ line pull-up, D- line pull-down */
 845                         dev_dbg(&rport->phy->dev, "FS/LS online\n");
 846                 }
 847                 break;
 848         case PHY_STATE_DISCONNECT:
 849                 if (!rport->suspended) {
 850                         dev_dbg(&rport->phy->dev, "Disconnected\n");
 851                         rockchip_usb2phy_power_off(rport->phy);
 852                         rport->suspended = true;
 853                 }
 854
 855                 /*
 856                  * activate the linestate detection to get the next device
 857                  * plug-in irq.
 858                  */
 859                 property_enable(rphy, &rport->port_cfg->ls_det_clr, true);
 860                 property_enable(rphy, &rport->port_cfg->ls_det_en, true);
 861
 862                 /*
 863                  * we don't need to rearm the delayed work when the phy port
 864                  * is suspended.
 865                  */
 866                 mutex_unlock(&rport->mutex);
 867                 return;
 868         default:
 869                 dev_dbg(&rport->phy->dev, "unknown phy state\n");
 870                 break;
 871         }
 872
 873 next_schedule:
 874         mutex_unlock(&rport->mutex);
 875         schedule_delayed_work(&rport->sm_work, SCHEDULE_DELAY);
 876 }
 877
 878 static irqreturn_t rockchip_usb2phy_linestate_irq(int irq, void *data)
 879 {
 880         struct rockchip_usb2phy_port *rport = data;
 881         struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
 882
 883         if (!property_enabled(rphy, &rport->port_cfg->ls_det_st))
 884                 return IRQ_NONE;
 885
 886         mutex_lock(&rport->mutex);
 887
 888         /* disable linestate detect irq and clear its status */
 889         property_enable(rphy, &rport->port_cfg->ls_det_en, false);
 890         property_enable(rphy, &rport->port_cfg->ls_det_clr, true);
 891
 892         mutex_unlock(&rport->mutex);
 893
 894         /*
 895          * In this case for host phy port, a new device is plugged in,
 896          * meanwhile, if the phy port is suspended, we need rearm the work to
 897          * resume it and mange its states; otherwise, we do nothing about that.
 898          */
 899         if (rport->suspended && rport->port_id == USB2PHY_PORT_HOST)
 900                 rockchip_usb2phy_sm_work(&rport->sm_work.work);
 901
 902         return IRQ_HANDLED;
 903 }
 904
 905 static irqreturn_t rockchip_usb2phy_bvalid_irq(int irq, void *data)
 906 {
 907         struct rockchip_usb2phy_port *rport = data;
 908         struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
 909
 910         if (!property_enabled(rphy, &rport->port_cfg->bvalid_det_st))
 911                 return IRQ_NONE;
 912
 913         mutex_lock(&rport->mutex);
 914
 915         /* clear bvalid detect irq pending status */
 916         property_enable(rphy, &rport->port_cfg->bvalid_det_clr, true);
 917
 918         mutex_unlock(&rport->mutex);
 919
 920         rockchip_usb2phy_otg_sm_work(&rport->otg_sm_work.work);
 921
 922         return IRQ_HANDLED;
 923 }
 924
 925 static int rockchip_usb2phy_host_port_init(struct rockchip_usb2phy *rphy,
 926                                            struct rockchip_usb2phy_port *rport,
 927                                            struct device_node *child_np)
 928 {
 929         int ret;
 930
 931         rport->port_id = USB2PHY_PORT_HOST;
 932         rport->port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_HOST];
 933         rport->suspended = true;
 934
 935         mutex_init(&rport->mutex);
 936         INIT_DELAYED_WORK(&rport->sm_work, rockchip_usb2phy_sm_work);
 937
 938         rport->ls_irq = of_irq_get_byname(child_np, "linestate");
 939         if (rport->ls_irq < 0) {
 940                 dev_err(rphy->dev, "no linestate irq provided\n");
 941                 return rport->ls_irq;
 942         }
 943
 944         ret = devm_request_threaded_irq(rphy->dev, rport->ls_irq, NULL,
 945                                         rockchip_usb2phy_linestate_irq,
 946                                         IRQF_ONESHOT,
 947                                         "rockchip_usb2phy", rport);
 948         if (ret) {
 949                 dev_err(rphy->dev, "failed to request linestate irq handle\n");
 950                 return ret;
 951         }
 952
 953         return 0;
 954 }
 955
 956 static int rockchip_otg_event(struct notifier_block *nb,
 957                               unsigned long event, void *ptr)
 958 {
 959         struct rockchip_usb2phy_port *rport =
 960                 container_of(nb, struct rockchip_usb2phy_port, event_nb);
 961
 962         schedule_delayed_work(&rport->otg_sm_work, OTG_SCHEDULE_DELAY);
 963
 964         return NOTIFY_DONE;
 965 }
 966
 967 static int rockchip_usb2phy_otg_port_init(struct rockchip_usb2phy *rphy,
 968                                           struct rockchip_usb2phy_port *rport,
 969                                           struct device_node *child_np)
 970 {
 971         int ret;
 972
 973         rport->port_id = USB2PHY_PORT_OTG;
 974         rport->port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG];
 975         rport->state = OTG_STATE_UNDEFINED;
 976         /*
 977          * set suspended flag to true, but actually don't
 978          * put phy in suspend mode, it aims to enable usb
 979          * phy and clock in power_on() called by usb controller
 980          * driver during probe.
 981          */
 982         rport->suspended = true;
 983         rport->vbus_attached = false;
 984
 985         mutex_init(&rport->mutex);
 986         wake_lock_init(&rport->wakelock, WAKE_LOCK_SUSPEND, "rockchip_otg");
 987         INIT_DELAYED_WORK(&rport->chg_work, rockchip_chg_detect_work);
 988         INIT_DELAYED_WORK(&rport->otg_sm_work, rockchip_usb2phy_otg_sm_work);
 989
 990         rport->utmi_avalid =
 991                 of_property_read_bool(child_np, "rockchip,utmi-avalid");
 992
 993         rport->bvalid_irq = of_irq_get_byname(child_np, "otg-bvalid");
 994         if (rport->bvalid_irq < 0) {
 995                 dev_err(rphy->dev, "no vbus valid irq provided\n");
 996                 return rport->bvalid_irq;
 997         }
 998
 999         ret = devm_request_threaded_irq(rphy->dev, rport->bvalid_irq, NULL,
1000                                         rockchip_usb2phy_bvalid_irq,
1001                                         IRQF_ONESHOT,
1002                                         "rockchip_usb2phy_bvalid", rport);
1003         if (ret) {
1004                 dev_err(rphy->dev, "failed to request otg-bvalid irq handle\n");
1005                 return ret;
1006         }
1007
1008         if (!IS_ERR(rphy->edev)) {
1009                 rport->event_nb.notifier_call = rockchip_otg_event;
1010
1011                 ret = extcon_register_notifier(rphy->edev, EXTCON_USB_HOST,
1012                                                &rport->event_nb);
1013                 if (ret < 0) {
1014                         dev_err(rphy->dev, "register USB HOST notifier failed\n");
1015                         return ret;
1016                 }
1017         }
1018
1019         return 0;
1020 }
1021
1022 static int rockchip_usb2phy_probe(struct platform_device *pdev)
1023 {
1024         struct device *dev = &pdev->dev;
1025         struct device_node *np = dev->of_node;
1026         struct device_node *child_np;
1027         struct phy_provider *provider;
1028         struct rockchip_usb2phy *rphy;
1029         const struct rockchip_usb2phy_cfg *phy_cfgs;
1030         const struct of_device_id *match;
1031         unsigned int reg;
1032         int index, ret;
1033
1034         rphy = devm_kzalloc(dev, sizeof(*rphy), GFP_KERNEL);
1035         if (!rphy)
1036                 return -ENOMEM;
1037
1038         match = of_match_device(dev->driver->of_match_table, dev);
1039         if (!match || !match->data) {
1040                 dev_err(dev, "phy configs are not assigned!\n");
1041                 return -EINVAL;
1042         }
1043
1044         if (!dev->parent || !dev->parent->of_node)
1045                 return -EINVAL;
1046
1047         rphy->grf = syscon_node_to_regmap(dev->parent->of_node);
1048         if (IS_ERR(rphy->grf))
1049                 return PTR_ERR(rphy->grf);
1050
1051         if (of_property_read_u32(np, "reg", &reg)) {
1052                 dev_err(dev, "the reg property is not assigned in %s node\n",
1053                         np->name);
1054                 return -EINVAL;
1055         }
1056
1057         rphy->dev = dev;
1058         phy_cfgs = match->data;
1059         rphy->chg_state = USB_CHG_STATE_UNDEFINED;
1060         rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
1061         platform_set_drvdata(pdev, rphy);
1062
1063         ret = rockchip_usb2phy_extcon_register(rphy);
1064         if (ret)
1065                 return ret;
1066
1067         /* find out a proper config which can be matched with dt. */
1068         index = 0;
1069         while (phy_cfgs[index].reg) {
1070                 if (phy_cfgs[index].reg == reg) {
1071                         rphy->phy_cfg = &phy_cfgs[index];
1072                         break;
1073                 }
1074
1075                 ++index;
1076         }
1077
1078         if (!rphy->phy_cfg) {
1079                 dev_err(dev, "no phy-config can be matched with %s node\n",
1080                         np->name);
1081                 return -EINVAL;
1082         }
1083
1084         rphy->clk = of_clk_get_by_name(np, "phyclk");
1085         if (!IS_ERR(rphy->clk)) {
1086                 clk_prepare_enable(rphy->clk);
1087         } else {
1088                 dev_info(&pdev->dev, "no phyclk specified\n");
1089                 rphy->clk = NULL;
1090         }
1091
1092         ret = rockchip_usb2phy_clk480m_register(rphy);
1093         if (ret) {
1094                 dev_err(dev, "failed to register 480m output clock\n");
1095                 goto disable_clks;
1096         }
1097
1098         if (rphy->phy_cfg->phy_tuning) {
1099                 ret = rphy->phy_cfg->phy_tuning(rphy);
1100                 if (ret)
1101                         goto disable_clks;
1102         }
1103
1104         index = 0;
1105         for_each_available_child_of_node(np, child_np) {
1106                 struct rockchip_usb2phy_port *rport = &rphy->ports[index];
1107                 struct phy *phy;
1108
1109                 /* This driver aims to support both otg-port and host-port */
1110                 if (of_node_cmp(child_np->name, "host-port") &&
1111                     of_node_cmp(child_np->name, "otg-port"))
1112                         goto next_child;
1113
1114                 phy = devm_phy_create(dev, child_np, &rockchip_usb2phy_ops);
1115                 if (IS_ERR(phy)) {
1116                         dev_err(dev, "failed to create phy\n");
1117                         ret = PTR_ERR(phy);
1118                         goto put_child;
1119                 }
1120
1121                 rport->phy = phy;
1122                 phy_set_drvdata(rport->phy, rport);
1123
1124                 /* initialize otg/host port separately */
1125                 if (!of_node_cmp(child_np->name, "host-port")) {
1126                         ret = rockchip_usb2phy_host_port_init(rphy, rport,
1127                                                               child_np);
1128                         if (ret)
1129                                 goto put_child;
1130                 } else {
1131                         ret = rockchip_usb2phy_otg_port_init(rphy, rport,
1132                                                              child_np);
1133                         if (ret)
1134                                 goto put_child;
1135                 }
1136
1137 next_child:
1138                 /* to prevent out of boundary */
1139                 if (++index >= rphy->phy_cfg->num_ports)
1140                         break;
1141         }
1142
1143         provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
1144         return PTR_ERR_OR_ZERO(provider);
1145
1146 put_child:
1147         of_node_put(child_np);
1148 disable_clks:
1149         if (rphy->clk) {
1150                 clk_disable_unprepare(rphy->clk);
1151                 clk_put(rphy->clk);
1152         }
1153         return ret;
1154 }
1155
1156 static int rk3366_usb2phy_tuning(struct rockchip_usb2phy *rphy)
1157 {
1158         unsigned int open_pre_emphasize = 0xffff851f;
1159         unsigned int eye_height_tuning = 0xffff68c8;
1160         unsigned int compensation_tuning = 0xffff026e;
1161         int ret = 0;
1162
1163         /* open HS pre-emphasize to expand HS slew rate for each port. */
1164         ret |= regmap_write(rphy->grf, 0x0780, open_pre_emphasize);
1165         ret |= regmap_write(rphy->grf, 0x079c, eye_height_tuning);
1166         ret |= regmap_write(rphy->grf, 0x07b0, open_pre_emphasize);
1167         ret |= regmap_write(rphy->grf, 0x07cc, eye_height_tuning);
1168
1169         /* compensate default tuning reference relate to ODT and etc. */
1170         ret |= regmap_write(rphy->grf, 0x078c, compensation_tuning);
1171
1172         return ret;
1173 }
1174
1175 static const struct rockchip_usb2phy_cfg rk3366_phy_cfgs[] = {
1176         {
1177                 .reg = 0x700,
1178                 .num_ports      = 2,
1179                 .phy_tuning     = rk3366_usb2phy_tuning,
1180                 .clkout_ctl     = { 0x0724, 15, 15, 1, 0 },
1181                 .port_cfgs      = {
1182                         [USB2PHY_PORT_HOST] = {
1183                                 .phy_sus        = { 0x0728, 15, 0, 0, 0x1d1 },
1184                                 .ls_det_en      = { 0x0680, 4, 4, 0, 1 },
1185                                 .ls_det_st      = { 0x0690, 4, 4, 0, 1 },
1186                                 .ls_det_clr     = { 0x06a0, 4, 4, 0, 1 },
1187                                 .utmi_ls        = { 0x049c, 14, 13, 0, 1 },
1188                                 .utmi_hstdet    = { 0x049c, 12, 12, 0, 1 }
1189                         }
1190                 },
1191         },
1192         { /* sentinel */ }
1193 };
1194
1195 static const struct rockchip_usb2phy_cfg rk3399_phy_cfgs[] = {
1196         {
1197                 .reg            = 0xe450,
1198                 .num_ports      = 2,
1199                 .clkout_ctl     = { 0xe450, 4, 4, 1, 0 },
1200                 .port_cfgs      = {
1201                         [USB2PHY_PORT_OTG] = {
1202                                 .phy_sus        = { 0xe454, 1, 0, 2, 2 },
1203                                 .bvalid_det_en  = { 0xe3c0, 3, 3, 0, 1 },
1204                                 .bvalid_det_st  = { 0xe3e0, 3, 3, 0, 1 },
1205                                 .bvalid_det_clr = { 0xe3d0, 3, 3, 0, 1 },
1206                                 .utmi_avalid    = { 0xe2ac, 7, 7, 0, 1 },
1207                                 .utmi_bvalid    = { 0xe2ac, 12, 12, 0, 1 },
1208                         },
1209                         [USB2PHY_PORT_HOST] = {
1210                                 .phy_sus        = { 0xe458, 1, 0, 0x2, 0x1 },
1211                                 .ls_det_en      = { 0xe3c0, 6, 6, 0, 1 },
1212                                 .ls_det_st      = { 0xe3e0, 6, 6, 0, 1 },
1213                                 .ls_det_clr     = { 0xe3d0, 6, 6, 0, 1 },
1214                                 .utmi_ls        = { 0xe2ac, 22, 21, 0, 1 },
1215                                 .utmi_hstdet    = { 0xe2ac, 23, 23, 0, 1 }
1216                         }
1217                 },
1218                 .chg_det = {
1219                         .opmode         = { 0xe454, 3, 0, 5, 1 },
1220                         .cp_det         = { 0xe2ac, 2, 2, 0, 1 },
1221                         .dcp_det        = { 0xe2ac, 1, 1, 0, 1 },
1222                         .dp_det         = { 0xe2ac, 0, 0, 0, 1 },
1223                         .idm_sink_en    = { 0xe450, 8, 8, 0, 1 },
1224                         .idp_sink_en    = { 0xe450, 7, 7, 0, 1 },
1225                         .idp_src_en     = { 0xe450, 9, 9, 0, 1 },
1226                         .rdm_pdwn_en    = { 0xe450, 10, 10, 0, 1 },
1227                         .vdm_src_en     = { 0xe450, 12, 12, 0, 1 },
1228                         .vdp_src_en     = { 0xe450, 11, 11, 0, 1 },
1229                 },
1230         },
1231         {
1232                 .reg            = 0xe460,
1233                 .num_ports      = 2,
1234                 .clkout_ctl     = { 0xe460, 4, 4, 1, 0 },
1235                 .port_cfgs      = {
1236                         [USB2PHY_PORT_OTG] = {
1237                                 .phy_sus        = { 0xe464, 1, 0, 2, 2 },
1238                                 .bvalid_det_en  = { 0xe3c0, 8, 8, 0, 1 },
1239                                 .bvalid_det_st  = { 0xe3e0, 8, 8, 0, 1 },
1240                                 .bvalid_det_clr = { 0xe3d0, 8, 8, 0, 1 },
1241                                 .utmi_avalid    = { 0xe2ac, 10, 10, 0, 1 },
1242                                 .utmi_bvalid    = { 0xe2ac, 16, 16, 0, 1 },
1243                         },
1244                         [USB2PHY_PORT_HOST] = {
1245                                 .phy_sus        = { 0xe468, 1, 0, 0x2, 0x1 },
1246                                 .ls_det_en      = { 0xe3c0, 11, 11, 0, 1 },
1247                                 .ls_det_st      = { 0xe3e0, 11, 11, 0, 1 },
1248                                 .ls_det_clr     = { 0xe3d0, 11, 11, 0, 1 },
1249                                 .utmi_ls        = { 0xe2ac, 26, 25, 0, 1 },
1250                                 .utmi_hstdet    = { 0xe2ac, 27, 27, 0, 1 }
1251                         }
1252                 },
1253         },
1254         { /* sentinel */ }
1255 };
1256
1257 static const struct of_device_id rockchip_usb2phy_dt_match[] = {
1258         { .compatible = "rockchip,rk3366-usb2phy", .data = &rk3366_phy_cfgs },
1259         { .compatible = "rockchip,rk3399-usb2phy", .data = &rk3399_phy_cfgs },
1260         {}
1261 };
1262 MODULE_DEVICE_TABLE(of, rockchip_usb2phy_dt_match);
1263
1264 static struct platform_driver rockchip_usb2phy_driver = {
1265         .probe          = rockchip_usb2phy_probe,
1266         .driver         = {
1267                 .name   = "rockchip-usb2phy",
1268                 .of_match_table = rockchip_usb2phy_dt_match,
1269         },
1270 };
1271 module_platform_driver(rockchip_usb2phy_driver);
1272
1273 MODULE_AUTHOR("Frank Wang <frank.wang@rock-chips.com>");
1274 MODULE_DESCRIPTION("Rockchip USB2.0 PHY driver");
1275 MODULE_LICENSE("GPL v2");