2 * Rockchip USB2.0 PHY with Innosilicon IP block driver
4 * Copyright (C) 2016 Fuzhou Rockchip Electronics Co., Ltd
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/clk.h>
18 #include <linux/clk-provider.h>
19 #include <linux/delay.h>
20 #include <linux/interrupt.h>
22 #include <linux/gpio/consumer.h>
23 #include <linux/jiffies.h>
24 #include <linux/kernel.h>
25 #include <linux/module.h>
26 #include <linux/mutex.h>
28 #include <linux/of_address.h>
29 #include <linux/of_irq.h>
30 #include <linux/of_platform.h>
31 #include <linux/phy/phy.h>
32 #include <linux/platform_device.h>
33 #include <linux/regmap.h>
34 #include <linux/mfd/syscon.h>
36 #define BIT_WRITEABLE_SHIFT 16
37 #define SCHEDULE_DELAY (60 * HZ)
39 struct rockchip_usb2phy;
41 enum rockchip_usb2phy_port_id {
47 enum rockchip_usb2phy_host_state {
48 PHY_STATE_HS_ONLINE = 0,
49 PHY_STATE_DISCONNECT = 1,
50 PHY_STATE_HS_CONNECT = 2,
51 PHY_STATE_FS_CONNECT = 4,
57 unsigned int bitstart;
63 * struct rockchip_usb2phy_port_cfg: usb-phy port configuration.
64 * @phy_sus: phy suspend register.
65 * @ls_det_en: linestate detection enable register.
66 * @ls_det_st: linestate detection state register.
67 * @ls_det_clr: linestate detection clear register.
68 * @utmi_ls: utmi linestate state register.
69 * @utmi_hstdet: utmi host disconnect register.
71 struct rockchip_usb2phy_port_cfg {
72 struct usb2phy_reg phy_sus;
73 struct usb2phy_reg ls_det_en;
74 struct usb2phy_reg ls_det_st;
75 struct usb2phy_reg ls_det_clr;
76 struct usb2phy_reg utmi_ls;
77 struct usb2phy_reg utmi_hstdet;
81 * struct rockchip_usb2phy_cfg: usb-phy configuration.
82 * @reg: the address offset of grf for usb-phy config.
83 * @num_ports: specify how many ports that the phy has.
84 * @phy_tuning: phy default parameters tunning.
85 * @clkout_ctl: keep on/turn off output clk of phy.
87 struct rockchip_usb2phy_cfg {
89 unsigned int num_ports;
90 int (*phy_tuning)(struct rockchip_usb2phy *);
91 struct usb2phy_reg clkout_ctl;
92 const struct rockchip_usb2phy_port_cfg port_cfgs[USB2PHY_NUM_PORTS];
96 * struct rockchip_usb2phy_port: usb-phy port data.
97 * @port_id: flag for otg port or host port.
98 * @suspended: phy suspended flag.
99 * @ls_irq: IRQ number assigned for linestate detection.
100 * @mutex: for register updating in sm_work.
101 * @sm_work: OTG state machine work.
102 * @phy_cfg: port register configuration, assigned by driver data.
104 struct rockchip_usb2phy_port {
106 unsigned int port_id;
110 struct delayed_work sm_work;
111 const struct rockchip_usb2phy_port_cfg *port_cfg;
115 * struct rockchip_usb2phy: usb2.0 phy driver data.
116 * @grf: General Register Files regmap.
117 * @clk: clock struct of phy input clk.
118 * @clk480m: clock struct of phy output clk.
119 * @clk_hw: clock struct of phy output clk management.
120 * @phy_cfg: phy register configuration, assigned by driver data.
121 * @ports: phy port instance.
123 struct rockchip_usb2phy {
128 struct clk_hw clk480m_hw;
129 const struct rockchip_usb2phy_cfg *phy_cfg;
130 struct rockchip_usb2phy_port ports[USB2PHY_NUM_PORTS];
133 static inline int property_enable(struct rockchip_usb2phy *rphy,
134 const struct usb2phy_reg *reg, bool en)
136 unsigned int val, mask, tmp;
138 tmp = en ? reg->enable : reg->disable;
139 mask = GENMASK(reg->bitend, reg->bitstart);
140 val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT);
142 return regmap_write(rphy->grf, reg->offset, val);
145 static inline bool property_enabled(struct rockchip_usb2phy *rphy,
146 const struct usb2phy_reg *reg)
149 unsigned int tmp, orig;
150 unsigned int mask = GENMASK(reg->bitend, reg->bitstart);
152 ret = regmap_read(rphy->grf, reg->offset, &orig);
156 tmp = (orig & mask) >> reg->bitstart;
157 return tmp == reg->enable;
160 static int rockchip_usb2phy_clk480m_enable(struct clk_hw *hw)
162 struct rockchip_usb2phy *rphy =
163 container_of(hw, struct rockchip_usb2phy, clk480m_hw);
166 /* turn on 480m clk output if it is off */
167 if (!property_enabled(rphy, &rphy->phy_cfg->clkout_ctl)) {
168 ret = property_enable(rphy, &rphy->phy_cfg->clkout_ctl, true);
172 /* waitting for the clk become stable */
179 static void rockchip_usb2phy_clk480m_disable(struct clk_hw *hw)
181 struct rockchip_usb2phy *rphy =
182 container_of(hw, struct rockchip_usb2phy, clk480m_hw);
184 /* turn off 480m clk output */
185 property_enable(rphy, &rphy->phy_cfg->clkout_ctl, false);
188 static int rockchip_usb2phy_clk480m_enabled(struct clk_hw *hw)
190 struct rockchip_usb2phy *rphy =
191 container_of(hw, struct rockchip_usb2phy, clk480m_hw);
193 return property_enabled(rphy, &rphy->phy_cfg->clkout_ctl);
197 rockchip_usb2phy_clk480m_recalc_rate(struct clk_hw *hw,
198 unsigned long parent_rate)
203 static const struct clk_ops rockchip_usb2phy_clkout_ops = {
204 .enable = rockchip_usb2phy_clk480m_enable,
205 .disable = rockchip_usb2phy_clk480m_disable,
206 .is_enabled = rockchip_usb2phy_clk480m_enabled,
207 .recalc_rate = rockchip_usb2phy_clk480m_recalc_rate,
210 static void rockchip_usb2phy_clk480m_unregister(void *data)
212 struct rockchip_usb2phy *rphy = data;
214 of_clk_del_provider(rphy->dev->of_node);
215 clk_unregister(rphy->clk480m);
222 rockchip_usb2phy_clk480m_register(struct rockchip_usb2phy *rphy)
224 struct device_node *node = rphy->dev->of_node;
225 struct clk_init_data init;
226 const char *clk_name;
230 init.name = "clk_usbphy_480m";
231 init.ops = &rockchip_usb2phy_clkout_ops;
233 /* optional override of the clockname */
234 of_property_read_string(node, "clock-output-names", &init.name);
236 rphy->clk = of_clk_get_by_name(node, "phyclk");
237 if (IS_ERR(rphy->clk)) {
239 init.parent_names = NULL;
240 init.num_parents = 0;
242 clk_name = __clk_get_name(rphy->clk);
243 init.parent_names = &clk_name;
244 init.num_parents = 1;
247 rphy->clk480m_hw.init = &init;
249 /* register the clock */
250 rphy->clk480m = clk_register(rphy->dev, &rphy->clk480m_hw);
251 if (IS_ERR(rphy->clk480m)) {
252 ret = PTR_ERR(rphy->clk480m);
256 ret = of_clk_add_provider(node, of_clk_src_simple_get, rphy->clk480m);
258 goto err_clk_provider;
260 ret = devm_add_action(rphy->dev, rockchip_usb2phy_clk480m_unregister,
263 goto err_unreg_action;
268 of_clk_del_provider(node);
270 clk_unregister(rphy->clk480m);
277 static int rockchip_usb2phy_init(struct phy *phy)
279 struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
280 struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
283 if (rport->port_id == USB2PHY_PORT_HOST) {
284 /* clear linestate and enable linestate detect irq */
285 mutex_lock(&rport->mutex);
287 ret = property_enable(rphy, &rport->port_cfg->ls_det_clr, true);
289 mutex_unlock(&rport->mutex);
293 ret = property_enable(rphy, &rport->port_cfg->ls_det_en, true);
295 mutex_unlock(&rport->mutex);
299 mutex_unlock(&rport->mutex);
300 schedule_delayed_work(&rport->sm_work, SCHEDULE_DELAY);
306 static int rockchip_usb2phy_power_on(struct phy *phy)
308 struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
309 struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
312 dev_dbg(&rport->phy->dev, "port power on\n");
314 if (!rport->suspended)
317 ret = clk_prepare_enable(rphy->clk480m);
321 ret = property_enable(rphy, &rport->port_cfg->phy_sus, false);
325 rport->suspended = false;
329 static int rockchip_usb2phy_power_off(struct phy *phy)
331 struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
332 struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
335 dev_dbg(&rport->phy->dev, "port power off\n");
337 if (rport->suspended)
340 ret = property_enable(rphy, &rport->port_cfg->phy_sus, true);
344 rport->suspended = true;
345 clk_disable_unprepare(rphy->clk480m);
350 static int rockchip_usb2phy_exit(struct phy *phy)
352 struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
354 if (rport->port_id == USB2PHY_PORT_HOST)
355 cancel_delayed_work_sync(&rport->sm_work);
360 static const struct phy_ops rockchip_usb2phy_ops = {
361 .init = rockchip_usb2phy_init,
362 .exit = rockchip_usb2phy_exit,
363 .power_on = rockchip_usb2phy_power_on,
364 .power_off = rockchip_usb2phy_power_off,
365 .owner = THIS_MODULE,
369 * The function manage host-phy port state and suspend/resume phy port
372 * we rely on utmi_linestate and utmi_hostdisconnect to identify whether
373 * FS/HS is disconnect or not. Besides, we do not need care it is FS
374 * disconnected or HS disconnected, actually, we just only need get the
375 * device is disconnected at last through rearm the delayed work,
376 * to suspend the phy port in _PHY_STATE_DISCONNECT_ case.
378 * NOTE: It may invoke *phy_powr_off or *phy_power_on which will invoke
379 * some clk related APIs, so do not invoke it from interrupt context directly.
381 static void rockchip_usb2phy_sm_work(struct work_struct *work)
383 struct rockchip_usb2phy_port *rport =
384 container_of(work, struct rockchip_usb2phy_port, sm_work.work);
385 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
386 unsigned int sh = rport->port_cfg->utmi_hstdet.bitend -
387 rport->port_cfg->utmi_hstdet.bitstart + 1;
388 unsigned int ul, uhd, state;
389 unsigned int ul_mask, uhd_mask;
392 mutex_lock(&rport->mutex);
394 ret = regmap_read(rphy->grf, rport->port_cfg->utmi_ls.offset, &ul);
398 ret = regmap_read(rphy->grf, rport->port_cfg->utmi_hstdet.offset,
403 uhd_mask = GENMASK(rport->port_cfg->utmi_hstdet.bitend,
404 rport->port_cfg->utmi_hstdet.bitstart);
405 ul_mask = GENMASK(rport->port_cfg->utmi_ls.bitend,
406 rport->port_cfg->utmi_ls.bitstart);
408 /* stitch on utmi_ls and utmi_hstdet as phy state */
409 state = ((uhd & uhd_mask) >> rport->port_cfg->utmi_hstdet.bitstart) |
410 (((ul & ul_mask) >> rport->port_cfg->utmi_ls.bitstart) << sh);
413 case PHY_STATE_HS_ONLINE:
414 dev_dbg(&rport->phy->dev, "HS online\n");
416 case PHY_STATE_FS_CONNECT:
418 * For FS device, the online state share with connect state
419 * from utmi_ls and utmi_hstdet register, so we distinguish
420 * them via suspended flag.
422 if (!rport->suspended) {
423 dev_dbg(&rport->phy->dev, "FS online\n");
427 case PHY_STATE_HS_CONNECT:
428 if (rport->suspended) {
429 dev_dbg(&rport->phy->dev, "HS/FS connected\n");
430 rockchip_usb2phy_power_on(rport->phy);
431 rport->suspended = false;
434 case PHY_STATE_DISCONNECT:
435 if (!rport->suspended) {
436 dev_dbg(&rport->phy->dev, "HS/FS disconnected\n");
437 rockchip_usb2phy_power_off(rport->phy);
438 rport->suspended = true;
442 * activate the linestate detection to get the next device
445 property_enable(rphy, &rport->port_cfg->ls_det_clr, true);
446 property_enable(rphy, &rport->port_cfg->ls_det_en, true);
449 * we don't need to rearm the delayed work when the phy port
452 mutex_unlock(&rport->mutex);
455 dev_dbg(&rport->phy->dev, "unknown phy state\n");
460 mutex_unlock(&rport->mutex);
461 schedule_delayed_work(&rport->sm_work, SCHEDULE_DELAY);
464 static irqreturn_t rockchip_usb2phy_linestate_irq(int irq, void *data)
466 struct rockchip_usb2phy_port *rport = data;
467 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
469 if (!property_enabled(rphy, &rport->port_cfg->ls_det_st))
472 mutex_lock(&rport->mutex);
474 /* disable linestate detect irq and clear its status */
475 property_enable(rphy, &rport->port_cfg->ls_det_en, false);
476 property_enable(rphy, &rport->port_cfg->ls_det_clr, true);
478 mutex_unlock(&rport->mutex);
481 * In this case for host phy port, a new device is plugged in,
482 * meanwhile, if the phy port is suspended, we need rearm the work to
483 * resume it and mange its states; otherwise, we do nothing about that.
485 if (rport->suspended && rport->port_id == USB2PHY_PORT_HOST)
486 rockchip_usb2phy_sm_work(&rport->sm_work.work);
491 static int rockchip_usb2phy_host_port_init(struct rockchip_usb2phy *rphy,
492 struct rockchip_usb2phy_port *rport,
493 struct device_node *child_np)
497 rport->port_id = USB2PHY_PORT_HOST;
498 rport->port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_HOST];
499 rport->suspended = true;
501 mutex_init(&rport->mutex);
502 INIT_DELAYED_WORK(&rport->sm_work, rockchip_usb2phy_sm_work);
504 rport->ls_irq = of_irq_get_byname(child_np, "linestate");
505 if (rport->ls_irq < 0) {
506 dev_err(rphy->dev, "no linestate irq provided\n");
507 return rport->ls_irq;
510 ret = devm_request_threaded_irq(rphy->dev, rport->ls_irq, NULL,
511 rockchip_usb2phy_linestate_irq,
513 "rockchip_usb2phy", rport);
515 dev_err(rphy->dev, "failed to request irq handle\n");
522 static int rockchip_usb2phy_probe(struct platform_device *pdev)
524 struct device *dev = &pdev->dev;
525 struct device_node *np = dev->of_node;
526 struct device_node *child_np;
527 struct phy_provider *provider;
528 struct rockchip_usb2phy *rphy;
529 const struct rockchip_usb2phy_cfg *phy_cfgs;
530 const struct of_device_id *match;
534 rphy = devm_kzalloc(dev, sizeof(*rphy), GFP_KERNEL);
538 match = of_match_device(dev->driver->of_match_table, dev);
539 if (!match || !match->data) {
540 dev_err(dev, "phy configs are not assigned!\n");
544 if (!dev->parent || !dev->parent->of_node)
547 rphy->grf = syscon_node_to_regmap(dev->parent->of_node);
548 if (IS_ERR(rphy->grf))
549 return PTR_ERR(rphy->grf);
551 if (of_property_read_u32(np, "reg", ®)) {
552 dev_err(dev, "the reg property is not assigned in %s node\n",
558 phy_cfgs = match->data;
559 platform_set_drvdata(pdev, rphy);
561 /* find out a proper config which can be matched with dt. */
563 while (phy_cfgs[index].reg) {
564 if (phy_cfgs[index].reg == reg) {
565 rphy->phy_cfg = &phy_cfgs[index];
572 if (!rphy->phy_cfg) {
573 dev_err(dev, "no phy-config can be matched with %s node\n",
578 ret = rockchip_usb2phy_clk480m_register(rphy);
580 dev_err(dev, "failed to register 480m output clock\n");
584 if (rphy->phy_cfg->phy_tuning) {
585 ret = rphy->phy_cfg->phy_tuning(rphy);
591 for_each_available_child_of_node(np, child_np) {
592 struct rockchip_usb2phy_port *rport = &rphy->ports[index];
596 * This driver aim to support both otg-port and host-port,
597 * but unfortunately, the otg part is not ready in current,
598 * so this comments and below codes are interim, which should
599 * be changed after otg-port is supplied soon.
601 if (of_node_cmp(child_np->name, "host-port"))
604 phy = devm_phy_create(dev, child_np, &rockchip_usb2phy_ops);
606 dev_err(dev, "failed to create phy\n");
612 phy_set_drvdata(rport->phy, rport);
614 ret = rockchip_usb2phy_host_port_init(rphy, rport, child_np);
619 /* to prevent out of boundary */
620 if (++index >= rphy->phy_cfg->num_ports)
624 provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
625 return PTR_ERR_OR_ZERO(provider);
628 of_node_put(child_np);
632 static int rk3366_usb2phy_tuning(struct rockchip_usb2phy *rphy)
634 unsigned int open_pre_emphasize = 0xffff851f;
635 unsigned int eye_height_tuning = 0xffff68c8;
636 unsigned int compensation_tuning = 0xffff026e;
639 /* open HS pre-emphasize to expand HS slew rate for each port. */
640 ret |= regmap_write(rphy->grf, 0x0780, open_pre_emphasize);
641 ret |= regmap_write(rphy->grf, 0x079c, eye_height_tuning);
642 ret |= regmap_write(rphy->grf, 0x07b0, open_pre_emphasize);
643 ret |= regmap_write(rphy->grf, 0x07cc, eye_height_tuning);
645 /* compensate default tuning reference relate to ODT and etc. */
646 ret |= regmap_write(rphy->grf, 0x078c, compensation_tuning);
651 static const struct rockchip_usb2phy_cfg rk3366_phy_cfgs[] = {
655 .phy_tuning = rk3366_usb2phy_tuning,
656 .clkout_ctl = { 0x0724, 15, 15, 1, 0 },
658 [USB2PHY_PORT_HOST] = {
659 .phy_sus = { 0x0728, 15, 0, 0, 0x1d1 },
660 .ls_det_en = { 0x0680, 4, 4, 0, 1 },
661 .ls_det_st = { 0x0690, 4, 4, 0, 1 },
662 .ls_det_clr = { 0x06a0, 4, 4, 0, 1 },
663 .utmi_ls = { 0x049c, 14, 13, 0, 1 },
664 .utmi_hstdet = { 0x049c, 12, 12, 0, 1 }
671 static const struct of_device_id rockchip_usb2phy_dt_match[] = {
672 { .compatible = "rockchip,rk3366-usb2phy", .data = &rk3366_phy_cfgs },
675 MODULE_DEVICE_TABLE(of, rockchip_usb2phy_dt_match);
677 static struct platform_driver rockchip_usb2phy_driver = {
678 .probe = rockchip_usb2phy_probe,
680 .name = "rockchip-usb2phy",
681 .of_match_table = rockchip_usb2phy_dt_match,
684 module_platform_driver(rockchip_usb2phy_driver);
686 MODULE_AUTHOR("Frank Wang <frank.wang@rock-chips.com>");
687 MODULE_DESCRIPTION("Rockchip USB2.0 PHY driver");
688 MODULE_LICENSE("GPL v2");