2 * Rockchip USB2.0 PHY with Innosilicon IP block driver
4 * Copyright (C) 2016 Fuzhou Rockchip Electronics Co., Ltd
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/clk.h>
18 #include <linux/clk-provider.h>
19 #include <linux/delay.h>
20 #include <linux/extcon.h>
21 #include <linux/interrupt.h>
23 #include <linux/gpio/consumer.h>
24 #include <linux/jiffies.h>
25 #include <linux/kernel.h>
26 #include <linux/module.h>
27 #include <linux/mutex.h>
29 #include <linux/of_address.h>
30 #include <linux/of_irq.h>
31 #include <linux/of_platform.h>
32 #include <linux/phy/phy.h>
33 #include <linux/platform_device.h>
34 #include <linux/power_supply.h>
35 #include <linux/regmap.h>
36 #include <linux/mfd/syscon.h>
37 #include <linux/usb/of.h>
38 #include <linux/usb/otg.h>
39 #include <linux/wakelock.h>
41 #define BIT_WRITEABLE_SHIFT 16
42 #define SCHEDULE_DELAY (60 * HZ)
43 #define OTG_SCHEDULE_DELAY (2 * HZ)
45 struct rockchip_usb2phy;
47 enum rockchip_usb2phy_port_id {
53 enum rockchip_usb2phy_host_state {
54 PHY_STATE_HS_ONLINE = 0,
55 PHY_STATE_DISCONNECT = 1,
56 PHY_STATE_CONNECT = 2,
57 PHY_STATE_FS_LS_ONLINE = 4,
61 * Different states involved in USB charger detection.
62 * USB_CHG_STATE_UNDEFINED USB charger is not connected or detection
63 * process is not yet started.
64 * USB_CHG_STATE_WAIT_FOR_DCD Waiting for Data pins contact.
65 * USB_CHG_STATE_DCD_DONE Data pin contact is detected.
66 * USB_CHG_STATE_PRIMARY_DONE Primary detection is completed (Detects
67 * between SDP and DCP/CDP).
68 * USB_CHG_STATE_SECONDARY_DONE Secondary detection is completed (Detects
69 * between DCP and CDP).
70 * USB_CHG_STATE_DETECTED USB charger type is determined.
73 USB_CHG_STATE_UNDEFINED = 0,
74 USB_CHG_STATE_WAIT_FOR_DCD,
75 USB_CHG_STATE_DCD_DONE,
76 USB_CHG_STATE_PRIMARY_DONE,
77 USB_CHG_STATE_SECONDARY_DONE,
78 USB_CHG_STATE_DETECTED,
81 static const unsigned int rockchip_usb2phy_extcon_cable[] = {
95 unsigned int bitstart;
101 * struct rockchip_chg_det_reg: usb charger detect registers
102 * @cp_det: charging port detected successfully.
103 * @dcp_det: dedicated charging port detected successfully.
104 * @dp_det: assert data pin connect successfully.
105 * @idm_sink_en: open dm sink curren.
106 * @idp_sink_en: open dp sink current.
107 * @idp_src_en: open dm source current.
108 * @rdm_pdwn_en: open dm pull down resistor.
109 * @vdm_src_en: open dm voltage source.
110 * @vdp_src_en: open dp voltage source.
111 * @opmode: utmi operational mode.
113 struct rockchip_chg_det_reg {
114 struct usb2phy_reg cp_det;
115 struct usb2phy_reg dcp_det;
116 struct usb2phy_reg dp_det;
117 struct usb2phy_reg idm_sink_en;
118 struct usb2phy_reg idp_sink_en;
119 struct usb2phy_reg idp_src_en;
120 struct usb2phy_reg rdm_pdwn_en;
121 struct usb2phy_reg vdm_src_en;
122 struct usb2phy_reg vdp_src_en;
123 struct usb2phy_reg opmode;
127 * struct rockchip_usb2phy_port_cfg: usb-phy port configuration.
128 * @phy_sus: phy suspend register.
129 * @bvalid_det_en: vbus valid rise detection enable register.
130 * @bvalid_det_st: vbus valid rise detection status register.
131 * @bvalid_det_clr: vbus valid rise detection clear register.
132 * @ls_det_en: linestate detection enable register.
133 * @ls_det_st: linestate detection state register.
134 * @ls_det_clr: linestate detection clear register.
135 * @idfall_det_en: id fall detection enable register.
136 * @idfall_det_st: id fall detection state register.
137 * @idfall_det_clr: id fall detection clear register.
138 * @idrise_det_en: id rise detection enable register.
139 * @idrise_det_st: id rise detection state register.
140 * @idrise_det_clr: id rise detection clear register.
141 * @utmi_avalid: utmi vbus avalid status register.
142 * @utmi_bvalid: utmi vbus bvalid status register.
143 * @utmi_iddig: otg port id pin status register.
144 * @utmi_ls: utmi linestate state register.
145 * @utmi_hstdet: utmi host disconnect register.
147 struct rockchip_usb2phy_port_cfg {
148 struct usb2phy_reg phy_sus;
149 struct usb2phy_reg bvalid_det_en;
150 struct usb2phy_reg bvalid_det_st;
151 struct usb2phy_reg bvalid_det_clr;
152 struct usb2phy_reg ls_det_en;
153 struct usb2phy_reg ls_det_st;
154 struct usb2phy_reg ls_det_clr;
155 struct usb2phy_reg idfall_det_en;
156 struct usb2phy_reg idfall_det_st;
157 struct usb2phy_reg idfall_det_clr;
158 struct usb2phy_reg idrise_det_en;
159 struct usb2phy_reg idrise_det_st;
160 struct usb2phy_reg idrise_det_clr;
161 struct usb2phy_reg utmi_avalid;
162 struct usb2phy_reg utmi_bvalid;
163 struct usb2phy_reg utmi_iddig;
164 struct usb2phy_reg utmi_ls;
165 struct usb2phy_reg utmi_hstdet;
169 * struct rockchip_usb2phy_cfg: usb-phy configuration.
170 * @reg: the address offset of grf for usb-phy config.
171 * @num_ports: specify how many ports that the phy has.
172 * @phy_tuning: phy default parameters tunning.
173 * @clkout_ctl: keep on/turn off output clk of phy.
174 * @chg_det: charger detection registers.
176 struct rockchip_usb2phy_cfg {
178 unsigned int num_ports;
179 int (*phy_tuning)(struct rockchip_usb2phy *);
180 struct usb2phy_reg clkout_ctl;
181 const struct rockchip_usb2phy_port_cfg port_cfgs[USB2PHY_NUM_PORTS];
182 const struct rockchip_chg_det_reg chg_det;
186 * struct rockchip_usb2phy_port: usb-phy port data.
187 * @port_id: flag for otg port or host port.
188 * @perip_connected: flag for periphyeral connect status.
189 * @suspended: phy suspended flag.
190 * @utmi_avalid: utmi avalid status usage flag.
191 * true - use avalid to get vbus status
192 * flase - use bvalid to get vbus status
193 * @vbus_attached: otg device vbus status.
194 * @vbus_always_on: otg vbus is always powered on.
195 * @bvalid_irq: IRQ number assigned for vbus valid rise detection.
196 * @ls_irq: IRQ number assigned for linestate detection.
197 * @id_irq: IRQ number assigned for id fall or rise detection.
198 * @mutex: for register updating in sm_work.
199 * @chg_work: charge detect work.
200 * @otg_sm_work: OTG state machine work.
201 * @sm_work: HOST state machine work.
202 * @phy_cfg: port register configuration, assigned by driver data.
203 * @event_nb: hold event notification callback.
204 * @wakelock: wake lock struct to prevent system suspend
205 * when USB is active.
206 * @state: define OTG enumeration states before device reset.
207 * @mode: the dr_mode of the controller.
209 struct rockchip_usb2phy_port {
211 unsigned int port_id;
212 bool perip_connected;
221 struct delayed_work chg_work;
222 struct delayed_work otg_sm_work;
223 struct delayed_work sm_work;
224 const struct rockchip_usb2phy_port_cfg *port_cfg;
225 struct notifier_block event_nb;
226 struct wake_lock wakelock;
227 enum usb_otg_state state;
228 enum usb_dr_mode mode;
232 * struct rockchip_usb2phy: usb2.0 phy driver data.
233 * @grf: General Register Files regmap.
234 * @clk: clock struct of phy input clk.
235 * @clk480m: clock struct of phy output clk.
236 * @clk_hw: clock struct of phy output clk management.
237 * @chg_state: states involved in USB charger detection.
238 * @chg_type: USB charger types.
239 * @dcd_retries: The retry count used to track Data contact
241 * @edev_self: represent the source of extcon.
242 * @edev: extcon device for notification registration
243 * @phy_cfg: phy register configuration, assigned by driver data.
244 * @ports: phy port instance.
246 struct rockchip_usb2phy {
251 struct clk_hw clk480m_hw;
252 enum usb_chg_state chg_state;
253 enum power_supply_type chg_type;
257 struct extcon_dev *edev;
258 const struct rockchip_usb2phy_cfg *phy_cfg;
259 struct rockchip_usb2phy_port ports[USB2PHY_NUM_PORTS];
262 static inline int property_enable(struct rockchip_usb2phy *rphy,
263 const struct usb2phy_reg *reg, bool en)
265 unsigned int val, mask, tmp;
267 tmp = en ? reg->enable : reg->disable;
268 mask = GENMASK(reg->bitend, reg->bitstart);
269 val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT);
271 return regmap_write(rphy->grf, reg->offset, val);
274 static inline bool property_enabled(struct rockchip_usb2phy *rphy,
275 const struct usb2phy_reg *reg)
278 unsigned int tmp, orig;
279 unsigned int mask = GENMASK(reg->bitend, reg->bitstart);
281 ret = regmap_read(rphy->grf, reg->offset, &orig);
285 tmp = (orig & mask) >> reg->bitstart;
286 return tmp == reg->enable;
289 static int rockchip_usb2phy_clk480m_prepare(struct clk_hw *hw)
291 struct rockchip_usb2phy *rphy =
292 container_of(hw, struct rockchip_usb2phy, clk480m_hw);
295 /* turn on 480m clk output if it is off */
296 if (!property_enabled(rphy, &rphy->phy_cfg->clkout_ctl)) {
297 ret = property_enable(rphy, &rphy->phy_cfg->clkout_ctl, true);
301 /* waiting for the clk become stable */
302 usleep_range(1200, 1300);
308 static void rockchip_usb2phy_clk480m_unprepare(struct clk_hw *hw)
310 struct rockchip_usb2phy *rphy =
311 container_of(hw, struct rockchip_usb2phy, clk480m_hw);
313 /* turn off 480m clk output */
314 property_enable(rphy, &rphy->phy_cfg->clkout_ctl, false);
317 static int rockchip_usb2phy_clk480m_prepared(struct clk_hw *hw)
319 struct rockchip_usb2phy *rphy =
320 container_of(hw, struct rockchip_usb2phy, clk480m_hw);
322 return property_enabled(rphy, &rphy->phy_cfg->clkout_ctl);
326 rockchip_usb2phy_clk480m_recalc_rate(struct clk_hw *hw,
327 unsigned long parent_rate)
332 static const struct clk_ops rockchip_usb2phy_clkout_ops = {
333 .prepare = rockchip_usb2phy_clk480m_prepare,
334 .unprepare = rockchip_usb2phy_clk480m_unprepare,
335 .is_prepared = rockchip_usb2phy_clk480m_prepared,
336 .recalc_rate = rockchip_usb2phy_clk480m_recalc_rate,
339 static void rockchip_usb2phy_clk480m_unregister(void *data)
341 struct rockchip_usb2phy *rphy = data;
343 of_clk_del_provider(rphy->dev->of_node);
344 clk_unregister(rphy->clk480m);
348 rockchip_usb2phy_clk480m_register(struct rockchip_usb2phy *rphy)
350 struct device_node *node = rphy->dev->of_node;
351 struct clk_init_data init;
352 const char *clk_name;
356 init.name = "clk_usbphy_480m";
357 init.ops = &rockchip_usb2phy_clkout_ops;
359 /* optional override of the clockname */
360 of_property_read_string(node, "clock-output-names", &init.name);
363 clk_name = __clk_get_name(rphy->clk);
364 init.parent_names = &clk_name;
365 init.num_parents = 1;
367 init.parent_names = NULL;
368 init.num_parents = 0;
371 rphy->clk480m_hw.init = &init;
373 /* register the clock */
374 rphy->clk480m = clk_register(rphy->dev, &rphy->clk480m_hw);
375 if (IS_ERR(rphy->clk480m)) {
376 ret = PTR_ERR(rphy->clk480m);
380 ret = of_clk_add_provider(node, of_clk_src_simple_get, rphy->clk480m);
382 goto err_clk_provider;
384 ret = devm_add_action(rphy->dev, rockchip_usb2phy_clk480m_unregister,
387 goto err_unreg_action;
392 of_clk_del_provider(node);
394 clk_unregister(rphy->clk480m);
399 static int rockchip_usb2phy_extcon_register(struct rockchip_usb2phy *rphy)
402 struct device_node *node = rphy->dev->of_node;
403 struct extcon_dev *edev;
405 if (of_property_read_bool(node, "extcon")) {
406 edev = extcon_get_edev_by_phandle(rphy->dev, 0);
408 if (PTR_ERR(edev) != -EPROBE_DEFER)
409 dev_err(rphy->dev, "Invalid or missing extcon\n");
410 return PTR_ERR(edev);
413 /* Initialize extcon device */
414 edev = devm_extcon_dev_allocate(rphy->dev,
415 rockchip_usb2phy_extcon_cable);
420 ret = devm_extcon_dev_register(rphy->dev, edev);
422 dev_err(rphy->dev, "failed to register extcon device\n");
426 rphy->edev_self = true;
434 static int rockchip_usb2phy_init(struct phy *phy)
436 struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
437 struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
440 mutex_lock(&rport->mutex);
442 if (rport->port_id == USB2PHY_PORT_OTG) {
443 if (rport->mode != USB_DR_MODE_HOST &&
444 !rport->vbus_always_on) {
445 /* clear bvalid status and enable bvalid detect irq */
446 ret = property_enable(rphy,
453 ret = property_enable(rphy,
460 if (rphy->edev_self) {
461 ret = property_enable(rphy,
468 ret = property_enable(rphy,
475 ret = property_enable(rphy,
482 ret = property_enable(rphy,
490 schedule_delayed_work(&rport->otg_sm_work,
493 /* If OTG works in host only mode, do nothing. */
494 dev_dbg(&rport->phy->dev, "mode %d\n", rport->mode);
496 } else if (rport->port_id == USB2PHY_PORT_HOST) {
497 /* clear linestate and enable linestate detect irq */
498 ret = property_enable(rphy, &rport->port_cfg->ls_det_clr, true);
502 ret = property_enable(rphy, &rport->port_cfg->ls_det_en, true);
506 schedule_delayed_work(&rport->sm_work, SCHEDULE_DELAY);
510 mutex_unlock(&rport->mutex);
514 static int rockchip_usb2phy_power_on(struct phy *phy)
516 struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
517 struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
520 dev_dbg(&rport->phy->dev, "port power on\n");
522 if (!rport->suspended)
525 ret = clk_prepare_enable(rphy->clk480m);
529 ret = property_enable(rphy, &rport->port_cfg->phy_sus, false);
533 rport->suspended = false;
537 static int rockchip_usb2phy_power_off(struct phy *phy)
539 struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
540 struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
543 dev_dbg(&rport->phy->dev, "port power off\n");
545 if (rport->suspended)
548 ret = property_enable(rphy, &rport->port_cfg->phy_sus, true);
552 rport->suspended = true;
553 clk_disable_unprepare(rphy->clk480m);
558 static int rockchip_usb2phy_exit(struct phy *phy)
560 struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
562 if (rport->port_id == USB2PHY_PORT_OTG &&
563 rport->mode != USB_DR_MODE_HOST &&
564 !rport->vbus_always_on)
565 cancel_delayed_work_sync(&rport->chg_work);
566 else if (rport->port_id == USB2PHY_PORT_HOST)
567 cancel_delayed_work_sync(&rport->sm_work);
572 static const struct phy_ops rockchip_usb2phy_ops = {
573 .init = rockchip_usb2phy_init,
574 .exit = rockchip_usb2phy_exit,
575 .power_on = rockchip_usb2phy_power_on,
576 .power_off = rockchip_usb2phy_power_off,
577 .owner = THIS_MODULE,
580 static void rockchip_usb2phy_otg_sm_work(struct work_struct *work)
582 struct rockchip_usb2phy_port *rport =
583 container_of(work, struct rockchip_usb2phy_port,
585 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
586 static unsigned int cable;
590 if (rport->utmi_avalid)
591 rport->vbus_attached =
592 property_enabled(rphy, &rport->port_cfg->utmi_avalid);
594 rport->vbus_attached =
595 property_enabled(rphy, &rport->port_cfg->utmi_bvalid);
598 delay = OTG_SCHEDULE_DELAY;
600 dev_dbg(&rport->phy->dev, "%s otg sm work\n",
601 usb_otg_state_string(rport->state));
603 switch (rport->state) {
604 case OTG_STATE_UNDEFINED:
605 rport->state = OTG_STATE_B_IDLE;
606 if (!rport->vbus_attached)
607 rockchip_usb2phy_power_off(rport->phy);
609 case OTG_STATE_B_IDLE:
610 if (extcon_get_cable_state_(rphy->edev, EXTCON_USB_HOST) > 0 ||
611 extcon_get_cable_state_(rphy->edev,
612 EXTCON_USB_VBUS_EN) > 0) {
613 dev_dbg(&rport->phy->dev, "usb otg host connect\n");
614 rport->state = OTG_STATE_A_HOST;
615 rockchip_usb2phy_power_on(rport->phy);
617 } else if (rport->vbus_attached) {
618 dev_dbg(&rport->phy->dev, "vbus_attach\n");
619 switch (rphy->chg_state) {
620 case USB_CHG_STATE_UNDEFINED:
621 schedule_delayed_work(&rport->chg_work, 0);
623 case USB_CHG_STATE_DETECTED:
624 switch (rphy->chg_type) {
625 case POWER_SUPPLY_TYPE_USB:
626 dev_dbg(&rport->phy->dev,
627 "sdp cable is connecetd\n");
628 wake_lock(&rport->wakelock);
629 cable = EXTCON_CHG_USB_SDP;
630 rockchip_usb2phy_power_on(rport->phy);
631 rport->state = OTG_STATE_B_PERIPHERAL;
632 rport->perip_connected = true;
635 case POWER_SUPPLY_TYPE_USB_DCP:
636 dev_dbg(&rport->phy->dev,
637 "dcp cable is connecetd\n");
638 cable = EXTCON_CHG_USB_DCP;
639 rockchip_usb2phy_power_off(rport->phy);
642 case POWER_SUPPLY_TYPE_USB_CDP:
643 dev_dbg(&rport->phy->dev,
644 "cdp cable is connecetd\n");
645 wake_lock(&rport->wakelock);
646 cable = EXTCON_CHG_USB_CDP;
647 rockchip_usb2phy_power_on(rport->phy);
648 rport->state = OTG_STATE_B_PERIPHERAL;
649 rport->perip_connected = true;
652 case POWER_SUPPLY_TYPE_USB_FLOATING:
653 dev_dbg(&rport->phy->dev,
654 "floating cable is connecetd\n");
655 cable = EXTCON_CHG_USB_DCP;
656 rockchip_usb2phy_power_off(rport->phy);
667 rphy->chg_state = USB_CHG_STATE_UNDEFINED;
668 rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
671 case OTG_STATE_B_PERIPHERAL:
672 if (!rport->vbus_attached) {
673 dev_dbg(&rport->phy->dev, "usb disconnect\n");
674 rphy->chg_state = USB_CHG_STATE_UNDEFINED;
675 rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
676 rport->state = OTG_STATE_B_IDLE;
677 rport->perip_connected = false;
679 rockchip_usb2phy_power_off(rport->phy);
680 wake_unlock(&rport->wakelock);
685 case OTG_STATE_A_HOST:
686 if (extcon_get_cable_state_(rphy->edev, EXTCON_USB_HOST) == 0) {
687 dev_dbg(&rport->phy->dev, "usb otg host disconnect\n");
688 rport->state = OTG_STATE_B_IDLE;
689 rockchip_usb2phy_power_off(rport->phy);
696 if (extcon_get_state(rphy->edev, cable) != rport->vbus_attached)
697 extcon_set_cable_state_(rphy->edev,
698 cable, rport->vbus_attached);
700 if (rphy->edev_self &&
701 (extcon_get_state(rphy->edev, EXTCON_USB) !=
702 rport->perip_connected))
703 extcon_set_cable_state_(rphy->edev,
705 rport->perip_connected);
708 schedule_delayed_work(&rport->otg_sm_work, delay);
711 static const char *chg_to_string(enum power_supply_type chg_type)
714 case POWER_SUPPLY_TYPE_USB:
715 return "USB_SDP_CHARGER";
716 case POWER_SUPPLY_TYPE_USB_DCP:
717 return "USB_DCP_CHARGER";
718 case POWER_SUPPLY_TYPE_USB_CDP:
719 return "USB_CDP_CHARGER";
720 case POWER_SUPPLY_TYPE_USB_FLOATING:
721 return "USB_FLOATING_CHARGER";
723 return "INVALID_CHARGER";
727 static void rockchip_chg_enable_dcd(struct rockchip_usb2phy *rphy,
730 property_enable(rphy, &rphy->phy_cfg->chg_det.rdm_pdwn_en, en);
731 property_enable(rphy, &rphy->phy_cfg->chg_det.idp_src_en, en);
734 static void rockchip_chg_enable_primary_det(struct rockchip_usb2phy *rphy,
737 property_enable(rphy, &rphy->phy_cfg->chg_det.vdp_src_en, en);
738 property_enable(rphy, &rphy->phy_cfg->chg_det.idm_sink_en, en);
741 static void rockchip_chg_enable_secondary_det(struct rockchip_usb2phy *rphy,
744 property_enable(rphy, &rphy->phy_cfg->chg_det.vdm_src_en, en);
745 property_enable(rphy, &rphy->phy_cfg->chg_det.idp_sink_en, en);
748 #define CHG_DCD_POLL_TIME (100 * HZ / 1000)
749 #define CHG_DCD_MAX_RETRIES 6
750 #define CHG_PRIMARY_DET_TIME (40 * HZ / 1000)
751 #define CHG_SECONDARY_DET_TIME (40 * HZ / 1000)
752 static void rockchip_chg_detect_work(struct work_struct *work)
754 struct rockchip_usb2phy_port *rport =
755 container_of(work, struct rockchip_usb2phy_port, chg_work.work);
756 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
757 bool is_dcd, tmout, vout;
760 dev_dbg(&rport->phy->dev, "chg detection work state = %d\n",
762 switch (rphy->chg_state) {
763 case USB_CHG_STATE_UNDEFINED:
764 if (!rport->suspended)
765 rockchip_usb2phy_power_off(rport->phy);
766 /* put the controller in non-driving mode */
767 property_enable(rphy, &rphy->phy_cfg->chg_det.opmode, false);
768 /* Start DCD processing stage 1 */
769 rockchip_chg_enable_dcd(rphy, true);
770 rphy->chg_state = USB_CHG_STATE_WAIT_FOR_DCD;
771 rphy->dcd_retries = 0;
772 rphy->primary_retries = 0;
773 delay = CHG_DCD_POLL_TIME;
775 case USB_CHG_STATE_WAIT_FOR_DCD:
776 /* get data contact detection status */
777 is_dcd = property_enabled(rphy, &rphy->phy_cfg->chg_det.dp_det);
778 tmout = ++rphy->dcd_retries == CHG_DCD_MAX_RETRIES;
780 if (is_dcd || tmout) {
782 /* Turn off DCD circuitry */
783 rockchip_chg_enable_dcd(rphy, false);
784 /* Voltage Source on DP, Probe on DM */
785 rockchip_chg_enable_primary_det(rphy, true);
786 delay = CHG_PRIMARY_DET_TIME;
787 rphy->chg_state = USB_CHG_STATE_DCD_DONE;
790 delay = CHG_DCD_POLL_TIME;
793 case USB_CHG_STATE_DCD_DONE:
794 vout = property_enabled(rphy, &rphy->phy_cfg->chg_det.cp_det);
795 rockchip_chg_enable_primary_det(rphy, false);
797 /* Voltage Source on DM, Probe on DP */
798 rockchip_chg_enable_secondary_det(rphy, true);
799 delay = CHG_SECONDARY_DET_TIME;
800 rphy->chg_state = USB_CHG_STATE_PRIMARY_DONE;
802 if (rphy->dcd_retries == CHG_DCD_MAX_RETRIES) {
803 /* floating charger found */
804 rphy->chg_type = POWER_SUPPLY_TYPE_USB_FLOATING;
805 rphy->chg_state = USB_CHG_STATE_DETECTED;
808 if (rphy->primary_retries < 2) {
809 /* Turn off DCD circuitry */
810 rockchip_chg_enable_dcd(rphy, false);
811 /* Voltage Source on DP, Probe on DM */
812 rockchip_chg_enable_primary_det(rphy,
814 delay = CHG_PRIMARY_DET_TIME;
816 USB_CHG_STATE_DCD_DONE;
817 rphy->primary_retries++;
818 /* break USB_CHG_STATE_DCD_DONE */
821 rphy->chg_type = POWER_SUPPLY_TYPE_USB;
822 rphy->chg_state = USB_CHG_STATE_DETECTED;
827 case USB_CHG_STATE_PRIMARY_DONE:
828 vout = property_enabled(rphy, &rphy->phy_cfg->chg_det.dcp_det);
829 /* Turn off voltage source */
830 rockchip_chg_enable_secondary_det(rphy, false);
832 rphy->chg_type = POWER_SUPPLY_TYPE_USB_DCP;
834 rphy->chg_type = POWER_SUPPLY_TYPE_USB_CDP;
836 case USB_CHG_STATE_SECONDARY_DONE:
837 rphy->chg_state = USB_CHG_STATE_DETECTED;
840 case USB_CHG_STATE_DETECTED:
841 /* put the controller in normal mode */
842 property_enable(rphy, &rphy->phy_cfg->chg_det.opmode, true);
843 rockchip_usb2phy_otg_sm_work(&rport->otg_sm_work.work);
844 dev_info(&rport->phy->dev, "charger = %s\n",
845 chg_to_string(rphy->chg_type));
851 schedule_delayed_work(&rport->chg_work, delay);
855 * The function manage host-phy port state and suspend/resume phy port
858 * we rely on utmi_linestate and utmi_hostdisconnect to identify whether
859 * devices is disconnect or not. Besides, we do not need care it is FS/LS
860 * disconnected or HS disconnected, actually, we just only need get the
861 * device is disconnected at last through rearm the delayed work,
862 * to suspend the phy port in _PHY_STATE_DISCONNECT_ case.
864 * NOTE: It may invoke *phy_powr_off or *phy_power_on which will invoke
865 * some clk related APIs, so do not invoke it from interrupt context directly.
867 static void rockchip_usb2phy_sm_work(struct work_struct *work)
869 struct rockchip_usb2phy_port *rport =
870 container_of(work, struct rockchip_usb2phy_port, sm_work.work);
871 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
872 unsigned int sh = rport->port_cfg->utmi_hstdet.bitend -
873 rport->port_cfg->utmi_hstdet.bitstart + 1;
874 unsigned int ul, uhd, state;
875 unsigned int ul_mask, uhd_mask;
878 mutex_lock(&rport->mutex);
880 ret = regmap_read(rphy->grf, rport->port_cfg->utmi_ls.offset, &ul);
884 ret = regmap_read(rphy->grf, rport->port_cfg->utmi_hstdet.offset,
889 uhd_mask = GENMASK(rport->port_cfg->utmi_hstdet.bitend,
890 rport->port_cfg->utmi_hstdet.bitstart);
891 ul_mask = GENMASK(rport->port_cfg->utmi_ls.bitend,
892 rport->port_cfg->utmi_ls.bitstart);
894 /* stitch on utmi_ls and utmi_hstdet as phy state */
895 state = ((uhd & uhd_mask) >> rport->port_cfg->utmi_hstdet.bitstart) |
896 (((ul & ul_mask) >> rport->port_cfg->utmi_ls.bitstart) << sh);
899 case PHY_STATE_HS_ONLINE:
900 dev_dbg(&rport->phy->dev, "HS online\n");
902 case PHY_STATE_FS_LS_ONLINE:
904 * For FS/LS device, the online state share with connect state
905 * from utmi_ls and utmi_hstdet register, so we distinguish
906 * them via suspended flag.
908 * Plus, there are two cases, one is D- Line pull-up, and D+
909 * line pull-down, the state is 4; another is D+ line pull-up,
910 * and D- line pull-down, the state is 2.
912 if (!rport->suspended) {
913 /* D- line pull-up, D+ line pull-down */
914 dev_dbg(&rport->phy->dev, "FS/LS online\n");
918 case PHY_STATE_CONNECT:
919 if (rport->suspended) {
920 dev_dbg(&rport->phy->dev, "Connected\n");
921 rockchip_usb2phy_power_on(rport->phy);
922 rport->suspended = false;
924 /* D+ line pull-up, D- line pull-down */
925 dev_dbg(&rport->phy->dev, "FS/LS online\n");
928 case PHY_STATE_DISCONNECT:
929 if (!rport->suspended) {
930 dev_dbg(&rport->phy->dev, "Disconnected\n");
931 rockchip_usb2phy_power_off(rport->phy);
932 rport->suspended = true;
936 * activate the linestate detection to get the next device
939 property_enable(rphy, &rport->port_cfg->ls_det_clr, true);
940 property_enable(rphy, &rport->port_cfg->ls_det_en, true);
943 * we don't need to rearm the delayed work when the phy port
946 mutex_unlock(&rport->mutex);
949 dev_dbg(&rport->phy->dev, "unknown phy state\n");
954 mutex_unlock(&rport->mutex);
955 schedule_delayed_work(&rport->sm_work, SCHEDULE_DELAY);
958 static irqreturn_t rockchip_usb2phy_linestate_irq(int irq, void *data)
960 struct rockchip_usb2phy_port *rport = data;
961 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
963 if (!property_enabled(rphy, &rport->port_cfg->ls_det_st))
966 dev_dbg(&rport->phy->dev, "linestate interrupt\n");
968 mutex_lock(&rport->mutex);
970 /* disable linestate detect irq and clear its status */
971 property_enable(rphy, &rport->port_cfg->ls_det_en, false);
972 property_enable(rphy, &rport->port_cfg->ls_det_clr, true);
974 mutex_unlock(&rport->mutex);
977 * In this case for host phy port, a new device is plugged in,
978 * meanwhile, if the phy port is suspended, we need rearm the work to
979 * resume it and mange its states; otherwise, we do nothing about that.
981 if (rport->suspended) {
982 if (rport->port_id == USB2PHY_PORT_HOST)
983 rockchip_usb2phy_sm_work(&rport->sm_work.work);
985 rockchip_usb2phy_power_on(rport->phy);
991 static irqreturn_t rockchip_usb2phy_bvalid_irq(int irq, void *data)
993 struct rockchip_usb2phy_port *rport = data;
994 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
996 if (!property_enabled(rphy, &rport->port_cfg->bvalid_det_st))
999 mutex_lock(&rport->mutex);
1001 /* clear bvalid detect irq pending status */
1002 property_enable(rphy, &rport->port_cfg->bvalid_det_clr, true);
1004 mutex_unlock(&rport->mutex);
1006 rockchip_usb2phy_otg_sm_work(&rport->otg_sm_work.work);
1011 static irqreturn_t rockchip_usb2phy_id_irq(int irq, void *data)
1013 struct rockchip_usb2phy_port *rport = data;
1014 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
1016 if (!property_enabled(rphy, &rport->port_cfg->idfall_det_st) &&
1017 !property_enabled(rphy, &rport->port_cfg->idrise_det_st))
1020 mutex_lock(&rport->mutex);
1022 /* clear id fall or rise detect irq pending status */
1023 if (property_enabled(rphy, &rport->port_cfg->idfall_det_st)) {
1024 property_enable(rphy, &rport->port_cfg->idfall_det_clr,
1026 extcon_set_state(rphy->edev, EXTCON_USB_HOST, true);
1027 extcon_set_state(rphy->edev, EXTCON_USB_VBUS_EN, true);
1028 } else if (property_enabled(rphy, &rport->port_cfg->idrise_det_st)) {
1029 property_enable(rphy, &rport->port_cfg->idrise_det_clr,
1031 extcon_set_state(rphy->edev, EXTCON_USB_HOST, false);
1032 extcon_set_state(rphy->edev, EXTCON_USB_VBUS_EN, false);
1035 extcon_sync(rphy->edev, EXTCON_USB_HOST);
1036 extcon_sync(rphy->edev, EXTCON_USB_VBUS_EN);
1038 mutex_unlock(&rport->mutex);
1043 static int rockchip_usb2phy_host_port_init(struct rockchip_usb2phy *rphy,
1044 struct rockchip_usb2phy_port *rport,
1045 struct device_node *child_np)
1049 rport->port_id = USB2PHY_PORT_HOST;
1050 rport->port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_HOST];
1051 rport->suspended = true;
1053 mutex_init(&rport->mutex);
1054 INIT_DELAYED_WORK(&rport->sm_work, rockchip_usb2phy_sm_work);
1056 rport->ls_irq = of_irq_get_byname(child_np, "linestate");
1057 if (rport->ls_irq < 0) {
1058 dev_err(rphy->dev, "no linestate irq provided\n");
1059 return rport->ls_irq;
1062 ret = devm_request_threaded_irq(rphy->dev, rport->ls_irq, NULL,
1063 rockchip_usb2phy_linestate_irq,
1065 "rockchip_usb2phy", rport);
1067 dev_err(rphy->dev, "failed to request linestate irq handle\n");
1074 static int rockchip_otg_event(struct notifier_block *nb,
1075 unsigned long event, void *ptr)
1077 struct rockchip_usb2phy_port *rport =
1078 container_of(nb, struct rockchip_usb2phy_port, event_nb);
1080 schedule_delayed_work(&rport->otg_sm_work, OTG_SCHEDULE_DELAY);
1085 static int rockchip_usb2phy_otg_port_init(struct rockchip_usb2phy *rphy,
1086 struct rockchip_usb2phy_port *rport,
1087 struct device_node *child_np)
1092 rport->port_id = USB2PHY_PORT_OTG;
1093 rport->port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG];
1094 rport->state = OTG_STATE_UNDEFINED;
1097 * set suspended flag to true, but actually don't
1098 * put phy in suspend mode, it aims to enable usb
1099 * phy and clock in power_on() called by usb controller
1100 * driver during probe.
1102 rport->suspended = true;
1103 rport->vbus_attached = false;
1104 rport->perip_connected = false;
1106 mutex_init(&rport->mutex);
1108 rport->ls_irq = of_irq_get_byname(child_np, "linestate");
1109 if (rport->ls_irq < 0) {
1110 dev_err(rphy->dev, "no linestate irq provided\n");
1111 return rport->ls_irq;
1114 ret = devm_request_threaded_irq(rphy->dev, rport->ls_irq, NULL,
1115 rockchip_usb2phy_linestate_irq,
1117 "rockchip_usb2phy", rport);
1119 dev_err(rphy->dev, "failed to request linestate irq handle\n");
1123 rport->vbus_always_on =
1124 of_property_read_bool(child_np, "rockchip,vbus-always-on");
1126 rport->mode = of_usb_get_dr_mode_by_phy(child_np, -1);
1127 if (rport->mode == USB_DR_MODE_HOST || rport->vbus_always_on)
1130 wake_lock_init(&rport->wakelock, WAKE_LOCK_SUSPEND, "rockchip_otg");
1131 INIT_DELAYED_WORK(&rport->chg_work, rockchip_chg_detect_work);
1132 INIT_DELAYED_WORK(&rport->otg_sm_work, rockchip_usb2phy_otg_sm_work);
1134 rport->utmi_avalid =
1135 of_property_read_bool(child_np, "rockchip,utmi-avalid");
1137 rport->bvalid_irq = of_irq_get_byname(child_np, "otg-bvalid");
1138 if (rport->bvalid_irq < 0) {
1139 dev_err(rphy->dev, "no vbus valid irq provided\n");
1140 return rport->bvalid_irq;
1143 ret = devm_request_threaded_irq(rphy->dev, rport->bvalid_irq, NULL,
1144 rockchip_usb2phy_bvalid_irq,
1146 "rockchip_usb2phy_bvalid", rport);
1148 dev_err(rphy->dev, "failed to request otg-bvalid irq handle\n");
1152 if (rphy->edev_self) {
1153 rport->id_irq = of_irq_get_byname(child_np, "otg-id");
1154 if (rport->id_irq < 0) {
1155 dev_err(rphy->dev, "no otg id irq provided\n");
1156 return rport->id_irq;
1159 ret = devm_request_threaded_irq(rphy->dev, rport->id_irq, NULL,
1160 rockchip_usb2phy_id_irq,
1162 "rockchip_usb2phy_id", rport);
1164 dev_err(rphy->dev, "failed to request otg-id irq handle\n");
1168 iddig = property_enabled(rphy, &rport->port_cfg->utmi_iddig);
1170 extcon_set_state(rphy->edev, EXTCON_USB, false);
1171 extcon_set_state(rphy->edev, EXTCON_USB_HOST, true);
1172 extcon_set_state(rphy->edev, EXTCON_USB_VBUS_EN, true);
1174 extcon_set_state(rphy->edev, EXTCON_USB_HOST, false);
1175 extcon_set_state(rphy->edev, EXTCON_USB_VBUS_EN, false);
1179 if (!IS_ERR(rphy->edev)) {
1180 rport->event_nb.notifier_call = rockchip_otg_event;
1182 ret = extcon_register_notifier(rphy->edev, EXTCON_USB_HOST,
1185 dev_err(rphy->dev, "register USB HOST notifier failed\n");
1193 static int rockchip_usb2phy_probe(struct platform_device *pdev)
1195 struct device *dev = &pdev->dev;
1196 struct device_node *np = dev->of_node;
1197 struct device_node *child_np;
1198 struct phy_provider *provider;
1199 struct rockchip_usb2phy *rphy;
1200 const struct rockchip_usb2phy_cfg *phy_cfgs;
1201 const struct of_device_id *match;
1205 rphy = devm_kzalloc(dev, sizeof(*rphy), GFP_KERNEL);
1209 match = of_match_device(dev->driver->of_match_table, dev);
1210 if (!match || !match->data) {
1211 dev_err(dev, "phy configs are not assigned!\n");
1215 if (!dev->parent || !dev->parent->of_node)
1218 rphy->grf = syscon_node_to_regmap(dev->parent->of_node);
1219 if (IS_ERR(rphy->grf))
1220 return PTR_ERR(rphy->grf);
1222 if (of_property_read_u32(np, "reg", ®)) {
1223 dev_err(dev, "the reg property is not assigned in %s node\n",
1229 phy_cfgs = match->data;
1230 rphy->chg_state = USB_CHG_STATE_UNDEFINED;
1231 rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
1232 rphy->edev_self = false;
1233 platform_set_drvdata(pdev, rphy);
1235 ret = rockchip_usb2phy_extcon_register(rphy);
1239 /* find out a proper config which can be matched with dt. */
1241 while (phy_cfgs[index].reg) {
1242 if (phy_cfgs[index].reg == reg) {
1243 rphy->phy_cfg = &phy_cfgs[index];
1250 if (!rphy->phy_cfg) {
1251 dev_err(dev, "no phy-config can be matched with %s node\n",
1256 rphy->clk = of_clk_get_by_name(np, "phyclk");
1257 if (!IS_ERR(rphy->clk)) {
1258 clk_prepare_enable(rphy->clk);
1260 dev_info(&pdev->dev, "no phyclk specified\n");
1264 ret = rockchip_usb2phy_clk480m_register(rphy);
1266 dev_err(dev, "failed to register 480m output clock\n");
1270 if (rphy->phy_cfg->phy_tuning) {
1271 ret = rphy->phy_cfg->phy_tuning(rphy);
1277 for_each_available_child_of_node(np, child_np) {
1278 struct rockchip_usb2phy_port *rport = &rphy->ports[index];
1281 /* This driver aims to support both otg-port and host-port */
1282 if (of_node_cmp(child_np->name, "host-port") &&
1283 of_node_cmp(child_np->name, "otg-port"))
1286 phy = devm_phy_create(dev, child_np, &rockchip_usb2phy_ops);
1288 dev_err(dev, "failed to create phy\n");
1294 phy_set_drvdata(rport->phy, rport);
1296 /* initialize otg/host port separately */
1297 if (!of_node_cmp(child_np->name, "host-port")) {
1298 ret = rockchip_usb2phy_host_port_init(rphy, rport,
1303 ret = rockchip_usb2phy_otg_port_init(rphy, rport,
1310 /* to prevent out of boundary */
1311 if (++index >= rphy->phy_cfg->num_ports)
1315 provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
1316 return PTR_ERR_OR_ZERO(provider);
1319 of_node_put(child_np);
1322 clk_disable_unprepare(rphy->clk);
1328 static int rk3366_usb2phy_tuning(struct rockchip_usb2phy *rphy)
1330 unsigned int open_pre_emphasize = 0xffff851f;
1331 unsigned int eye_height_tuning = 0xffff68c8;
1332 unsigned int compensation_tuning = 0xffff026e;
1335 /* open HS pre-emphasize to expand HS slew rate for each port. */
1336 ret |= regmap_write(rphy->grf, 0x0780, open_pre_emphasize);
1337 ret |= regmap_write(rphy->grf, 0x079c, eye_height_tuning);
1338 ret |= regmap_write(rphy->grf, 0x07b0, open_pre_emphasize);
1339 ret |= regmap_write(rphy->grf, 0x07cc, eye_height_tuning);
1341 /* compensate default tuning reference relate to ODT and etc. */
1342 ret |= regmap_write(rphy->grf, 0x078c, compensation_tuning);
1347 #ifdef CONFIG_PM_SLEEP
1348 static int rockchip_usb2phy_pm_suspend(struct device *dev)
1350 struct rockchip_usb2phy *rphy = dev_get_drvdata(dev);
1351 struct rockchip_usb2phy_port *rport;
1354 for (index = 0; index < rphy->phy_cfg->num_ports; index++) {
1355 rport = &rphy->ports[index];
1359 /* activate the linestate to detect the next interrupt. */
1360 property_enable(rphy, &rport->port_cfg->ls_det_clr, true);
1361 property_enable(rphy, &rport->port_cfg->ls_det_en, true);
1367 static int rockchip_usb2phy_pm_resume(struct device *dev)
1372 static const struct dev_pm_ops rockchip_usb2phy_dev_pm_ops = {
1373 SET_SYSTEM_SLEEP_PM_OPS(rockchip_usb2phy_pm_suspend,
1374 rockchip_usb2phy_pm_resume)
1377 #define ROCKCHIP_USB2PHY_DEV_PM (&rockchip_usb2phy_dev_pm_ops)
1379 #define ROCKCHIP_USB2PHY_DEV_PM NULL
1380 #endif /* CONFIG_PM_SLEEP */
1382 static const struct rockchip_usb2phy_cfg rk3366_phy_cfgs[] = {
1386 .phy_tuning = rk3366_usb2phy_tuning,
1387 .clkout_ctl = { 0x0724, 15, 15, 1, 0 },
1389 [USB2PHY_PORT_HOST] = {
1390 .phy_sus = { 0x0728, 15, 0, 0, 0x1d1 },
1391 .ls_det_en = { 0x0680, 4, 4, 0, 1 },
1392 .ls_det_st = { 0x0690, 4, 4, 0, 1 },
1393 .ls_det_clr = { 0x06a0, 4, 4, 0, 1 },
1394 .utmi_ls = { 0x049c, 14, 13, 0, 1 },
1395 .utmi_hstdet = { 0x049c, 12, 12, 0, 1 }
1402 static const struct rockchip_usb2phy_cfg rk3399_phy_cfgs[] = {
1406 .clkout_ctl = { 0xe450, 4, 4, 1, 0 },
1408 [USB2PHY_PORT_OTG] = {
1409 .phy_sus = { 0xe454, 15, 0, 0x1452, 0x15d1 },
1410 .bvalid_det_en = { 0xe3c0, 3, 3, 0, 1 },
1411 .bvalid_det_st = { 0xe3e0, 3, 3, 0, 1 },
1412 .bvalid_det_clr = { 0xe3d0, 3, 3, 0, 1 },
1413 .idfall_det_en = { 0xe3c0, 5, 5, 0, 1 },
1414 .idfall_det_st = { 0xe3e0, 5, 5, 0, 1 },
1415 .idfall_det_clr = { 0xe3d0, 5, 5, 0, 1 },
1416 .idrise_det_en = { 0xe3c0, 4, 4, 0, 1 },
1417 .idrise_det_st = { 0xe3e0, 4, 4, 0, 1 },
1418 .idrise_det_clr = { 0xe3d0, 4, 4, 0, 1 },
1419 .ls_det_en = { 0xe3c0, 2, 2, 0, 1 },
1420 .ls_det_st = { 0xe3e0, 2, 2, 0, 1 },
1421 .ls_det_clr = { 0xe3d0, 2, 2, 0, 1 },
1422 .utmi_avalid = { 0xe2ac, 7, 7, 0, 1 },
1423 .utmi_bvalid = { 0xe2ac, 12, 12, 0, 1 },
1424 .utmi_iddig = { 0xe2ac, 8, 8, 0, 1 },
1425 .utmi_ls = { 0xe2ac, 14, 13, 0, 1 },
1427 [USB2PHY_PORT_HOST] = {
1428 .phy_sus = { 0xe458, 1, 0, 0x2, 0x1 },
1429 .ls_det_en = { 0xe3c0, 6, 6, 0, 1 },
1430 .ls_det_st = { 0xe3e0, 6, 6, 0, 1 },
1431 .ls_det_clr = { 0xe3d0, 6, 6, 0, 1 },
1432 .utmi_ls = { 0xe2ac, 22, 21, 0, 1 },
1433 .utmi_hstdet = { 0xe2ac, 23, 23, 0, 1 }
1437 .opmode = { 0xe454, 3, 0, 5, 1 },
1438 .cp_det = { 0xe2ac, 2, 2, 0, 1 },
1439 .dcp_det = { 0xe2ac, 1, 1, 0, 1 },
1440 .dp_det = { 0xe2ac, 0, 0, 0, 1 },
1441 .idm_sink_en = { 0xe450, 8, 8, 0, 1 },
1442 .idp_sink_en = { 0xe450, 7, 7, 0, 1 },
1443 .idp_src_en = { 0xe450, 9, 9, 0, 1 },
1444 .rdm_pdwn_en = { 0xe450, 10, 10, 0, 1 },
1445 .vdm_src_en = { 0xe450, 12, 12, 0, 1 },
1446 .vdp_src_en = { 0xe450, 11, 11, 0, 1 },
1452 .clkout_ctl = { 0xe460, 4, 4, 1, 0 },
1454 [USB2PHY_PORT_OTG] = {
1455 .phy_sus = { 0xe464, 15, 0, 0x1452, 0x15d1 },
1456 .bvalid_det_en = { 0xe3c0, 8, 8, 0, 1 },
1457 .bvalid_det_st = { 0xe3e0, 8, 8, 0, 1 },
1458 .bvalid_det_clr = { 0xe3d0, 8, 8, 0, 1 },
1459 .idfall_det_en = { 0xe3c0, 10, 10, 0, 1 },
1460 .idfall_det_st = { 0xe3e0, 10, 10, 0, 1 },
1461 .idfall_det_clr = { 0xe3d0, 10, 10, 0, 1 },
1462 .idrise_det_en = { 0xe3c0, 9, 9, 0, 1 },
1463 .idrise_det_st = { 0xe3e0, 9, 9, 0, 1 },
1464 .idrise_det_clr = { 0xe3d0, 9, 9, 0, 1 },
1465 .ls_det_en = { 0xe3c0, 7, 7, 0, 1 },
1466 .ls_det_st = { 0xe3e0, 7, 7, 0, 1 },
1467 .ls_det_clr = { 0xe3d0, 7, 7, 0, 1 },
1468 .utmi_avalid = { 0xe2ac, 10, 10, 0, 1 },
1469 .utmi_bvalid = { 0xe2ac, 16, 16, 0, 1 },
1470 .utmi_iddig = { 0xe2ac, 11, 11, 0, 1 },
1471 .utmi_ls = { 0xe2ac, 18, 17, 0, 1 },
1473 [USB2PHY_PORT_HOST] = {
1474 .phy_sus = { 0xe468, 1, 0, 0x2, 0x1 },
1475 .ls_det_en = { 0xe3c0, 11, 11, 0, 1 },
1476 .ls_det_st = { 0xe3e0, 11, 11, 0, 1 },
1477 .ls_det_clr = { 0xe3d0, 11, 11, 0, 1 },
1478 .utmi_ls = { 0xe2ac, 26, 25, 0, 1 },
1479 .utmi_hstdet = { 0xe2ac, 27, 27, 0, 1 }
1486 static const struct of_device_id rockchip_usb2phy_dt_match[] = {
1487 { .compatible = "rockchip,rk3366-usb2phy", .data = &rk3366_phy_cfgs },
1488 { .compatible = "rockchip,rk3399-usb2phy", .data = &rk3399_phy_cfgs },
1491 MODULE_DEVICE_TABLE(of, rockchip_usb2phy_dt_match);
1493 static struct platform_driver rockchip_usb2phy_driver = {
1494 .probe = rockchip_usb2phy_probe,
1496 .name = "rockchip-usb2phy",
1497 .pm = ROCKCHIP_USB2PHY_DEV_PM,
1498 .of_match_table = rockchip_usb2phy_dt_match,
1501 module_platform_driver(rockchip_usb2phy_driver);
1503 MODULE_AUTHOR("Frank Wang <frank.wang@rock-chips.com>");
1504 MODULE_DESCRIPTION("Rockchip USB2.0 PHY driver");
1505 MODULE_LICENSE("GPL v2");