2 * Rockchip emmc PHY driver
4 * Copyright (C) 2016 Shawn Lin <shawn.lin@rock-chips.com>
5 * Copyright (C) 2016 ROCKCHIP, Inc.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/delay.h>
19 #include <linux/mfd/syscon.h>
20 #include <linux/module.h>
22 #include <linux/of_address.h>
23 #include <linux/phy/phy.h>
24 #include <linux/platform_device.h>
25 #include <linux/regmap.h>
28 * The higher 16-bit of this register is used for write protection
29 * only if BIT(x + 16) set to 1 the BIT(x) can be written.
31 #define HIWORD_UPDATE(val, mask, shift) \
32 ((val) << (shift) | (mask) << ((shift) + 16))
34 /* Register definition */
35 #define GRF_EMMCPHY_CON0 0x0
36 #define GRF_EMMCPHY_CON1 0x4
37 #define GRF_EMMCPHY_CON2 0x8
38 #define GRF_EMMCPHY_CON3 0xc
39 #define GRF_EMMCPHY_CON4 0x10
40 #define GRF_EMMCPHY_CON5 0x14
41 #define GRF_EMMCPHY_CON6 0x18
42 #define GRF_EMMCPHY_STATUS 0x20
43 #define CTRL_OFFSET 0x2c
45 #define CTRL_INTER_CLKEN 0x1
46 #define CTRL_INTER_CLKRDY 0x1
47 #define CTRL_INTER_CLKOUT 0x1
48 #define PHYCTRL_PDB_MASK 0x1
49 #define PHYCTRL_PDB_SHIFT 0x0
50 #define PHYCTRL_PDB_PWR_ON 0x1
51 #define PHYCTRL_PDB_PWR_OFF 0x0
52 #define PHYCTRL_ENDLL_MASK 0x1
53 #define PHYCTRL_ENDLL_SHIFT 0x1
54 #define PHYCTRL_ENDLL_ENABLE 0x1
55 #define PHYCTRL_ENDLL_DISABLE 0x0
56 #define PHYCTRL_CALDONE_MASK 0x1
57 #define PHYCTRL_CALDONE_SHIFT 0x6
58 #define PHYCTRL_CALDONE_DONE 0x1
59 #define PHYCTRL_CALDONE_GOING 0x0
60 #define PHYCTRL_DLLRDY_MASK 0x1
61 #define PHYCTRL_DLLRDY_SHIFT 0x5
62 #define PHYCTRL_DLLRDY_DONE 0x1
63 #define PHYCTRL_DLLRDY_GOING 0x0
64 #define PHYCTRL_FREQSEL_200M 0x0
65 #define PHYCTRL_FREQSEL_50M 0x1
66 #define PHYCTRL_FREQSEL_100M 0x2
67 #define PHYCTRL_FREQSEL_150M 0x3
68 #define PHYCTRL_FREQSEL_MASK 0x3
69 #define PHYCTRL_FREQSEL_SHIFT 0xc
70 #define PHYCTRL_DR_MASK 0x7
71 #define PHYCTRL_DR_SHIFT 0x4
72 #define PHYCTRL_DR_50OHM 0x0
73 #define PHYCTRL_DR_33OHM 0x1
74 #define PHYCTRL_DR_66OHM 0x2
75 #define PHYCTRL_DR_100OHM 0x3
76 #define PHYCTRL_DR_40OHM 0x4
77 #define PHYCTRL_OTAPDLYENA 0x1
78 #define PHYCTRL_OTAPDLYENA_MASK 0x1
79 #define PHYCTRL_OTAPDLYENA_SHIFT 11
80 #define PHYCTRL_OTAPDLYSEL_MASK 0xf
81 #define PHYCTRL_OTAPDLYSEL_SHIFT 7
83 struct rockchip_emmc_phy {
84 unsigned int reg_offset;
85 struct regmap *reg_base;
86 void __iomem *ctrl_base;
92 static int rockchip_emmc_phy_power(struct rockchip_emmc_phy *rk_phy,
98 unsigned long timeout;
101 * Keep phyctrl_pdb and phyctrl_endll low to allow
102 * initialization of CALIO state M/C DFFs
104 regmap_write(rk_phy->reg_base,
105 rk_phy->reg_offset + GRF_EMMCPHY_CON6,
106 HIWORD_UPDATE(PHYCTRL_PDB_PWR_OFF,
109 regmap_write(rk_phy->reg_base,
110 rk_phy->reg_offset + GRF_EMMCPHY_CON6,
111 HIWORD_UPDATE(PHYCTRL_ENDLL_DISABLE,
113 PHYCTRL_ENDLL_SHIFT));
115 /* Already finish power_off above */
116 if (on_off == PHYCTRL_PDB_PWR_OFF)
119 ctrl_val = readw(rk_phy->ctrl_base + CTRL_OFFSET);
120 ctrl_val |= CTRL_INTER_CLKEN;
121 writew(ctrl_val, rk_phy->ctrl_base + CTRL_OFFSET);
123 while (!((ctrl_val = readw(rk_phy->ctrl_base + CTRL_OFFSET))
124 & CTRL_INTER_CLKRDY)) {
126 pr_err("rockchip_emmc_phy_power_on: inter_clk not rdy\n");
132 ctrl_val |= CTRL_INTER_CLKOUT;
133 writew(ctrl_val, rk_phy->ctrl_base + CTRL_OFFSET);
136 * According to the user manual, calpad calibration
137 * cycle takes more than 2us without the minimal recommended
138 * value, so we may need a little margin here
141 regmap_write(rk_phy->reg_base,
142 rk_phy->reg_offset + GRF_EMMCPHY_CON6,
143 HIWORD_UPDATE(PHYCTRL_PDB_PWR_ON,
148 * According to the user manual, it asks driver to
149 * wait 5us for calpad busy trimming
152 regmap_read(rk_phy->reg_base,
153 rk_phy->reg_offset + GRF_EMMCPHY_STATUS,
155 caldone = (caldone >> PHYCTRL_CALDONE_SHIFT) & PHYCTRL_CALDONE_MASK;
156 if (caldone != PHYCTRL_CALDONE_DONE) {
157 pr_err("rockchip_emmc_phy_power: caldone timeout.\n");
161 regmap_write(rk_phy->reg_base,
162 rk_phy->reg_offset + GRF_EMMCPHY_CON6,
163 HIWORD_UPDATE(PHYCTRL_ENDLL_ENABLE,
165 PHYCTRL_ENDLL_SHIFT));
167 * After enable analog DLL circuits, we need extra 10.2us
168 * for dll to be ready for work. But according to the test, we
169 * find some chips need more than 25us.
172 regmap_read(rk_phy->reg_base,
173 rk_phy->reg_offset + GRF_EMMCPHY_STATUS,
175 dllrdy = (dllrdy >> PHYCTRL_DLLRDY_SHIFT) & PHYCTRL_DLLRDY_MASK;
176 if (dllrdy != PHYCTRL_DLLRDY_DONE) {
177 pr_err("rockchip_emmc_phy_power: dllrdy timeout.\n");
184 static int rockchip_emmc_phy_init(struct phy *phy)
186 struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy);
188 regmap_write(rk_phy->reg_base,
189 rk_phy->reg_offset + GRF_EMMCPHY_CON0,
190 HIWORD_UPDATE(rk_phy->freq_sel,
191 PHYCTRL_FREQSEL_MASK,
192 PHYCTRL_FREQSEL_SHIFT));
194 regmap_write(rk_phy->reg_base,
195 rk_phy->reg_offset + GRF_EMMCPHY_CON6,
196 HIWORD_UPDATE(rk_phy->dr_sel,
200 regmap_write(rk_phy->reg_base,
201 rk_phy->reg_offset + GRF_EMMCPHY_CON0,
202 HIWORD_UPDATE(PHYCTRL_OTAPDLYENA,
203 PHYCTRL_OTAPDLYENA_MASK,
204 PHYCTRL_OTAPDLYENA_SHIFT));
206 regmap_write(rk_phy->reg_base,
207 rk_phy->reg_offset + GRF_EMMCPHY_CON0,
208 HIWORD_UPDATE(rk_phy->opdelay,
209 PHYCTRL_OTAPDLYSEL_MASK,
210 PHYCTRL_OTAPDLYSEL_SHIFT));
215 static int rockchip_emmc_phy_power_off(struct phy *phy)
217 struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy);
220 /* Power down emmc phy analog blocks */
221 ret = rockchip_emmc_phy_power(rk_phy, PHYCTRL_PDB_PWR_OFF);
228 static int rockchip_emmc_phy_power_on(struct phy *phy)
230 struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy);
233 /* Power up emmc phy analog blocks */
234 ret = rockchip_emmc_phy_power(rk_phy, PHYCTRL_PDB_PWR_ON);
241 static const struct phy_ops ops = {
242 .init = rockchip_emmc_phy_init,
243 .power_on = rockchip_emmc_phy_power_on,
244 .power_off = rockchip_emmc_phy_power_off,
245 .owner = THIS_MODULE,
248 static int rockchip_emmc_phy_probe(struct platform_device *pdev)
250 struct device *dev = &pdev->dev;
251 struct rockchip_emmc_phy *rk_phy;
252 struct phy *generic_phy;
253 struct phy_provider *phy_provider;
255 unsigned int reg_offset;
261 grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,grf");
263 dev_err(dev, "Missing rockchip,grf property\n");
267 rk_phy = devm_kzalloc(dev, sizeof(*rk_phy), GFP_KERNEL);
271 if (of_property_read_u32(dev->of_node, "reg-offset", ®_offset)) {
272 dev_err(dev, "missing reg property in node %s\n",
277 if (of_property_read_u32(dev->of_node, "ctrl-base", &ctrl_base)) {
278 dev_err(dev, "missing ctrl-base property in node %s\n",
283 rk_phy->ctrl_base = ioremap(ctrl_base, SZ_1K);
284 if (!rk_phy->ctrl_base) {
285 dev_err(dev, "failed to remap ctrl_base!\n");
289 rk_phy->freq_sel = 0x0;
290 if (!of_property_read_u32(dev->of_node, "freq-sel", &freq_sel)) {
293 rk_phy->freq_sel = PHYCTRL_FREQSEL_50M;
296 rk_phy->freq_sel = PHYCTRL_FREQSEL_100M;
299 rk_phy->freq_sel = PHYCTRL_FREQSEL_150M;
302 rk_phy->freq_sel = PHYCTRL_FREQSEL_200M;
305 dev_info(dev, "Not support freq_sel, default 200M\n");
310 rk_phy->dr_sel = 0x0;
311 if (!of_property_read_u32(dev->of_node, "dr-sel", &dr_sel)) {
314 rk_phy->dr_sel = PHYCTRL_DR_50OHM;
317 rk_phy->dr_sel = PHYCTRL_DR_33OHM;
320 rk_phy->dr_sel = PHYCTRL_DR_66OHM;
323 rk_phy->dr_sel = PHYCTRL_DR_100OHM;
326 rk_phy->dr_sel = PHYCTRL_DR_40OHM;
329 dev_info(dev, "Not support dr_sel, default 50OHM\n");
334 rk_phy->opdelay = 0x4;
335 if (!of_property_read_u32(dev->of_node, "opdelay", &opdelay)) {
337 dev_info(dev, "opdelay shouldn't larger than 15\n");
339 rk_phy->opdelay = opdelay;
342 rk_phy->reg_offset = reg_offset;
343 rk_phy->reg_base = grf;
345 generic_phy = devm_phy_create(dev, dev->of_node, &ops);
346 if (IS_ERR(generic_phy)) {
347 dev_err(dev, "failed to create PHY\n");
348 iounmap(rk_phy->ctrl_base);
349 return PTR_ERR(generic_phy);
352 phy_set_drvdata(generic_phy, rk_phy);
353 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
355 return PTR_ERR_OR_ZERO(phy_provider);
358 static const struct of_device_id rockchip_emmc_phy_dt_ids[] = {
359 { .compatible = "rockchip,rk3399-emmc-phy" },
363 MODULE_DEVICE_TABLE(of, rockchip_emmc_phy_dt_ids);
365 static struct platform_driver rockchip_emmc_driver = {
366 .probe = rockchip_emmc_phy_probe,
368 .name = "rockchip-emmc-phy",
369 .of_match_table = rockchip_emmc_phy_dt_ids,
373 module_platform_driver(rockchip_emmc_driver);
375 MODULE_AUTHOR("Shawn Lin <shawn.lin@rock-chips.com>");
376 MODULE_DESCRIPTION("Rockchip EMMC PHY driver");
377 MODULE_LICENSE("GPL v2");