2 * Rockchip emmc PHY driver
4 * Copyright (C) 2016 Shawn Lin <shawn.lin@rock-chips.com>
5 * Copyright (C) 2016 ROCKCHIP, Inc.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
17 #include <linux/delay.h>
19 #include <linux/mfd/syscon.h>
20 #include <linux/module.h>
22 #include <linux/of_address.h>
23 #include <linux/phy/phy.h>
24 #include <linux/platform_device.h>
25 #include <linux/regmap.h>
28 * The higher 16-bit of this register is used for write protection
29 * only if BIT(x + 16) set to 1 the BIT(x) can be written.
31 #define HIWORD_UPDATE(val, mask, shift) \
32 ((val) << (shift) | (mask) << ((shift) + 16))
34 /* Register definition */
35 #define GRF_EMMCPHY_CON0 0x0
36 #define GRF_EMMCPHY_CON1 0x4
37 #define GRF_EMMCPHY_CON2 0x8
38 #define GRF_EMMCPHY_CON3 0xc
39 #define GRF_EMMCPHY_CON4 0x10
40 #define GRF_EMMCPHY_CON5 0x14
41 #define GRF_EMMCPHY_CON6 0x18
42 #define GRF_EMMCPHY_STATUS 0x20
43 #define CTRL_OFFSET 0x2c
45 #define CTRL_INTER_CLKEN 0x1
46 #define CTRL_INTER_CLKRDY 0x2
47 #define CTRL_INTER_CLKOUT 0x4
48 #define PHYCTRL_PDB_MASK 0x1
49 #define PHYCTRL_PDB_SHIFT 0x0
50 #define PHYCTRL_PDB_PWR_ON 0x1
51 #define PHYCTRL_PDB_PWR_OFF 0x0
52 #define PHYCTRL_ENDLL_MASK 0x1
53 #define PHYCTRL_ENDLL_SHIFT 0x1
54 #define PHYCTRL_ENDLL_ENABLE 0x1
55 #define PHYCTRL_ENDLL_DISABLE 0x0
56 #define PHYCTRL_CALDONE_MASK 0x1
57 #define PHYCTRL_CALDONE_SHIFT 0x6
58 #define PHYCTRL_CALDONE_DONE 0x1
59 #define PHYCTRL_CALDONE_GOING 0x0
60 #define PHYCTRL_DLLRDY_MASK 0x1
61 #define PHYCTRL_DLLRDY_SHIFT 0x5
62 #define PHYCTRL_DLLRDY_DONE 0x1
63 #define PHYCTRL_DLLRDY_GOING 0x0
64 #define PHYCTRL_FREQSEL_200M 0x0
65 #define PHYCTRL_FREQSEL_50M 0x1
66 #define PHYCTRL_FREQSEL_100M 0x2
67 #define PHYCTRL_FREQSEL_150M 0x3
68 #define PHYCTRL_FREQSEL_MASK 0x3
69 #define PHYCTRL_FREQSEL_SHIFT 0xc
70 #define PHYCTRL_DR_MASK 0x7
71 #define PHYCTRL_DR_SHIFT 0x4
72 #define PHYCTRL_DR_50OHM 0x0
73 #define PHYCTRL_DR_33OHM 0x1
74 #define PHYCTRL_DR_66OHM 0x2
75 #define PHYCTRL_DR_100OHM 0x3
76 #define PHYCTRL_DR_40OHM 0x4
77 #define PHYCTRL_OTAPDLYENA 0x1
78 #define PHYCTRL_OTAPDLYENA_MASK 0x1
79 #define PHYCTRL_OTAPDLYENA_SHIFT 11
80 #define PHYCTRL_OTAPDLYSEL_MASK 0xf
81 #define PHYCTRL_OTAPDLYSEL_SHIFT 7
82 #define PHYCTRL_REN_STRB_ENABLE 0x1
83 #define PHYCTRL_REN_STRB_MASK 0x1
84 #define PHYCTRL_REN_STRB_SHIFT 9
86 struct rockchip_emmc_phy {
87 unsigned int reg_offset;
88 struct regmap *reg_base;
89 void __iomem *ctrl_base;
95 static int rockchip_emmc_phy_power(struct rockchip_emmc_phy *rk_phy,
101 unsigned long timeout;
104 * Keep phyctrl_pdb and phyctrl_endll low to allow
105 * initialization of CALIO state M/C DFFs
107 regmap_write(rk_phy->reg_base,
108 rk_phy->reg_offset + GRF_EMMCPHY_CON6,
109 HIWORD_UPDATE(PHYCTRL_PDB_PWR_OFF,
112 regmap_write(rk_phy->reg_base,
113 rk_phy->reg_offset + GRF_EMMCPHY_CON6,
114 HIWORD_UPDATE(PHYCTRL_ENDLL_DISABLE,
116 PHYCTRL_ENDLL_SHIFT));
118 /* Already finish power_off above */
119 if (on_off == PHYCTRL_PDB_PWR_OFF)
122 ctrl_val = readw(rk_phy->ctrl_base + CTRL_OFFSET);
123 ctrl_val |= CTRL_INTER_CLKEN;
124 writew(ctrl_val, rk_phy->ctrl_base + CTRL_OFFSET);
126 while (!((ctrl_val = readw(rk_phy->ctrl_base + CTRL_OFFSET))
127 & CTRL_INTER_CLKRDY)) {
129 pr_err("rockchip_emmc_phy_power_on: inter_clk not rdy\n");
135 ctrl_val |= CTRL_INTER_CLKOUT;
136 writew(ctrl_val, rk_phy->ctrl_base + CTRL_OFFSET);
139 * According to the user manual, calpad calibration
140 * cycle takes more than 2us without the minimal recommended
141 * value, so we may need a little margin here
144 regmap_write(rk_phy->reg_base,
145 rk_phy->reg_offset + GRF_EMMCPHY_CON6,
146 HIWORD_UPDATE(PHYCTRL_PDB_PWR_ON,
151 * According to the user manual, it asks driver to
152 * wait 5us for calpad busy trimming
155 regmap_read(rk_phy->reg_base,
156 rk_phy->reg_offset + GRF_EMMCPHY_STATUS,
158 caldone = (caldone >> PHYCTRL_CALDONE_SHIFT) & PHYCTRL_CALDONE_MASK;
159 if (caldone != PHYCTRL_CALDONE_DONE) {
160 pr_err("rockchip_emmc_phy_power: caldone timeout.\n");
164 regmap_write(rk_phy->reg_base,
165 rk_phy->reg_offset + GRF_EMMCPHY_CON6,
166 HIWORD_UPDATE(PHYCTRL_ENDLL_ENABLE,
168 PHYCTRL_ENDLL_SHIFT));
170 * After enable analog DLL circuits, we need extra 10.2us
171 * for dll to be ready for work. But according to the test, we
172 * find some chips need more than 25us.
175 regmap_read(rk_phy->reg_base,
176 rk_phy->reg_offset + GRF_EMMCPHY_STATUS,
178 dllrdy = (dllrdy >> PHYCTRL_DLLRDY_SHIFT) & PHYCTRL_DLLRDY_MASK;
179 if (dllrdy != PHYCTRL_DLLRDY_DONE) {
180 pr_err("rockchip_emmc_phy_power: dllrdy timeout.\n");
187 static int rockchip_emmc_phy_init(struct phy *phy)
189 struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy);
191 regmap_write(rk_phy->reg_base,
192 rk_phy->reg_offset + GRF_EMMCPHY_CON0,
193 HIWORD_UPDATE(rk_phy->freq_sel,
194 PHYCTRL_FREQSEL_MASK,
195 PHYCTRL_FREQSEL_SHIFT));
197 regmap_write(rk_phy->reg_base,
198 rk_phy->reg_offset + GRF_EMMCPHY_CON6,
199 HIWORD_UPDATE(rk_phy->dr_sel,
203 regmap_write(rk_phy->reg_base,
204 rk_phy->reg_offset + GRF_EMMCPHY_CON0,
205 HIWORD_UPDATE(PHYCTRL_OTAPDLYENA,
206 PHYCTRL_OTAPDLYENA_MASK,
207 PHYCTRL_OTAPDLYENA_SHIFT));
209 regmap_write(rk_phy->reg_base,
210 rk_phy->reg_offset + GRF_EMMCPHY_CON2,
211 HIWORD_UPDATE(PHYCTRL_REN_STRB_ENABLE,
212 PHYCTRL_REN_STRB_MASK,
213 PHYCTRL_REN_STRB_SHIFT));
215 regmap_write(rk_phy->reg_base,
216 rk_phy->reg_offset + GRF_EMMCPHY_CON0,
217 HIWORD_UPDATE(rk_phy->opdelay,
218 PHYCTRL_OTAPDLYSEL_MASK,
219 PHYCTRL_OTAPDLYSEL_SHIFT));
224 static int rockchip_emmc_phy_power_off(struct phy *phy)
226 struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy);
229 /* Power down emmc phy analog blocks */
230 ret = rockchip_emmc_phy_power(rk_phy, PHYCTRL_PDB_PWR_OFF);
237 static int rockchip_emmc_phy_power_on(struct phy *phy)
239 struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy);
242 /* Power up emmc phy analog blocks */
243 ret = rockchip_emmc_phy_power(rk_phy, PHYCTRL_PDB_PWR_ON);
250 static const struct phy_ops ops = {
251 .init = rockchip_emmc_phy_init,
252 .power_on = rockchip_emmc_phy_power_on,
253 .power_off = rockchip_emmc_phy_power_off,
254 .owner = THIS_MODULE,
257 static int rockchip_emmc_phy_probe(struct platform_device *pdev)
259 struct device *dev = &pdev->dev;
260 struct rockchip_emmc_phy *rk_phy;
261 struct phy *generic_phy;
262 struct phy_provider *phy_provider;
264 unsigned int reg_offset;
270 grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,grf");
272 dev_err(dev, "Missing rockchip,grf property\n");
276 rk_phy = devm_kzalloc(dev, sizeof(*rk_phy), GFP_KERNEL);
280 if (of_property_read_u32(dev->of_node, "reg-offset", ®_offset)) {
281 dev_err(dev, "missing reg property in node %s\n",
286 if (of_property_read_u32(dev->of_node, "ctrl-base", &ctrl_base)) {
287 dev_err(dev, "missing ctrl-base property in node %s\n",
292 rk_phy->ctrl_base = ioremap(ctrl_base, SZ_1K);
293 if (!rk_phy->ctrl_base) {
294 dev_err(dev, "failed to remap ctrl_base!\n");
298 rk_phy->freq_sel = 0x0;
299 if (!of_property_read_u32(dev->of_node, "freq-sel", &freq_sel)) {
302 rk_phy->freq_sel = PHYCTRL_FREQSEL_50M;
305 rk_phy->freq_sel = PHYCTRL_FREQSEL_100M;
308 rk_phy->freq_sel = PHYCTRL_FREQSEL_150M;
311 rk_phy->freq_sel = PHYCTRL_FREQSEL_200M;
314 dev_info(dev, "Not support freq_sel, default 200M\n");
319 rk_phy->dr_sel = 0x0;
320 if (!of_property_read_u32(dev->of_node, "dr-sel", &dr_sel)) {
323 rk_phy->dr_sel = PHYCTRL_DR_50OHM;
326 rk_phy->dr_sel = PHYCTRL_DR_33OHM;
329 rk_phy->dr_sel = PHYCTRL_DR_66OHM;
332 rk_phy->dr_sel = PHYCTRL_DR_100OHM;
335 rk_phy->dr_sel = PHYCTRL_DR_40OHM;
338 dev_info(dev, "Not support dr_sel, default 50OHM\n");
343 rk_phy->opdelay = 0x4;
344 if (!of_property_read_u32(dev->of_node, "opdelay", &opdelay)) {
346 dev_info(dev, "opdelay shouldn't larger than 15\n");
348 rk_phy->opdelay = opdelay;
351 rk_phy->reg_offset = reg_offset;
352 rk_phy->reg_base = grf;
354 generic_phy = devm_phy_create(dev, dev->of_node, &ops);
355 if (IS_ERR(generic_phy)) {
356 dev_err(dev, "failed to create PHY\n");
357 iounmap(rk_phy->ctrl_base);
358 return PTR_ERR(generic_phy);
361 phy_set_drvdata(generic_phy, rk_phy);
362 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
364 return PTR_ERR_OR_ZERO(phy_provider);
367 static const struct of_device_id rockchip_emmc_phy_dt_ids[] = {
368 { .compatible = "rockchip,rk3399-emmc-phy" },
372 MODULE_DEVICE_TABLE(of, rockchip_emmc_phy_dt_ids);
374 static struct platform_driver rockchip_emmc_driver = {
375 .probe = rockchip_emmc_phy_probe,
377 .name = "rockchip-emmc-phy",
378 .of_match_table = rockchip_emmc_phy_dt_ids,
382 module_platform_driver(rockchip_emmc_driver);
384 MODULE_AUTHOR("Shawn Lin <shawn.lin@rock-chips.com>");
385 MODULE_DESCRIPTION("Rockchip EMMC PHY driver");
386 MODULE_LICENSE("GPL v2");