2 * Rockchip DP PHY driver
4 * Copyright (C) 2016 FuZhou Rockchip Co., Ltd.
5 * Author: Yakir Yang <ykk@@rock-chips.com>
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License as published by
9 * the Free Software Foundation; either version 2 of the License.
12 #include <linux/clk.h>
13 #include <linux/delay.h>
14 #include <linux/mfd/syscon.h>
15 #include <linux/module.h>
17 #include <linux/of_device.h>
18 #include <linux/phy/phy.h>
19 #include <linux/platform_device.h>
20 #include <linux/regmap.h>
21 #include <linux/reset.h>
23 struct rockchip_dp_phy_drv_data {
25 u32 ref_clk_sel_inter;
30 struct rockchip_dp_phy {
34 struct reset_control *rst_24m;
36 const struct rockchip_dp_phy_drv_data *drv_data;
39 static int rockchip_set_phy_state(struct phy *phy, bool enable)
41 struct rockchip_dp_phy *dp = phy_get_drvdata(phy);
42 const struct rockchip_dp_phy_drv_data *drv_data = dp->drv_data;
46 /* EDP 24m clock domain software reset request. */
47 reset_control_assert(dp->rst_24m);
49 reset_control_deassert(dp->rst_24m);
52 ret = regmap_write(dp->grf, drv_data->grf_reg_offset,
55 dev_err(dp->dev, "Can't enable PHY power %d\n", ret);
59 ret = clk_prepare_enable(dp->phy_24m);
61 clk_disable_unprepare(dp->phy_24m);
63 ret = regmap_write(dp->grf, drv_data->grf_reg_offset,
70 static int rockchip_dp_phy_power_on(struct phy *phy)
72 return rockchip_set_phy_state(phy, true);
75 static int rockchip_dp_phy_power_off(struct phy *phy)
77 return rockchip_set_phy_state(phy, false);
80 static const struct phy_ops rockchip_dp_phy_ops = {
81 .power_on = rockchip_dp_phy_power_on,
82 .power_off = rockchip_dp_phy_power_off,
86 static int rockchip_dp_phy_probe(struct platform_device *pdev)
88 struct device *dev = &pdev->dev;
89 struct device_node *np = dev->of_node;
90 struct phy_provider *phy_provider;
91 struct rockchip_dp_phy *dp;
92 const struct rockchip_dp_phy_drv_data *drv_data;
99 if (!dev->parent || !dev->parent->of_node)
102 drv_data = of_device_get_match_data(dev);
104 dev_err(dev, "No OF match data provided\n");
108 dp = devm_kzalloc(dev, sizeof(*dp), GFP_KERNEL);
113 dp->drv_data = drv_data;
115 dp->phy_24m = devm_clk_get(dev, "24m");
116 if (IS_ERR(dp->phy_24m)) {
117 dev_err(dev, "cannot get clock 24m\n");
118 return PTR_ERR(dp->phy_24m);
121 ret = clk_set_rate(dp->phy_24m, 24000000);
123 dev_err(dp->dev, "cannot set clock phy_24m %d\n", ret);
128 dp->rst_24m = devm_reset_control_get_optional(&pdev->dev, "edp_24m");
129 if (IS_ERR(dp->rst_24m)) {
130 dev_info(dev, "No edp_24m reset control specified\n");
134 dp->grf = syscon_node_to_regmap(dev->parent->of_node);
135 if (IS_ERR(dp->grf)) {
136 dev_err(dev, "rk3288-dp needs the General Register Files syscon\n");
137 return PTR_ERR(dp->grf);
140 ret = regmap_write(dp->grf, drv_data->grf_reg_offset,
141 drv_data->ref_clk_sel_inter);
143 dev_err(dp->dev, "Could not config GRF edp ref clk: %d\n", ret);
147 phy = devm_phy_create(dev, np, &rockchip_dp_phy_ops);
149 dev_err(dev, "failed to create phy\n");
152 phy_set_drvdata(phy, dp);
154 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
156 return PTR_ERR_OR_ZERO(phy_provider);
159 static const struct rockchip_dp_phy_drv_data rk3288_dp_phy_drv_data = {
160 .grf_reg_offset = 0x274,
161 .ref_clk_sel_inter = BIT(4) | BIT(20),
162 .siddq_on = 0 | BIT(21),
163 .siddq_off = BIT(5) | BIT(21),
166 static const struct rockchip_dp_phy_drv_data rk3368_dp_phy_drv_data = {
167 .grf_reg_offset = 0x410,
168 .ref_clk_sel_inter = BIT(0) | BIT(16),
169 .siddq_on = 0 | BIT(17),
170 .siddq_off = BIT(1) | BIT(17),
173 static const struct of_device_id rockchip_dp_phy_dt_ids[] = {
174 { .compatible = "rockchip,rk3288-dp-phy",
175 .data = &rk3288_dp_phy_drv_data },
176 { .compatible = "rockchip,rk3368-dp-phy",
177 .data = &rk3368_dp_phy_drv_data },
181 MODULE_DEVICE_TABLE(of, rockchip_dp_phy_dt_ids);
183 static struct platform_driver rockchip_dp_phy_driver = {
184 .probe = rockchip_dp_phy_probe,
186 .name = "rockchip-dp-phy",
187 .of_match_table = rockchip_dp_phy_dt_ids,
191 module_platform_driver(rockchip_dp_phy_driver);
193 MODULE_AUTHOR("Yakir Yang <ykk@rock-chips.com>");
194 MODULE_DESCRIPTION("Rockchip DP PHY driver");
195 MODULE_LICENSE("GPL v2");