2 * probe.c - PCI detection and setup code
5 #include <linux/kernel.h>
6 #include <linux/delay.h>
7 #include <linux/init.h>
9 #include <linux/pci_hotplug.h>
10 #include <linux/slab.h>
11 #include <linux/module.h>
12 #include <linux/cpumask.h>
13 #include <linux/pci-aspm.h>
14 #include <asm-generic/pci-bridge.h>
17 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
18 #define CARDBUS_RESERVE_BUSNR 3
20 static struct resource busn_resource = {
24 .flags = IORESOURCE_BUS,
27 /* Ugh. Need to stop exporting this to modules. */
28 LIST_HEAD(pci_root_buses);
29 EXPORT_SYMBOL(pci_root_buses);
31 static LIST_HEAD(pci_domain_busn_res_list);
33 struct pci_domain_busn_res {
34 struct list_head list;
39 static struct resource *get_pci_domain_busn_res(int domain_nr)
41 struct pci_domain_busn_res *r;
43 list_for_each_entry(r, &pci_domain_busn_res_list, list)
44 if (r->domain_nr == domain_nr)
47 r = kzalloc(sizeof(*r), GFP_KERNEL);
51 r->domain_nr = domain_nr;
54 r->res.flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED;
56 list_add_tail(&r->list, &pci_domain_busn_res_list);
61 static int find_anything(struct device *dev, void *data)
67 * Some device drivers need know if pci is initiated.
68 * Basically, we think pci is not initiated when there
69 * is no device to be found on the pci_bus_type.
71 int no_pci_devices(void)
76 dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything);
77 no_devices = (dev == NULL);
81 EXPORT_SYMBOL(no_pci_devices);
86 static void release_pcibus_dev(struct device *dev)
88 struct pci_bus *pci_bus = to_pci_bus(dev);
90 put_device(pci_bus->bridge);
91 pci_bus_remove_resources(pci_bus);
92 pci_release_bus_of_node(pci_bus);
96 static struct class pcibus_class = {
98 .dev_release = &release_pcibus_dev,
99 .dev_groups = pcibus_groups,
102 static int __init pcibus_class_init(void)
104 return class_register(&pcibus_class);
106 postcore_initcall(pcibus_class_init);
108 static u64 pci_size(u64 base, u64 maxbase, u64 mask)
110 u64 size = mask & maxbase; /* Find the significant bits */
114 /* Get the lowest of them to find the decode size, and
115 from that the extent. */
116 size = (size & ~(size-1)) - 1;
118 /* base == maxbase can be valid only if the BAR has
119 already been programmed with all 1s. */
120 if (base == maxbase && ((base | size) & mask) != mask)
126 static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar)
131 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
132 flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
133 flags |= IORESOURCE_IO;
137 flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
138 flags |= IORESOURCE_MEM;
139 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
140 flags |= IORESOURCE_PREFETCH;
142 mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
144 case PCI_BASE_ADDRESS_MEM_TYPE_32:
146 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
147 /* 1M mem BAR treated as 32-bit BAR */
149 case PCI_BASE_ADDRESS_MEM_TYPE_64:
150 flags |= IORESOURCE_MEM_64;
153 /* mem unknown type treated as 32-bit BAR */
159 #define PCI_COMMAND_DECODE_ENABLE (PCI_COMMAND_MEMORY | PCI_COMMAND_IO)
162 * pci_read_base - read a PCI BAR
163 * @dev: the PCI device
164 * @type: type of the BAR
165 * @res: resource buffer to be filled in
166 * @pos: BAR position in the config space
168 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
170 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
171 struct resource *res, unsigned int pos)
174 u64 l64, sz64, mask64;
176 struct pci_bus_region region, inverted_region;
178 mask = type ? PCI_ROM_ADDRESS_MASK : ~0;
180 /* No printks while decoding is disabled! */
181 if (!dev->mmio_always_on) {
182 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);
183 if (orig_cmd & PCI_COMMAND_DECODE_ENABLE) {
184 pci_write_config_word(dev, PCI_COMMAND,
185 orig_cmd & ~PCI_COMMAND_DECODE_ENABLE);
189 res->name = pci_name(dev);
191 pci_read_config_dword(dev, pos, &l);
192 pci_write_config_dword(dev, pos, l | mask);
193 pci_read_config_dword(dev, pos, &sz);
194 pci_write_config_dword(dev, pos, l);
197 * All bits set in sz means the device isn't working properly.
198 * If the BAR isn't implemented, all bits must be 0. If it's a
199 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
202 if (sz == 0xffffffff)
206 * I don't know how l can have all bits set. Copied from old code.
207 * Maybe it fixes a bug on some ancient platform.
212 if (type == pci_bar_unknown) {
213 res->flags = decode_bar(dev, l);
214 res->flags |= IORESOURCE_SIZEALIGN;
215 if (res->flags & IORESOURCE_IO) {
216 l64 = l & PCI_BASE_ADDRESS_IO_MASK;
217 sz64 = sz & PCI_BASE_ADDRESS_IO_MASK;
218 mask64 = PCI_BASE_ADDRESS_IO_MASK & (u32)IO_SPACE_LIMIT;
220 l64 = l & PCI_BASE_ADDRESS_MEM_MASK;
221 sz64 = sz & PCI_BASE_ADDRESS_MEM_MASK;
222 mask64 = (u32)PCI_BASE_ADDRESS_MEM_MASK;
225 res->flags |= (l & IORESOURCE_ROM_ENABLE);
226 l64 = l & PCI_ROM_ADDRESS_MASK;
227 sz64 = sz & PCI_ROM_ADDRESS_MASK;
228 mask64 = (u32)PCI_ROM_ADDRESS_MASK;
231 if (res->flags & IORESOURCE_MEM_64) {
232 pci_read_config_dword(dev, pos + 4, &l);
233 pci_write_config_dword(dev, pos + 4, ~0);
234 pci_read_config_dword(dev, pos + 4, &sz);
235 pci_write_config_dword(dev, pos + 4, l);
237 l64 |= ((u64)l << 32);
238 sz64 |= ((u64)sz << 32);
239 mask64 |= ((u64)~0 << 32);
242 if (!dev->mmio_always_on && (orig_cmd & PCI_COMMAND_DECODE_ENABLE))
243 pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
248 sz64 = pci_size(l64, sz64, mask64);
250 dev_info(&dev->dev, FW_BUG "reg 0x%x: invalid BAR (can't size)\n",
255 if (res->flags & IORESOURCE_MEM_64) {
256 if ((sizeof(dma_addr_t) < 8 || sizeof(resource_size_t) < 8) &&
257 sz64 > 0x100000000ULL) {
258 res->flags |= IORESOURCE_UNSET | IORESOURCE_DISABLED;
261 dev_err(&dev->dev, "reg 0x%x: can't handle BAR larger than 4GB (size %#010llx)\n",
262 pos, (unsigned long long)sz64);
266 if ((sizeof(dma_addr_t) < 8) && l) {
267 /* Above 32-bit boundary; try to reallocate */
268 res->flags |= IORESOURCE_UNSET;
271 dev_info(&dev->dev, "reg 0x%x: can't handle BAR above 4GB (bus address %#010llx)\n",
272 pos, (unsigned long long)l64);
278 region.end = l64 + sz64;
280 pcibios_bus_to_resource(dev->bus, res, ®ion);
281 pcibios_resource_to_bus(dev->bus, &inverted_region, res);
284 * If "A" is a BAR value (a bus address), "bus_to_resource(A)" is
285 * the corresponding resource address (the physical address used by
286 * the CPU. Converting that resource address back to a bus address
287 * should yield the original BAR value:
289 * resource_to_bus(bus_to_resource(A)) == A
291 * If it doesn't, CPU accesses to "bus_to_resource(A)" will not
292 * be claimed by the device.
294 if (inverted_region.start != region.start) {
295 res->flags |= IORESOURCE_UNSET;
297 res->end = region.end - region.start;
298 dev_info(&dev->dev, "reg 0x%x: initial BAR value %#010llx invalid\n",
299 pos, (unsigned long long)region.start);
309 dev_printk(KERN_DEBUG, &dev->dev, "reg 0x%x: %pR\n", pos, res);
311 return (res->flags & IORESOURCE_MEM_64) ? 1 : 0;
314 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
316 unsigned int pos, reg;
318 for (pos = 0; pos < howmany; pos++) {
319 struct resource *res = &dev->resource[pos];
320 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
321 pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
325 struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
326 dev->rom_base_reg = rom;
327 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
328 IORESOURCE_READONLY | IORESOURCE_CACHEABLE |
329 IORESOURCE_SIZEALIGN;
330 __pci_read_base(dev, pci_bar_mem32, res, rom);
334 static void pci_read_bridge_io(struct pci_bus *child)
336 struct pci_dev *dev = child->self;
337 u8 io_base_lo, io_limit_lo;
338 unsigned long io_mask, io_granularity, base, limit;
339 struct pci_bus_region region;
340 struct resource *res;
342 io_mask = PCI_IO_RANGE_MASK;
343 io_granularity = 0x1000;
344 if (dev->io_window_1k) {
345 /* Support 1K I/O space granularity */
346 io_mask = PCI_IO_1K_RANGE_MASK;
347 io_granularity = 0x400;
350 res = child->resource[0];
351 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
352 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
353 base = (io_base_lo & io_mask) << 8;
354 limit = (io_limit_lo & io_mask) << 8;
356 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
357 u16 io_base_hi, io_limit_hi;
359 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
360 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
361 base |= ((unsigned long) io_base_hi << 16);
362 limit |= ((unsigned long) io_limit_hi << 16);
366 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
368 region.end = limit + io_granularity - 1;
369 pcibios_bus_to_resource(dev->bus, res, ®ion);
370 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
374 static void pci_read_bridge_mmio(struct pci_bus *child)
376 struct pci_dev *dev = child->self;
377 u16 mem_base_lo, mem_limit_lo;
378 unsigned long base, limit;
379 struct pci_bus_region region;
380 struct resource *res;
382 res = child->resource[1];
383 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
384 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
385 base = ((unsigned long) mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
386 limit = ((unsigned long) mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
388 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
390 region.end = limit + 0xfffff;
391 pcibios_bus_to_resource(dev->bus, res, ®ion);
392 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
396 static void pci_read_bridge_mmio_pref(struct pci_bus *child)
398 struct pci_dev *dev = child->self;
399 u16 mem_base_lo, mem_limit_lo;
400 unsigned long base, limit;
401 struct pci_bus_region region;
402 struct resource *res;
404 res = child->resource[2];
405 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
406 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
407 base = ((unsigned long) mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
408 limit = ((unsigned long) mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
410 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
411 u32 mem_base_hi, mem_limit_hi;
413 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
414 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
417 * Some bridges set the base > limit by default, and some
418 * (broken) BIOSes do not initialize them. If we find
419 * this, just assume they are not being used.
421 if (mem_base_hi <= mem_limit_hi) {
422 #if BITS_PER_LONG == 64
423 base |= ((unsigned long) mem_base_hi) << 32;
424 limit |= ((unsigned long) mem_limit_hi) << 32;
426 if (mem_base_hi || mem_limit_hi) {
427 dev_err(&dev->dev, "can't handle 64-bit address space for bridge\n");
434 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) |
435 IORESOURCE_MEM | IORESOURCE_PREFETCH;
436 if (res->flags & PCI_PREF_RANGE_TYPE_64)
437 res->flags |= IORESOURCE_MEM_64;
439 region.end = limit + 0xfffff;
440 pcibios_bus_to_resource(dev->bus, res, ®ion);
441 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
445 void pci_read_bridge_bases(struct pci_bus *child)
447 struct pci_dev *dev = child->self;
448 struct resource *res;
451 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */
454 dev_info(&dev->dev, "PCI bridge to %pR%s\n",
456 dev->transparent ? " (subtractive decode)" : "");
458 pci_bus_remove_resources(child);
459 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
460 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
462 pci_read_bridge_io(child);
463 pci_read_bridge_mmio(child);
464 pci_read_bridge_mmio_pref(child);
466 if (dev->transparent) {
467 pci_bus_for_each_resource(child->parent, res, i) {
468 if (res && res->flags) {
469 pci_bus_add_resource(child, res,
470 PCI_SUBTRACTIVE_DECODE);
471 dev_printk(KERN_DEBUG, &dev->dev,
472 " bridge window %pR (subtractive decode)\n",
479 static struct pci_bus *pci_alloc_bus(struct pci_bus *parent)
483 b = kzalloc(sizeof(*b), GFP_KERNEL);
487 INIT_LIST_HEAD(&b->node);
488 INIT_LIST_HEAD(&b->children);
489 INIT_LIST_HEAD(&b->devices);
490 INIT_LIST_HEAD(&b->slots);
491 INIT_LIST_HEAD(&b->resources);
492 b->max_bus_speed = PCI_SPEED_UNKNOWN;
493 b->cur_bus_speed = PCI_SPEED_UNKNOWN;
494 #ifdef CONFIG_PCI_DOMAINS_GENERIC
496 b->domain_nr = parent->domain_nr;
501 static void pci_release_host_bridge_dev(struct device *dev)
503 struct pci_host_bridge *bridge = to_pci_host_bridge(dev);
505 if (bridge->release_fn)
506 bridge->release_fn(bridge);
508 pci_free_resource_list(&bridge->windows);
513 static struct pci_host_bridge *pci_alloc_host_bridge(struct pci_bus *b)
515 struct pci_host_bridge *bridge;
517 bridge = kzalloc(sizeof(*bridge), GFP_KERNEL);
521 INIT_LIST_HEAD(&bridge->windows);
526 static const unsigned char pcix_bus_speed[] = {
527 PCI_SPEED_UNKNOWN, /* 0 */
528 PCI_SPEED_66MHz_PCIX, /* 1 */
529 PCI_SPEED_100MHz_PCIX, /* 2 */
530 PCI_SPEED_133MHz_PCIX, /* 3 */
531 PCI_SPEED_UNKNOWN, /* 4 */
532 PCI_SPEED_66MHz_PCIX_ECC, /* 5 */
533 PCI_SPEED_100MHz_PCIX_ECC, /* 6 */
534 PCI_SPEED_133MHz_PCIX_ECC, /* 7 */
535 PCI_SPEED_UNKNOWN, /* 8 */
536 PCI_SPEED_66MHz_PCIX_266, /* 9 */
537 PCI_SPEED_100MHz_PCIX_266, /* A */
538 PCI_SPEED_133MHz_PCIX_266, /* B */
539 PCI_SPEED_UNKNOWN, /* C */
540 PCI_SPEED_66MHz_PCIX_533, /* D */
541 PCI_SPEED_100MHz_PCIX_533, /* E */
542 PCI_SPEED_133MHz_PCIX_533 /* F */
545 const unsigned char pcie_link_speed[] = {
546 PCI_SPEED_UNKNOWN, /* 0 */
547 PCIE_SPEED_2_5GT, /* 1 */
548 PCIE_SPEED_5_0GT, /* 2 */
549 PCIE_SPEED_8_0GT, /* 3 */
550 PCI_SPEED_UNKNOWN, /* 4 */
551 PCI_SPEED_UNKNOWN, /* 5 */
552 PCI_SPEED_UNKNOWN, /* 6 */
553 PCI_SPEED_UNKNOWN, /* 7 */
554 PCI_SPEED_UNKNOWN, /* 8 */
555 PCI_SPEED_UNKNOWN, /* 9 */
556 PCI_SPEED_UNKNOWN, /* A */
557 PCI_SPEED_UNKNOWN, /* B */
558 PCI_SPEED_UNKNOWN, /* C */
559 PCI_SPEED_UNKNOWN, /* D */
560 PCI_SPEED_UNKNOWN, /* E */
561 PCI_SPEED_UNKNOWN /* F */
564 void pcie_update_link_speed(struct pci_bus *bus, u16 linksta)
566 bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS];
568 EXPORT_SYMBOL_GPL(pcie_update_link_speed);
570 static unsigned char agp_speeds[] = {
578 static enum pci_bus_speed agp_speed(int agp3, int agpstat)
584 else if (agpstat & 2)
586 else if (agpstat & 1)
598 return agp_speeds[index];
601 static void pci_set_bus_speed(struct pci_bus *bus)
603 struct pci_dev *bridge = bus->self;
606 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP);
608 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3);
612 pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat);
613 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7);
615 pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd);
616 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7);
619 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
622 enum pci_bus_speed max;
624 pci_read_config_word(bridge, pos + PCI_X_BRIDGE_SSTATUS,
627 if (status & PCI_X_SSTATUS_533MHZ) {
628 max = PCI_SPEED_133MHz_PCIX_533;
629 } else if (status & PCI_X_SSTATUS_266MHZ) {
630 max = PCI_SPEED_133MHz_PCIX_266;
631 } else if (status & PCI_X_SSTATUS_133MHZ) {
632 if ((status & PCI_X_SSTATUS_VERS) == PCI_X_SSTATUS_V2)
633 max = PCI_SPEED_133MHz_PCIX_ECC;
635 max = PCI_SPEED_133MHz_PCIX;
637 max = PCI_SPEED_66MHz_PCIX;
640 bus->max_bus_speed = max;
641 bus->cur_bus_speed = pcix_bus_speed[
642 (status & PCI_X_SSTATUS_FREQ) >> 6];
647 if (pci_is_pcie(bridge)) {
651 pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap);
652 bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS];
654 pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta);
655 pcie_update_link_speed(bus, linksta);
659 static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
660 struct pci_dev *bridge, int busnr)
662 struct pci_bus *child;
667 * Allocate a new bus, and inherit stuff from the parent..
669 child = pci_alloc_bus(parent);
673 child->parent = parent;
674 child->ops = parent->ops;
675 child->msi = parent->msi;
676 child->sysdata = parent->sysdata;
677 child->bus_flags = parent->bus_flags;
679 /* initialize some portions of the bus device, but don't register it
680 * now as the parent is not properly set up yet.
682 child->dev.class = &pcibus_class;
683 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
686 * Set up the primary, secondary and subordinate
689 child->number = child->busn_res.start = busnr;
690 child->primary = parent->busn_res.start;
691 child->busn_res.end = 0xff;
694 child->dev.parent = parent->bridge;
698 child->self = bridge;
699 child->bridge = get_device(&bridge->dev);
700 child->dev.parent = child->bridge;
701 pci_set_bus_of_node(child);
702 pci_set_bus_speed(child);
704 /* Set up default resource pointers and names.. */
705 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
706 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
707 child->resource[i]->name = child->name;
709 bridge->subordinate = child;
712 ret = device_register(&child->dev);
715 pcibios_add_bus(child);
717 /* Create legacy_io and legacy_mem files for this bus */
718 pci_create_legacy_files(child);
723 struct pci_bus *pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev,
726 struct pci_bus *child;
728 child = pci_alloc_child_bus(parent, dev, busnr);
730 down_write(&pci_bus_sem);
731 list_add_tail(&child->node, &parent->children);
732 up_write(&pci_bus_sem);
736 EXPORT_SYMBOL(pci_add_new_bus);
738 static void pci_enable_crs(struct pci_dev *pdev)
742 /* Enable CRS Software Visibility if supported */
743 pcie_capability_read_word(pdev, PCI_EXP_RTCAP, &root_cap);
744 if (root_cap & PCI_EXP_RTCAP_CRSVIS)
745 pcie_capability_set_word(pdev, PCI_EXP_RTCTL,
746 PCI_EXP_RTCTL_CRSSVE);
750 * If it's a bridge, configure it and scan the bus behind it.
751 * For CardBus bridges, we don't scan behind as the devices will
752 * be handled by the bridge driver itself.
754 * We need to process bridges in two passes -- first we scan those
755 * already configured by the BIOS and after we are done with all of
756 * them, we proceed to assigning numbers to the remaining buses in
757 * order to avoid overlaps between old and new bus numbers.
759 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
761 struct pci_bus *child;
762 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
765 u8 primary, secondary, subordinate;
768 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
769 primary = buses & 0xFF;
770 secondary = (buses >> 8) & 0xFF;
771 subordinate = (buses >> 16) & 0xFF;
773 dev_dbg(&dev->dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
774 secondary, subordinate, pass);
776 if (!primary && (primary != bus->number) && secondary && subordinate) {
777 dev_warn(&dev->dev, "Primary bus is hard wired to 0\n");
778 primary = bus->number;
781 /* Check if setup is sensible at all */
783 (primary != bus->number || secondary <= bus->number ||
784 secondary > subordinate)) {
785 dev_info(&dev->dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n",
786 secondary, subordinate);
790 /* Disable MasterAbortMode during probing to avoid reporting
791 of bus errors (in some architectures) */
792 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
793 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
794 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
798 if ((secondary || subordinate) && !pcibios_assign_all_busses() &&
799 !is_cardbus && !broken) {
802 * Bus already configured by firmware, process it in the first
803 * pass and just note the configuration.
809 * The bus might already exist for two reasons: Either we are
810 * rescanning the bus or the bus is reachable through more than
811 * one bridge. The second case can happen with the i450NX
814 child = pci_find_bus(pci_domain_nr(bus), secondary);
816 child = pci_add_new_bus(bus, dev, secondary);
819 child->primary = primary;
820 pci_bus_insert_busn_res(child, secondary, subordinate);
821 child->bridge_ctl = bctl;
824 cmax = pci_scan_child_bus(child);
825 if (cmax > subordinate)
826 dev_warn(&dev->dev, "bridge has subordinate %02x but max busn %02x\n",
828 /* subordinate should equal child->busn_res.end */
829 if (subordinate > max)
833 * We need to assign a number to this bus which we always
834 * do in the second pass.
837 if (pcibios_assign_all_busses() || broken || is_cardbus)
838 /* Temporarily disable forwarding of the
839 configuration cycles on all bridges in
840 this bus segment to avoid possible
841 conflicts in the second pass between two
842 bridges programmed with overlapping
844 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
850 pci_write_config_word(dev, PCI_STATUS, 0xffff);
852 /* Prevent assigning a bus number that already exists.
853 * This can happen when a bridge is hot-plugged, so in
854 * this case we only re-scan this bus. */
855 child = pci_find_bus(pci_domain_nr(bus), max+1);
857 child = pci_add_new_bus(bus, dev, max+1);
860 pci_bus_insert_busn_res(child, max+1, 0xff);
863 buses = (buses & 0xff000000)
864 | ((unsigned int)(child->primary) << 0)
865 | ((unsigned int)(child->busn_res.start) << 8)
866 | ((unsigned int)(child->busn_res.end) << 16);
869 * yenta.c forces a secondary latency timer of 176.
870 * Copy that behaviour here.
873 buses &= ~0xff000000;
874 buses |= CARDBUS_LATENCY_TIMER << 24;
878 * We need to blast all three values with a single write.
880 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
883 child->bridge_ctl = bctl;
884 max = pci_scan_child_bus(child);
887 * For CardBus bridges, we leave 4 bus numbers
888 * as cards with a PCI-to-PCI bridge can be
891 for (i = 0; i < CARDBUS_RESERVE_BUSNR; i++) {
892 struct pci_bus *parent = bus;
893 if (pci_find_bus(pci_domain_nr(bus),
896 while (parent->parent) {
897 if ((!pcibios_assign_all_busses()) &&
898 (parent->busn_res.end > max) &&
899 (parent->busn_res.end <= max+i)) {
902 parent = parent->parent;
906 * Often, there are two cardbus bridges
907 * -- try to leave one valid bus number
917 * Set the subordinate bus number to its real value.
919 pci_bus_update_busn_res_end(child, max);
920 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
924 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
925 pci_domain_nr(bus), child->number);
927 /* Has only triggered on CardBus, fixup is in yenta_socket */
928 while (bus->parent) {
929 if ((child->busn_res.end > bus->busn_res.end) ||
930 (child->number > bus->busn_res.end) ||
931 (child->number < bus->number) ||
932 (child->busn_res.end < bus->number)) {
933 dev_info(&child->dev, "%pR %s hidden behind%s bridge %s %pR\n",
935 (bus->number > child->busn_res.end &&
936 bus->busn_res.end < child->number) ?
937 "wholly" : "partially",
938 bus->self->transparent ? " transparent" : "",
946 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
950 EXPORT_SYMBOL(pci_scan_bridge);
953 * Read interrupt line and base address registers.
954 * The architecture-dependent code can tweak these, of course.
956 static void pci_read_irq(struct pci_dev *dev)
960 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
963 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
967 void set_pcie_port_type(struct pci_dev *pdev)
972 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
975 pdev->pcie_cap = pos;
976 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
977 pdev->pcie_flags_reg = reg16;
978 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16);
979 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
982 void set_pcie_hotplug_bridge(struct pci_dev *pdev)
986 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, ®32);
987 if (reg32 & PCI_EXP_SLTCAP_HPC)
988 pdev->is_hotplug_bridge = 1;
992 * pci_ext_cfg_is_aliased - is ext config space just an alias of std config?
995 * PCI Express to PCI/PCI-X Bridge Specification, rev 1.0, 4.1.4 says that
996 * when forwarding a type1 configuration request the bridge must check that
997 * the extended register address field is zero. The bridge is not permitted
998 * to forward the transactions and must handle it as an Unsupported Request.
999 * Some bridges do not follow this rule and simply drop the extended register
1000 * bits, resulting in the standard config space being aliased, every 256
1001 * bytes across the entire configuration space. Test for this condition by
1002 * comparing the first dword of each potential alias to the vendor/device ID.
1004 * ASM1083/1085 PCIe-to-PCI Reversible Bridge (1b21:1080, rev 01 & 03)
1005 * AMD/ATI SBx00 PCI to PCI Bridge (1002:4384, rev 40)
1007 static bool pci_ext_cfg_is_aliased(struct pci_dev *dev)
1009 #ifdef CONFIG_PCI_QUIRKS
1013 pci_read_config_dword(dev, PCI_VENDOR_ID, &header);
1015 for (pos = PCI_CFG_SPACE_SIZE;
1016 pos < PCI_CFG_SPACE_EXP_SIZE; pos += PCI_CFG_SPACE_SIZE) {
1017 if (pci_read_config_dword(dev, pos, &tmp) != PCIBIOS_SUCCESSFUL
1029 * pci_cfg_space_size - get the configuration space size of the PCI device.
1032 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
1033 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
1034 * access it. Maybe we don't have a way to generate extended config space
1035 * accesses, or the device is behind a reverse Express bridge. So we try
1036 * reading the dword at 0x100 which must either be 0 or a valid extended
1037 * capability header.
1039 static int pci_cfg_space_size_ext(struct pci_dev *dev)
1042 int pos = PCI_CFG_SPACE_SIZE;
1044 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
1046 if (status == 0xffffffff || pci_ext_cfg_is_aliased(dev))
1049 return PCI_CFG_SPACE_EXP_SIZE;
1052 return PCI_CFG_SPACE_SIZE;
1055 int pci_cfg_space_size(struct pci_dev *dev)
1061 class = dev->class >> 8;
1062 if (class == PCI_CLASS_BRIDGE_HOST)
1063 return pci_cfg_space_size_ext(dev);
1065 if (!pci_is_pcie(dev)) {
1066 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1070 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
1071 if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
1075 return pci_cfg_space_size_ext(dev);
1078 return PCI_CFG_SPACE_SIZE;
1081 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
1084 * pci_setup_device - fill in class and map information of a device
1085 * @dev: the device structure to fill
1087 * Initialize the device structure with information about the device's
1088 * vendor,class,memory and IO-space addresses,IRQ lines etc.
1089 * Called at initialisation of the PCI subsystem and by CardBus services.
1090 * Returns 0 on success and negative if unknown type of device (not normal,
1091 * bridge or CardBus).
1093 int pci_setup_device(struct pci_dev *dev)
1097 struct pci_slot *slot;
1099 struct pci_bus_region region;
1100 struct resource *res;
1102 if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type))
1105 dev->sysdata = dev->bus->sysdata;
1106 dev->dev.parent = dev->bus->bridge;
1107 dev->dev.bus = &pci_bus_type;
1108 dev->hdr_type = hdr_type & 0x7f;
1109 dev->multifunction = !!(hdr_type & 0x80);
1110 dev->error_state = pci_channel_io_normal;
1111 set_pcie_port_type(dev);
1113 list_for_each_entry(slot, &dev->bus->slots, list)
1114 if (PCI_SLOT(dev->devfn) == slot->number)
1117 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
1118 set this higher, assuming the system even supports it. */
1119 dev->dma_mask = 0xffffffff;
1121 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
1122 dev->bus->number, PCI_SLOT(dev->devfn),
1123 PCI_FUNC(dev->devfn));
1125 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
1126 dev->revision = class & 0xff;
1127 dev->class = class >> 8; /* upper 3 bytes */
1129 dev_printk(KERN_DEBUG, &dev->dev, "[%04x:%04x] type %02x class %#08x\n",
1130 dev->vendor, dev->device, dev->hdr_type, dev->class);
1132 /* need to have dev->class ready */
1133 dev->cfg_size = pci_cfg_space_size(dev);
1135 /* "Unknown power state" */
1136 dev->current_state = PCI_UNKNOWN;
1138 /* Early fixups, before probing the BARs */
1139 pci_fixup_device(pci_fixup_early, dev);
1140 /* device class may be changed after fixup */
1141 class = dev->class >> 8;
1143 switch (dev->hdr_type) { /* header type */
1144 case PCI_HEADER_TYPE_NORMAL: /* standard header */
1145 if (class == PCI_CLASS_BRIDGE_PCI)
1148 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
1149 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1150 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
1153 * Do the ugly legacy mode stuff here rather than broken chip
1154 * quirk code. Legacy mode ATA controllers have fixed
1155 * addresses. These are not always echoed in BAR0-3, and
1156 * BAR0-3 in a few cases contain junk!
1158 if (class == PCI_CLASS_STORAGE_IDE) {
1160 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
1161 if ((progif & 1) == 0) {
1162 region.start = 0x1F0;
1164 res = &dev->resource[0];
1165 res->flags = LEGACY_IO_RESOURCE;
1166 pcibios_bus_to_resource(dev->bus, res, ®ion);
1167 dev_info(&dev->dev, "legacy IDE quirk: reg 0x10: %pR\n",
1169 region.start = 0x3F6;
1171 res = &dev->resource[1];
1172 res->flags = LEGACY_IO_RESOURCE;
1173 pcibios_bus_to_resource(dev->bus, res, ®ion);
1174 dev_info(&dev->dev, "legacy IDE quirk: reg 0x14: %pR\n",
1177 if ((progif & 4) == 0) {
1178 region.start = 0x170;
1180 res = &dev->resource[2];
1181 res->flags = LEGACY_IO_RESOURCE;
1182 pcibios_bus_to_resource(dev->bus, res, ®ion);
1183 dev_info(&dev->dev, "legacy IDE quirk: reg 0x18: %pR\n",
1185 region.start = 0x376;
1187 res = &dev->resource[3];
1188 res->flags = LEGACY_IO_RESOURCE;
1189 pcibios_bus_to_resource(dev->bus, res, ®ion);
1190 dev_info(&dev->dev, "legacy IDE quirk: reg 0x1c: %pR\n",
1196 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
1197 if (class != PCI_CLASS_BRIDGE_PCI)
1199 /* The PCI-to-PCI bridge spec requires that subtractive
1200 decoding (i.e. transparent) bridge must have programming
1201 interface code of 0x01. */
1203 dev->transparent = ((dev->class & 0xff) == 1);
1204 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
1205 set_pcie_hotplug_bridge(dev);
1206 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID);
1208 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor);
1209 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device);
1213 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
1214 if (class != PCI_CLASS_BRIDGE_CARDBUS)
1217 pci_read_bases(dev, 1, 0);
1218 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1219 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
1222 default: /* unknown header */
1223 dev_err(&dev->dev, "unknown header type %02x, ignoring device\n",
1228 dev_err(&dev->dev, "ignoring class %#08x (doesn't match header type %02x)\n",
1229 dev->class, dev->hdr_type);
1230 dev->class = PCI_CLASS_NOT_DEFINED;
1233 /* We found a fine healthy device, go go go... */
1237 static struct hpp_type0 pci_default_type0 = {
1239 .cache_line_size = 8,
1240 .latency_timer = 0x40,
1245 static void program_hpp_type0(struct pci_dev *dev, struct hpp_type0 *hpp)
1247 u16 pci_cmd, pci_bctl;
1250 hpp = &pci_default_type0;
1252 if (hpp->revision > 1) {
1254 "PCI settings rev %d not supported; using defaults\n",
1256 hpp = &pci_default_type0;
1259 pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, hpp->cache_line_size);
1260 pci_write_config_byte(dev, PCI_LATENCY_TIMER, hpp->latency_timer);
1261 pci_read_config_word(dev, PCI_COMMAND, &pci_cmd);
1262 if (hpp->enable_serr)
1263 pci_cmd |= PCI_COMMAND_SERR;
1264 if (hpp->enable_perr)
1265 pci_cmd |= PCI_COMMAND_PARITY;
1266 pci_write_config_word(dev, PCI_COMMAND, pci_cmd);
1268 /* Program bridge control value */
1269 if ((dev->class >> 8) == PCI_CLASS_BRIDGE_PCI) {
1270 pci_write_config_byte(dev, PCI_SEC_LATENCY_TIMER,
1271 hpp->latency_timer);
1272 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &pci_bctl);
1273 if (hpp->enable_serr)
1274 pci_bctl |= PCI_BRIDGE_CTL_SERR;
1275 if (hpp->enable_perr)
1276 pci_bctl |= PCI_BRIDGE_CTL_PARITY;
1277 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, pci_bctl);
1281 static void program_hpp_type1(struct pci_dev *dev, struct hpp_type1 *hpp)
1284 dev_warn(&dev->dev, "PCI-X settings not supported\n");
1287 static void program_hpp_type2(struct pci_dev *dev, struct hpp_type2 *hpp)
1295 if (hpp->revision > 1) {
1296 dev_warn(&dev->dev, "PCIe settings rev %d not supported\n",
1302 * Don't allow _HPX to change MPS or MRRS settings. We manage
1303 * those to make sure they're consistent with the rest of the
1306 hpp->pci_exp_devctl_and |= PCI_EXP_DEVCTL_PAYLOAD |
1307 PCI_EXP_DEVCTL_READRQ;
1308 hpp->pci_exp_devctl_or &= ~(PCI_EXP_DEVCTL_PAYLOAD |
1309 PCI_EXP_DEVCTL_READRQ);
1311 /* Initialize Device Control Register */
1312 pcie_capability_clear_and_set_word(dev, PCI_EXP_DEVCTL,
1313 ~hpp->pci_exp_devctl_and, hpp->pci_exp_devctl_or);
1315 /* Initialize Link Control Register */
1316 if (dev->subordinate)
1317 pcie_capability_clear_and_set_word(dev, PCI_EXP_LNKCTL,
1318 ~hpp->pci_exp_lnkctl_and, hpp->pci_exp_lnkctl_or);
1320 /* Find Advanced Error Reporting Enhanced Capability */
1321 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ERR);
1325 /* Initialize Uncorrectable Error Mask Register */
1326 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, ®32);
1327 reg32 = (reg32 & hpp->unc_err_mask_and) | hpp->unc_err_mask_or;
1328 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_MASK, reg32);
1330 /* Initialize Uncorrectable Error Severity Register */
1331 pci_read_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, ®32);
1332 reg32 = (reg32 & hpp->unc_err_sever_and) | hpp->unc_err_sever_or;
1333 pci_write_config_dword(dev, pos + PCI_ERR_UNCOR_SEVER, reg32);
1335 /* Initialize Correctable Error Mask Register */
1336 pci_read_config_dword(dev, pos + PCI_ERR_COR_MASK, ®32);
1337 reg32 = (reg32 & hpp->cor_err_mask_and) | hpp->cor_err_mask_or;
1338 pci_write_config_dword(dev, pos + PCI_ERR_COR_MASK, reg32);
1340 /* Initialize Advanced Error Capabilities and Control Register */
1341 pci_read_config_dword(dev, pos + PCI_ERR_CAP, ®32);
1342 reg32 = (reg32 & hpp->adv_err_cap_and) | hpp->adv_err_cap_or;
1343 pci_write_config_dword(dev, pos + PCI_ERR_CAP, reg32);
1346 * FIXME: The following two registers are not supported yet.
1348 * o Secondary Uncorrectable Error Severity Register
1349 * o Secondary Uncorrectable Error Mask Register
1353 static void pci_configure_device(struct pci_dev *dev)
1355 struct hotplug_params hpp;
1358 memset(&hpp, 0, sizeof(hpp));
1359 ret = pci_get_hp_params(dev, &hpp);
1363 program_hpp_type2(dev, hpp.t2);
1364 program_hpp_type1(dev, hpp.t1);
1365 program_hpp_type0(dev, hpp.t0);
1368 static void pci_release_capabilities(struct pci_dev *dev)
1370 pci_vpd_release(dev);
1371 pci_iov_release(dev);
1372 pci_free_cap_save_buffers(dev);
1376 * pci_release_dev - free a pci device structure when all users of it are finished.
1377 * @dev: device that's been disconnected
1379 * Will be called only by the device core when all users of this pci device are
1382 static void pci_release_dev(struct device *dev)
1384 struct pci_dev *pci_dev;
1386 pci_dev = to_pci_dev(dev);
1387 pci_release_capabilities(pci_dev);
1388 pci_release_of_node(pci_dev);
1389 pcibios_release_device(pci_dev);
1390 pci_bus_put(pci_dev->bus);
1391 kfree(pci_dev->driver_override);
1395 struct pci_dev *pci_alloc_dev(struct pci_bus *bus)
1397 struct pci_dev *dev;
1399 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
1403 INIT_LIST_HEAD(&dev->bus_list);
1404 dev->dev.type = &pci_dev_type;
1405 dev->bus = pci_bus_get(bus);
1409 EXPORT_SYMBOL(pci_alloc_dev);
1411 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
1416 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
1419 /* some broken boards return 0 or ~0 if a slot is empty: */
1420 if (*l == 0xffffffff || *l == 0x00000000 ||
1421 *l == 0x0000ffff || *l == 0xffff0000)
1425 * Configuration Request Retry Status. Some root ports return the
1426 * actual device ID instead of the synthetic ID (0xFFFF) required
1427 * by the PCIe spec. Ignore the device ID and only check for
1430 while ((*l & 0xffff) == 0x0001) {
1436 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
1438 /* Card hasn't responded in 60 seconds? Must be stuck. */
1439 if (delay > crs_timeout) {
1440 printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not responding\n",
1441 pci_domain_nr(bus), bus->number, PCI_SLOT(devfn),
1449 EXPORT_SYMBOL(pci_bus_read_dev_vendor_id);
1452 * Read the config data for a PCI device, sanity-check it
1453 * and fill in the dev structure...
1455 static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
1457 struct pci_dev *dev;
1460 if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000))
1463 dev = pci_alloc_dev(bus);
1468 dev->vendor = l & 0xffff;
1469 dev->device = (l >> 16) & 0xffff;
1471 pci_set_of_node(dev);
1473 if (pci_setup_device(dev)) {
1474 pci_bus_put(dev->bus);
1482 static void pci_init_capabilities(struct pci_dev *dev)
1484 /* MSI/MSI-X list */
1485 pci_msi_init_pci_dev(dev);
1487 /* Buffers for saving PCIe and PCI-X capabilities */
1488 pci_allocate_cap_save_buffers(dev);
1490 /* Power Management */
1493 /* Vital Product Data */
1494 pci_vpd_pci22_init(dev);
1496 /* Alternative Routing-ID Forwarding */
1497 pci_configure_ari(dev);
1499 /* Single Root I/O Virtualization */
1502 /* Enable ACS P2P upstream forwarding */
1503 pci_enable_acs(dev);
1506 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
1510 pci_configure_device(dev);
1512 device_initialize(&dev->dev);
1513 dev->dev.release = pci_release_dev;
1515 set_dev_node(&dev->dev, pcibus_to_node(bus));
1516 dev->dev.dma_mask = &dev->dma_mask;
1517 dev->dev.dma_parms = &dev->dma_parms;
1518 dev->dev.coherent_dma_mask = 0xffffffffull;
1520 pci_set_dma_max_seg_size(dev, 65536);
1521 pci_set_dma_seg_boundary(dev, 0xffffffff);
1523 /* Fix up broken headers */
1524 pci_fixup_device(pci_fixup_header, dev);
1526 /* moved out from quirk header fixup code */
1527 pci_reassigndev_resource_alignment(dev);
1529 /* Clear the state_saved flag. */
1530 dev->state_saved = false;
1532 /* Initialize various capabilities */
1533 pci_init_capabilities(dev);
1536 * Add the device to our list of discovered devices
1537 * and the bus list for fixup functions, etc.
1539 down_write(&pci_bus_sem);
1540 list_add_tail(&dev->bus_list, &bus->devices);
1541 up_write(&pci_bus_sem);
1543 ret = pcibios_add_device(dev);
1546 /* Notifier could use PCI capabilities */
1547 dev->match_driver = false;
1548 ret = device_add(&dev->dev);
1552 struct pci_dev *pci_scan_single_device(struct pci_bus *bus, int devfn)
1554 struct pci_dev *dev;
1556 dev = pci_get_slot(bus, devfn);
1562 dev = pci_scan_device(bus, devfn);
1566 pci_device_add(dev, bus);
1570 EXPORT_SYMBOL(pci_scan_single_device);
1572 static unsigned next_fn(struct pci_bus *bus, struct pci_dev *dev, unsigned fn)
1578 if (pci_ari_enabled(bus)) {
1581 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
1585 pci_read_config_word(dev, pos + PCI_ARI_CAP, &cap);
1586 next_fn = PCI_ARI_CAP_NFN(cap);
1588 return 0; /* protect against malformed list */
1593 /* dev may be NULL for non-contiguous multifunction devices */
1594 if (!dev || dev->multifunction)
1595 return (fn + 1) % 8;
1600 static int only_one_child(struct pci_bus *bus)
1602 struct pci_dev *parent = bus->self;
1604 if (!parent || !pci_is_pcie(parent))
1606 if (pci_pcie_type(parent) == PCI_EXP_TYPE_ROOT_PORT)
1608 if (pci_pcie_type(parent) == PCI_EXP_TYPE_DOWNSTREAM &&
1609 !pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS))
1615 * pci_scan_slot - scan a PCI slot on a bus for devices.
1616 * @bus: PCI bus to scan
1617 * @devfn: slot number to scan (must have zero function.)
1619 * Scan a PCI slot on the specified PCI bus for devices, adding
1620 * discovered devices to the @bus->devices list. New devices
1621 * will not have is_added set.
1623 * Returns the number of new devices found.
1625 int pci_scan_slot(struct pci_bus *bus, int devfn)
1627 unsigned fn, nr = 0;
1628 struct pci_dev *dev;
1630 if (only_one_child(bus) && (devfn > 0))
1631 return 0; /* Already scanned the entire slot */
1633 dev = pci_scan_single_device(bus, devfn);
1639 for (fn = next_fn(bus, dev, 0); fn > 0; fn = next_fn(bus, dev, fn)) {
1640 dev = pci_scan_single_device(bus, devfn + fn);
1644 dev->multifunction = 1;
1648 /* only one slot has pcie device */
1649 if (bus->self && nr)
1650 pcie_aspm_init_link_state(bus->self);
1654 EXPORT_SYMBOL(pci_scan_slot);
1656 static int pcie_find_smpss(struct pci_dev *dev, void *data)
1660 if (!pci_is_pcie(dev))
1664 * We don't have a way to change MPS settings on devices that have
1665 * drivers attached. A hot-added device might support only the minimum
1666 * MPS setting (MPS=128). Therefore, if the fabric contains a bridge
1667 * where devices may be hot-added, we limit the fabric MPS to 128 so
1668 * hot-added devices will work correctly.
1670 * However, if we hot-add a device to a slot directly below a Root
1671 * Port, it's impossible for there to be other existing devices below
1672 * the port. We don't limit the MPS in this case because we can
1673 * reconfigure MPS on both the Root Port and the hot-added device,
1674 * and there are no other devices involved.
1676 * Note that this PCIE_BUS_SAFE path assumes no peer-to-peer DMA.
1678 if (dev->is_hotplug_bridge &&
1679 pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT)
1682 if (*smpss > dev->pcie_mpss)
1683 *smpss = dev->pcie_mpss;
1688 static void pcie_write_mps(struct pci_dev *dev, int mps)
1692 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
1693 mps = 128 << dev->pcie_mpss;
1695 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT &&
1697 /* For "Performance", the assumption is made that
1698 * downstream communication will never be larger than
1699 * the MRRS. So, the MPS only needs to be configured
1700 * for the upstream communication. This being the case,
1701 * walk from the top down and set the MPS of the child
1702 * to that of the parent bus.
1704 * Configure the device MPS with the smaller of the
1705 * device MPSS or the bridge MPS (which is assumed to be
1706 * properly configured at this point to the largest
1707 * allowable MPS based on its parent bus).
1709 mps = min(mps, pcie_get_mps(dev->bus->self));
1712 rc = pcie_set_mps(dev, mps);
1714 dev_err(&dev->dev, "Failed attempting to set the MPS\n");
1717 static void pcie_write_mrrs(struct pci_dev *dev)
1721 /* In the "safe" case, do not configure the MRRS. There appear to be
1722 * issues with setting MRRS to 0 on a number of devices.
1724 if (pcie_bus_config != PCIE_BUS_PERFORMANCE)
1727 /* For Max performance, the MRRS must be set to the largest supported
1728 * value. However, it cannot be configured larger than the MPS the
1729 * device or the bus can support. This should already be properly
1730 * configured by a prior call to pcie_write_mps.
1732 mrrs = pcie_get_mps(dev);
1734 /* MRRS is a R/W register. Invalid values can be written, but a
1735 * subsequent read will verify if the value is acceptable or not.
1736 * If the MRRS value provided is not acceptable (e.g., too large),
1737 * shrink the value until it is acceptable to the HW.
1739 while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) {
1740 rc = pcie_set_readrq(dev, mrrs);
1744 dev_warn(&dev->dev, "Failed attempting to set the MRRS\n");
1749 dev_err(&dev->dev, "MRRS was unable to be configured with a safe value. If problems are experienced, try running with pci=pcie_bus_safe\n");
1752 static void pcie_bus_detect_mps(struct pci_dev *dev)
1754 struct pci_dev *bridge = dev->bus->self;
1760 mps = pcie_get_mps(dev);
1761 p_mps = pcie_get_mps(bridge);
1764 dev_warn(&dev->dev, "Max Payload Size %d, but upstream %s set to %d; if necessary, use \"pci=pcie_bus_safe\" and report a bug\n",
1765 mps, pci_name(bridge), p_mps);
1768 static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
1772 if (!pci_is_pcie(dev))
1775 if (pcie_bus_config == PCIE_BUS_TUNE_OFF) {
1776 pcie_bus_detect_mps(dev);
1780 mps = 128 << *(u8 *)data;
1781 orig_mps = pcie_get_mps(dev);
1783 pcie_write_mps(dev, mps);
1784 pcie_write_mrrs(dev);
1786 dev_info(&dev->dev, "Max Payload Size set to %4d/%4d (was %4d), Max Read Rq %4d\n",
1787 pcie_get_mps(dev), 128 << dev->pcie_mpss,
1788 orig_mps, pcie_get_readrq(dev));
1793 /* pcie_bus_configure_settings requires that pci_walk_bus work in a top-down,
1794 * parents then children fashion. If this changes, then this code will not
1797 void pcie_bus_configure_settings(struct pci_bus *bus)
1804 if (!pci_is_pcie(bus->self))
1807 /* FIXME - Peer to peer DMA is possible, though the endpoint would need
1808 * to be aware of the MPS of the destination. To work around this,
1809 * simply force the MPS of the entire system to the smallest possible.
1811 if (pcie_bus_config == PCIE_BUS_PEER2PEER)
1814 if (pcie_bus_config == PCIE_BUS_SAFE) {
1815 smpss = bus->self->pcie_mpss;
1817 pcie_find_smpss(bus->self, &smpss);
1818 pci_walk_bus(bus, pcie_find_smpss, &smpss);
1821 pcie_bus_configure_set(bus->self, &smpss);
1822 pci_walk_bus(bus, pcie_bus_configure_set, &smpss);
1824 EXPORT_SYMBOL_GPL(pcie_bus_configure_settings);
1826 unsigned int pci_scan_child_bus(struct pci_bus *bus)
1828 unsigned int devfn, pass, max = bus->busn_res.start;
1829 struct pci_dev *dev;
1831 dev_dbg(&bus->dev, "scanning bus\n");
1833 /* Go find them, Rover! */
1834 for (devfn = 0; devfn < 0x100; devfn += 8)
1835 pci_scan_slot(bus, devfn);
1837 /* Reserve buses for SR-IOV capability. */
1838 max += pci_iov_bus_range(bus);
1841 * After performing arch-dependent fixup of the bus, look behind
1842 * all PCI-to-PCI bridges on this bus.
1844 if (!bus->is_added) {
1845 dev_dbg(&bus->dev, "fixups for bus\n");
1846 pcibios_fixup_bus(bus);
1850 for (pass = 0; pass < 2; pass++)
1851 list_for_each_entry(dev, &bus->devices, bus_list) {
1852 if (pci_is_bridge(dev))
1853 max = pci_scan_bridge(bus, dev, max, pass);
1857 * We've scanned the bus and so we know all about what's on
1858 * the other side of any bridges that may be on this bus plus
1861 * Return how far we've got finding sub-buses.
1863 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max);
1866 EXPORT_SYMBOL_GPL(pci_scan_child_bus);
1869 * pcibios_root_bridge_prepare - Platform-specific host bridge setup.
1870 * @bridge: Host bridge to set up.
1872 * Default empty implementation. Replace with an architecture-specific setup
1873 * routine, if necessary.
1875 int __weak pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
1880 void __weak pcibios_add_bus(struct pci_bus *bus)
1884 void __weak pcibios_remove_bus(struct pci_bus *bus)
1888 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
1889 struct pci_ops *ops, void *sysdata, struct list_head *resources)
1892 struct pci_host_bridge *bridge;
1893 struct pci_bus *b, *b2;
1894 struct pci_host_bridge_window *window, *n;
1895 struct resource *res;
1896 resource_size_t offset;
1900 b = pci_alloc_bus(NULL);
1904 b->sysdata = sysdata;
1906 b->number = b->busn_res.start = bus;
1907 pci_bus_assign_domain_nr(b, parent);
1908 b2 = pci_find_bus(pci_domain_nr(b), bus);
1910 /* If we already got to this bus through a different bridge, ignore it */
1911 dev_dbg(&b2->dev, "bus already known\n");
1915 bridge = pci_alloc_host_bridge(b);
1919 bridge->dev.parent = parent;
1920 bridge->dev.release = pci_release_host_bridge_dev;
1921 dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(b), bus);
1922 error = pcibios_root_bridge_prepare(bridge);
1928 error = device_register(&bridge->dev);
1930 put_device(&bridge->dev);
1933 b->bridge = get_device(&bridge->dev);
1934 device_enable_async_suspend(b->bridge);
1935 pci_set_bus_of_node(b);
1938 set_dev_node(b->bridge, pcibus_to_node(b));
1940 b->dev.class = &pcibus_class;
1941 b->dev.parent = b->bridge;
1942 dev_set_name(&b->dev, "%04x:%02x", pci_domain_nr(b), bus);
1943 error = device_register(&b->dev);
1945 goto class_dev_reg_err;
1949 /* Create legacy_io and legacy_mem files for this bus */
1950 pci_create_legacy_files(b);
1953 dev_info(parent, "PCI host bridge to bus %s\n", dev_name(&b->dev));
1955 printk(KERN_INFO "PCI host bridge to bus %s\n", dev_name(&b->dev));
1957 /* Add initial resources to the bus */
1958 list_for_each_entry_safe(window, n, resources, list) {
1959 list_move_tail(&window->list, &bridge->windows);
1961 offset = window->offset;
1962 if (res->flags & IORESOURCE_BUS)
1963 pci_bus_insert_busn_res(b, bus, res->end);
1965 pci_bus_add_resource(b, res, 0);
1967 if (resource_type(res) == IORESOURCE_IO)
1968 fmt = " (bus address [%#06llx-%#06llx])";
1970 fmt = " (bus address [%#010llx-%#010llx])";
1971 snprintf(bus_addr, sizeof(bus_addr), fmt,
1972 (unsigned long long) (res->start - offset),
1973 (unsigned long long) (res->end - offset));
1976 dev_info(&b->dev, "root bus resource %pR%s\n", res, bus_addr);
1979 down_write(&pci_bus_sem);
1980 list_add_tail(&b->node, &pci_root_buses);
1981 up_write(&pci_bus_sem);
1986 put_device(&bridge->dev);
1987 device_unregister(&bridge->dev);
1993 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max)
1995 struct resource *res = &b->busn_res;
1996 struct resource *parent_res, *conflict;
2000 res->flags = IORESOURCE_BUS;
2002 if (!pci_is_root_bus(b))
2003 parent_res = &b->parent->busn_res;
2005 parent_res = get_pci_domain_busn_res(pci_domain_nr(b));
2006 res->flags |= IORESOURCE_PCI_FIXED;
2009 conflict = request_resource_conflict(parent_res, res);
2012 dev_printk(KERN_DEBUG, &b->dev,
2013 "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n",
2014 res, pci_is_root_bus(b) ? "domain " : "",
2015 parent_res, conflict->name, conflict);
2017 return conflict == NULL;
2020 int pci_bus_update_busn_res_end(struct pci_bus *b, int bus_max)
2022 struct resource *res = &b->busn_res;
2023 struct resource old_res = *res;
2024 resource_size_t size;
2027 if (res->start > bus_max)
2030 size = bus_max - res->start + 1;
2031 ret = adjust_resource(res, res->start, size);
2032 dev_printk(KERN_DEBUG, &b->dev,
2033 "busn_res: %pR end %s updated to %02x\n",
2034 &old_res, ret ? "can not be" : "is", bus_max);
2036 if (!ret && !res->parent)
2037 pci_bus_insert_busn_res(b, res->start, res->end);
2042 void pci_bus_release_busn_res(struct pci_bus *b)
2044 struct resource *res = &b->busn_res;
2047 if (!res->flags || !res->parent)
2050 ret = release_resource(res);
2051 dev_printk(KERN_DEBUG, &b->dev,
2052 "busn_res: %pR %s released\n",
2053 res, ret ? "can not be" : "is");
2056 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
2057 struct pci_ops *ops, void *sysdata, struct list_head *resources)
2059 struct pci_host_bridge_window *window;
2064 list_for_each_entry(window, resources, list)
2065 if (window->res->flags & IORESOURCE_BUS) {
2070 b = pci_create_root_bus(parent, bus, ops, sysdata, resources);
2076 "No busn resource found for root bus, will use [bus %02x-ff]\n",
2078 pci_bus_insert_busn_res(b, bus, 255);
2081 max = pci_scan_child_bus(b);
2084 pci_bus_update_busn_res_end(b, max);
2086 pci_bus_add_devices(b);
2089 EXPORT_SYMBOL(pci_scan_root_bus);
2091 /* Deprecated; use pci_scan_root_bus() instead */
2092 struct pci_bus *pci_scan_bus_parented(struct device *parent,
2093 int bus, struct pci_ops *ops, void *sysdata)
2095 LIST_HEAD(resources);
2098 pci_add_resource(&resources, &ioport_resource);
2099 pci_add_resource(&resources, &iomem_resource);
2100 pci_add_resource(&resources, &busn_resource);
2101 b = pci_create_root_bus(parent, bus, ops, sysdata, &resources);
2103 pci_scan_child_bus(b);
2105 pci_free_resource_list(&resources);
2108 EXPORT_SYMBOL(pci_scan_bus_parented);
2110 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops,
2113 LIST_HEAD(resources);
2116 pci_add_resource(&resources, &ioport_resource);
2117 pci_add_resource(&resources, &iomem_resource);
2118 pci_add_resource(&resources, &busn_resource);
2119 b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources);
2121 pci_scan_child_bus(b);
2122 pci_bus_add_devices(b);
2124 pci_free_resource_list(&resources);
2128 EXPORT_SYMBOL(pci_scan_bus);
2131 * pci_rescan_bus_bridge_resize - scan a PCI bus for devices.
2132 * @bridge: PCI bridge for the bus to scan
2134 * Scan a PCI bus and child buses for new devices, add them,
2135 * and enable them, resizing bridge mmio/io resource if necessary
2136 * and possible. The caller must ensure the child devices are already
2137 * removed for resizing to occur.
2139 * Returns the max number of subordinate bus discovered.
2141 unsigned int pci_rescan_bus_bridge_resize(struct pci_dev *bridge)
2144 struct pci_bus *bus = bridge->subordinate;
2146 max = pci_scan_child_bus(bus);
2148 pci_assign_unassigned_bridge_resources(bridge);
2150 pci_bus_add_devices(bus);
2156 * pci_rescan_bus - scan a PCI bus for devices.
2157 * @bus: PCI bus to scan
2159 * Scan a PCI bus and child buses for new devices, adds them,
2162 * Returns the max number of subordinate bus discovered.
2164 unsigned int pci_rescan_bus(struct pci_bus *bus)
2168 max = pci_scan_child_bus(bus);
2169 pci_assign_unassigned_bus_resources(bus);
2170 pci_bus_add_devices(bus);
2174 EXPORT_SYMBOL_GPL(pci_rescan_bus);
2177 * pci_rescan_bus(), pci_rescan_bus_bridge_resize() and PCI device removal
2178 * routines should always be executed under this mutex.
2180 static DEFINE_MUTEX(pci_rescan_remove_lock);
2182 void pci_lock_rescan_remove(void)
2184 mutex_lock(&pci_rescan_remove_lock);
2186 EXPORT_SYMBOL_GPL(pci_lock_rescan_remove);
2188 void pci_unlock_rescan_remove(void)
2190 mutex_unlock(&pci_rescan_remove_lock);
2192 EXPORT_SYMBOL_GPL(pci_unlock_rescan_remove);
2194 static int __init pci_sort_bf_cmp(const struct device *d_a,
2195 const struct device *d_b)
2197 const struct pci_dev *a = to_pci_dev(d_a);
2198 const struct pci_dev *b = to_pci_dev(d_b);
2200 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
2201 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
2203 if (a->bus->number < b->bus->number) return -1;
2204 else if (a->bus->number > b->bus->number) return 1;
2206 if (a->devfn < b->devfn) return -1;
2207 else if (a->devfn > b->devfn) return 1;
2212 void __init pci_sort_breadthfirst(void)
2214 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp);