2 * probe.c - PCI detection and setup code
5 #include <linux/kernel.h>
6 #include <linux/delay.h>
7 #include <linux/init.h>
9 #include <linux/slab.h>
10 #include <linux/module.h>
11 #include <linux/cpumask.h>
12 #include <linux/pci-aspm.h>
13 #include <asm-generic/pci-bridge.h>
16 #define CARDBUS_LATENCY_TIMER 176 /* secondary latency timer */
17 #define CARDBUS_RESERVE_BUSNR 3
19 struct resource busn_resource = {
23 .flags = IORESOURCE_BUS,
26 /* Ugh. Need to stop exporting this to modules. */
27 LIST_HEAD(pci_root_buses);
28 EXPORT_SYMBOL(pci_root_buses);
30 static LIST_HEAD(pci_domain_busn_res_list);
32 struct pci_domain_busn_res {
33 struct list_head list;
38 static struct resource *get_pci_domain_busn_res(int domain_nr)
40 struct pci_domain_busn_res *r;
42 list_for_each_entry(r, &pci_domain_busn_res_list, list)
43 if (r->domain_nr == domain_nr)
46 r = kzalloc(sizeof(*r), GFP_KERNEL);
50 r->domain_nr = domain_nr;
53 r->res.flags = IORESOURCE_BUS | IORESOURCE_PCI_FIXED;
55 list_add_tail(&r->list, &pci_domain_busn_res_list);
60 static int find_anything(struct device *dev, void *data)
66 * Some device drivers need know if pci is initiated.
67 * Basically, we think pci is not initiated when there
68 * is no device to be found on the pci_bus_type.
70 int no_pci_devices(void)
75 dev = bus_find_device(&pci_bus_type, NULL, NULL, find_anything);
76 no_devices = (dev == NULL);
80 EXPORT_SYMBOL(no_pci_devices);
85 static void release_pcibus_dev(struct device *dev)
87 struct pci_bus *pci_bus = to_pci_bus(dev);
90 put_device(pci_bus->bridge);
91 pci_bus_remove_resources(pci_bus);
92 pci_release_bus_of_node(pci_bus);
96 static struct class pcibus_class = {
98 .dev_release = &release_pcibus_dev,
99 .dev_attrs = pcibus_dev_attrs,
102 static int __init pcibus_class_init(void)
104 return class_register(&pcibus_class);
106 postcore_initcall(pcibus_class_init);
108 static u64 pci_size(u64 base, u64 maxbase, u64 mask)
110 u64 size = mask & maxbase; /* Find the significant bits */
114 /* Get the lowest of them to find the decode size, and
115 from that the extent. */
116 size = (size & ~(size-1)) - 1;
118 /* base == maxbase can be valid only if the BAR has
119 already been programmed with all 1s. */
120 if (base == maxbase && ((base | size) & mask) != mask)
126 static inline unsigned long decode_bar(struct pci_dev *dev, u32 bar)
131 if ((bar & PCI_BASE_ADDRESS_SPACE) == PCI_BASE_ADDRESS_SPACE_IO) {
132 flags = bar & ~PCI_BASE_ADDRESS_IO_MASK;
133 flags |= IORESOURCE_IO;
137 flags = bar & ~PCI_BASE_ADDRESS_MEM_MASK;
138 flags |= IORESOURCE_MEM;
139 if (flags & PCI_BASE_ADDRESS_MEM_PREFETCH)
140 flags |= IORESOURCE_PREFETCH;
142 mem_type = bar & PCI_BASE_ADDRESS_MEM_TYPE_MASK;
144 case PCI_BASE_ADDRESS_MEM_TYPE_32:
146 case PCI_BASE_ADDRESS_MEM_TYPE_1M:
147 /* 1M mem BAR treated as 32-bit BAR */
149 case PCI_BASE_ADDRESS_MEM_TYPE_64:
150 flags |= IORESOURCE_MEM_64;
153 /* mem unknown type treated as 32-bit BAR */
160 * pci_read_base - read a PCI BAR
161 * @dev: the PCI device
162 * @type: type of the BAR
163 * @res: resource buffer to be filled in
164 * @pos: BAR position in the config space
166 * Returns 1 if the BAR is 64-bit, or 0 if 32-bit.
168 int __pci_read_base(struct pci_dev *dev, enum pci_bar_type type,
169 struct resource *res, unsigned int pos)
173 struct pci_bus_region region;
174 bool bar_too_big = false, bar_disabled = false;
176 mask = type ? PCI_ROM_ADDRESS_MASK : ~0;
178 /* No printks while decoding is disabled! */
179 if (!dev->mmio_always_on) {
180 pci_read_config_word(dev, PCI_COMMAND, &orig_cmd);
181 pci_write_config_word(dev, PCI_COMMAND,
182 orig_cmd & ~(PCI_COMMAND_MEMORY | PCI_COMMAND_IO));
185 res->name = pci_name(dev);
187 pci_read_config_dword(dev, pos, &l);
188 pci_write_config_dword(dev, pos, l | mask);
189 pci_read_config_dword(dev, pos, &sz);
190 pci_write_config_dword(dev, pos, l);
193 * All bits set in sz means the device isn't working properly.
194 * If the BAR isn't implemented, all bits must be 0. If it's a
195 * memory BAR or a ROM, bit 0 must be clear; if it's an io BAR, bit
198 if (!sz || sz == 0xffffffff)
202 * I don't know how l can have all bits set. Copied from old code.
203 * Maybe it fixes a bug on some ancient platform.
208 if (type == pci_bar_unknown) {
209 res->flags = decode_bar(dev, l);
210 res->flags |= IORESOURCE_SIZEALIGN;
211 if (res->flags & IORESOURCE_IO) {
212 l &= PCI_BASE_ADDRESS_IO_MASK;
213 sz &= PCI_BASE_ADDRESS_IO_MASK;
214 mask = PCI_BASE_ADDRESS_IO_MASK & (u32) IO_SPACE_LIMIT;
216 l &= PCI_BASE_ADDRESS_MEM_MASK;
217 sz &= PCI_BASE_ADDRESS_MEM_MASK;
218 mask = (u32)PCI_BASE_ADDRESS_MEM_MASK;
221 res->flags |= (l & IORESOURCE_ROM_ENABLE);
222 l &= PCI_ROM_ADDRESS_MASK;
223 sz &= PCI_ROM_ADDRESS_MASK;
224 mask = (u32)PCI_ROM_ADDRESS_MASK;
227 if (res->flags & IORESOURCE_MEM_64) {
230 u64 mask64 = mask | (u64)~0 << 32;
232 pci_read_config_dword(dev, pos + 4, &l);
233 pci_write_config_dword(dev, pos + 4, ~0);
234 pci_read_config_dword(dev, pos + 4, &sz);
235 pci_write_config_dword(dev, pos + 4, l);
237 l64 |= ((u64)l << 32);
238 sz64 |= ((u64)sz << 32);
240 sz64 = pci_size(l64, sz64, mask64);
245 if ((sizeof(resource_size_t) < 8) && (sz64 > 0x100000000ULL)) {
250 if ((sizeof(resource_size_t) < 8) && l) {
251 /* Address above 32-bit boundary; disable the BAR */
252 pci_write_config_dword(dev, pos, 0);
253 pci_write_config_dword(dev, pos + 4, 0);
256 pcibios_bus_to_resource(dev, res, ®ion);
260 region.end = l64 + sz64;
261 pcibios_bus_to_resource(dev, res, ®ion);
264 sz = pci_size(l, sz, mask);
271 pcibios_bus_to_resource(dev, res, ®ion);
280 if (!dev->mmio_always_on)
281 pci_write_config_word(dev, PCI_COMMAND, orig_cmd);
284 dev_err(&dev->dev, "reg %x: can't handle 64-bit BAR\n", pos);
285 if (res->flags && !bar_disabled)
286 dev_printk(KERN_DEBUG, &dev->dev, "reg %x: %pR\n", pos, res);
288 return (res->flags & IORESOURCE_MEM_64) ? 1 : 0;
291 static void pci_read_bases(struct pci_dev *dev, unsigned int howmany, int rom)
293 unsigned int pos, reg;
295 for (pos = 0; pos < howmany; pos++) {
296 struct resource *res = &dev->resource[pos];
297 reg = PCI_BASE_ADDRESS_0 + (pos << 2);
298 pos += __pci_read_base(dev, pci_bar_unknown, res, reg);
302 struct resource *res = &dev->resource[PCI_ROM_RESOURCE];
303 dev->rom_base_reg = rom;
304 res->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH |
305 IORESOURCE_READONLY | IORESOURCE_CACHEABLE |
306 IORESOURCE_SIZEALIGN;
307 __pci_read_base(dev, pci_bar_mem32, res, rom);
311 static void pci_read_bridge_io(struct pci_bus *child)
313 struct pci_dev *dev = child->self;
314 u8 io_base_lo, io_limit_lo;
315 unsigned long io_mask, io_granularity, base, limit;
316 struct pci_bus_region region;
317 struct resource *res;
319 io_mask = PCI_IO_RANGE_MASK;
320 io_granularity = 0x1000;
321 if (dev->io_window_1k) {
322 /* Support 1K I/O space granularity */
323 io_mask = PCI_IO_1K_RANGE_MASK;
324 io_granularity = 0x400;
327 res = child->resource[0];
328 pci_read_config_byte(dev, PCI_IO_BASE, &io_base_lo);
329 pci_read_config_byte(dev, PCI_IO_LIMIT, &io_limit_lo);
330 base = (io_base_lo & io_mask) << 8;
331 limit = (io_limit_lo & io_mask) << 8;
333 if ((io_base_lo & PCI_IO_RANGE_TYPE_MASK) == PCI_IO_RANGE_TYPE_32) {
334 u16 io_base_hi, io_limit_hi;
336 pci_read_config_word(dev, PCI_IO_BASE_UPPER16, &io_base_hi);
337 pci_read_config_word(dev, PCI_IO_LIMIT_UPPER16, &io_limit_hi);
338 base |= ((unsigned long) io_base_hi << 16);
339 limit |= ((unsigned long) io_limit_hi << 16);
343 res->flags = (io_base_lo & PCI_IO_RANGE_TYPE_MASK) | IORESOURCE_IO;
345 region.end = limit + io_granularity - 1;
346 pcibios_bus_to_resource(dev, res, ®ion);
347 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
351 static void pci_read_bridge_mmio(struct pci_bus *child)
353 struct pci_dev *dev = child->self;
354 u16 mem_base_lo, mem_limit_lo;
355 unsigned long base, limit;
356 struct pci_bus_region region;
357 struct resource *res;
359 res = child->resource[1];
360 pci_read_config_word(dev, PCI_MEMORY_BASE, &mem_base_lo);
361 pci_read_config_word(dev, PCI_MEMORY_LIMIT, &mem_limit_lo);
362 base = ((unsigned long) mem_base_lo & PCI_MEMORY_RANGE_MASK) << 16;
363 limit = ((unsigned long) mem_limit_lo & PCI_MEMORY_RANGE_MASK) << 16;
365 res->flags = (mem_base_lo & PCI_MEMORY_RANGE_TYPE_MASK) | IORESOURCE_MEM;
367 region.end = limit + 0xfffff;
368 pcibios_bus_to_resource(dev, res, ®ion);
369 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
373 static void pci_read_bridge_mmio_pref(struct pci_bus *child)
375 struct pci_dev *dev = child->self;
376 u16 mem_base_lo, mem_limit_lo;
377 unsigned long base, limit;
378 struct pci_bus_region region;
379 struct resource *res;
381 res = child->resource[2];
382 pci_read_config_word(dev, PCI_PREF_MEMORY_BASE, &mem_base_lo);
383 pci_read_config_word(dev, PCI_PREF_MEMORY_LIMIT, &mem_limit_lo);
384 base = ((unsigned long) mem_base_lo & PCI_PREF_RANGE_MASK) << 16;
385 limit = ((unsigned long) mem_limit_lo & PCI_PREF_RANGE_MASK) << 16;
387 if ((mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) == PCI_PREF_RANGE_TYPE_64) {
388 u32 mem_base_hi, mem_limit_hi;
390 pci_read_config_dword(dev, PCI_PREF_BASE_UPPER32, &mem_base_hi);
391 pci_read_config_dword(dev, PCI_PREF_LIMIT_UPPER32, &mem_limit_hi);
394 * Some bridges set the base > limit by default, and some
395 * (broken) BIOSes do not initialize them. If we find
396 * this, just assume they are not being used.
398 if (mem_base_hi <= mem_limit_hi) {
399 #if BITS_PER_LONG == 64
400 base |= ((unsigned long) mem_base_hi) << 32;
401 limit |= ((unsigned long) mem_limit_hi) << 32;
403 if (mem_base_hi || mem_limit_hi) {
404 dev_err(&dev->dev, "can't handle 64-bit "
405 "address space for bridge\n");
412 res->flags = (mem_base_lo & PCI_PREF_RANGE_TYPE_MASK) |
413 IORESOURCE_MEM | IORESOURCE_PREFETCH;
414 if (res->flags & PCI_PREF_RANGE_TYPE_64)
415 res->flags |= IORESOURCE_MEM_64;
417 region.end = limit + 0xfffff;
418 pcibios_bus_to_resource(dev, res, ®ion);
419 dev_printk(KERN_DEBUG, &dev->dev, " bridge window %pR\n", res);
423 void pci_read_bridge_bases(struct pci_bus *child)
425 struct pci_dev *dev = child->self;
426 struct resource *res;
429 if (pci_is_root_bus(child)) /* It's a host bus, nothing to read */
432 dev_info(&dev->dev, "PCI bridge to %pR%s\n",
434 dev->transparent ? " (subtractive decode)" : "");
436 pci_bus_remove_resources(child);
437 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++)
438 child->resource[i] = &dev->resource[PCI_BRIDGE_RESOURCES+i];
440 pci_read_bridge_io(child);
441 pci_read_bridge_mmio(child);
442 pci_read_bridge_mmio_pref(child);
444 if (dev->transparent) {
445 pci_bus_for_each_resource(child->parent, res, i) {
447 pci_bus_add_resource(child, res,
448 PCI_SUBTRACTIVE_DECODE);
449 dev_printk(KERN_DEBUG, &dev->dev,
450 " bridge window %pR (subtractive decode)\n",
457 static struct pci_bus * pci_alloc_bus(void)
461 b = kzalloc(sizeof(*b), GFP_KERNEL);
463 INIT_LIST_HEAD(&b->node);
464 INIT_LIST_HEAD(&b->children);
465 INIT_LIST_HEAD(&b->devices);
466 INIT_LIST_HEAD(&b->slots);
467 INIT_LIST_HEAD(&b->resources);
468 b->max_bus_speed = PCI_SPEED_UNKNOWN;
469 b->cur_bus_speed = PCI_SPEED_UNKNOWN;
474 static struct pci_host_bridge *pci_alloc_host_bridge(struct pci_bus *b)
476 struct pci_host_bridge *bridge;
478 bridge = kzalloc(sizeof(*bridge), GFP_KERNEL);
480 INIT_LIST_HEAD(&bridge->windows);
487 static unsigned char pcix_bus_speed[] = {
488 PCI_SPEED_UNKNOWN, /* 0 */
489 PCI_SPEED_66MHz_PCIX, /* 1 */
490 PCI_SPEED_100MHz_PCIX, /* 2 */
491 PCI_SPEED_133MHz_PCIX, /* 3 */
492 PCI_SPEED_UNKNOWN, /* 4 */
493 PCI_SPEED_66MHz_PCIX_ECC, /* 5 */
494 PCI_SPEED_100MHz_PCIX_ECC, /* 6 */
495 PCI_SPEED_133MHz_PCIX_ECC, /* 7 */
496 PCI_SPEED_UNKNOWN, /* 8 */
497 PCI_SPEED_66MHz_PCIX_266, /* 9 */
498 PCI_SPEED_100MHz_PCIX_266, /* A */
499 PCI_SPEED_133MHz_PCIX_266, /* B */
500 PCI_SPEED_UNKNOWN, /* C */
501 PCI_SPEED_66MHz_PCIX_533, /* D */
502 PCI_SPEED_100MHz_PCIX_533, /* E */
503 PCI_SPEED_133MHz_PCIX_533 /* F */
506 static unsigned char pcie_link_speed[] = {
507 PCI_SPEED_UNKNOWN, /* 0 */
508 PCIE_SPEED_2_5GT, /* 1 */
509 PCIE_SPEED_5_0GT, /* 2 */
510 PCIE_SPEED_8_0GT, /* 3 */
511 PCI_SPEED_UNKNOWN, /* 4 */
512 PCI_SPEED_UNKNOWN, /* 5 */
513 PCI_SPEED_UNKNOWN, /* 6 */
514 PCI_SPEED_UNKNOWN, /* 7 */
515 PCI_SPEED_UNKNOWN, /* 8 */
516 PCI_SPEED_UNKNOWN, /* 9 */
517 PCI_SPEED_UNKNOWN, /* A */
518 PCI_SPEED_UNKNOWN, /* B */
519 PCI_SPEED_UNKNOWN, /* C */
520 PCI_SPEED_UNKNOWN, /* D */
521 PCI_SPEED_UNKNOWN, /* E */
522 PCI_SPEED_UNKNOWN /* F */
525 void pcie_update_link_speed(struct pci_bus *bus, u16 linksta)
527 bus->cur_bus_speed = pcie_link_speed[linksta & PCI_EXP_LNKSTA_CLS];
529 EXPORT_SYMBOL_GPL(pcie_update_link_speed);
531 static unsigned char agp_speeds[] = {
539 static enum pci_bus_speed agp_speed(int agp3, int agpstat)
545 else if (agpstat & 2)
547 else if (agpstat & 1)
559 return agp_speeds[index];
563 static void pci_set_bus_speed(struct pci_bus *bus)
565 struct pci_dev *bridge = bus->self;
568 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP);
570 pos = pci_find_capability(bridge, PCI_CAP_ID_AGP3);
574 pci_read_config_dword(bridge, pos + PCI_AGP_STATUS, &agpstat);
575 bus->max_bus_speed = agp_speed(agpstat & 8, agpstat & 7);
577 pci_read_config_dword(bridge, pos + PCI_AGP_COMMAND, &agpcmd);
578 bus->cur_bus_speed = agp_speed(agpstat & 8, agpcmd & 7);
581 pos = pci_find_capability(bridge, PCI_CAP_ID_PCIX);
584 enum pci_bus_speed max;
586 pci_read_config_word(bridge, pos + PCI_X_BRIDGE_SSTATUS,
589 if (status & PCI_X_SSTATUS_533MHZ) {
590 max = PCI_SPEED_133MHz_PCIX_533;
591 } else if (status & PCI_X_SSTATUS_266MHZ) {
592 max = PCI_SPEED_133MHz_PCIX_266;
593 } else if (status & PCI_X_SSTATUS_133MHZ) {
594 if ((status & PCI_X_SSTATUS_VERS) == PCI_X_SSTATUS_V2) {
595 max = PCI_SPEED_133MHz_PCIX_ECC;
597 max = PCI_SPEED_133MHz_PCIX;
600 max = PCI_SPEED_66MHz_PCIX;
603 bus->max_bus_speed = max;
604 bus->cur_bus_speed = pcix_bus_speed[
605 (status & PCI_X_SSTATUS_FREQ) >> 6];
610 pos = pci_find_capability(bridge, PCI_CAP_ID_EXP);
615 pcie_capability_read_dword(bridge, PCI_EXP_LNKCAP, &linkcap);
616 bus->max_bus_speed = pcie_link_speed[linkcap & PCI_EXP_LNKCAP_SLS];
618 pcie_capability_read_word(bridge, PCI_EXP_LNKSTA, &linksta);
619 pcie_update_link_speed(bus, linksta);
624 static struct pci_bus *pci_alloc_child_bus(struct pci_bus *parent,
625 struct pci_dev *bridge, int busnr)
627 struct pci_bus *child;
632 * Allocate a new bus, and inherit stuff from the parent..
634 child = pci_alloc_bus();
638 child->parent = parent;
639 child->ops = parent->ops;
640 child->sysdata = parent->sysdata;
641 child->bus_flags = parent->bus_flags;
643 /* initialize some portions of the bus device, but don't register it
644 * now as the parent is not properly set up yet.
646 child->dev.class = &pcibus_class;
647 dev_set_name(&child->dev, "%04x:%02x", pci_domain_nr(child), busnr);
650 * Set up the primary, secondary and subordinate
653 child->number = child->busn_res.start = busnr;
654 child->primary = parent->busn_res.start;
655 child->busn_res.end = 0xff;
658 child->dev.parent = parent->bridge;
662 child->self = bridge;
663 child->bridge = get_device(&bridge->dev);
664 child->dev.parent = child->bridge;
665 pci_set_bus_of_node(child);
666 pci_set_bus_speed(child);
668 /* Set up default resource pointers and names.. */
669 for (i = 0; i < PCI_BRIDGE_RESOURCE_NUM; i++) {
670 child->resource[i] = &bridge->resource[PCI_BRIDGE_RESOURCES+i];
671 child->resource[i]->name = child->name;
673 bridge->subordinate = child;
676 ret = device_register(&child->dev);
679 pcibios_add_bus(child);
681 /* Create legacy_io and legacy_mem files for this bus */
682 pci_create_legacy_files(child);
687 struct pci_bus *__ref pci_add_new_bus(struct pci_bus *parent, struct pci_dev *dev, int busnr)
689 struct pci_bus *child;
691 child = pci_alloc_child_bus(parent, dev, busnr);
693 down_write(&pci_bus_sem);
694 list_add_tail(&child->node, &parent->children);
695 up_write(&pci_bus_sem);
700 static void pci_fixup_parent_subordinate_busnr(struct pci_bus *child, int max)
702 struct pci_bus *parent = child->parent;
704 /* Attempts to fix that up are really dangerous unless
705 we're going to re-assign all bus numbers. */
706 if (!pcibios_assign_all_busses())
709 while (parent->parent && parent->busn_res.end < max) {
710 parent->busn_res.end = max;
711 pci_write_config_byte(parent->self, PCI_SUBORDINATE_BUS, max);
712 parent = parent->parent;
717 * If it's a bridge, configure it and scan the bus behind it.
718 * For CardBus bridges, we don't scan behind as the devices will
719 * be handled by the bridge driver itself.
721 * We need to process bridges in two passes -- first we scan those
722 * already configured by the BIOS and after we are done with all of
723 * them, we proceed to assigning numbers to the remaining buses in
724 * order to avoid overlaps between old and new bus numbers.
726 int pci_scan_bridge(struct pci_bus *bus, struct pci_dev *dev, int max, int pass)
728 struct pci_bus *child;
729 int is_cardbus = (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS);
732 u8 primary, secondary, subordinate;
735 pci_read_config_dword(dev, PCI_PRIMARY_BUS, &buses);
736 primary = buses & 0xFF;
737 secondary = (buses >> 8) & 0xFF;
738 subordinate = (buses >> 16) & 0xFF;
740 dev_dbg(&dev->dev, "scanning [bus %02x-%02x] behind bridge, pass %d\n",
741 secondary, subordinate, pass);
743 if (!primary && (primary != bus->number) && secondary && subordinate) {
744 dev_warn(&dev->dev, "Primary bus is hard wired to 0\n");
745 primary = bus->number;
748 /* Check if setup is sensible at all */
750 (primary != bus->number || secondary <= bus->number ||
751 secondary > subordinate)) {
752 dev_info(&dev->dev, "bridge configuration invalid ([bus %02x-%02x]), reconfiguring\n",
753 secondary, subordinate);
757 /* Disable MasterAbortMode during probing to avoid reporting
758 of bus errors (in some architectures) */
759 pci_read_config_word(dev, PCI_BRIDGE_CONTROL, &bctl);
760 pci_write_config_word(dev, PCI_BRIDGE_CONTROL,
761 bctl & ~PCI_BRIDGE_CTL_MASTER_ABORT);
763 if ((secondary || subordinate) && !pcibios_assign_all_busses() &&
764 !is_cardbus && !broken) {
767 * Bus already configured by firmware, process it in the first
768 * pass and just note the configuration.
774 * If we already got to this bus through a different bridge,
775 * don't re-add it. This can happen with the i450NX chipset.
777 * However, we continue to descend down the hierarchy and
778 * scan remaining child buses.
780 child = pci_find_bus(pci_domain_nr(bus), secondary);
782 child = pci_add_new_bus(bus, dev, secondary);
785 child->primary = primary;
786 pci_bus_insert_busn_res(child, secondary, subordinate);
787 child->bridge_ctl = bctl;
790 cmax = pci_scan_child_bus(child);
793 if (child->busn_res.end > max)
794 max = child->busn_res.end;
797 * We need to assign a number to this bus which we always
798 * do in the second pass.
801 if (pcibios_assign_all_busses() || broken)
802 /* Temporarily disable forwarding of the
803 configuration cycles on all bridges in
804 this bus segment to avoid possible
805 conflicts in the second pass between two
806 bridges programmed with overlapping
808 pci_write_config_dword(dev, PCI_PRIMARY_BUS,
814 pci_write_config_word(dev, PCI_STATUS, 0xffff);
816 /* Prevent assigning a bus number that already exists.
817 * This can happen when a bridge is hot-plugged, so in
818 * this case we only re-scan this bus. */
819 child = pci_find_bus(pci_domain_nr(bus), max+1);
821 child = pci_add_new_bus(bus, dev, ++max);
824 pci_bus_insert_busn_res(child, max, 0xff);
826 buses = (buses & 0xff000000)
827 | ((unsigned int)(child->primary) << 0)
828 | ((unsigned int)(child->busn_res.start) << 8)
829 | ((unsigned int)(child->busn_res.end) << 16);
832 * yenta.c forces a secondary latency timer of 176.
833 * Copy that behaviour here.
836 buses &= ~0xff000000;
837 buses |= CARDBUS_LATENCY_TIMER << 24;
841 * We need to blast all three values with a single write.
843 pci_write_config_dword(dev, PCI_PRIMARY_BUS, buses);
846 child->bridge_ctl = bctl;
848 * Adjust subordinate busnr in parent buses.
849 * We do this before scanning for children because
850 * some devices may not be detected if the bios
853 pci_fixup_parent_subordinate_busnr(child, max);
854 /* Now we can scan all subordinate buses... */
855 max = pci_scan_child_bus(child);
857 * now fix it up again since we have found
858 * the real value of max.
860 pci_fixup_parent_subordinate_busnr(child, max);
863 * For CardBus bridges, we leave 4 bus numbers
864 * as cards with a PCI-to-PCI bridge can be
867 for (i=0; i<CARDBUS_RESERVE_BUSNR; i++) {
868 struct pci_bus *parent = bus;
869 if (pci_find_bus(pci_domain_nr(bus),
872 while (parent->parent) {
873 if ((!pcibios_assign_all_busses()) &&
874 (parent->busn_res.end > max) &&
875 (parent->busn_res.end <= max+i)) {
878 parent = parent->parent;
882 * Often, there are two cardbus bridges
883 * -- try to leave one valid bus number
891 pci_fixup_parent_subordinate_busnr(child, max);
894 * Set the subordinate bus number to its real value.
896 pci_bus_update_busn_res_end(child, max);
897 pci_write_config_byte(dev, PCI_SUBORDINATE_BUS, max);
901 (is_cardbus ? "PCI CardBus %04x:%02x" : "PCI Bus %04x:%02x"),
902 pci_domain_nr(bus), child->number);
904 /* Has only triggered on CardBus, fixup is in yenta_socket */
905 while (bus->parent) {
906 if ((child->busn_res.end > bus->busn_res.end) ||
907 (child->number > bus->busn_res.end) ||
908 (child->number < bus->number) ||
909 (child->busn_res.end < bus->number)) {
910 dev_info(&child->dev, "%pR %s "
911 "hidden behind%s bridge %s %pR\n",
913 (bus->number > child->busn_res.end &&
914 bus->busn_res.end < child->number) ?
915 "wholly" : "partially",
916 bus->self->transparent ? " transparent" : "",
924 pci_write_config_word(dev, PCI_BRIDGE_CONTROL, bctl);
930 * Read interrupt line and base address registers.
931 * The architecture-dependent code can tweak these, of course.
933 static void pci_read_irq(struct pci_dev *dev)
937 pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &irq);
940 pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &irq);
944 void set_pcie_port_type(struct pci_dev *pdev)
949 pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
953 pdev->pcie_cap = pos;
954 pci_read_config_word(pdev, pos + PCI_EXP_FLAGS, ®16);
955 pdev->pcie_flags_reg = reg16;
956 pci_read_config_word(pdev, pos + PCI_EXP_DEVCAP, ®16);
957 pdev->pcie_mpss = reg16 & PCI_EXP_DEVCAP_PAYLOAD;
960 void set_pcie_hotplug_bridge(struct pci_dev *pdev)
964 pcie_capability_read_dword(pdev, PCI_EXP_SLTCAP, ®32);
965 if (reg32 & PCI_EXP_SLTCAP_HPC)
966 pdev->is_hotplug_bridge = 1;
969 #define LEGACY_IO_RESOURCE (IORESOURCE_IO | IORESOURCE_PCI_FIXED)
972 * pci_setup_device - fill in class and map information of a device
973 * @dev: the device structure to fill
975 * Initialize the device structure with information about the device's
976 * vendor,class,memory and IO-space addresses,IRQ lines etc.
977 * Called at initialisation of the PCI subsystem and by CardBus services.
978 * Returns 0 on success and negative if unknown type of device (not normal,
979 * bridge or CardBus).
981 int pci_setup_device(struct pci_dev *dev)
985 struct pci_slot *slot;
987 struct pci_bus_region region;
988 struct resource *res;
990 if (pci_read_config_byte(dev, PCI_HEADER_TYPE, &hdr_type))
993 dev->sysdata = dev->bus->sysdata;
994 dev->dev.parent = dev->bus->bridge;
995 dev->dev.bus = &pci_bus_type;
996 dev->hdr_type = hdr_type & 0x7f;
997 dev->multifunction = !!(hdr_type & 0x80);
998 dev->error_state = pci_channel_io_normal;
999 set_pcie_port_type(dev);
1001 list_for_each_entry(slot, &dev->bus->slots, list)
1002 if (PCI_SLOT(dev->devfn) == slot->number)
1005 /* Assume 32-bit PCI; let 64-bit PCI cards (which are far rarer)
1006 set this higher, assuming the system even supports it. */
1007 dev->dma_mask = 0xffffffff;
1009 dev_set_name(&dev->dev, "%04x:%02x:%02x.%d", pci_domain_nr(dev->bus),
1010 dev->bus->number, PCI_SLOT(dev->devfn),
1011 PCI_FUNC(dev->devfn));
1013 pci_read_config_dword(dev, PCI_CLASS_REVISION, &class);
1014 dev->revision = class & 0xff;
1015 dev->class = class >> 8; /* upper 3 bytes */
1017 dev_printk(KERN_DEBUG, &dev->dev, "[%04x:%04x] type %02x class %#08x\n",
1018 dev->vendor, dev->device, dev->hdr_type, dev->class);
1020 /* need to have dev->class ready */
1021 dev->cfg_size = pci_cfg_space_size(dev);
1023 /* "Unknown power state" */
1024 dev->current_state = PCI_UNKNOWN;
1026 /* Early fixups, before probing the BARs */
1027 pci_fixup_device(pci_fixup_early, dev);
1028 /* device class may be changed after fixup */
1029 class = dev->class >> 8;
1031 switch (dev->hdr_type) { /* header type */
1032 case PCI_HEADER_TYPE_NORMAL: /* standard header */
1033 if (class == PCI_CLASS_BRIDGE_PCI)
1036 pci_read_bases(dev, 6, PCI_ROM_ADDRESS);
1037 pci_read_config_word(dev, PCI_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1038 pci_read_config_word(dev, PCI_SUBSYSTEM_ID, &dev->subsystem_device);
1041 * Do the ugly legacy mode stuff here rather than broken chip
1042 * quirk code. Legacy mode ATA controllers have fixed
1043 * addresses. These are not always echoed in BAR0-3, and
1044 * BAR0-3 in a few cases contain junk!
1046 if (class == PCI_CLASS_STORAGE_IDE) {
1048 pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
1049 if ((progif & 1) == 0) {
1050 region.start = 0x1F0;
1052 res = &dev->resource[0];
1053 res->flags = LEGACY_IO_RESOURCE;
1054 pcibios_bus_to_resource(dev, res, ®ion);
1055 region.start = 0x3F6;
1057 res = &dev->resource[1];
1058 res->flags = LEGACY_IO_RESOURCE;
1059 pcibios_bus_to_resource(dev, res, ®ion);
1061 if ((progif & 4) == 0) {
1062 region.start = 0x170;
1064 res = &dev->resource[2];
1065 res->flags = LEGACY_IO_RESOURCE;
1066 pcibios_bus_to_resource(dev, res, ®ion);
1067 region.start = 0x376;
1069 res = &dev->resource[3];
1070 res->flags = LEGACY_IO_RESOURCE;
1071 pcibios_bus_to_resource(dev, res, ®ion);
1076 case PCI_HEADER_TYPE_BRIDGE: /* bridge header */
1077 if (class != PCI_CLASS_BRIDGE_PCI)
1079 /* The PCI-to-PCI bridge spec requires that subtractive
1080 decoding (i.e. transparent) bridge must have programming
1081 interface code of 0x01. */
1083 dev->transparent = ((dev->class & 0xff) == 1);
1084 pci_read_bases(dev, 2, PCI_ROM_ADDRESS1);
1085 set_pcie_hotplug_bridge(dev);
1086 pos = pci_find_capability(dev, PCI_CAP_ID_SSVID);
1088 pci_read_config_word(dev, pos + PCI_SSVID_VENDOR_ID, &dev->subsystem_vendor);
1089 pci_read_config_word(dev, pos + PCI_SSVID_DEVICE_ID, &dev->subsystem_device);
1093 case PCI_HEADER_TYPE_CARDBUS: /* CardBus bridge header */
1094 if (class != PCI_CLASS_BRIDGE_CARDBUS)
1097 pci_read_bases(dev, 1, 0);
1098 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_VENDOR_ID, &dev->subsystem_vendor);
1099 pci_read_config_word(dev, PCI_CB_SUBSYSTEM_ID, &dev->subsystem_device);
1102 default: /* unknown header */
1103 dev_err(&dev->dev, "unknown header type %02x, "
1104 "ignoring device\n", dev->hdr_type);
1108 dev_err(&dev->dev, "ignoring class %#08x (doesn't match header "
1109 "type %02x)\n", dev->class, dev->hdr_type);
1110 dev->class = PCI_CLASS_NOT_DEFINED;
1113 /* We found a fine healthy device, go go go... */
1117 static void pci_release_capabilities(struct pci_dev *dev)
1119 pci_vpd_release(dev);
1120 pci_iov_release(dev);
1121 pci_free_cap_save_buffers(dev);
1125 * pci_release_dev - free a pci device structure when all users of it are finished.
1126 * @dev: device that's been disconnected
1128 * Will be called only by the device core when all users of this pci device are
1131 static void pci_release_dev(struct device *dev)
1133 struct pci_dev *pci_dev;
1135 pci_dev = to_pci_dev(dev);
1136 pci_release_capabilities(pci_dev);
1137 pci_release_of_node(pci_dev);
1142 * pci_cfg_space_size - get the configuration space size of the PCI device.
1145 * Regular PCI devices have 256 bytes, but PCI-X 2 and PCI Express devices
1146 * have 4096 bytes. Even if the device is capable, that doesn't mean we can
1147 * access it. Maybe we don't have a way to generate extended config space
1148 * accesses, or the device is behind a reverse Express bridge. So we try
1149 * reading the dword at 0x100 which must either be 0 or a valid extended
1150 * capability header.
1152 int pci_cfg_space_size_ext(struct pci_dev *dev)
1155 int pos = PCI_CFG_SPACE_SIZE;
1157 if (pci_read_config_dword(dev, pos, &status) != PCIBIOS_SUCCESSFUL)
1159 if (status == 0xffffffff)
1162 return PCI_CFG_SPACE_EXP_SIZE;
1165 return PCI_CFG_SPACE_SIZE;
1168 int pci_cfg_space_size(struct pci_dev *dev)
1174 class = dev->class >> 8;
1175 if (class == PCI_CLASS_BRIDGE_HOST)
1176 return pci_cfg_space_size_ext(dev);
1178 if (!pci_is_pcie(dev)) {
1179 pos = pci_find_capability(dev, PCI_CAP_ID_PCIX);
1183 pci_read_config_dword(dev, pos + PCI_X_STATUS, &status);
1184 if (!(status & (PCI_X_STATUS_266MHZ | PCI_X_STATUS_533MHZ)))
1188 return pci_cfg_space_size_ext(dev);
1191 return PCI_CFG_SPACE_SIZE;
1194 static void pci_release_bus_bridge_dev(struct device *dev)
1196 struct pci_host_bridge *bridge = to_pci_host_bridge(dev);
1198 if (bridge->release_fn)
1199 bridge->release_fn(bridge);
1201 pci_free_resource_list(&bridge->windows);
1206 struct pci_dev *alloc_pci_dev(void)
1208 struct pci_dev *dev;
1210 dev = kzalloc(sizeof(struct pci_dev), GFP_KERNEL);
1214 INIT_LIST_HEAD(&dev->bus_list);
1215 dev->dev.type = &pci_dev_type;
1219 EXPORT_SYMBOL(alloc_pci_dev);
1221 bool pci_bus_read_dev_vendor_id(struct pci_bus *bus, int devfn, u32 *l,
1226 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
1229 /* some broken boards return 0 or ~0 if a slot is empty: */
1230 if (*l == 0xffffffff || *l == 0x00000000 ||
1231 *l == 0x0000ffff || *l == 0xffff0000)
1234 /* Configuration request Retry Status */
1235 while (*l == 0xffff0001) {
1241 if (pci_bus_read_config_dword(bus, devfn, PCI_VENDOR_ID, l))
1243 /* Card hasn't responded in 60 seconds? Must be stuck. */
1244 if (delay > crs_timeout) {
1245 printk(KERN_WARNING "pci %04x:%02x:%02x.%d: not "
1246 "responding\n", pci_domain_nr(bus),
1247 bus->number, PCI_SLOT(devfn),
1255 EXPORT_SYMBOL(pci_bus_read_dev_vendor_id);
1258 * Read the config data for a PCI device, sanity-check it
1259 * and fill in the dev structure...
1261 static struct pci_dev *pci_scan_device(struct pci_bus *bus, int devfn)
1263 struct pci_dev *dev;
1266 if (!pci_bus_read_dev_vendor_id(bus, devfn, &l, 60*1000))
1269 dev = alloc_pci_dev();
1275 dev->vendor = l & 0xffff;
1276 dev->device = (l >> 16) & 0xffff;
1278 pci_set_of_node(dev);
1280 if (pci_setup_device(dev)) {
1288 static void pci_init_capabilities(struct pci_dev *dev)
1290 /* MSI/MSI-X list */
1291 pci_msi_init_pci_dev(dev);
1293 /* Buffers for saving PCIe and PCI-X capabilities */
1294 pci_allocate_cap_save_buffers(dev);
1296 /* Power Management */
1299 /* Vital Product Data */
1300 pci_vpd_pci22_init(dev);
1302 /* Alternative Routing-ID Forwarding */
1303 pci_configure_ari(dev);
1305 /* Single Root I/O Virtualization */
1308 /* Enable ACS P2P upstream forwarding */
1309 pci_enable_acs(dev);
1312 void pci_device_add(struct pci_dev *dev, struct pci_bus *bus)
1316 device_initialize(&dev->dev);
1317 dev->dev.release = pci_release_dev;
1319 set_dev_node(&dev->dev, pcibus_to_node(bus));
1320 dev->dev.dma_mask = &dev->dma_mask;
1321 dev->dev.dma_parms = &dev->dma_parms;
1322 dev->dev.coherent_dma_mask = 0xffffffffull;
1324 pci_set_dma_max_seg_size(dev, 65536);
1325 pci_set_dma_seg_boundary(dev, 0xffffffff);
1327 /* Fix up broken headers */
1328 pci_fixup_device(pci_fixup_header, dev);
1330 /* moved out from quirk header fixup code */
1331 pci_reassigndev_resource_alignment(dev);
1333 /* Clear the state_saved flag. */
1334 dev->state_saved = false;
1336 /* Initialize various capabilities */
1337 pci_init_capabilities(dev);
1340 * Add the device to our list of discovered devices
1341 * and the bus list for fixup functions, etc.
1343 down_write(&pci_bus_sem);
1344 list_add_tail(&dev->bus_list, &bus->devices);
1345 up_write(&pci_bus_sem);
1347 ret = pcibios_add_device(dev);
1350 /* Notifier could use PCI capabilities */
1351 dev->match_driver = false;
1352 ret = device_add(&dev->dev);
1355 pci_proc_attach_device(dev);
1358 struct pci_dev *__ref pci_scan_single_device(struct pci_bus *bus, int devfn)
1360 struct pci_dev *dev;
1362 dev = pci_get_slot(bus, devfn);
1368 dev = pci_scan_device(bus, devfn);
1372 pci_device_add(dev, bus);
1376 EXPORT_SYMBOL(pci_scan_single_device);
1378 static unsigned next_fn(struct pci_bus *bus, struct pci_dev *dev, unsigned fn)
1384 if (pci_ari_enabled(bus)) {
1387 pos = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ARI);
1391 pci_read_config_word(dev, pos + PCI_ARI_CAP, &cap);
1392 next_fn = PCI_ARI_CAP_NFN(cap);
1394 return 0; /* protect against malformed list */
1399 /* dev may be NULL for non-contiguous multifunction devices */
1400 if (!dev || dev->multifunction)
1401 return (fn + 1) % 8;
1406 static int only_one_child(struct pci_bus *bus)
1408 struct pci_dev *parent = bus->self;
1410 if (!parent || !pci_is_pcie(parent))
1412 if (pci_pcie_type(parent) == PCI_EXP_TYPE_ROOT_PORT)
1414 if (pci_pcie_type(parent) == PCI_EXP_TYPE_DOWNSTREAM &&
1415 !pci_has_flag(PCI_SCAN_ALL_PCIE_DEVS))
1421 * pci_scan_slot - scan a PCI slot on a bus for devices.
1422 * @bus: PCI bus to scan
1423 * @devfn: slot number to scan (must have zero function.)
1425 * Scan a PCI slot on the specified PCI bus for devices, adding
1426 * discovered devices to the @bus->devices list. New devices
1427 * will not have is_added set.
1429 * Returns the number of new devices found.
1431 int pci_scan_slot(struct pci_bus *bus, int devfn)
1433 unsigned fn, nr = 0;
1434 struct pci_dev *dev;
1436 if (only_one_child(bus) && (devfn > 0))
1437 return 0; /* Already scanned the entire slot */
1439 dev = pci_scan_single_device(bus, devfn);
1445 for (fn = next_fn(bus, dev, 0); fn > 0; fn = next_fn(bus, dev, fn)) {
1446 dev = pci_scan_single_device(bus, devfn + fn);
1450 dev->multifunction = 1;
1454 /* only one slot has pcie device */
1455 if (bus->self && nr)
1456 pcie_aspm_init_link_state(bus->self);
1461 static int pcie_find_smpss(struct pci_dev *dev, void *data)
1465 if (!pci_is_pcie(dev))
1468 /* For PCIE hotplug enabled slots not connected directly to a
1469 * PCI-E root port, there can be problems when hotplugging
1470 * devices. This is due to the possibility of hotplugging a
1471 * device into the fabric with a smaller MPS that the devices
1472 * currently running have configured. Modifying the MPS on the
1473 * running devices could cause a fatal bus error due to an
1474 * incoming frame being larger than the newly configured MPS.
1475 * To work around this, the MPS for the entire fabric must be
1476 * set to the minimum size. Any devices hotplugged into this
1477 * fabric will have the minimum MPS set. If the PCI hotplug
1478 * slot is directly connected to the root port and there are not
1479 * other devices on the fabric (which seems to be the most
1480 * common case), then this is not an issue and MPS discovery
1481 * will occur as normal.
1483 if (dev->is_hotplug_bridge && (!list_is_singular(&dev->bus->devices) ||
1485 pci_pcie_type(dev->bus->self) != PCI_EXP_TYPE_ROOT_PORT)))
1488 if (*smpss > dev->pcie_mpss)
1489 *smpss = dev->pcie_mpss;
1494 static void pcie_write_mps(struct pci_dev *dev, int mps)
1498 if (pcie_bus_config == PCIE_BUS_PERFORMANCE) {
1499 mps = 128 << dev->pcie_mpss;
1501 if (pci_pcie_type(dev) != PCI_EXP_TYPE_ROOT_PORT &&
1503 /* For "Performance", the assumption is made that
1504 * downstream communication will never be larger than
1505 * the MRRS. So, the MPS only needs to be configured
1506 * for the upstream communication. This being the case,
1507 * walk from the top down and set the MPS of the child
1508 * to that of the parent bus.
1510 * Configure the device MPS with the smaller of the
1511 * device MPSS or the bridge MPS (which is assumed to be
1512 * properly configured at this point to the largest
1513 * allowable MPS based on its parent bus).
1515 mps = min(mps, pcie_get_mps(dev->bus->self));
1518 rc = pcie_set_mps(dev, mps);
1520 dev_err(&dev->dev, "Failed attempting to set the MPS\n");
1523 static void pcie_write_mrrs(struct pci_dev *dev)
1527 /* In the "safe" case, do not configure the MRRS. There appear to be
1528 * issues with setting MRRS to 0 on a number of devices.
1530 if (pcie_bus_config != PCIE_BUS_PERFORMANCE)
1533 /* For Max performance, the MRRS must be set to the largest supported
1534 * value. However, it cannot be configured larger than the MPS the
1535 * device or the bus can support. This should already be properly
1536 * configured by a prior call to pcie_write_mps.
1538 mrrs = pcie_get_mps(dev);
1540 /* MRRS is a R/W register. Invalid values can be written, but a
1541 * subsequent read will verify if the value is acceptable or not.
1542 * If the MRRS value provided is not acceptable (e.g., too large),
1543 * shrink the value until it is acceptable to the HW.
1545 while (mrrs != pcie_get_readrq(dev) && mrrs >= 128) {
1546 rc = pcie_set_readrq(dev, mrrs);
1550 dev_warn(&dev->dev, "Failed attempting to set the MRRS\n");
1555 dev_err(&dev->dev, "MRRS was unable to be configured with a "
1556 "safe value. If problems are experienced, try running "
1557 "with pci=pcie_bus_safe.\n");
1560 static int pcie_bus_configure_set(struct pci_dev *dev, void *data)
1564 if (!pci_is_pcie(dev))
1567 mps = 128 << *(u8 *)data;
1568 orig_mps = pcie_get_mps(dev);
1570 pcie_write_mps(dev, mps);
1571 pcie_write_mrrs(dev);
1573 dev_info(&dev->dev, "PCI-E Max Payload Size set to %4d/%4d (was %4d), "
1574 "Max Read Rq %4d\n", pcie_get_mps(dev), 128 << dev->pcie_mpss,
1575 orig_mps, pcie_get_readrq(dev));
1580 /* pcie_bus_configure_settings requires that pci_walk_bus work in a top-down,
1581 * parents then children fashion. If this changes, then this code will not
1584 void pcie_bus_configure_settings(struct pci_bus *bus, u8 mpss)
1588 if (!pci_is_pcie(bus->self))
1591 if (pcie_bus_config == PCIE_BUS_TUNE_OFF)
1594 /* FIXME - Peer to peer DMA is possible, though the endpoint would need
1595 * to be aware to the MPS of the destination. To work around this,
1596 * simply force the MPS of the entire system to the smallest possible.
1598 if (pcie_bus_config == PCIE_BUS_PEER2PEER)
1601 if (pcie_bus_config == PCIE_BUS_SAFE) {
1604 pcie_find_smpss(bus->self, &smpss);
1605 pci_walk_bus(bus, pcie_find_smpss, &smpss);
1608 pcie_bus_configure_set(bus->self, &smpss);
1609 pci_walk_bus(bus, pcie_bus_configure_set, &smpss);
1611 EXPORT_SYMBOL_GPL(pcie_bus_configure_settings);
1613 unsigned int pci_scan_child_bus(struct pci_bus *bus)
1615 unsigned int devfn, pass, max = bus->busn_res.start;
1616 struct pci_dev *dev;
1618 dev_dbg(&bus->dev, "scanning bus\n");
1620 /* Go find them, Rover! */
1621 for (devfn = 0; devfn < 0x100; devfn += 8)
1622 pci_scan_slot(bus, devfn);
1624 /* Reserve buses for SR-IOV capability. */
1625 max += pci_iov_bus_range(bus);
1628 * After performing arch-dependent fixup of the bus, look behind
1629 * all PCI-to-PCI bridges on this bus.
1631 if (!bus->is_added) {
1632 dev_dbg(&bus->dev, "fixups for bus\n");
1633 pcibios_fixup_bus(bus);
1637 for (pass=0; pass < 2; pass++)
1638 list_for_each_entry(dev, &bus->devices, bus_list) {
1639 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE ||
1640 dev->hdr_type == PCI_HEADER_TYPE_CARDBUS)
1641 max = pci_scan_bridge(bus, dev, max, pass);
1645 * We've scanned the bus and so we know all about what's on
1646 * the other side of any bridges that may be on this bus plus
1649 * Return how far we've got finding sub-buses.
1651 dev_dbg(&bus->dev, "bus scan returning with max=%02x\n", max);
1656 * pcibios_root_bridge_prepare - Platform-specific host bridge setup.
1657 * @bridge: Host bridge to set up.
1659 * Default empty implementation. Replace with an architecture-specific setup
1660 * routine, if necessary.
1662 int __weak pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
1667 void __weak pcibios_add_bus(struct pci_bus *bus)
1671 void __weak pcibios_remove_bus(struct pci_bus *bus)
1675 struct pci_bus *pci_create_root_bus(struct device *parent, int bus,
1676 struct pci_ops *ops, void *sysdata, struct list_head *resources)
1679 struct pci_host_bridge *bridge;
1680 struct pci_bus *b, *b2;
1681 struct pci_host_bridge_window *window, *n;
1682 struct resource *res;
1683 resource_size_t offset;
1687 b = pci_alloc_bus();
1691 b->sysdata = sysdata;
1693 b->number = b->busn_res.start = bus;
1694 b2 = pci_find_bus(pci_domain_nr(b), bus);
1696 /* If we already got to this bus through a different bridge, ignore it */
1697 dev_dbg(&b2->dev, "bus already known\n");
1701 bridge = pci_alloc_host_bridge(b);
1705 bridge->dev.parent = parent;
1706 bridge->dev.release = pci_release_bus_bridge_dev;
1707 dev_set_name(&bridge->dev, "pci%04x:%02x", pci_domain_nr(b), bus);
1708 error = pcibios_root_bridge_prepare(bridge);
1714 error = device_register(&bridge->dev);
1716 put_device(&bridge->dev);
1719 b->bridge = get_device(&bridge->dev);
1720 device_enable_async_suspend(b->bridge);
1721 pci_set_bus_of_node(b);
1724 set_dev_node(b->bridge, pcibus_to_node(b));
1726 b->dev.class = &pcibus_class;
1727 b->dev.parent = b->bridge;
1728 dev_set_name(&b->dev, "%04x:%02x", pci_domain_nr(b), bus);
1729 error = device_register(&b->dev);
1731 goto class_dev_reg_err;
1735 /* Create legacy_io and legacy_mem files for this bus */
1736 pci_create_legacy_files(b);
1739 dev_info(parent, "PCI host bridge to bus %s\n", dev_name(&b->dev));
1741 printk(KERN_INFO "PCI host bridge to bus %s\n", dev_name(&b->dev));
1743 /* Add initial resources to the bus */
1744 list_for_each_entry_safe(window, n, resources, list) {
1745 list_move_tail(&window->list, &bridge->windows);
1747 offset = window->offset;
1748 if (res->flags & IORESOURCE_BUS)
1749 pci_bus_insert_busn_res(b, bus, res->end);
1751 pci_bus_add_resource(b, res, 0);
1753 if (resource_type(res) == IORESOURCE_IO)
1754 fmt = " (bus address [%#06llx-%#06llx])";
1756 fmt = " (bus address [%#010llx-%#010llx])";
1757 snprintf(bus_addr, sizeof(bus_addr), fmt,
1758 (unsigned long long) (res->start - offset),
1759 (unsigned long long) (res->end - offset));
1762 dev_info(&b->dev, "root bus resource %pR%s\n", res, bus_addr);
1765 down_write(&pci_bus_sem);
1766 list_add_tail(&b->node, &pci_root_buses);
1767 up_write(&pci_bus_sem);
1772 put_device(&bridge->dev);
1773 device_unregister(&bridge->dev);
1779 int pci_bus_insert_busn_res(struct pci_bus *b, int bus, int bus_max)
1781 struct resource *res = &b->busn_res;
1782 struct resource *parent_res, *conflict;
1786 res->flags = IORESOURCE_BUS;
1788 if (!pci_is_root_bus(b))
1789 parent_res = &b->parent->busn_res;
1791 parent_res = get_pci_domain_busn_res(pci_domain_nr(b));
1792 res->flags |= IORESOURCE_PCI_FIXED;
1795 conflict = insert_resource_conflict(parent_res, res);
1798 dev_printk(KERN_DEBUG, &b->dev,
1799 "busn_res: can not insert %pR under %s%pR (conflicts with %s %pR)\n",
1800 res, pci_is_root_bus(b) ? "domain " : "",
1801 parent_res, conflict->name, conflict);
1803 return conflict == NULL;
1806 int pci_bus_update_busn_res_end(struct pci_bus *b, int bus_max)
1808 struct resource *res = &b->busn_res;
1809 struct resource old_res = *res;
1810 resource_size_t size;
1813 if (res->start > bus_max)
1816 size = bus_max - res->start + 1;
1817 ret = adjust_resource(res, res->start, size);
1818 dev_printk(KERN_DEBUG, &b->dev,
1819 "busn_res: %pR end %s updated to %02x\n",
1820 &old_res, ret ? "can not be" : "is", bus_max);
1822 if (!ret && !res->parent)
1823 pci_bus_insert_busn_res(b, res->start, res->end);
1828 void pci_bus_release_busn_res(struct pci_bus *b)
1830 struct resource *res = &b->busn_res;
1833 if (!res->flags || !res->parent)
1836 ret = release_resource(res);
1837 dev_printk(KERN_DEBUG, &b->dev,
1838 "busn_res: %pR %s released\n",
1839 res, ret ? "can not be" : "is");
1842 struct pci_bus *pci_scan_root_bus(struct device *parent, int bus,
1843 struct pci_ops *ops, void *sysdata, struct list_head *resources)
1845 struct pci_host_bridge_window *window;
1850 list_for_each_entry(window, resources, list)
1851 if (window->res->flags & IORESOURCE_BUS) {
1856 b = pci_create_root_bus(parent, bus, ops, sysdata, resources);
1862 "No busn resource found for root bus, will use [bus %02x-ff]\n",
1864 pci_bus_insert_busn_res(b, bus, 255);
1867 max = pci_scan_child_bus(b);
1870 pci_bus_update_busn_res_end(b, max);
1872 pci_bus_add_devices(b);
1875 EXPORT_SYMBOL(pci_scan_root_bus);
1877 /* Deprecated; use pci_scan_root_bus() instead */
1878 struct pci_bus *pci_scan_bus_parented(struct device *parent,
1879 int bus, struct pci_ops *ops, void *sysdata)
1881 LIST_HEAD(resources);
1884 pci_add_resource(&resources, &ioport_resource);
1885 pci_add_resource(&resources, &iomem_resource);
1886 pci_add_resource(&resources, &busn_resource);
1887 b = pci_create_root_bus(parent, bus, ops, sysdata, &resources);
1889 pci_scan_child_bus(b);
1891 pci_free_resource_list(&resources);
1894 EXPORT_SYMBOL(pci_scan_bus_parented);
1896 struct pci_bus *pci_scan_bus(int bus, struct pci_ops *ops,
1899 LIST_HEAD(resources);
1902 pci_add_resource(&resources, &ioport_resource);
1903 pci_add_resource(&resources, &iomem_resource);
1904 pci_add_resource(&resources, &busn_resource);
1905 b = pci_create_root_bus(NULL, bus, ops, sysdata, &resources);
1907 pci_scan_child_bus(b);
1908 pci_bus_add_devices(b);
1910 pci_free_resource_list(&resources);
1914 EXPORT_SYMBOL(pci_scan_bus);
1917 * pci_rescan_bus_bridge_resize - scan a PCI bus for devices.
1918 * @bridge: PCI bridge for the bus to scan
1920 * Scan a PCI bus and child buses for new devices, add them,
1921 * and enable them, resizing bridge mmio/io resource if necessary
1922 * and possible. The caller must ensure the child devices are already
1923 * removed for resizing to occur.
1925 * Returns the max number of subordinate bus discovered.
1927 unsigned int __ref pci_rescan_bus_bridge_resize(struct pci_dev *bridge)
1930 struct pci_bus *bus = bridge->subordinate;
1932 max = pci_scan_child_bus(bus);
1934 pci_assign_unassigned_bridge_resources(bridge);
1936 pci_bus_add_devices(bus);
1942 * pci_rescan_bus - scan a PCI bus for devices.
1943 * @bus: PCI bus to scan
1945 * Scan a PCI bus and child buses for new devices, adds them,
1948 * Returns the max number of subordinate bus discovered.
1950 unsigned int __ref pci_rescan_bus(struct pci_bus *bus)
1954 max = pci_scan_child_bus(bus);
1955 pci_assign_unassigned_bus_resources(bus);
1956 pci_enable_bridges(bus);
1957 pci_bus_add_devices(bus);
1961 EXPORT_SYMBOL_GPL(pci_rescan_bus);
1963 EXPORT_SYMBOL(pci_add_new_bus);
1964 EXPORT_SYMBOL(pci_scan_slot);
1965 EXPORT_SYMBOL(pci_scan_bridge);
1966 EXPORT_SYMBOL_GPL(pci_scan_child_bus);
1968 static int __init pci_sort_bf_cmp(const struct device *d_a, const struct device *d_b)
1970 const struct pci_dev *a = to_pci_dev(d_a);
1971 const struct pci_dev *b = to_pci_dev(d_b);
1973 if (pci_domain_nr(a->bus) < pci_domain_nr(b->bus)) return -1;
1974 else if (pci_domain_nr(a->bus) > pci_domain_nr(b->bus)) return 1;
1976 if (a->bus->number < b->bus->number) return -1;
1977 else if (a->bus->number > b->bus->number) return 1;
1979 if (a->devfn < b->devfn) return -1;
1980 else if (a->devfn > b->devfn) return 1;
1985 void __init pci_sort_breadthfirst(void)
1987 bus_sort_breadthfirst(&pci_bus_type, &pci_sort_bf_cmp);