3 * Purpose: PCI Message Signaled Interrupt (MSI)
5 * Copyright (C) 2003-2004 Intel
6 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
11 #include <linux/irq.h>
12 #include <linux/interrupt.h>
13 #include <linux/init.h>
14 #include <linux/export.h>
15 #include <linux/ioport.h>
16 #include <linux/pci.h>
17 #include <linux/proc_fs.h>
18 #include <linux/msi.h>
19 #include <linux/smp.h>
20 #include <linux/errno.h>
22 #include <linux/slab.h>
27 static int pci_msi_enable = 1;
31 #ifndef arch_msi_check_device
32 int arch_msi_check_device(struct pci_dev *dev, int nvec, int type)
38 #ifndef arch_setup_msi_irqs
39 # define arch_setup_msi_irqs default_setup_msi_irqs
40 # define HAVE_DEFAULT_MSI_SETUP_IRQS
43 #ifdef HAVE_DEFAULT_MSI_SETUP_IRQS
44 int default_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
46 struct msi_desc *entry;
50 * If an architecture wants to support multiple MSI, it needs to
51 * override arch_setup_msi_irqs()
53 if (type == PCI_CAP_ID_MSI && nvec > 1)
56 list_for_each_entry(entry, &dev->msi_list, list) {
57 ret = arch_setup_msi_irq(dev, entry);
68 #ifndef arch_teardown_msi_irqs
69 # define arch_teardown_msi_irqs default_teardown_msi_irqs
70 # define HAVE_DEFAULT_MSI_TEARDOWN_IRQS
73 #ifdef HAVE_DEFAULT_MSI_TEARDOWN_IRQS
74 void default_teardown_msi_irqs(struct pci_dev *dev)
76 struct msi_desc *entry;
78 list_for_each_entry(entry, &dev->msi_list, list) {
82 nvec = 1 << entry->msi_attrib.multiple;
83 for (i = 0; i < nvec; i++)
84 arch_teardown_msi_irq(entry->irq + i);
89 #ifndef arch_restore_msi_irqs
90 # define arch_restore_msi_irqs default_restore_msi_irqs
91 # define HAVE_DEFAULT_MSI_RESTORE_IRQS
94 #ifdef HAVE_DEFAULT_MSI_RESTORE_IRQS
95 void default_restore_msi_irqs(struct pci_dev *dev, int irq)
97 struct msi_desc *entry;
100 if (dev->msix_enabled) {
101 list_for_each_entry(entry, &dev->msi_list, list) {
102 if (irq == entry->irq)
105 } else if (dev->msi_enabled) {
106 entry = irq_get_msi_desc(irq);
110 write_msi_msg(irq, &entry->msg);
114 static void msi_set_enable(struct pci_dev *dev, int enable)
118 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
119 control &= ~PCI_MSI_FLAGS_ENABLE;
121 control |= PCI_MSI_FLAGS_ENABLE;
122 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
125 static void msix_set_enable(struct pci_dev *dev, int enable)
129 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
130 control &= ~PCI_MSIX_FLAGS_ENABLE;
132 control |= PCI_MSIX_FLAGS_ENABLE;
133 pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control);
136 static inline __attribute_const__ u32 msi_mask(unsigned x)
138 /* Don't shift by >= width of type */
141 return (1 << (1 << x)) - 1;
144 static inline __attribute_const__ u32 msi_capable_mask(u16 control)
146 return msi_mask((control >> 1) & 7);
149 static inline __attribute_const__ u32 msi_enabled_mask(u16 control)
151 return msi_mask((control >> 4) & 7);
155 * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to
156 * mask all MSI interrupts by clearing the MSI enable bit does not work
157 * reliably as devices without an INTx disable bit will then generate a
158 * level IRQ which will never be cleared.
160 static u32 __msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
162 u32 mask_bits = desc->masked;
164 if (!desc->msi_attrib.maskbit)
169 pci_write_config_dword(desc->dev, desc->mask_pos, mask_bits);
174 static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
176 desc->masked = __msi_mask_irq(desc, mask, flag);
180 * This internal function does not flush PCI writes to the device.
181 * All users must ensure that they read from the device before either
182 * assuming that the device state is up to date, or returning out of this
183 * file. This saves a few milliseconds when initialising devices with lots
184 * of MSI-X interrupts.
186 static u32 __msix_mask_irq(struct msi_desc *desc, u32 flag)
188 u32 mask_bits = desc->masked;
189 unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
190 PCI_MSIX_ENTRY_VECTOR_CTRL;
191 mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT;
193 mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT;
194 writel(mask_bits, desc->mask_base + offset);
199 static void msix_mask_irq(struct msi_desc *desc, u32 flag)
201 desc->masked = __msix_mask_irq(desc, flag);
204 #ifdef CONFIG_GENERIC_HARDIRQS
206 static void msi_set_mask_bit(struct irq_data *data, u32 flag)
208 struct msi_desc *desc = irq_data_get_msi(data);
210 if (desc->msi_attrib.is_msix) {
211 msix_mask_irq(desc, flag);
212 readl(desc->mask_base); /* Flush write to device */
214 unsigned offset = data->irq - desc->dev->irq;
215 msi_mask_irq(desc, 1 << offset, flag << offset);
219 void mask_msi_irq(struct irq_data *data)
221 msi_set_mask_bit(data, 1);
224 void unmask_msi_irq(struct irq_data *data)
226 msi_set_mask_bit(data, 0);
229 #endif /* CONFIG_GENERIC_HARDIRQS */
231 void __read_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
233 BUG_ON(entry->dev->current_state != PCI_D0);
235 if (entry->msi_attrib.is_msix) {
236 void __iomem *base = entry->mask_base +
237 entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
239 msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR);
240 msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR);
241 msg->data = readl(base + PCI_MSIX_ENTRY_DATA);
243 struct pci_dev *dev = entry->dev;
244 int pos = dev->msi_cap;
247 pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_LO,
249 if (entry->msi_attrib.is_64) {
250 pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_HI,
252 pci_read_config_word(dev, msi_data_reg(pos, 1), &data);
255 pci_read_config_word(dev, msi_data_reg(pos, 0), &data);
261 void read_msi_msg(unsigned int irq, struct msi_msg *msg)
263 struct msi_desc *entry = irq_get_msi_desc(irq);
265 __read_msi_msg(entry, msg);
268 void __get_cached_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
270 /* Assert that the cache is valid, assuming that
271 * valid messages are not all-zeroes. */
272 BUG_ON(!(entry->msg.address_hi | entry->msg.address_lo |
278 void get_cached_msi_msg(unsigned int irq, struct msi_msg *msg)
280 struct msi_desc *entry = irq_get_msi_desc(irq);
282 __get_cached_msi_msg(entry, msg);
285 void __write_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
287 if (entry->dev->current_state != PCI_D0) {
288 /* Don't touch the hardware now */
289 } else if (entry->msi_attrib.is_msix) {
291 base = entry->mask_base +
292 entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
294 writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR);
295 writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR);
296 writel(msg->data, base + PCI_MSIX_ENTRY_DATA);
298 struct pci_dev *dev = entry->dev;
299 int pos = dev->msi_cap;
302 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl);
303 msgctl &= ~PCI_MSI_FLAGS_QSIZE;
304 msgctl |= entry->msi_attrib.multiple << 4;
305 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, msgctl);
307 pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO,
309 if (entry->msi_attrib.is_64) {
310 pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_HI,
312 pci_write_config_word(dev, msi_data_reg(pos, 1),
315 pci_write_config_word(dev, msi_data_reg(pos, 0),
322 void write_msi_msg(unsigned int irq, struct msi_msg *msg)
324 struct msi_desc *entry = irq_get_msi_desc(irq);
326 __write_msi_msg(entry, msg);
329 static void free_msi_irqs(struct pci_dev *dev)
331 struct msi_desc *entry, *tmp;
333 list_for_each_entry(entry, &dev->msi_list, list) {
337 nvec = 1 << entry->msi_attrib.multiple;
338 #ifdef CONFIG_GENERIC_HARDIRQS
339 for (i = 0; i < nvec; i++)
340 BUG_ON(irq_has_action(entry->irq + i));
344 arch_teardown_msi_irqs(dev);
346 list_for_each_entry_safe(entry, tmp, &dev->msi_list, list) {
347 if (entry->msi_attrib.is_msix) {
348 if (list_is_last(&entry->list, &dev->msi_list))
349 iounmap(entry->mask_base);
353 * Its possible that we get into this path
354 * When populate_msi_sysfs fails, which means the entries
355 * were not registered with sysfs. In that case don't
358 if (entry->kobj.parent) {
359 kobject_del(&entry->kobj);
360 kobject_put(&entry->kobj);
363 list_del(&entry->list);
368 static struct msi_desc *alloc_msi_entry(struct pci_dev *dev)
370 struct msi_desc *desc = kzalloc(sizeof(*desc), GFP_KERNEL);
374 INIT_LIST_HEAD(&desc->list);
380 static void pci_intx_for_msi(struct pci_dev *dev, int enable)
382 if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG))
383 pci_intx(dev, enable);
386 static void __pci_restore_msi_state(struct pci_dev *dev)
389 struct msi_desc *entry;
391 if (!dev->msi_enabled)
394 entry = irq_get_msi_desc(dev->irq);
396 pci_intx_for_msi(dev, 0);
397 msi_set_enable(dev, 0);
398 arch_restore_msi_irqs(dev, dev->irq);
400 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
401 msi_mask_irq(entry, msi_capable_mask(control), entry->masked);
402 control &= ~PCI_MSI_FLAGS_QSIZE;
403 control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE;
404 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
407 static void __pci_restore_msix_state(struct pci_dev *dev)
409 struct msi_desc *entry;
412 if (!dev->msix_enabled)
414 BUG_ON(list_empty(&dev->msi_list));
415 entry = list_first_entry(&dev->msi_list, struct msi_desc, list);
416 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
418 /* route the table */
419 pci_intx_for_msi(dev, 0);
420 control |= PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL;
421 pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control);
423 list_for_each_entry(entry, &dev->msi_list, list) {
424 arch_restore_msi_irqs(dev, entry->irq);
425 msix_mask_irq(entry, entry->masked);
428 control &= ~PCI_MSIX_FLAGS_MASKALL;
429 pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control);
432 void pci_restore_msi_state(struct pci_dev *dev)
434 __pci_restore_msi_state(dev);
435 __pci_restore_msix_state(dev);
437 EXPORT_SYMBOL_GPL(pci_restore_msi_state);
440 #define to_msi_attr(obj) container_of(obj, struct msi_attribute, attr)
441 #define to_msi_desc(obj) container_of(obj, struct msi_desc, kobj)
443 struct msi_attribute {
444 struct attribute attr;
445 ssize_t (*show)(struct msi_desc *entry, struct msi_attribute *attr,
447 ssize_t (*store)(struct msi_desc *entry, struct msi_attribute *attr,
448 const char *buf, size_t count);
451 static ssize_t show_msi_mode(struct msi_desc *entry, struct msi_attribute *atr,
454 return sprintf(buf, "%s\n", entry->msi_attrib.is_msix ? "msix" : "msi");
457 static ssize_t msi_irq_attr_show(struct kobject *kobj,
458 struct attribute *attr, char *buf)
460 struct msi_attribute *attribute = to_msi_attr(attr);
461 struct msi_desc *entry = to_msi_desc(kobj);
463 if (!attribute->show)
466 return attribute->show(entry, attribute, buf);
469 static const struct sysfs_ops msi_irq_sysfs_ops = {
470 .show = msi_irq_attr_show,
473 static struct msi_attribute mode_attribute =
474 __ATTR(mode, S_IRUGO, show_msi_mode, NULL);
477 struct attribute *msi_irq_default_attrs[] = {
478 &mode_attribute.attr,
482 void msi_kobj_release(struct kobject *kobj)
484 struct msi_desc *entry = to_msi_desc(kobj);
486 pci_dev_put(entry->dev);
489 static struct kobj_type msi_irq_ktype = {
490 .release = msi_kobj_release,
491 .sysfs_ops = &msi_irq_sysfs_ops,
492 .default_attrs = msi_irq_default_attrs,
495 static int populate_msi_sysfs(struct pci_dev *pdev)
497 struct msi_desc *entry;
498 struct kobject *kobj;
502 pdev->msi_kset = kset_create_and_add("msi_irqs", NULL, &pdev->dev.kobj);
506 list_for_each_entry(entry, &pdev->msi_list, list) {
508 kobj->kset = pdev->msi_kset;
510 ret = kobject_init_and_add(kobj, &msi_irq_ktype, NULL,
521 list_for_each_entry(entry, &pdev->msi_list, list) {
524 kobject_del(&entry->kobj);
525 kobject_put(&entry->kobj);
532 * msi_capability_init - configure device's MSI capability structure
533 * @dev: pointer to the pci_dev data structure of MSI device function
534 * @nvec: number of interrupts to allocate
536 * Setup the MSI capability structure of the device with the requested
537 * number of interrupts. A return value of zero indicates the successful
538 * setup of an entry with the new MSI irq. A negative return value indicates
539 * an error, and a positive return value indicates the number of interrupts
540 * which could have been allocated.
542 static int msi_capability_init(struct pci_dev *dev, int nvec)
544 struct msi_desc *entry;
549 msi_set_enable(dev, 0); /* Disable MSI during set up */
551 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
552 /* MSI Entry Initialization */
553 entry = alloc_msi_entry(dev);
557 entry->msi_attrib.is_msix = 0;
558 entry->msi_attrib.is_64 = is_64bit_address(control);
559 entry->msi_attrib.entry_nr = 0;
560 entry->msi_attrib.maskbit = is_mask_bit_support(control);
561 entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */
562 entry->msi_attrib.pos = dev->msi_cap;
564 entry->mask_pos = msi_mask_reg(dev->msi_cap, entry->msi_attrib.is_64);
565 /* All MSIs are unmasked by default, Mask them all */
566 if (entry->msi_attrib.maskbit)
567 pci_read_config_dword(dev, entry->mask_pos, &entry->masked);
568 mask = msi_capable_mask(control);
569 msi_mask_irq(entry, mask, mask);
571 list_add_tail(&entry->list, &dev->msi_list);
573 /* Configure MSI capability structure */
574 ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI);
576 msi_mask_irq(entry, mask, ~mask);
581 ret = populate_msi_sysfs(dev);
583 msi_mask_irq(entry, mask, ~mask);
588 /* Set MSI enabled bits */
589 pci_intx_for_msi(dev, 0);
590 msi_set_enable(dev, 1);
591 dev->msi_enabled = 1;
593 dev->irq = entry->irq;
597 static void __iomem *msix_map_region(struct pci_dev *dev, unsigned nr_entries)
599 resource_size_t phys_addr;
603 pci_read_config_dword(dev,
604 msix_table_offset_reg(dev->msix_cap), &table_offset);
605 bir = (u8)(table_offset & PCI_MSIX_FLAGS_BIRMASK);
606 table_offset &= ~PCI_MSIX_FLAGS_BIRMASK;
607 phys_addr = pci_resource_start(dev, bir) + table_offset;
609 return ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE);
612 static int msix_setup_entries(struct pci_dev *dev, void __iomem *base,
613 struct msix_entry *entries, int nvec)
615 struct msi_desc *entry;
618 for (i = 0; i < nvec; i++) {
619 entry = alloc_msi_entry(dev);
625 /* No enough memory. Don't try again */
629 entry->msi_attrib.is_msix = 1;
630 entry->msi_attrib.is_64 = 1;
631 entry->msi_attrib.entry_nr = entries[i].entry;
632 entry->msi_attrib.default_irq = dev->irq;
633 entry->msi_attrib.pos = dev->msix_cap;
634 entry->mask_base = base;
636 list_add_tail(&entry->list, &dev->msi_list);
642 static void msix_program_entries(struct pci_dev *dev,
643 struct msix_entry *entries)
645 struct msi_desc *entry;
648 list_for_each_entry(entry, &dev->msi_list, list) {
649 int offset = entries[i].entry * PCI_MSIX_ENTRY_SIZE +
650 PCI_MSIX_ENTRY_VECTOR_CTRL;
652 entries[i].vector = entry->irq;
653 irq_set_msi_desc(entry->irq, entry);
654 entry->masked = readl(entry->mask_base + offset);
655 msix_mask_irq(entry, 1);
661 * msix_capability_init - configure device's MSI-X capability
662 * @dev: pointer to the pci_dev data structure of MSI-X device function
663 * @entries: pointer to an array of struct msix_entry entries
664 * @nvec: number of @entries
666 * Setup the MSI-X capability structure of device function with a
667 * single MSI-X irq. A return of zero indicates the successful setup of
668 * requested MSI-X entries with allocated irqs or non-zero for otherwise.
670 static int msix_capability_init(struct pci_dev *dev,
671 struct msix_entry *entries, int nvec)
677 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
679 /* Ensure MSI-X is disabled while it is set up */
680 control &= ~PCI_MSIX_FLAGS_ENABLE;
681 pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control);
683 /* Request & Map MSI-X table region */
684 base = msix_map_region(dev, multi_msix_capable(control));
688 ret = msix_setup_entries(dev, base, entries, nvec);
692 ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX);
697 * Some devices require MSI-X to be enabled before we can touch the
698 * MSI-X registers. We need to mask all the vectors to prevent
699 * interrupts coming in before they're fully set up.
701 control |= PCI_MSIX_FLAGS_MASKALL | PCI_MSIX_FLAGS_ENABLE;
702 pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control);
704 msix_program_entries(dev, entries);
706 ret = populate_msi_sysfs(dev);
712 /* Set MSI-X enabled bits and unmask the function */
713 pci_intx_for_msi(dev, 0);
714 dev->msix_enabled = 1;
716 control &= ~PCI_MSIX_FLAGS_MASKALL;
717 pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control);
724 * If we had some success, report the number of irqs
725 * we succeeded in setting up.
727 struct msi_desc *entry;
730 list_for_each_entry(entry, &dev->msi_list, list) {
744 * pci_msi_check_device - check whether MSI may be enabled on a device
745 * @dev: pointer to the pci_dev data structure of MSI device function
746 * @nvec: how many MSIs have been requested ?
747 * @type: are we checking for MSI or MSI-X ?
749 * Look at global flags, the device itself, and its parent busses
750 * to determine if MSI/-X are supported for the device. If MSI/-X is
751 * supported return 0, else return an error code.
753 static int pci_msi_check_device(struct pci_dev *dev, int nvec, int type)
758 /* MSI must be globally enabled and supported by the device */
759 if (!pci_msi_enable || !dev || dev->no_msi)
763 * You can't ask to have 0 or less MSIs configured.
765 * b) the list manipulation code assumes nvec >= 1.
771 * Any bridge which does NOT route MSI transactions from its
772 * secondary bus to its primary bus must set NO_MSI flag on
773 * the secondary pci_bus.
774 * We expect only arch-specific PCI host bus controller driver
775 * or quirks for specific PCI bridges to be setting NO_MSI.
777 for (bus = dev->bus; bus; bus = bus->parent)
778 if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI)
781 ret = arch_msi_check_device(dev, nvec, type);
789 * pci_enable_msi_block - configure device's MSI capability structure
790 * @dev: device to configure
791 * @nvec: number of interrupts to configure
793 * Allocate IRQs for a device with the MSI capability.
794 * This function returns a negative errno if an error occurs. If it
795 * is unable to allocate the number of interrupts requested, it returns
796 * the number of interrupts it might be able to allocate. If it successfully
797 * allocates at least the number of interrupts requested, it returns 0 and
798 * updates the @dev's irq member to the lowest new interrupt number; the
799 * other interrupt numbers allocated to this device are consecutive.
801 int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec)
809 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &msgctl);
810 maxvec = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1);
814 status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSI);
818 WARN_ON(!!dev->msi_enabled);
820 /* Check whether driver already requested MSI-X irqs */
821 if (dev->msix_enabled) {
822 dev_info(&dev->dev, "can't enable MSI "
823 "(MSI-X already enabled)\n");
827 status = msi_capability_init(dev, nvec);
830 EXPORT_SYMBOL(pci_enable_msi_block);
832 int pci_enable_msi_block_auto(struct pci_dev *dev, unsigned int *maxvec)
840 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &msgctl);
841 ret = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1);
848 ret = pci_enable_msi_block(dev, nvec);
855 EXPORT_SYMBOL(pci_enable_msi_block_auto);
857 void pci_msi_shutdown(struct pci_dev *dev)
859 struct msi_desc *desc;
863 if (!pci_msi_enable || !dev || !dev->msi_enabled)
866 BUG_ON(list_empty(&dev->msi_list));
867 desc = list_first_entry(&dev->msi_list, struct msi_desc, list);
869 msi_set_enable(dev, 0);
870 pci_intx_for_msi(dev, 1);
871 dev->msi_enabled = 0;
873 /* Return the device with MSI unmasked as initial states */
874 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &ctrl);
875 mask = msi_capable_mask(ctrl);
876 /* Keep cached state to be restored */
877 __msi_mask_irq(desc, mask, ~mask);
879 /* Restore dev->irq to its default pin-assertion irq */
880 dev->irq = desc->msi_attrib.default_irq;
883 void pci_disable_msi(struct pci_dev *dev)
885 if (!pci_msi_enable || !dev || !dev->msi_enabled)
888 pci_msi_shutdown(dev);
890 kset_unregister(dev->msi_kset);
891 dev->msi_kset = NULL;
893 EXPORT_SYMBOL(pci_disable_msi);
896 * pci_msix_table_size - return the number of device's MSI-X table entries
897 * @dev: pointer to the pci_dev data structure of MSI-X device function
899 int pci_msix_table_size(struct pci_dev *dev)
906 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
907 return multi_msix_capable(control);
911 * pci_enable_msix - configure device's MSI-X capability structure
912 * @dev: pointer to the pci_dev data structure of MSI-X device function
913 * @entries: pointer to an array of MSI-X entries
914 * @nvec: number of MSI-X irqs requested for allocation by device driver
916 * Setup the MSI-X capability structure of device function with the number
917 * of requested irqs upon its software driver call to request for
918 * MSI-X mode enabled on its hardware device function. A return of zero
919 * indicates the successful configuration of MSI-X capability structure
920 * with new allocated MSI-X irqs. A return of < 0 indicates a failure.
921 * Or a return of > 0 indicates that driver request is exceeding the number
922 * of irqs or MSI-X vectors available. Driver should use the returned value to
923 * re-send its request.
925 int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec)
927 int status, nr_entries;
930 if (!entries || !dev->msix_cap)
933 status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSIX);
937 nr_entries = pci_msix_table_size(dev);
938 if (nvec > nr_entries)
941 /* Check for any invalid entries */
942 for (i = 0; i < nvec; i++) {
943 if (entries[i].entry >= nr_entries)
944 return -EINVAL; /* invalid entry */
945 for (j = i + 1; j < nvec; j++) {
946 if (entries[i].entry == entries[j].entry)
947 return -EINVAL; /* duplicate entry */
950 WARN_ON(!!dev->msix_enabled);
952 /* Check whether driver already requested for MSI irq */
953 if (dev->msi_enabled) {
954 dev_info(&dev->dev, "can't enable MSI-X "
955 "(MSI IRQ already assigned)\n");
958 status = msix_capability_init(dev, entries, nvec);
961 EXPORT_SYMBOL(pci_enable_msix);
963 void pci_msix_shutdown(struct pci_dev *dev)
965 struct msi_desc *entry;
967 if (!pci_msi_enable || !dev || !dev->msix_enabled)
970 /* Return the device with MSI-X masked as initial states */
971 list_for_each_entry(entry, &dev->msi_list, list) {
972 /* Keep cached states to be restored */
973 __msix_mask_irq(entry, 1);
976 msix_set_enable(dev, 0);
977 pci_intx_for_msi(dev, 1);
978 dev->msix_enabled = 0;
981 void pci_disable_msix(struct pci_dev *dev)
983 if (!pci_msi_enable || !dev || !dev->msix_enabled)
986 pci_msix_shutdown(dev);
988 kset_unregister(dev->msi_kset);
989 dev->msi_kset = NULL;
991 EXPORT_SYMBOL(pci_disable_msix);
994 * msi_remove_pci_irq_vectors - reclaim MSI(X) irqs to unused state
995 * @dev: pointer to the pci_dev data structure of MSI(X) device function
997 * Being called during hotplug remove, from which the device function
998 * is hot-removed. All previous assigned MSI/MSI-X irqs, if
999 * allocated for this device function, are reclaimed to unused state,
1000 * which may be used later on.
1002 void msi_remove_pci_irq_vectors(struct pci_dev *dev)
1004 if (!pci_msi_enable || !dev)
1007 if (dev->msi_enabled || dev->msix_enabled)
1011 void pci_no_msi(void)
1017 * pci_msi_enabled - is MSI enabled?
1019 * Returns true if MSI has not been disabled by the command-line option
1022 int pci_msi_enabled(void)
1024 return pci_msi_enable;
1026 EXPORT_SYMBOL(pci_msi_enabled);
1028 void pci_msi_init_pci_dev(struct pci_dev *dev)
1030 INIT_LIST_HEAD(&dev->msi_list);
1032 /* Disable the msi hardware to avoid screaming interrupts
1033 * during boot. This is the power on reset default so
1034 * usually this should be a noop.
1036 dev->msi_cap = pci_find_capability(dev, PCI_CAP_ID_MSI);
1038 msi_set_enable(dev, 0);
1040 dev->msix_cap = pci_find_capability(dev, PCI_CAP_ID_MSIX);
1042 msix_set_enable(dev, 0);