3 * Purpose: PCI Message Signaled Interrupt (MSI)
5 * Copyright (C) 2003-2004 Intel
6 * Copyright (C) Tom Long Nguyen (tom.l.nguyen@intel.com)
11 #include <linux/irq.h>
12 #include <linux/interrupt.h>
13 #include <linux/init.h>
14 #include <linux/export.h>
15 #include <linux/ioport.h>
16 #include <linux/pci.h>
17 #include <linux/proc_fs.h>
18 #include <linux/msi.h>
19 #include <linux/smp.h>
20 #include <linux/errno.h>
22 #include <linux/slab.h>
26 static int pci_msi_enable = 1;
28 #define msix_table_size(flags) ((flags & PCI_MSIX_FLAGS_QSIZE) + 1)
33 #ifndef arch_msi_check_device
34 int arch_msi_check_device(struct pci_dev *dev, int nvec, int type)
40 #ifndef arch_setup_msi_irqs
41 # define arch_setup_msi_irqs default_setup_msi_irqs
42 # define HAVE_DEFAULT_MSI_SETUP_IRQS
45 #ifdef HAVE_DEFAULT_MSI_SETUP_IRQS
46 int default_setup_msi_irqs(struct pci_dev *dev, int nvec, int type)
48 struct msi_desc *entry;
52 * If an architecture wants to support multiple MSI, it needs to
53 * override arch_setup_msi_irqs()
55 if (type == PCI_CAP_ID_MSI && nvec > 1)
58 list_for_each_entry(entry, &dev->msi_list, list) {
59 ret = arch_setup_msi_irq(dev, entry);
70 #ifndef arch_teardown_msi_irqs
71 # define arch_teardown_msi_irqs default_teardown_msi_irqs
72 # define HAVE_DEFAULT_MSI_TEARDOWN_IRQS
75 #ifdef HAVE_DEFAULT_MSI_TEARDOWN_IRQS
76 void default_teardown_msi_irqs(struct pci_dev *dev)
78 struct msi_desc *entry;
80 list_for_each_entry(entry, &dev->msi_list, list) {
84 nvec = 1 << entry->msi_attrib.multiple;
85 for (i = 0; i < nvec; i++)
86 arch_teardown_msi_irq(entry->irq + i);
91 #ifndef arch_restore_msi_irqs
92 # define arch_restore_msi_irqs default_restore_msi_irqs
93 # define HAVE_DEFAULT_MSI_RESTORE_IRQS
96 #ifdef HAVE_DEFAULT_MSI_RESTORE_IRQS
97 void default_restore_msi_irqs(struct pci_dev *dev, int irq)
99 struct msi_desc *entry;
102 if (dev->msix_enabled) {
103 list_for_each_entry(entry, &dev->msi_list, list) {
104 if (irq == entry->irq)
107 } else if (dev->msi_enabled) {
108 entry = irq_get_msi_desc(irq);
112 write_msi_msg(irq, &entry->msg);
116 static void msi_set_enable(struct pci_dev *dev, int enable)
120 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
121 control &= ~PCI_MSI_FLAGS_ENABLE;
123 control |= PCI_MSI_FLAGS_ENABLE;
124 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
127 static void msix_set_enable(struct pci_dev *dev, int enable)
131 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
132 control &= ~PCI_MSIX_FLAGS_ENABLE;
134 control |= PCI_MSIX_FLAGS_ENABLE;
135 pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control);
138 static inline __attribute_const__ u32 msi_mask(unsigned x)
140 /* Don't shift by >= width of type */
143 return (1 << (1 << x)) - 1;
146 static inline __attribute_const__ u32 msi_capable_mask(u16 control)
148 return msi_mask((control >> 1) & 7);
151 static inline __attribute_const__ u32 msi_enabled_mask(u16 control)
153 return msi_mask((control >> 4) & 7);
157 * PCI 2.3 does not specify mask bits for each MSI interrupt. Attempting to
158 * mask all MSI interrupts by clearing the MSI enable bit does not work
159 * reliably as devices without an INTx disable bit will then generate a
160 * level IRQ which will never be cleared.
162 static u32 __msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
164 u32 mask_bits = desc->masked;
166 if (!desc->msi_attrib.maskbit)
171 pci_write_config_dword(desc->dev, desc->mask_pos, mask_bits);
176 static void msi_mask_irq(struct msi_desc *desc, u32 mask, u32 flag)
178 desc->masked = __msi_mask_irq(desc, mask, flag);
182 * This internal function does not flush PCI writes to the device.
183 * All users must ensure that they read from the device before either
184 * assuming that the device state is up to date, or returning out of this
185 * file. This saves a few milliseconds when initialising devices with lots
186 * of MSI-X interrupts.
188 static u32 __msix_mask_irq(struct msi_desc *desc, u32 flag)
190 u32 mask_bits = desc->masked;
191 unsigned offset = desc->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE +
192 PCI_MSIX_ENTRY_VECTOR_CTRL;
193 mask_bits &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT;
195 mask_bits |= PCI_MSIX_ENTRY_CTRL_MASKBIT;
196 writel(mask_bits, desc->mask_base + offset);
201 static void msix_mask_irq(struct msi_desc *desc, u32 flag)
203 desc->masked = __msix_mask_irq(desc, flag);
206 #ifdef CONFIG_GENERIC_HARDIRQS
208 static void msi_set_mask_bit(struct irq_data *data, u32 flag)
210 struct msi_desc *desc = irq_data_get_msi(data);
212 if (desc->msi_attrib.is_msix) {
213 msix_mask_irq(desc, flag);
214 readl(desc->mask_base); /* Flush write to device */
216 unsigned offset = data->irq - desc->dev->irq;
217 msi_mask_irq(desc, 1 << offset, flag << offset);
221 void mask_msi_irq(struct irq_data *data)
223 msi_set_mask_bit(data, 1);
226 void unmask_msi_irq(struct irq_data *data)
228 msi_set_mask_bit(data, 0);
231 #endif /* CONFIG_GENERIC_HARDIRQS */
233 void __read_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
235 BUG_ON(entry->dev->current_state != PCI_D0);
237 if (entry->msi_attrib.is_msix) {
238 void __iomem *base = entry->mask_base +
239 entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
241 msg->address_lo = readl(base + PCI_MSIX_ENTRY_LOWER_ADDR);
242 msg->address_hi = readl(base + PCI_MSIX_ENTRY_UPPER_ADDR);
243 msg->data = readl(base + PCI_MSIX_ENTRY_DATA);
245 struct pci_dev *dev = entry->dev;
246 int pos = dev->msi_cap;
249 pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_LO,
251 if (entry->msi_attrib.is_64) {
252 pci_read_config_dword(dev, pos + PCI_MSI_ADDRESS_HI,
254 pci_read_config_word(dev, pos + PCI_MSI_DATA_64, &data);
257 pci_read_config_word(dev, pos + PCI_MSI_DATA_32, &data);
263 void read_msi_msg(unsigned int irq, struct msi_msg *msg)
265 struct msi_desc *entry = irq_get_msi_desc(irq);
267 __read_msi_msg(entry, msg);
270 void __get_cached_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
272 /* Assert that the cache is valid, assuming that
273 * valid messages are not all-zeroes. */
274 BUG_ON(!(entry->msg.address_hi | entry->msg.address_lo |
280 void get_cached_msi_msg(unsigned int irq, struct msi_msg *msg)
282 struct msi_desc *entry = irq_get_msi_desc(irq);
284 __get_cached_msi_msg(entry, msg);
287 void __write_msi_msg(struct msi_desc *entry, struct msi_msg *msg)
289 if (entry->dev->current_state != PCI_D0) {
290 /* Don't touch the hardware now */
291 } else if (entry->msi_attrib.is_msix) {
293 base = entry->mask_base +
294 entry->msi_attrib.entry_nr * PCI_MSIX_ENTRY_SIZE;
296 writel(msg->address_lo, base + PCI_MSIX_ENTRY_LOWER_ADDR);
297 writel(msg->address_hi, base + PCI_MSIX_ENTRY_UPPER_ADDR);
298 writel(msg->data, base + PCI_MSIX_ENTRY_DATA);
300 struct pci_dev *dev = entry->dev;
301 int pos = dev->msi_cap;
304 pci_read_config_word(dev, pos + PCI_MSI_FLAGS, &msgctl);
305 msgctl &= ~PCI_MSI_FLAGS_QSIZE;
306 msgctl |= entry->msi_attrib.multiple << 4;
307 pci_write_config_word(dev, pos + PCI_MSI_FLAGS, msgctl);
309 pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_LO,
311 if (entry->msi_attrib.is_64) {
312 pci_write_config_dword(dev, pos + PCI_MSI_ADDRESS_HI,
314 pci_write_config_word(dev, pos + PCI_MSI_DATA_64,
317 pci_write_config_word(dev, pos + PCI_MSI_DATA_32,
324 void write_msi_msg(unsigned int irq, struct msi_msg *msg)
326 struct msi_desc *entry = irq_get_msi_desc(irq);
328 __write_msi_msg(entry, msg);
331 static void free_msi_irqs(struct pci_dev *dev)
333 struct msi_desc *entry, *tmp;
335 list_for_each_entry(entry, &dev->msi_list, list) {
339 nvec = 1 << entry->msi_attrib.multiple;
340 #ifdef CONFIG_GENERIC_HARDIRQS
341 for (i = 0; i < nvec; i++)
342 BUG_ON(irq_has_action(entry->irq + i));
346 arch_teardown_msi_irqs(dev);
348 list_for_each_entry_safe(entry, tmp, &dev->msi_list, list) {
349 if (entry->msi_attrib.is_msix) {
350 if (list_is_last(&entry->list, &dev->msi_list))
351 iounmap(entry->mask_base);
355 * Its possible that we get into this path
356 * When populate_msi_sysfs fails, which means the entries
357 * were not registered with sysfs. In that case don't
360 if (entry->kobj.parent) {
361 kobject_del(&entry->kobj);
362 kobject_put(&entry->kobj);
365 list_del(&entry->list);
370 static struct msi_desc *alloc_msi_entry(struct pci_dev *dev)
372 struct msi_desc *desc = kzalloc(sizeof(*desc), GFP_KERNEL);
376 INIT_LIST_HEAD(&desc->list);
382 static void pci_intx_for_msi(struct pci_dev *dev, int enable)
384 if (!(dev->dev_flags & PCI_DEV_FLAGS_MSI_INTX_DISABLE_BUG))
385 pci_intx(dev, enable);
388 static void __pci_restore_msi_state(struct pci_dev *dev)
391 struct msi_desc *entry;
393 if (!dev->msi_enabled)
396 entry = irq_get_msi_desc(dev->irq);
398 pci_intx_for_msi(dev, 0);
399 msi_set_enable(dev, 0);
400 arch_restore_msi_irqs(dev, dev->irq);
402 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
403 msi_mask_irq(entry, msi_capable_mask(control), entry->masked);
404 control &= ~PCI_MSI_FLAGS_QSIZE;
405 control |= (entry->msi_attrib.multiple << 4) | PCI_MSI_FLAGS_ENABLE;
406 pci_write_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, control);
409 static void __pci_restore_msix_state(struct pci_dev *dev)
411 struct msi_desc *entry;
414 if (!dev->msix_enabled)
416 BUG_ON(list_empty(&dev->msi_list));
417 entry = list_first_entry(&dev->msi_list, struct msi_desc, list);
418 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
420 /* route the table */
421 pci_intx_for_msi(dev, 0);
422 control |= PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL;
423 pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control);
425 list_for_each_entry(entry, &dev->msi_list, list) {
426 arch_restore_msi_irqs(dev, entry->irq);
427 msix_mask_irq(entry, entry->masked);
430 control &= ~PCI_MSIX_FLAGS_MASKALL;
431 pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control);
434 void pci_restore_msi_state(struct pci_dev *dev)
436 __pci_restore_msi_state(dev);
437 __pci_restore_msix_state(dev);
439 EXPORT_SYMBOL_GPL(pci_restore_msi_state);
442 #define to_msi_attr(obj) container_of(obj, struct msi_attribute, attr)
443 #define to_msi_desc(obj) container_of(obj, struct msi_desc, kobj)
445 struct msi_attribute {
446 struct attribute attr;
447 ssize_t (*show)(struct msi_desc *entry, struct msi_attribute *attr,
449 ssize_t (*store)(struct msi_desc *entry, struct msi_attribute *attr,
450 const char *buf, size_t count);
453 static ssize_t show_msi_mode(struct msi_desc *entry, struct msi_attribute *atr,
456 return sprintf(buf, "%s\n", entry->msi_attrib.is_msix ? "msix" : "msi");
459 static ssize_t msi_irq_attr_show(struct kobject *kobj,
460 struct attribute *attr, char *buf)
462 struct msi_attribute *attribute = to_msi_attr(attr);
463 struct msi_desc *entry = to_msi_desc(kobj);
465 if (!attribute->show)
468 return attribute->show(entry, attribute, buf);
471 static const struct sysfs_ops msi_irq_sysfs_ops = {
472 .show = msi_irq_attr_show,
475 static struct msi_attribute mode_attribute =
476 __ATTR(mode, S_IRUGO, show_msi_mode, NULL);
479 static struct attribute *msi_irq_default_attrs[] = {
480 &mode_attribute.attr,
484 static void msi_kobj_release(struct kobject *kobj)
486 struct msi_desc *entry = to_msi_desc(kobj);
488 pci_dev_put(entry->dev);
491 static struct kobj_type msi_irq_ktype = {
492 .release = msi_kobj_release,
493 .sysfs_ops = &msi_irq_sysfs_ops,
494 .default_attrs = msi_irq_default_attrs,
497 static int populate_msi_sysfs(struct pci_dev *pdev)
499 struct msi_desc *entry;
500 struct kobject *kobj;
504 pdev->msi_kset = kset_create_and_add("msi_irqs", NULL, &pdev->dev.kobj);
508 list_for_each_entry(entry, &pdev->msi_list, list) {
510 kobj->kset = pdev->msi_kset;
512 ret = kobject_init_and_add(kobj, &msi_irq_ktype, NULL,
523 list_for_each_entry(entry, &pdev->msi_list, list) {
526 kobject_del(&entry->kobj);
527 kobject_put(&entry->kobj);
534 * msi_capability_init - configure device's MSI capability structure
535 * @dev: pointer to the pci_dev data structure of MSI device function
536 * @nvec: number of interrupts to allocate
538 * Setup the MSI capability structure of the device with the requested
539 * number of interrupts. A return value of zero indicates the successful
540 * setup of an entry with the new MSI irq. A negative return value indicates
541 * an error, and a positive return value indicates the number of interrupts
542 * which could have been allocated.
544 static int msi_capability_init(struct pci_dev *dev, int nvec)
546 struct msi_desc *entry;
551 msi_set_enable(dev, 0); /* Disable MSI during set up */
553 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &control);
554 /* MSI Entry Initialization */
555 entry = alloc_msi_entry(dev);
559 entry->msi_attrib.is_msix = 0;
560 entry->msi_attrib.is_64 = !!(control & PCI_MSI_FLAGS_64BIT);
561 entry->msi_attrib.entry_nr = 0;
562 entry->msi_attrib.maskbit = !!(control & PCI_MSI_FLAGS_MASKBIT);
563 entry->msi_attrib.default_irq = dev->irq; /* Save IOAPIC IRQ */
564 entry->msi_attrib.pos = dev->msi_cap;
566 entry->mask_pos = dev->msi_cap + (control & PCI_MSI_FLAGS_64BIT) ?
567 PCI_MSI_MASK_64 : PCI_MSI_MASK_32;
568 /* All MSIs are unmasked by default, Mask them all */
569 if (entry->msi_attrib.maskbit)
570 pci_read_config_dword(dev, entry->mask_pos, &entry->masked);
571 mask = msi_capable_mask(control);
572 msi_mask_irq(entry, mask, mask);
574 list_add_tail(&entry->list, &dev->msi_list);
576 /* Configure MSI capability structure */
577 ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSI);
579 msi_mask_irq(entry, mask, ~mask);
584 ret = populate_msi_sysfs(dev);
586 msi_mask_irq(entry, mask, ~mask);
591 /* Set MSI enabled bits */
592 pci_intx_for_msi(dev, 0);
593 msi_set_enable(dev, 1);
594 dev->msi_enabled = 1;
596 dev->irq = entry->irq;
600 static void __iomem *msix_map_region(struct pci_dev *dev, unsigned nr_entries)
602 resource_size_t phys_addr;
606 pci_read_config_dword(dev, dev->msix_cap + PCI_MSIX_TABLE,
608 bir = (u8)(table_offset & PCI_MSIX_TABLE_BIR);
609 table_offset &= PCI_MSIX_TABLE_OFFSET;
610 phys_addr = pci_resource_start(dev, bir) + table_offset;
612 return ioremap_nocache(phys_addr, nr_entries * PCI_MSIX_ENTRY_SIZE);
615 static int msix_setup_entries(struct pci_dev *dev, void __iomem *base,
616 struct msix_entry *entries, int nvec)
618 struct msi_desc *entry;
621 for (i = 0; i < nvec; i++) {
622 entry = alloc_msi_entry(dev);
628 /* No enough memory. Don't try again */
632 entry->msi_attrib.is_msix = 1;
633 entry->msi_attrib.is_64 = 1;
634 entry->msi_attrib.entry_nr = entries[i].entry;
635 entry->msi_attrib.default_irq = dev->irq;
636 entry->msi_attrib.pos = dev->msix_cap;
637 entry->mask_base = base;
639 list_add_tail(&entry->list, &dev->msi_list);
645 static void msix_program_entries(struct pci_dev *dev,
646 struct msix_entry *entries)
648 struct msi_desc *entry;
651 list_for_each_entry(entry, &dev->msi_list, list) {
652 int offset = entries[i].entry * PCI_MSIX_ENTRY_SIZE +
653 PCI_MSIX_ENTRY_VECTOR_CTRL;
655 entries[i].vector = entry->irq;
656 irq_set_msi_desc(entry->irq, entry);
657 entry->masked = readl(entry->mask_base + offset);
658 msix_mask_irq(entry, 1);
664 * msix_capability_init - configure device's MSI-X capability
665 * @dev: pointer to the pci_dev data structure of MSI-X device function
666 * @entries: pointer to an array of struct msix_entry entries
667 * @nvec: number of @entries
669 * Setup the MSI-X capability structure of device function with a
670 * single MSI-X irq. A return of zero indicates the successful setup of
671 * requested MSI-X entries with allocated irqs or non-zero for otherwise.
673 static int msix_capability_init(struct pci_dev *dev,
674 struct msix_entry *entries, int nvec)
680 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
682 /* Ensure MSI-X is disabled while it is set up */
683 control &= ~PCI_MSIX_FLAGS_ENABLE;
684 pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control);
686 /* Request & Map MSI-X table region */
687 base = msix_map_region(dev, msix_table_size(control));
691 ret = msix_setup_entries(dev, base, entries, nvec);
695 ret = arch_setup_msi_irqs(dev, nvec, PCI_CAP_ID_MSIX);
700 * Some devices require MSI-X to be enabled before we can touch the
701 * MSI-X registers. We need to mask all the vectors to prevent
702 * interrupts coming in before they're fully set up.
704 control |= PCI_MSIX_FLAGS_MASKALL | PCI_MSIX_FLAGS_ENABLE;
705 pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control);
707 msix_program_entries(dev, entries);
709 ret = populate_msi_sysfs(dev);
715 /* Set MSI-X enabled bits and unmask the function */
716 pci_intx_for_msi(dev, 0);
717 dev->msix_enabled = 1;
719 control &= ~PCI_MSIX_FLAGS_MASKALL;
720 pci_write_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, control);
727 * If we had some success, report the number of irqs
728 * we succeeded in setting up.
730 struct msi_desc *entry;
733 list_for_each_entry(entry, &dev->msi_list, list) {
747 * pci_msi_check_device - check whether MSI may be enabled on a device
748 * @dev: pointer to the pci_dev data structure of MSI device function
749 * @nvec: how many MSIs have been requested ?
750 * @type: are we checking for MSI or MSI-X ?
752 * Look at global flags, the device itself, and its parent busses
753 * to determine if MSI/-X are supported for the device. If MSI/-X is
754 * supported return 0, else return an error code.
756 static int pci_msi_check_device(struct pci_dev *dev, int nvec, int type)
761 /* MSI must be globally enabled and supported by the device */
762 if (!pci_msi_enable || !dev || dev->no_msi)
766 * You can't ask to have 0 or less MSIs configured.
768 * b) the list manipulation code assumes nvec >= 1.
774 * Any bridge which does NOT route MSI transactions from its
775 * secondary bus to its primary bus must set NO_MSI flag on
776 * the secondary pci_bus.
777 * We expect only arch-specific PCI host bus controller driver
778 * or quirks for specific PCI bridges to be setting NO_MSI.
780 for (bus = dev->bus; bus; bus = bus->parent)
781 if (bus->bus_flags & PCI_BUS_FLAGS_NO_MSI)
784 ret = arch_msi_check_device(dev, nvec, type);
792 * pci_enable_msi_block - configure device's MSI capability structure
793 * @dev: device to configure
794 * @nvec: number of interrupts to configure
796 * Allocate IRQs for a device with the MSI capability.
797 * This function returns a negative errno if an error occurs. If it
798 * is unable to allocate the number of interrupts requested, it returns
799 * the number of interrupts it might be able to allocate. If it successfully
800 * allocates at least the number of interrupts requested, it returns 0 and
801 * updates the @dev's irq member to the lowest new interrupt number; the
802 * other interrupt numbers allocated to this device are consecutive.
804 int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec)
812 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &msgctl);
813 maxvec = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1);
817 status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSI);
821 WARN_ON(!!dev->msi_enabled);
823 /* Check whether driver already requested MSI-X irqs */
824 if (dev->msix_enabled) {
825 dev_info(&dev->dev, "can't enable MSI "
826 "(MSI-X already enabled)\n");
830 status = msi_capability_init(dev, nvec);
833 EXPORT_SYMBOL(pci_enable_msi_block);
835 int pci_enable_msi_block_auto(struct pci_dev *dev, unsigned int *maxvec)
843 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &msgctl);
844 ret = 1 << ((msgctl & PCI_MSI_FLAGS_QMASK) >> 1);
851 ret = pci_enable_msi_block(dev, nvec);
858 EXPORT_SYMBOL(pci_enable_msi_block_auto);
860 void pci_msi_shutdown(struct pci_dev *dev)
862 struct msi_desc *desc;
866 if (!pci_msi_enable || !dev || !dev->msi_enabled)
869 BUG_ON(list_empty(&dev->msi_list));
870 desc = list_first_entry(&dev->msi_list, struct msi_desc, list);
872 msi_set_enable(dev, 0);
873 pci_intx_for_msi(dev, 1);
874 dev->msi_enabled = 0;
876 /* Return the device with MSI unmasked as initial states */
877 pci_read_config_word(dev, dev->msi_cap + PCI_MSI_FLAGS, &ctrl);
878 mask = msi_capable_mask(ctrl);
879 /* Keep cached state to be restored */
880 __msi_mask_irq(desc, mask, ~mask);
882 /* Restore dev->irq to its default pin-assertion irq */
883 dev->irq = desc->msi_attrib.default_irq;
886 void pci_disable_msi(struct pci_dev *dev)
888 if (!pci_msi_enable || !dev || !dev->msi_enabled)
891 pci_msi_shutdown(dev);
893 kset_unregister(dev->msi_kset);
894 dev->msi_kset = NULL;
896 EXPORT_SYMBOL(pci_disable_msi);
899 * pci_msix_table_size - return the number of device's MSI-X table entries
900 * @dev: pointer to the pci_dev data structure of MSI-X device function
902 int pci_msix_table_size(struct pci_dev *dev)
909 pci_read_config_word(dev, dev->msix_cap + PCI_MSIX_FLAGS, &control);
910 return msix_table_size(control);
914 * pci_enable_msix - configure device's MSI-X capability structure
915 * @dev: pointer to the pci_dev data structure of MSI-X device function
916 * @entries: pointer to an array of MSI-X entries
917 * @nvec: number of MSI-X irqs requested for allocation by device driver
919 * Setup the MSI-X capability structure of device function with the number
920 * of requested irqs upon its software driver call to request for
921 * MSI-X mode enabled on its hardware device function. A return of zero
922 * indicates the successful configuration of MSI-X capability structure
923 * with new allocated MSI-X irqs. A return of < 0 indicates a failure.
924 * Or a return of > 0 indicates that driver request is exceeding the number
925 * of irqs or MSI-X vectors available. Driver should use the returned value to
926 * re-send its request.
928 int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec)
930 int status, nr_entries;
933 if (!entries || !dev->msix_cap)
936 status = pci_msi_check_device(dev, nvec, PCI_CAP_ID_MSIX);
940 nr_entries = pci_msix_table_size(dev);
941 if (nvec > nr_entries)
944 /* Check for any invalid entries */
945 for (i = 0; i < nvec; i++) {
946 if (entries[i].entry >= nr_entries)
947 return -EINVAL; /* invalid entry */
948 for (j = i + 1; j < nvec; j++) {
949 if (entries[i].entry == entries[j].entry)
950 return -EINVAL; /* duplicate entry */
953 WARN_ON(!!dev->msix_enabled);
955 /* Check whether driver already requested for MSI irq */
956 if (dev->msi_enabled) {
957 dev_info(&dev->dev, "can't enable MSI-X "
958 "(MSI IRQ already assigned)\n");
961 status = msix_capability_init(dev, entries, nvec);
964 EXPORT_SYMBOL(pci_enable_msix);
966 void pci_msix_shutdown(struct pci_dev *dev)
968 struct msi_desc *entry;
970 if (!pci_msi_enable || !dev || !dev->msix_enabled)
973 /* Return the device with MSI-X masked as initial states */
974 list_for_each_entry(entry, &dev->msi_list, list) {
975 /* Keep cached states to be restored */
976 __msix_mask_irq(entry, 1);
979 msix_set_enable(dev, 0);
980 pci_intx_for_msi(dev, 1);
981 dev->msix_enabled = 0;
984 void pci_disable_msix(struct pci_dev *dev)
986 if (!pci_msi_enable || !dev || !dev->msix_enabled)
989 pci_msix_shutdown(dev);
991 kset_unregister(dev->msi_kset);
992 dev->msi_kset = NULL;
994 EXPORT_SYMBOL(pci_disable_msix);
997 * msi_remove_pci_irq_vectors - reclaim MSI(X) irqs to unused state
998 * @dev: pointer to the pci_dev data structure of MSI(X) device function
1000 * Being called during hotplug remove, from which the device function
1001 * is hot-removed. All previous assigned MSI/MSI-X irqs, if
1002 * allocated for this device function, are reclaimed to unused state,
1003 * which may be used later on.
1005 void msi_remove_pci_irq_vectors(struct pci_dev *dev)
1007 if (!pci_msi_enable || !dev)
1010 if (dev->msi_enabled || dev->msix_enabled)
1014 void pci_no_msi(void)
1020 * pci_msi_enabled - is MSI enabled?
1022 * Returns true if MSI has not been disabled by the command-line option
1025 int pci_msi_enabled(void)
1027 return pci_msi_enable;
1029 EXPORT_SYMBOL(pci_msi_enabled);
1031 void pci_msi_init_pci_dev(struct pci_dev *dev)
1033 INIT_LIST_HEAD(&dev->msi_list);
1035 /* Disable the msi hardware to avoid screaming interrupts
1036 * during boot. This is the power on reset default so
1037 * usually this should be a noop.
1039 dev->msi_cap = pci_find_capability(dev, PCI_CAP_ID_MSI);
1041 msi_set_enable(dev, 0);
1043 dev->msix_cap = pci_find_capability(dev, PCI_CAP_ID_MSIX);
1045 msix_set_enable(dev, 0);