2 * Rockchip AXI PCIe host controller driver
4 * Copyright (c) 2016 Rockchip, Inc.
6 * Author: Shawn Lin <shawn.lin@rock-chips.com>
7 * Wenrui Li <wenrui.li@rock-chips.com>
9 * Bits taken from Synopsys Designware Host controller driver and
10 * ARM PCI Host generic driver.
12 * This program is free software: you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation, either version 2 of the License, or
15 * (at your option) any later version.
18 #include <linux/clk.h>
19 #include <linux/delay.h>
20 #include <linux/gpio/consumer.h>
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
23 #include <linux/irq.h>
24 #include <linux/irqchip/chained_irq.h>
25 #include <linux/irqdomain.h>
26 #include <linux/kernel.h>
27 #include <linux/mfd/syscon.h>
28 #include <linux/of_address.h>
29 #include <linux/of_device.h>
30 #include <linux/of_pci.h>
31 #include <linux/of_platform.h>
32 #include <linux/of_irq.h>
33 #include <linux/pci.h>
34 #include <linux/pci_ids.h>
35 #include <linux/phy/phy.h>
36 #include <linux/platform_device.h>
37 #include <linux/reset.h>
38 #include <linux/regmap.h>
41 * The upper 16 bits of PCIE_CLIENT_CONFIG are a write mask for the lower 16
42 * bits. This allows atomic updates of the register without locking.
44 #define HIWORD_UPDATE(mask, val) (((mask) << 16) | (val))
45 #define HIWORD_UPDATE_BIT(val) HIWORD_UPDATE(val, val)
47 #define ENCODE_LANES(x) ((((x) >> 1) & 3) << 4)
49 #define PCIE_CLIENT_BASE 0x0
50 #define PCIE_CLIENT_CONFIG (PCIE_CLIENT_BASE + 0x00)
51 #define PCIE_CLIENT_CONF_ENABLE HIWORD_UPDATE_BIT(0x0001)
52 #define PCIE_CLIENT_LINK_TRAIN_ENABLE HIWORD_UPDATE_BIT(0x0002)
53 #define PCIE_CLIENT_ARI_ENABLE HIWORD_UPDATE_BIT(0x0008)
54 #define PCIE_CLIENT_CONF_LANE_NUM(x) HIWORD_UPDATE(0x0030, ENCODE_LANES(x))
55 #define PCIE_CLIENT_MODE_RC HIWORD_UPDATE_BIT(0x0040)
56 #define PCIE_CLIENT_GEN_SEL_2 HIWORD_UPDATE_BIT(0x0080)
57 #define PCIE_CLIENT_BASIC_STATUS1 (PCIE_CLIENT_BASE + 0x48)
58 #define PCIE_CLIENT_LINK_STATUS_UP 0x00300000
59 #define PCIE_CLIENT_LINK_STATUS_MASK 0x00300000
60 #define PCIE_CLIENT_INT_MASK (PCIE_CLIENT_BASE + 0x4c)
61 #define PCIE_CLIENT_INT_STATUS (PCIE_CLIENT_BASE + 0x50)
62 #define PCIE_CLIENT_INTR_MASK GENMASK(8, 5)
63 #define PCIE_CLIENT_INTR_SHIFT 5
64 #define PCIE_CLIENT_INT_LEGACY_DONE BIT(15)
65 #define PCIE_CLIENT_INT_MSG BIT(14)
66 #define PCIE_CLIENT_INT_HOT_RST BIT(13)
67 #define PCIE_CLIENT_INT_DPA BIT(12)
68 #define PCIE_CLIENT_INT_FATAL_ERR BIT(11)
69 #define PCIE_CLIENT_INT_NFATAL_ERR BIT(10)
70 #define PCIE_CLIENT_INT_CORR_ERR BIT(9)
71 #define PCIE_CLIENT_INT_INTD BIT(8)
72 #define PCIE_CLIENT_INT_INTC BIT(7)
73 #define PCIE_CLIENT_INT_INTB BIT(6)
74 #define PCIE_CLIENT_INT_INTA BIT(5)
75 #define PCIE_CLIENT_INT_LOCAL BIT(4)
76 #define PCIE_CLIENT_INT_UDMA BIT(3)
77 #define PCIE_CLIENT_INT_PHY BIT(2)
78 #define PCIE_CLIENT_INT_HOT_PLUG BIT(1)
79 #define PCIE_CLIENT_INT_PWR_STCG BIT(0)
81 #define PCIE_CLIENT_INT_LEGACY \
82 (PCIE_CLIENT_INT_INTA | PCIE_CLIENT_INT_INTB | \
83 PCIE_CLIENT_INT_INTC | PCIE_CLIENT_INT_INTD)
85 #define PCIE_CLIENT_INT_CLI \
86 (PCIE_CLIENT_INT_CORR_ERR | PCIE_CLIENT_INT_NFATAL_ERR | \
87 PCIE_CLIENT_INT_FATAL_ERR | PCIE_CLIENT_INT_DPA | \
88 PCIE_CLIENT_INT_HOT_RST | PCIE_CLIENT_INT_MSG | \
89 PCIE_CLIENT_INT_LEGACY_DONE | PCIE_CLIENT_INT_LEGACY | \
92 #define PCIE_CORE_CTRL_MGMT_BASE 0x900000
93 #define PCIE_CORE_CTRL (PCIE_CORE_CTRL_MGMT_BASE + 0x000)
94 #define PCIE_CORE_PL_CONF_SPEED_5G 0x00000008
95 #define PCIE_CORE_PL_CONF_SPEED_MASK 0x00000018
96 #define PCIE_CORE_PL_CONF_LANE_MASK 0x00000006
97 #define PCIE_CORE_PL_CONF_LANE_SHIFT 1
98 #define PCIE_CORE_TXCREDIT_CFG1 (PCIE_CORE_CTRL_MGMT_BASE + 0x020)
99 #define PCIE_CORE_TXCREDIT_CFG1_MUI_MASK 0xFFFF0000
100 #define PCIE_CORE_TXCREDIT_CFG1_MUI_SHIFT 16
101 #define PCIE_CORE_TXCREDIT_CFG1_MUI_ENCODE(x) \
102 (((x) >> 3) << PCIE_CORE_TXCREDIT_CFG1_MUI_SHIFT)
103 #define PCIE_CORE_INT_STATUS (PCIE_CORE_CTRL_MGMT_BASE + 0x20c)
104 #define PCIE_CORE_INT_PRFPE BIT(0)
105 #define PCIE_CORE_INT_CRFPE BIT(1)
106 #define PCIE_CORE_INT_RRPE BIT(2)
107 #define PCIE_CORE_INT_PRFO BIT(3)
108 #define PCIE_CORE_INT_CRFO BIT(4)
109 #define PCIE_CORE_INT_RT BIT(5)
110 #define PCIE_CORE_INT_RTR BIT(6)
111 #define PCIE_CORE_INT_PE BIT(7)
112 #define PCIE_CORE_INT_MTR BIT(8)
113 #define PCIE_CORE_INT_UCR BIT(9)
114 #define PCIE_CORE_INT_FCE BIT(10)
115 #define PCIE_CORE_INT_CT BIT(11)
116 #define PCIE_CORE_INT_UTC BIT(18)
117 #define PCIE_CORE_INT_MMVC BIT(19)
118 #define PCIE_CORE_INT_MASK (PCIE_CORE_CTRL_MGMT_BASE + 0x210)
119 #define PCIE_RC_BAR_CONF (PCIE_CORE_CTRL_MGMT_BASE + 0x300)
121 #define PCIE_CORE_INT \
122 (PCIE_CORE_INT_PRFPE | PCIE_CORE_INT_CRFPE | \
123 PCIE_CORE_INT_RRPE | PCIE_CORE_INT_CRFO | \
124 PCIE_CORE_INT_RT | PCIE_CORE_INT_RTR | \
125 PCIE_CORE_INT_PE | PCIE_CORE_INT_MTR | \
126 PCIE_CORE_INT_UCR | PCIE_CORE_INT_FCE | \
127 PCIE_CORE_INT_CT | PCIE_CORE_INT_UTC | \
130 #define PCIE_RC_CONFIG_BASE 0xa00000
131 #define PCIE_RC_CONFIG_VENDOR (PCIE_RC_CONFIG_BASE + 0x00)
132 #define PCIE_RC_CONFIG_RID_CCR (PCIE_RC_CONFIG_BASE + 0x08)
133 #define PCIE_RC_CONFIG_SCC_SHIFT 16
134 #define PCIE_RC_CONFIG_LCS (PCIE_RC_CONFIG_BASE + 0xd0)
135 #define PCIE_RC_CONFIG_LCS_RETRAIN_LINK BIT(5)
136 #define PCIE_RC_CONFIG_LCS_LBMIE BIT(10)
137 #define PCIE_RC_CONFIG_LCS_LABIE BIT(11)
138 #define PCIE_RC_CONFIG_LCS_LBMS BIT(30)
139 #define PCIE_RC_CONFIG_LCS_LAMS BIT(31)
140 #define PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2 (PCIE_RC_CONFIG_BASE + 0x90c)
142 #define PCIE_CORE_AXI_CONF_BASE 0xc00000
143 #define PCIE_CORE_OB_REGION_ADDR0 (PCIE_CORE_AXI_CONF_BASE + 0x0)
144 #define PCIE_CORE_OB_REGION_ADDR0_NUM_BITS 0x3f
145 #define PCIE_CORE_OB_REGION_ADDR0_LO_ADDR 0xffffff00
146 #define PCIE_CORE_OB_REGION_ADDR1 (PCIE_CORE_AXI_CONF_BASE + 0x4)
147 #define PCIE_CORE_OB_REGION_DESC0 (PCIE_CORE_AXI_CONF_BASE + 0x8)
148 #define PCIE_CORE_OB_REGION_DESC1 (PCIE_CORE_AXI_CONF_BASE + 0xc)
150 #define PCIE_CORE_AXI_INBOUND_BASE 0xc00800
151 #define PCIE_RP_IB_ADDR0 (PCIE_CORE_AXI_INBOUND_BASE + 0x0)
152 #define PCIE_CORE_IB_REGION_ADDR0_NUM_BITS 0x3f
153 #define PCIE_CORE_IB_REGION_ADDR0_LO_ADDR 0xffffff00
154 #define PCIE_RP_IB_ADDR1 (PCIE_CORE_AXI_INBOUND_BASE + 0x4)
156 /* Size of one AXI Region (not Region 0) */
157 #define AXI_REGION_SIZE BIT(20)
158 /* Size of Region 0, equal to sum of sizes of other regions */
159 #define AXI_REGION_0_SIZE (32 * (0x1 << 20))
160 #define OB_REG_SIZE_SHIFT 5
161 #define IB_ROOT_PORT_REG_SIZE_SHIFT 3
162 #define AXI_WRAPPER_IO_WRITE 0x6
163 #define AXI_WRAPPER_MEM_WRITE 0x2
165 #define MAX_AXI_IB_ROOTPORT_REGION_NUM 3
166 #define MIN_AXI_ADDR_BITS_PASSED 8
167 #define ROCKCHIP_VENDOR_ID 0x1d87
168 #define PCIE_ECAM_BUS(x) (((x) & 0xff) << 20)
169 #define PCIE_ECAM_DEV(x) (((x) & 0x1f) << 15)
170 #define PCIE_ECAM_FUNC(x) (((x) & 0x7) << 12)
171 #define PCIE_ECAM_REG(x) (((x) & 0xfff) << 0)
172 #define PCIE_ECAM_ADDR(bus, dev, func, reg) \
173 (PCIE_ECAM_BUS(bus) | PCIE_ECAM_DEV(dev) | \
174 PCIE_ECAM_FUNC(func) | PCIE_ECAM_REG(reg))
176 #define RC_REGION_0_ADDR_TRANS_H 0x00000000
177 #define RC_REGION_0_ADDR_TRANS_L 0x00000000
178 #define RC_REGION_0_PASS_BITS (25 - 1)
179 #define MAX_AXI_WRAPPER_REGION_NUM 33
181 struct rockchip_pcie {
182 void __iomem *reg_base; /* DT axi-base */
183 void __iomem *apb_base; /* DT apb-base */
185 struct reset_control *core_rst;
186 struct reset_control *mgmt_rst;
187 struct reset_control *mgmt_sticky_rst;
188 struct reset_control *pipe_rst;
189 struct clk *aclk_pcie;
190 struct clk *aclk_perf_pcie;
191 struct clk *hclk_pcie;
192 struct clk *clk_pcie_pm;
193 struct regulator *vpcie3v3; /* 3.3V power supply */
194 struct regulator *vpcie1v8; /* 1.8V power supply */
195 struct regulator *vpcie0v9; /* 0.9V power supply */
196 struct gpio_desc *ep_gpio;
200 struct irq_domain *irq_domain;
203 static u32 rockchip_pcie_read(struct rockchip_pcie *rockchip, u32 reg)
205 return readl(rockchip->apb_base + reg);
208 static void rockchip_pcie_write(struct rockchip_pcie *rockchip, u32 val,
211 writel(val, rockchip->apb_base + reg);
214 static void rockchip_pcie_enable_bw_int(struct rockchip_pcie *rockchip)
218 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS);
219 status |= (PCIE_RC_CONFIG_LCS_LBMIE | PCIE_RC_CONFIG_LCS_LABIE);
220 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS);
223 static void rockchip_pcie_clr_bw_int(struct rockchip_pcie *rockchip)
227 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS);
228 status |= (PCIE_RC_CONFIG_LCS_LBMS | PCIE_RC_CONFIG_LCS_LAMS);
229 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS);
232 static void rockchip_pcie_update_txcredit_mui(struct rockchip_pcie *rockchip)
236 /* Update Tx credit maximum update interval */
237 val = rockchip_pcie_read(rockchip, PCIE_CORE_TXCREDIT_CFG1);
238 val &= ~PCIE_CORE_TXCREDIT_CFG1_MUI_MASK;
239 val |= PCIE_CORE_TXCREDIT_CFG1_MUI_ENCODE(24000); /* ns */
240 rockchip_pcie_write(rockchip, val, PCIE_CORE_TXCREDIT_CFG1);
243 static int rockchip_pcie_valid_device(struct rockchip_pcie *rockchip,
244 struct pci_bus *bus, int dev)
246 /* access only one slot on each root port */
247 if (bus->number == rockchip->root_bus_nr && dev > 0)
251 * do not read more than one device on the bus directly attached
252 * to RC's downstream side.
254 if (bus->primary == rockchip->root_bus_nr && dev > 0)
260 static int rockchip_pcie_rd_own_conf(struct rockchip_pcie *rockchip,
261 int where, int size, u32 *val)
263 void __iomem *addr = rockchip->apb_base + PCIE_RC_CONFIG_BASE + where;
265 if (!IS_ALIGNED((uintptr_t)addr, size)) {
267 return PCIBIOS_BAD_REGISTER_NUMBER;
272 } else if (size == 2) {
274 } else if (size == 1) {
278 return PCIBIOS_BAD_REGISTER_NUMBER;
280 return PCIBIOS_SUCCESSFUL;
283 static int rockchip_pcie_wr_own_conf(struct rockchip_pcie *rockchip,
284 int where, int size, u32 val)
286 u32 mask, tmp, offset;
288 offset = where & ~0x3;
291 writel(val, rockchip->apb_base + PCIE_RC_CONFIG_BASE + offset);
292 return PCIBIOS_SUCCESSFUL;
295 mask = ~(((1 << (size * 8)) - 1) << ((where & 0x3) * 8));
298 * N.B. This read/modify/write isn't safe in general because it can
299 * corrupt RW1C bits in adjacent registers. But the hardware
300 * doesn't support smaller writes.
302 tmp = readl(rockchip->apb_base + PCIE_RC_CONFIG_BASE + offset) & mask;
303 tmp |= val << ((where & 0x3) * 8);
304 writel(tmp, rockchip->apb_base + PCIE_RC_CONFIG_BASE + offset);
306 return PCIBIOS_SUCCESSFUL;
309 static int rockchip_pcie_rd_other_conf(struct rockchip_pcie *rockchip,
310 struct pci_bus *bus, u32 devfn,
311 int where, int size, u32 *val)
315 busdev = PCIE_ECAM_ADDR(bus->number, PCI_SLOT(devfn),
316 PCI_FUNC(devfn), where);
318 if (!IS_ALIGNED(busdev, size)) {
320 return PCIBIOS_BAD_REGISTER_NUMBER;
324 *val = readl(rockchip->reg_base + busdev);
325 } else if (size == 2) {
326 *val = readw(rockchip->reg_base + busdev);
327 } else if (size == 1) {
328 *val = readb(rockchip->reg_base + busdev);
331 return PCIBIOS_BAD_REGISTER_NUMBER;
333 return PCIBIOS_SUCCESSFUL;
336 static int rockchip_pcie_wr_other_conf(struct rockchip_pcie *rockchip,
337 struct pci_bus *bus, u32 devfn,
338 int where, int size, u32 val)
342 busdev = PCIE_ECAM_ADDR(bus->number, PCI_SLOT(devfn),
343 PCI_FUNC(devfn), where);
344 if (!IS_ALIGNED(busdev, size))
345 return PCIBIOS_BAD_REGISTER_NUMBER;
348 writel(val, rockchip->reg_base + busdev);
350 writew(val, rockchip->reg_base + busdev);
352 writeb(val, rockchip->reg_base + busdev);
354 return PCIBIOS_BAD_REGISTER_NUMBER;
356 return PCIBIOS_SUCCESSFUL;
359 static int rockchip_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
362 struct rockchip_pcie *rockchip = bus->sysdata;
364 if (!rockchip_pcie_valid_device(rockchip, bus, PCI_SLOT(devfn))) {
366 return PCIBIOS_DEVICE_NOT_FOUND;
369 if (bus->number == rockchip->root_bus_nr)
370 return rockchip_pcie_rd_own_conf(rockchip, where, size, val);
372 return rockchip_pcie_rd_other_conf(rockchip, bus, devfn, where, size, val);
375 static int rockchip_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
376 int where, int size, u32 val)
378 struct rockchip_pcie *rockchip = bus->sysdata;
380 if (!rockchip_pcie_valid_device(rockchip, bus, PCI_SLOT(devfn)))
381 return PCIBIOS_DEVICE_NOT_FOUND;
383 if (bus->number == rockchip->root_bus_nr)
384 return rockchip_pcie_wr_own_conf(rockchip, where, size, val);
386 return rockchip_pcie_wr_other_conf(rockchip, bus, devfn, where, size, val);
389 static struct pci_ops rockchip_pcie_ops = {
390 .read = rockchip_pcie_rd_conf,
391 .write = rockchip_pcie_wr_conf,
395 * rockchip_pcie_init_port - Initialize hardware
396 * @rockchip: PCIe port information
398 static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
400 struct device *dev = rockchip->dev;
403 unsigned long timeout;
405 gpiod_set_value(rockchip->ep_gpio, 0);
407 err = phy_init(rockchip->phy);
409 dev_err(dev, "fail to init phy, err %d\n", err);
413 err = reset_control_assert(rockchip->core_rst);
415 dev_err(dev, "assert core_rst err %d\n", err);
419 err = reset_control_assert(rockchip->mgmt_rst);
421 dev_err(dev, "assert mgmt_rst err %d\n", err);
425 err = reset_control_assert(rockchip->mgmt_sticky_rst);
427 dev_err(dev, "assert mgmt_sticky_rst err %d\n", err);
431 err = reset_control_assert(rockchip->pipe_rst);
433 dev_err(dev, "assert pipe_rst err %d\n", err);
437 rockchip_pcie_write(rockchip,
438 PCIE_CLIENT_CONF_ENABLE |
439 PCIE_CLIENT_LINK_TRAIN_ENABLE |
440 PCIE_CLIENT_ARI_ENABLE |
441 PCIE_CLIENT_CONF_LANE_NUM(rockchip->lanes) |
442 PCIE_CLIENT_MODE_RC |
443 PCIE_CLIENT_GEN_SEL_2,
446 err = phy_power_on(rockchip->phy);
448 dev_err(dev, "fail to power on phy, err %d\n", err);
453 * Please don't reorder the deassert sequence of the following
456 err = reset_control_deassert(rockchip->mgmt_sticky_rst);
458 dev_err(dev, "deassert mgmt_sticky_rst err %d\n", err);
462 err = reset_control_deassert(rockchip->core_rst);
464 dev_err(dev, "deassert core_rst err %d\n", err);
468 err = reset_control_deassert(rockchip->mgmt_rst);
470 dev_err(dev, "deassert mgmt_rst err %d\n", err);
474 err = reset_control_deassert(rockchip->pipe_rst);
476 dev_err(dev, "deassert pipe_rst err %d\n", err);
481 * We need to read/write PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2 before
482 * enabling ASPM. Otherwise L1PwrOnSc and L1PwrOnVal isn't
483 * reliable and enabling ASPM doesn't work. This is a controller
484 * bug we need to work around.
486 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2);
487 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2);
489 /* Enable Gen1 training */
490 rockchip_pcie_write(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE,
493 gpiod_set_value(rockchip->ep_gpio, 1);
495 /* 500ms timeout value should be enough for Gen1/2 training */
496 timeout = jiffies + msecs_to_jiffies(500);
499 status = rockchip_pcie_read(rockchip,
500 PCIE_CLIENT_BASIC_STATUS1);
501 if ((status & PCIE_CLIENT_LINK_STATUS_MASK) ==
502 PCIE_CLIENT_LINK_STATUS_UP) {
503 dev_dbg(dev, "PCIe link training gen1 pass!\n");
507 if (time_after(jiffies, timeout)) {
508 dev_err(dev, "PCIe link training gen1 timeout!\n");
516 * Enable retrain for gen2. This should be configured only after
519 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS);
520 status |= PCIE_RC_CONFIG_LCS_RETRAIN_LINK;
521 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS);
523 timeout = jiffies + msecs_to_jiffies(500);
525 status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL);
526 if ((status & PCIE_CORE_PL_CONF_SPEED_MASK) ==
527 PCIE_CORE_PL_CONF_SPEED_5G) {
528 dev_dbg(dev, "PCIe link training gen2 pass!\n");
532 if (time_after(jiffies, timeout)) {
533 dev_dbg(dev, "PCIe link training gen2 timeout, fall back to gen1!\n");
540 /* Check the final link width from negotiated lane counter from MGMT */
541 status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL);
542 status = 0x1 << ((status & PCIE_CORE_PL_CONF_LANE_MASK) >>
543 PCIE_CORE_PL_CONF_LANE_MASK);
544 dev_dbg(dev, "current link width is x%d\n", status);
546 rockchip_pcie_write(rockchip, ROCKCHIP_VENDOR_ID,
547 PCIE_RC_CONFIG_VENDOR);
548 rockchip_pcie_write(rockchip,
549 PCI_CLASS_BRIDGE_PCI << PCIE_RC_CONFIG_SCC_SHIFT,
550 PCIE_RC_CONFIG_RID_CCR);
551 rockchip_pcie_write(rockchip, 0x0, PCIE_RC_BAR_CONF);
553 rockchip_pcie_write(rockchip,
554 (RC_REGION_0_ADDR_TRANS_L + RC_REGION_0_PASS_BITS),
555 PCIE_CORE_OB_REGION_ADDR0);
556 rockchip_pcie_write(rockchip, RC_REGION_0_ADDR_TRANS_H,
557 PCIE_CORE_OB_REGION_ADDR1);
558 rockchip_pcie_write(rockchip, 0x0080000a, PCIE_CORE_OB_REGION_DESC0);
559 rockchip_pcie_write(rockchip, 0x0, PCIE_CORE_OB_REGION_DESC1);
564 static irqreturn_t rockchip_pcie_subsys_irq_handler(int irq, void *arg)
566 struct rockchip_pcie *rockchip = arg;
567 struct device *dev = rockchip->dev;
571 reg = rockchip_pcie_read(rockchip, PCIE_CLIENT_INT_STATUS);
572 if (reg & PCIE_CLIENT_INT_LOCAL) {
573 dev_dbg(dev, "local interrupt received\n");
574 sub_reg = rockchip_pcie_read(rockchip, PCIE_CORE_INT_STATUS);
575 if (sub_reg & PCIE_CORE_INT_PRFPE)
576 dev_dbg(dev, "parity error detected while reading from the PNP receive FIFO RAM\n");
578 if (sub_reg & PCIE_CORE_INT_CRFPE)
579 dev_dbg(dev, "parity error detected while reading from the Completion Receive FIFO RAM\n");
581 if (sub_reg & PCIE_CORE_INT_RRPE)
582 dev_dbg(dev, "parity error detected while reading from replay buffer RAM\n");
584 if (sub_reg & PCIE_CORE_INT_PRFO)
585 dev_dbg(dev, "overflow occurred in the PNP receive FIFO\n");
587 if (sub_reg & PCIE_CORE_INT_CRFO)
588 dev_dbg(dev, "overflow occurred in the completion receive FIFO\n");
590 if (sub_reg & PCIE_CORE_INT_RT)
591 dev_dbg(dev, "replay timer timed out\n");
593 if (sub_reg & PCIE_CORE_INT_RTR)
594 dev_dbg(dev, "replay timer rolled over after 4 transmissions of the same TLP\n");
596 if (sub_reg & PCIE_CORE_INT_PE)
597 dev_dbg(dev, "phy error detected on receive side\n");
599 if (sub_reg & PCIE_CORE_INT_MTR)
600 dev_dbg(dev, "malformed TLP received from the link\n");
602 if (sub_reg & PCIE_CORE_INT_UCR)
603 dev_dbg(dev, "malformed TLP received from the link\n");
605 if (sub_reg & PCIE_CORE_INT_FCE)
606 dev_dbg(dev, "an error was observed in the flow control advertisements from the other side\n");
608 if (sub_reg & PCIE_CORE_INT_CT)
609 dev_dbg(dev, "a request timed out waiting for completion\n");
611 if (sub_reg & PCIE_CORE_INT_UTC)
612 dev_dbg(dev, "unmapped TC error\n");
614 if (sub_reg & PCIE_CORE_INT_MMVC)
615 dev_dbg(dev, "MSI mask register changes\n");
617 rockchip_pcie_write(rockchip, sub_reg, PCIE_CORE_INT_STATUS);
618 } else if (reg & PCIE_CLIENT_INT_PHY) {
619 dev_dbg(dev, "phy link changes\n");
620 rockchip_pcie_update_txcredit_mui(rockchip);
621 rockchip_pcie_clr_bw_int(rockchip);
624 rockchip_pcie_write(rockchip, reg & PCIE_CLIENT_INT_LOCAL,
625 PCIE_CLIENT_INT_STATUS);
630 static irqreturn_t rockchip_pcie_client_irq_handler(int irq, void *arg)
632 struct rockchip_pcie *rockchip = arg;
633 struct device *dev = rockchip->dev;
636 reg = rockchip_pcie_read(rockchip, PCIE_CLIENT_INT_STATUS);
637 if (reg & PCIE_CLIENT_INT_LEGACY_DONE)
638 dev_dbg(dev, "legacy done interrupt received\n");
640 if (reg & PCIE_CLIENT_INT_MSG)
641 dev_dbg(dev, "message done interrupt received\n");
643 if (reg & PCIE_CLIENT_INT_HOT_RST)
644 dev_dbg(dev, "hot reset interrupt received\n");
646 if (reg & PCIE_CLIENT_INT_DPA)
647 dev_dbg(dev, "dpa interrupt received\n");
649 if (reg & PCIE_CLIENT_INT_FATAL_ERR)
650 dev_dbg(dev, "fatal error interrupt received\n");
652 if (reg & PCIE_CLIENT_INT_NFATAL_ERR)
653 dev_dbg(dev, "no fatal error interrupt received\n");
655 if (reg & PCIE_CLIENT_INT_CORR_ERR)
656 dev_dbg(dev, "correctable error interrupt received\n");
658 if (reg & PCIE_CLIENT_INT_PHY)
659 dev_dbg(dev, "phy interrupt received\n");
661 rockchip_pcie_write(rockchip, reg & (PCIE_CLIENT_INT_LEGACY_DONE |
662 PCIE_CLIENT_INT_MSG | PCIE_CLIENT_INT_HOT_RST |
663 PCIE_CLIENT_INT_DPA | PCIE_CLIENT_INT_FATAL_ERR |
664 PCIE_CLIENT_INT_NFATAL_ERR |
665 PCIE_CLIENT_INT_CORR_ERR |
666 PCIE_CLIENT_INT_PHY),
667 PCIE_CLIENT_INT_STATUS);
672 static void rockchip_pcie_legacy_int_handler(struct irq_desc *desc)
674 struct irq_chip *chip = irq_desc_get_chip(desc);
675 struct rockchip_pcie *rockchip = irq_desc_get_handler_data(desc);
676 struct device *dev = rockchip->dev;
681 chained_irq_enter(chip, desc);
683 reg = rockchip_pcie_read(rockchip, PCIE_CLIENT_INT_STATUS);
684 reg = (reg & PCIE_CLIENT_INTR_MASK) >> PCIE_CLIENT_INTR_SHIFT;
687 hwirq = ffs(reg) - 1;
690 virq = irq_find_mapping(rockchip->irq_domain, hwirq);
692 generic_handle_irq(virq);
694 dev_err(dev, "unexpected IRQ, INT%d\n", hwirq);
697 chained_irq_exit(chip, desc);
702 * rockchip_pcie_parse_dt - Parse Device Tree
703 * @rockchip: PCIe port information
705 * Return: '0' on success and error value on failure
707 static int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip)
709 struct device *dev = rockchip->dev;
710 struct platform_device *pdev = to_platform_device(dev);
711 struct device_node *node = dev->of_node;
712 struct resource *regs;
716 regs = platform_get_resource_byname(pdev,
719 rockchip->reg_base = devm_ioremap_resource(dev, regs);
720 if (IS_ERR(rockchip->reg_base))
721 return PTR_ERR(rockchip->reg_base);
723 regs = platform_get_resource_byname(pdev,
726 rockchip->apb_base = devm_ioremap_resource(dev, regs);
727 if (IS_ERR(rockchip->apb_base))
728 return PTR_ERR(rockchip->apb_base);
730 rockchip->phy = devm_phy_get(dev, "pcie-phy");
731 if (IS_ERR(rockchip->phy)) {
732 if (PTR_ERR(rockchip->phy) != -EPROBE_DEFER)
733 dev_err(dev, "missing phy\n");
734 return PTR_ERR(rockchip->phy);
738 err = of_property_read_u32(node, "num-lanes", &rockchip->lanes);
739 if (!err && (rockchip->lanes == 0 ||
740 rockchip->lanes == 3 ||
741 rockchip->lanes > 4)) {
742 dev_warn(dev, "invalid num-lanes, default to use one lane\n");
746 rockchip->core_rst = devm_reset_control_get(dev, "core");
747 if (IS_ERR(rockchip->core_rst)) {
748 if (PTR_ERR(rockchip->core_rst) != -EPROBE_DEFER)
749 dev_err(dev, "missing core reset property in node\n");
750 return PTR_ERR(rockchip->core_rst);
753 rockchip->mgmt_rst = devm_reset_control_get(dev, "mgmt");
754 if (IS_ERR(rockchip->mgmt_rst)) {
755 if (PTR_ERR(rockchip->mgmt_rst) != -EPROBE_DEFER)
756 dev_err(dev, "missing mgmt reset property in node\n");
757 return PTR_ERR(rockchip->mgmt_rst);
760 rockchip->mgmt_sticky_rst = devm_reset_control_get(dev, "mgmt-sticky");
761 if (IS_ERR(rockchip->mgmt_sticky_rst)) {
762 if (PTR_ERR(rockchip->mgmt_sticky_rst) != -EPROBE_DEFER)
763 dev_err(dev, "missing mgmt-sticky reset property in node\n");
764 return PTR_ERR(rockchip->mgmt_sticky_rst);
767 rockchip->pipe_rst = devm_reset_control_get(dev, "pipe");
768 if (IS_ERR(rockchip->pipe_rst)) {
769 if (PTR_ERR(rockchip->pipe_rst) != -EPROBE_DEFER)
770 dev_err(dev, "missing pipe reset property in node\n");
771 return PTR_ERR(rockchip->pipe_rst);
774 rockchip->ep_gpio = devm_gpiod_get(dev, "ep", GPIOD_OUT_HIGH);
775 if (IS_ERR(rockchip->ep_gpio)) {
776 dev_err(dev, "missing ep-gpios property in node\n");
777 return PTR_ERR(rockchip->ep_gpio);
780 rockchip->aclk_pcie = devm_clk_get(dev, "aclk");
781 if (IS_ERR(rockchip->aclk_pcie)) {
782 dev_err(dev, "aclk clock not found\n");
783 return PTR_ERR(rockchip->aclk_pcie);
786 rockchip->aclk_perf_pcie = devm_clk_get(dev, "aclk-perf");
787 if (IS_ERR(rockchip->aclk_perf_pcie)) {
788 dev_err(dev, "aclk_perf clock not found\n");
789 return PTR_ERR(rockchip->aclk_perf_pcie);
792 rockchip->hclk_pcie = devm_clk_get(dev, "hclk");
793 if (IS_ERR(rockchip->hclk_pcie)) {
794 dev_err(dev, "hclk clock not found\n");
795 return PTR_ERR(rockchip->hclk_pcie);
798 rockchip->clk_pcie_pm = devm_clk_get(dev, "pm");
799 if (IS_ERR(rockchip->clk_pcie_pm)) {
800 dev_err(dev, "pm clock not found\n");
801 return PTR_ERR(rockchip->clk_pcie_pm);
804 irq = platform_get_irq_byname(pdev, "sys");
806 dev_err(dev, "missing sys IRQ resource\n");
810 err = devm_request_irq(dev, irq, rockchip_pcie_subsys_irq_handler,
811 IRQF_SHARED, "pcie-sys", rockchip);
813 dev_err(dev, "failed to request PCIe subsystem IRQ\n");
817 irq = platform_get_irq_byname(pdev, "legacy");
819 dev_err(dev, "missing legacy IRQ resource\n");
823 irq_set_chained_handler_and_data(irq,
824 rockchip_pcie_legacy_int_handler,
827 irq = platform_get_irq_byname(pdev, "client");
829 dev_err(dev, "missing client IRQ resource\n");
833 err = devm_request_irq(dev, irq, rockchip_pcie_client_irq_handler,
834 IRQF_SHARED, "pcie-client", rockchip);
836 dev_err(dev, "failed to request PCIe client IRQ\n");
840 rockchip->vpcie3v3 = devm_regulator_get_optional(dev, "vpcie3v3");
841 if (IS_ERR(rockchip->vpcie3v3)) {
842 if (PTR_ERR(rockchip->vpcie3v3) == -EPROBE_DEFER)
843 return -EPROBE_DEFER;
844 dev_info(dev, "no vpcie3v3 regulator found\n");
847 rockchip->vpcie1v8 = devm_regulator_get_optional(dev, "vpcie1v8");
848 if (IS_ERR(rockchip->vpcie1v8)) {
849 if (PTR_ERR(rockchip->vpcie1v8) == -EPROBE_DEFER)
850 return -EPROBE_DEFER;
851 dev_info(dev, "no vpcie1v8 regulator found\n");
854 rockchip->vpcie0v9 = devm_regulator_get_optional(dev, "vpcie0v9");
855 if (IS_ERR(rockchip->vpcie0v9)) {
856 if (PTR_ERR(rockchip->vpcie0v9) == -EPROBE_DEFER)
857 return -EPROBE_DEFER;
858 dev_info(dev, "no vpcie0v9 regulator found\n");
864 static int rockchip_pcie_set_vpcie(struct rockchip_pcie *rockchip)
866 struct device *dev = rockchip->dev;
869 if (!IS_ERR(rockchip->vpcie3v3)) {
870 err = regulator_enable(rockchip->vpcie3v3);
872 dev_err(dev, "fail to enable vpcie3v3 regulator\n");
877 if (!IS_ERR(rockchip->vpcie1v8)) {
878 err = regulator_enable(rockchip->vpcie1v8);
880 dev_err(dev, "fail to enable vpcie1v8 regulator\n");
881 goto err_disable_3v3;
885 if (!IS_ERR(rockchip->vpcie0v9)) {
886 err = regulator_enable(rockchip->vpcie0v9);
888 dev_err(dev, "fail to enable vpcie0v9 regulator\n");
889 goto err_disable_1v8;
896 if (!IS_ERR(rockchip->vpcie1v8))
897 regulator_disable(rockchip->vpcie1v8);
899 if (!IS_ERR(rockchip->vpcie3v3))
900 regulator_disable(rockchip->vpcie3v3);
905 static void rockchip_pcie_enable_interrupts(struct rockchip_pcie *rockchip)
907 rockchip_pcie_write(rockchip, (PCIE_CLIENT_INT_CLI << 16) &
908 (~PCIE_CLIENT_INT_CLI), PCIE_CLIENT_INT_MASK);
909 rockchip_pcie_write(rockchip, (u32)(~PCIE_CORE_INT),
912 rockchip_pcie_enable_bw_int(rockchip);
915 static int rockchip_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
916 irq_hw_number_t hwirq)
918 irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
919 irq_set_chip_data(irq, domain->host_data);
924 static const struct irq_domain_ops intx_domain_ops = {
925 .map = rockchip_pcie_intx_map,
928 static int rockchip_pcie_init_irq_domain(struct rockchip_pcie *rockchip)
930 struct device *dev = rockchip->dev;
931 struct device_node *intc = of_get_next_child(dev->of_node, NULL);
934 dev_err(dev, "missing child interrupt-controller node\n");
938 rockchip->irq_domain = irq_domain_add_linear(intc, 4,
939 &intx_domain_ops, rockchip);
940 if (!rockchip->irq_domain) {
941 dev_err(dev, "failed to get a INTx IRQ domain\n");
948 static int rockchip_pcie_prog_ob_atu(struct rockchip_pcie *rockchip,
949 int region_no, int type, u8 num_pass_bits,
950 u32 lower_addr, u32 upper_addr)
957 if (region_no >= MAX_AXI_WRAPPER_REGION_NUM)
959 if (num_pass_bits + 1 < 8)
961 if (num_pass_bits > 63)
963 if (region_no == 0) {
964 if (AXI_REGION_0_SIZE < (2ULL << num_pass_bits))
967 if (region_no != 0) {
968 if (AXI_REGION_SIZE < (2ULL << num_pass_bits))
972 aw_offset = (region_no << OB_REG_SIZE_SHIFT);
974 ob_addr_0 = num_pass_bits & PCIE_CORE_OB_REGION_ADDR0_NUM_BITS;
975 ob_addr_0 |= lower_addr & PCIE_CORE_OB_REGION_ADDR0_LO_ADDR;
976 ob_addr_1 = upper_addr;
977 ob_desc_0 = (1 << 23 | type);
979 rockchip_pcie_write(rockchip, ob_addr_0,
980 PCIE_CORE_OB_REGION_ADDR0 + aw_offset);
981 rockchip_pcie_write(rockchip, ob_addr_1,
982 PCIE_CORE_OB_REGION_ADDR1 + aw_offset);
983 rockchip_pcie_write(rockchip, ob_desc_0,
984 PCIE_CORE_OB_REGION_DESC0 + aw_offset);
985 rockchip_pcie_write(rockchip, 0,
986 PCIE_CORE_OB_REGION_DESC1 + aw_offset);
991 static int rockchip_pcie_prog_ib_atu(struct rockchip_pcie *rockchip,
992 int region_no, u8 num_pass_bits,
993 u32 lower_addr, u32 upper_addr)
999 if (region_no > MAX_AXI_IB_ROOTPORT_REGION_NUM)
1001 if (num_pass_bits + 1 < MIN_AXI_ADDR_BITS_PASSED)
1003 if (num_pass_bits > 63)
1006 aw_offset = (region_no << IB_ROOT_PORT_REG_SIZE_SHIFT);
1008 ib_addr_0 = num_pass_bits & PCIE_CORE_IB_REGION_ADDR0_NUM_BITS;
1009 ib_addr_0 |= (lower_addr << 8) & PCIE_CORE_IB_REGION_ADDR0_LO_ADDR;
1010 ib_addr_1 = upper_addr;
1012 rockchip_pcie_write(rockchip, ib_addr_0, PCIE_RP_IB_ADDR0 + aw_offset);
1013 rockchip_pcie_write(rockchip, ib_addr_1, PCIE_RP_IB_ADDR1 + aw_offset);
1018 static int rockchip_pcie_probe(struct platform_device *pdev)
1020 struct rockchip_pcie *rockchip;
1021 struct device *dev = &pdev->dev;
1022 struct pci_bus *bus, *child;
1023 struct resource_entry *win;
1024 resource_size_t io_base;
1025 struct resource *mem;
1026 struct resource *io;
1027 phys_addr_t io_bus_addr = 0;
1029 phys_addr_t mem_bus_addr = 0;
1040 rockchip = devm_kzalloc(dev, sizeof(*rockchip), GFP_KERNEL);
1044 rockchip->dev = dev;
1046 err = rockchip_pcie_parse_dt(rockchip);
1050 err = clk_prepare_enable(rockchip->aclk_pcie);
1052 dev_err(dev, "unable to enable aclk_pcie clock\n");
1056 err = clk_prepare_enable(rockchip->aclk_perf_pcie);
1058 dev_err(dev, "unable to enable aclk_perf_pcie clock\n");
1059 goto err_aclk_perf_pcie;
1062 err = clk_prepare_enable(rockchip->hclk_pcie);
1064 dev_err(dev, "unable to enable hclk_pcie clock\n");
1068 err = clk_prepare_enable(rockchip->clk_pcie_pm);
1070 dev_err(dev, "unable to enable hclk_pcie clock\n");
1074 err = rockchip_pcie_set_vpcie(rockchip);
1076 dev_err(dev, "failed to set vpcie regulator\n");
1080 err = rockchip_pcie_init_port(rockchip);
1084 platform_set_drvdata(pdev, rockchip);
1086 rockchip_pcie_enable_interrupts(rockchip);
1088 err = rockchip_pcie_init_irq_domain(rockchip);
1092 err = of_pci_get_host_bridge_resources(dev->of_node, 0, 0xff,
1097 err = devm_request_pci_bus_resources(dev, &res);
1101 /* Get the I/O and memory ranges from DT */
1103 resource_list_for_each_entry(win, &res) {
1104 switch (resource_type(win->res)) {
1108 io_size = resource_size(io);
1109 io_bus_addr = io->start - win->offset;
1110 err = pci_remap_iospace(io, io_base);
1112 dev_warn(dev, "error %d: failed to map resource %pR\n",
1117 case IORESOURCE_MEM:
1120 mem_size = resource_size(mem);
1121 mem_bus_addr = mem->start - win->offset;
1123 case IORESOURCE_BUS:
1124 rockchip->root_bus_nr = win->res->start;
1132 for (reg_no = 0; reg_no < (mem_size >> 20); reg_no++) {
1133 err = rockchip_pcie_prog_ob_atu(rockchip, reg_no + 1,
1134 AXI_WRAPPER_MEM_WRITE,
1140 dev_err(dev, "program RC mem outbound ATU failed\n");
1146 err = rockchip_pcie_prog_ib_atu(rockchip, 2, 32 - 1, 0x0, 0);
1148 dev_err(dev, "program RC mem inbound ATU failed\n");
1152 offset = mem_size >> 20;
1155 for (reg_no = 0; reg_no < (io_size >> 20); reg_no++) {
1156 err = rockchip_pcie_prog_ob_atu(rockchip,
1157 reg_no + 1 + offset,
1158 AXI_WRAPPER_IO_WRITE,
1164 dev_err(dev, "program RC io outbound ATU failed\n");
1170 bus = pci_scan_root_bus(&pdev->dev, 0, &rockchip_pcie_ops, rockchip, &res);
1176 pci_bus_size_bridges(bus);
1177 pci_bus_assign_resources(bus);
1178 list_for_each_entry(child, &bus->children, node)
1179 pcie_bus_configure_settings(child);
1181 pci_bus_add_devices(bus);
1183 dev_warn(dev, "only 32-bit config accesses supported; smaller writes may corrupt adjacent RW1C fields\n");
1188 if (!IS_ERR(rockchip->vpcie3v3))
1189 regulator_disable(rockchip->vpcie3v3);
1190 if (!IS_ERR(rockchip->vpcie1v8))
1191 regulator_disable(rockchip->vpcie1v8);
1192 if (!IS_ERR(rockchip->vpcie0v9))
1193 regulator_disable(rockchip->vpcie0v9);
1195 clk_disable_unprepare(rockchip->clk_pcie_pm);
1197 clk_disable_unprepare(rockchip->hclk_pcie);
1199 clk_disable_unprepare(rockchip->aclk_perf_pcie);
1201 clk_disable_unprepare(rockchip->aclk_pcie);
1206 static const struct of_device_id rockchip_pcie_of_match[] = {
1207 { .compatible = "rockchip,rk3399-pcie", },
1211 static struct platform_driver rockchip_pcie_driver = {
1213 .name = "rockchip-pcie",
1214 .of_match_table = rockchip_pcie_of_match,
1216 .probe = rockchip_pcie_probe,
1219 builtin_platform_driver(rockchip_pcie_driver);