2 * Rockchip AXI PCIe host controller driver
4 * Copyright (c) 2016 Rockchip, Inc.
6 * Author: Shawn Lin <shawn.lin@rock-chips.com>
7 * Wenrui Li <wenrui.li@rock-chips.com>
9 * Bits taken from Synopsys Designware Host controller driver and
10 * ARM PCI Host generic driver.
12 * This program is free software: you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation, either version 2 of the License, or
15 * (at your option) any later version.
18 #include <linux/clk.h>
19 #include <linux/delay.h>
20 #include <linux/gpio/consumer.h>
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
23 #include <linux/irq.h>
24 #include <linux/irqchip/chained_irq.h>
25 #include <linux/irqdomain.h>
26 #include <linux/kernel.h>
27 #include <linux/mfd/syscon.h>
28 #include <linux/of_address.h>
29 #include <linux/of_device.h>
30 #include <linux/of_pci.h>
31 #include <linux/of_platform.h>
32 #include <linux/of_irq.h>
33 #include <linux/pci.h>
34 #include <linux/pci_ids.h>
35 #include <linux/phy/phy.h>
36 #include <linux/platform_device.h>
37 #include <linux/reset.h>
38 #include <linux/regmap.h>
41 * The upper 16 bits of PCIE_CLIENT_CONFIG are a write mask for the lower 16
42 * bits. This allows atomic updates of the register without locking.
44 #define HIWORD_UPDATE(mask, val) (((mask) << 16) | (val))
45 #define HIWORD_UPDATE_BIT(val) HIWORD_UPDATE(val, val)
47 #define ENCODE_LANES(x) ((((x) >> 1) & 3) << 4)
49 #define PCIE_CLIENT_BASE 0x0
50 #define PCIE_CLIENT_CONFIG (PCIE_CLIENT_BASE + 0x00)
51 #define PCIE_CLIENT_CONF_ENABLE HIWORD_UPDATE_BIT(0x0001)
52 #define PCIE_CLIENT_LINK_TRAIN_ENABLE HIWORD_UPDATE_BIT(0x0002)
53 #define PCIE_CLIENT_ARI_ENABLE HIWORD_UPDATE_BIT(0x0008)
54 #define PCIE_CLIENT_CONF_LANE_NUM(x) HIWORD_UPDATE(0x0030, ENCODE_LANES(x))
55 #define PCIE_CLIENT_MODE_RC HIWORD_UPDATE_BIT(0x0040)
56 #define PCIE_CLIENT_GEN_SEL_2 HIWORD_UPDATE_BIT(0x0080)
57 #define PCIE_CLIENT_BASIC_STATUS1 (PCIE_CLIENT_BASE + 0x48)
58 #define PCIE_CLIENT_LINK_STATUS_UP 0x00300000
59 #define PCIE_CLIENT_LINK_STATUS_MASK 0x00300000
60 #define PCIE_CLIENT_INT_MASK (PCIE_CLIENT_BASE + 0x4c)
61 #define PCIE_CLIENT_INT_STATUS (PCIE_CLIENT_BASE + 0x50)
62 #define PCIE_CLIENT_INTR_MASK GENMASK(8, 5)
63 #define PCIE_CLIENT_INTR_SHIFT 5
64 #define PCIE_CLIENT_INT_LEGACY_DONE BIT(15)
65 #define PCIE_CLIENT_INT_MSG BIT(14)
66 #define PCIE_CLIENT_INT_HOT_RST BIT(13)
67 #define PCIE_CLIENT_INT_DPA BIT(12)
68 #define PCIE_CLIENT_INT_FATAL_ERR BIT(11)
69 #define PCIE_CLIENT_INT_NFATAL_ERR BIT(10)
70 #define PCIE_CLIENT_INT_CORR_ERR BIT(9)
71 #define PCIE_CLIENT_INT_INTD BIT(8)
72 #define PCIE_CLIENT_INT_INTC BIT(7)
73 #define PCIE_CLIENT_INT_INTB BIT(6)
74 #define PCIE_CLIENT_INT_INTA BIT(5)
75 #define PCIE_CLIENT_INT_LOCAL BIT(4)
76 #define PCIE_CLIENT_INT_UDMA BIT(3)
77 #define PCIE_CLIENT_INT_PHY BIT(2)
78 #define PCIE_CLIENT_INT_HOT_PLUG BIT(1)
79 #define PCIE_CLIENT_INT_PWR_STCG BIT(0)
81 #define PCIE_CLIENT_INT_LEGACY \
82 (PCIE_CLIENT_INT_INTA | PCIE_CLIENT_INT_INTB | \
83 PCIE_CLIENT_INT_INTC | PCIE_CLIENT_INT_INTD)
85 #define PCIE_CLIENT_INT_CLI \
86 (PCIE_CLIENT_INT_CORR_ERR | PCIE_CLIENT_INT_NFATAL_ERR | \
87 PCIE_CLIENT_INT_FATAL_ERR | PCIE_CLIENT_INT_DPA | \
88 PCIE_CLIENT_INT_HOT_RST | PCIE_CLIENT_INT_MSG | \
89 PCIE_CLIENT_INT_LEGACY_DONE | PCIE_CLIENT_INT_LEGACY | \
92 #define PCIE_CORE_CTRL_MGMT_BASE 0x900000
93 #define PCIE_CORE_CTRL (PCIE_CORE_CTRL_MGMT_BASE + 0x000)
94 #define PCIE_CORE_PL_CONF_SPEED_5G 0x00000008
95 #define PCIE_CORE_PL_CONF_SPEED_MASK 0x00000018
96 #define PCIE_CORE_PL_CONF_LANE_MASK 0x00000006
97 #define PCIE_CORE_PL_CONF_LANE_SHIFT 1
98 #define PCIE_CORE_CTRL_PLC1 (PCIE_CORE_CTRL_MGMT_BASE + 0x004)
99 #define PCIE_CORE_CTRL_PLC1_FTS_MASK GENMASK(23, 8)
100 #define PCIE_CORE_CTRL_PLC1_FTS_SHIFT 8
101 #define PCIE_CORE_CTRL_PLC1_FTS_CNT 0xffff
102 #define PCIE_CORE_TXCREDIT_CFG1 (PCIE_CORE_CTRL_MGMT_BASE + 0x020)
103 #define PCIE_CORE_TXCREDIT_CFG1_MUI_MASK 0xFFFF0000
104 #define PCIE_CORE_TXCREDIT_CFG1_MUI_SHIFT 16
105 #define PCIE_CORE_TXCREDIT_CFG1_MUI_ENCODE(x) \
106 (((x) >> 3) << PCIE_CORE_TXCREDIT_CFG1_MUI_SHIFT)
107 #define PCIE_CORE_INT_STATUS (PCIE_CORE_CTRL_MGMT_BASE + 0x20c)
108 #define PCIE_CORE_INT_PRFPE BIT(0)
109 #define PCIE_CORE_INT_CRFPE BIT(1)
110 #define PCIE_CORE_INT_RRPE BIT(2)
111 #define PCIE_CORE_INT_PRFO BIT(3)
112 #define PCIE_CORE_INT_CRFO BIT(4)
113 #define PCIE_CORE_INT_RT BIT(5)
114 #define PCIE_CORE_INT_RTR BIT(6)
115 #define PCIE_CORE_INT_PE BIT(7)
116 #define PCIE_CORE_INT_MTR BIT(8)
117 #define PCIE_CORE_INT_UCR BIT(9)
118 #define PCIE_CORE_INT_FCE BIT(10)
119 #define PCIE_CORE_INT_CT BIT(11)
120 #define PCIE_CORE_INT_UTC BIT(18)
121 #define PCIE_CORE_INT_MMVC BIT(19)
122 #define PCIE_CORE_INT_MASK (PCIE_CORE_CTRL_MGMT_BASE + 0x210)
123 #define PCIE_RC_BAR_CONF (PCIE_CORE_CTRL_MGMT_BASE + 0x300)
125 #define PCIE_CORE_INT \
126 (PCIE_CORE_INT_PRFPE | PCIE_CORE_INT_CRFPE | \
127 PCIE_CORE_INT_RRPE | PCIE_CORE_INT_CRFO | \
128 PCIE_CORE_INT_RT | PCIE_CORE_INT_RTR | \
129 PCIE_CORE_INT_PE | PCIE_CORE_INT_MTR | \
130 PCIE_CORE_INT_UCR | PCIE_CORE_INT_FCE | \
131 PCIE_CORE_INT_CT | PCIE_CORE_INT_UTC | \
134 #define PCIE_RC_CONFIG_BASE 0xa00000
135 #define PCIE_RC_CONFIG_VENDOR (PCIE_RC_CONFIG_BASE + 0x00)
136 #define PCIE_RC_CONFIG_RID_CCR (PCIE_RC_CONFIG_BASE + 0x08)
137 #define PCIE_RC_CONFIG_SCC_SHIFT 16
138 #define PCIE_RC_CONFIG_DCR (PCIE_RC_CONFIG_BASE + 0xc4)
139 #define PCIE_RC_CONFIG_DCR_CSPL_SHIFT 18
140 #define PCIE_RC_CONFIG_DCR_CSPL_LIMIT 0xff
141 #define PCIE_RC_CONFIG_DCR_CPLS_SHIFT 26
142 #define PCIE_RC_CONFIG_LCS (PCIE_RC_CONFIG_BASE + 0xd0)
143 #define PCIE_RC_CONFIG_LCS_RETRAIN_LINK BIT(5)
144 #define PCIE_RC_CONFIG_LCS_CCC BIT(6)
145 #define PCIE_RC_CONFIG_LCS_LBMIE BIT(10)
146 #define PCIE_RC_CONFIG_LCS_LABIE BIT(11)
147 #define PCIE_RC_CONFIG_LCS_LBMS BIT(30)
148 #define PCIE_RC_CONFIG_LCS_LAMS BIT(31)
149 #define PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2 (PCIE_RC_CONFIG_BASE + 0x90c)
151 #define PCIE_CORE_AXI_CONF_BASE 0xc00000
152 #define PCIE_CORE_OB_REGION_ADDR0 (PCIE_CORE_AXI_CONF_BASE + 0x0)
153 #define PCIE_CORE_OB_REGION_ADDR0_NUM_BITS 0x3f
154 #define PCIE_CORE_OB_REGION_ADDR0_LO_ADDR 0xffffff00
155 #define PCIE_CORE_OB_REGION_ADDR1 (PCIE_CORE_AXI_CONF_BASE + 0x4)
156 #define PCIE_CORE_OB_REGION_DESC0 (PCIE_CORE_AXI_CONF_BASE + 0x8)
157 #define PCIE_CORE_OB_REGION_DESC1 (PCIE_CORE_AXI_CONF_BASE + 0xc)
159 #define PCIE_CORE_AXI_INBOUND_BASE 0xc00800
160 #define PCIE_RP_IB_ADDR0 (PCIE_CORE_AXI_INBOUND_BASE + 0x0)
161 #define PCIE_CORE_IB_REGION_ADDR0_NUM_BITS 0x3f
162 #define PCIE_CORE_IB_REGION_ADDR0_LO_ADDR 0xffffff00
163 #define PCIE_RP_IB_ADDR1 (PCIE_CORE_AXI_INBOUND_BASE + 0x4)
165 /* Size of one AXI Region (not Region 0) */
166 #define AXI_REGION_SIZE BIT(20)
167 /* Size of Region 0, equal to sum of sizes of other regions */
168 #define AXI_REGION_0_SIZE (32 * (0x1 << 20))
169 #define OB_REG_SIZE_SHIFT 5
170 #define IB_ROOT_PORT_REG_SIZE_SHIFT 3
171 #define AXI_WRAPPER_IO_WRITE 0x6
172 #define AXI_WRAPPER_MEM_WRITE 0x2
174 #define MAX_AXI_IB_ROOTPORT_REGION_NUM 3
175 #define MIN_AXI_ADDR_BITS_PASSED 8
176 #define ROCKCHIP_VENDOR_ID 0x1d87
177 #define PCIE_ECAM_BUS(x) (((x) & 0xff) << 20)
178 #define PCIE_ECAM_DEV(x) (((x) & 0x1f) << 15)
179 #define PCIE_ECAM_FUNC(x) (((x) & 0x7) << 12)
180 #define PCIE_ECAM_REG(x) (((x) & 0xfff) << 0)
181 #define PCIE_ECAM_ADDR(bus, dev, func, reg) \
182 (PCIE_ECAM_BUS(bus) | PCIE_ECAM_DEV(dev) | \
183 PCIE_ECAM_FUNC(func) | PCIE_ECAM_REG(reg))
185 #define RC_REGION_0_ADDR_TRANS_H 0x00000000
186 #define RC_REGION_0_ADDR_TRANS_L 0x00000000
187 #define RC_REGION_0_PASS_BITS (25 - 1)
188 #define MAX_AXI_WRAPPER_REGION_NUM 33
190 struct rockchip_pcie {
191 void __iomem *reg_base; /* DT axi-base */
192 void __iomem *apb_base; /* DT apb-base */
194 struct reset_control *core_rst;
195 struct reset_control *mgmt_rst;
196 struct reset_control *mgmt_sticky_rst;
197 struct reset_control *pipe_rst;
198 struct clk *aclk_pcie;
199 struct clk *aclk_perf_pcie;
200 struct clk *hclk_pcie;
201 struct clk *clk_pcie_pm;
202 struct regulator *vpcie3v3; /* 3.3V power supply */
203 struct regulator *vpcie1v8; /* 1.8V power supply */
204 struct regulator *vpcie0v9; /* 0.9V power supply */
205 struct gpio_desc *ep_gpio;
209 struct irq_domain *irq_domain;
212 static u32 rockchip_pcie_read(struct rockchip_pcie *rockchip, u32 reg)
214 return readl(rockchip->apb_base + reg);
217 static void rockchip_pcie_write(struct rockchip_pcie *rockchip, u32 val,
220 writel(val, rockchip->apb_base + reg);
223 static void rockchip_pcie_enable_bw_int(struct rockchip_pcie *rockchip)
227 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS);
228 status |= (PCIE_RC_CONFIG_LCS_LBMIE | PCIE_RC_CONFIG_LCS_LABIE);
229 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS);
232 static void rockchip_pcie_clr_bw_int(struct rockchip_pcie *rockchip)
236 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS);
237 status |= (PCIE_RC_CONFIG_LCS_LBMS | PCIE_RC_CONFIG_LCS_LAMS);
238 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS);
241 static void rockchip_pcie_update_txcredit_mui(struct rockchip_pcie *rockchip)
245 /* Update Tx credit maximum update interval */
246 val = rockchip_pcie_read(rockchip, PCIE_CORE_TXCREDIT_CFG1);
247 val &= ~PCIE_CORE_TXCREDIT_CFG1_MUI_MASK;
248 val |= PCIE_CORE_TXCREDIT_CFG1_MUI_ENCODE(24000); /* ns */
249 rockchip_pcie_write(rockchip, val, PCIE_CORE_TXCREDIT_CFG1);
252 static int rockchip_pcie_valid_device(struct rockchip_pcie *rockchip,
253 struct pci_bus *bus, int dev)
255 /* access only one slot on each root port */
256 if (bus->number == rockchip->root_bus_nr && dev > 0)
260 * do not read more than one device on the bus directly attached
261 * to RC's downstream side.
263 if (bus->primary == rockchip->root_bus_nr && dev > 0)
269 static int rockchip_pcie_rd_own_conf(struct rockchip_pcie *rockchip,
270 int where, int size, u32 *val)
272 void __iomem *addr = rockchip->apb_base + PCIE_RC_CONFIG_BASE + where;
274 if (!IS_ALIGNED((uintptr_t)addr, size)) {
276 return PCIBIOS_BAD_REGISTER_NUMBER;
281 } else if (size == 2) {
283 } else if (size == 1) {
287 return PCIBIOS_BAD_REGISTER_NUMBER;
289 return PCIBIOS_SUCCESSFUL;
292 static int rockchip_pcie_wr_own_conf(struct rockchip_pcie *rockchip,
293 int where, int size, u32 val)
295 u32 mask, tmp, offset;
297 offset = where & ~0x3;
300 writel(val, rockchip->apb_base + PCIE_RC_CONFIG_BASE + offset);
301 return PCIBIOS_SUCCESSFUL;
304 mask = ~(((1 << (size * 8)) - 1) << ((where & 0x3) * 8));
307 * N.B. This read/modify/write isn't safe in general because it can
308 * corrupt RW1C bits in adjacent registers. But the hardware
309 * doesn't support smaller writes.
311 tmp = readl(rockchip->apb_base + PCIE_RC_CONFIG_BASE + offset) & mask;
312 tmp |= val << ((where & 0x3) * 8);
313 writel(tmp, rockchip->apb_base + PCIE_RC_CONFIG_BASE + offset);
315 return PCIBIOS_SUCCESSFUL;
318 static int rockchip_pcie_rd_other_conf(struct rockchip_pcie *rockchip,
319 struct pci_bus *bus, u32 devfn,
320 int where, int size, u32 *val)
324 busdev = PCIE_ECAM_ADDR(bus->number, PCI_SLOT(devfn),
325 PCI_FUNC(devfn), where);
327 if (!IS_ALIGNED(busdev, size)) {
329 return PCIBIOS_BAD_REGISTER_NUMBER;
333 *val = readl(rockchip->reg_base + busdev);
334 } else if (size == 2) {
335 *val = readw(rockchip->reg_base + busdev);
336 } else if (size == 1) {
337 *val = readb(rockchip->reg_base + busdev);
340 return PCIBIOS_BAD_REGISTER_NUMBER;
342 return PCIBIOS_SUCCESSFUL;
345 static int rockchip_pcie_wr_other_conf(struct rockchip_pcie *rockchip,
346 struct pci_bus *bus, u32 devfn,
347 int where, int size, u32 val)
351 busdev = PCIE_ECAM_ADDR(bus->number, PCI_SLOT(devfn),
352 PCI_FUNC(devfn), where);
353 if (!IS_ALIGNED(busdev, size))
354 return PCIBIOS_BAD_REGISTER_NUMBER;
357 writel(val, rockchip->reg_base + busdev);
359 writew(val, rockchip->reg_base + busdev);
361 writeb(val, rockchip->reg_base + busdev);
363 return PCIBIOS_BAD_REGISTER_NUMBER;
365 return PCIBIOS_SUCCESSFUL;
368 static int rockchip_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
371 struct rockchip_pcie *rockchip = bus->sysdata;
373 if (!rockchip_pcie_valid_device(rockchip, bus, PCI_SLOT(devfn))) {
375 return PCIBIOS_DEVICE_NOT_FOUND;
378 if (bus->number == rockchip->root_bus_nr)
379 return rockchip_pcie_rd_own_conf(rockchip, where, size, val);
381 return rockchip_pcie_rd_other_conf(rockchip, bus, devfn, where, size, val);
384 static int rockchip_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
385 int where, int size, u32 val)
387 struct rockchip_pcie *rockchip = bus->sysdata;
389 if (!rockchip_pcie_valid_device(rockchip, bus, PCI_SLOT(devfn)))
390 return PCIBIOS_DEVICE_NOT_FOUND;
392 if (bus->number == rockchip->root_bus_nr)
393 return rockchip_pcie_wr_own_conf(rockchip, where, size, val);
395 return rockchip_pcie_wr_other_conf(rockchip, bus, devfn, where, size, val);
398 static struct pci_ops rockchip_pcie_ops = {
399 .read = rockchip_pcie_rd_conf,
400 .write = rockchip_pcie_wr_conf,
403 static void rockchip_pcie_set_power_limit(struct rockchip_pcie *rockchip)
405 u32 status, curr, scale, power;
407 if (IS_ERR(rockchip->vpcie3v3))
411 * Set RC's captured slot power limit and scale if
412 * vpcie3v3 available. The default values are both zero
413 * which means the software should set these two according
414 * to the actual power supply.
416 curr = regulator_get_current_limit(rockchip->vpcie3v3);
418 scale = 3; /* 0.001x */
419 curr = curr / 1000; /* convert to mA */
420 power = (curr * 3300) / 1000; /* milliwatt */
421 while (power > PCIE_RC_CONFIG_DCR_CSPL_LIMIT) {
423 dev_warn(rockchip->dev, "invalid power supply\n");
430 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_DCR);
431 status |= (power << PCIE_RC_CONFIG_DCR_CSPL_SHIFT) |
432 (scale << PCIE_RC_CONFIG_DCR_CPLS_SHIFT);
433 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_DCR);
438 * rockchip_pcie_init_port - Initialize hardware
439 * @rockchip: PCIe port information
441 static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
443 struct device *dev = rockchip->dev;
446 unsigned long timeout;
448 gpiod_set_value(rockchip->ep_gpio, 0);
450 err = phy_init(rockchip->phy);
452 dev_err(dev, "fail to init phy, err %d\n", err);
456 err = reset_control_assert(rockchip->core_rst);
458 dev_err(dev, "assert core_rst err %d\n", err);
462 err = reset_control_assert(rockchip->mgmt_rst);
464 dev_err(dev, "assert mgmt_rst err %d\n", err);
468 err = reset_control_assert(rockchip->mgmt_sticky_rst);
470 dev_err(dev, "assert mgmt_sticky_rst err %d\n", err);
474 err = reset_control_assert(rockchip->pipe_rst);
476 dev_err(dev, "assert pipe_rst err %d\n", err);
480 rockchip_pcie_write(rockchip,
481 PCIE_CLIENT_CONF_ENABLE |
482 PCIE_CLIENT_LINK_TRAIN_ENABLE |
483 PCIE_CLIENT_ARI_ENABLE |
484 PCIE_CLIENT_CONF_LANE_NUM(rockchip->lanes) |
485 PCIE_CLIENT_MODE_RC |
486 PCIE_CLIENT_GEN_SEL_2,
489 err = phy_power_on(rockchip->phy);
491 dev_err(dev, "fail to power on phy, err %d\n", err);
496 * Please don't reorder the deassert sequence of the following
499 err = reset_control_deassert(rockchip->mgmt_sticky_rst);
501 dev_err(dev, "deassert mgmt_sticky_rst err %d\n", err);
505 err = reset_control_deassert(rockchip->core_rst);
507 dev_err(dev, "deassert core_rst err %d\n", err);
511 err = reset_control_deassert(rockchip->mgmt_rst);
513 dev_err(dev, "deassert mgmt_rst err %d\n", err);
517 err = reset_control_deassert(rockchip->pipe_rst);
519 dev_err(dev, "deassert pipe_rst err %d\n", err);
524 * We need to read/write PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2 before
525 * enabling ASPM. Otherwise L1PwrOnSc and L1PwrOnVal isn't
526 * reliable and enabling ASPM doesn't work. This is a controller
527 * bug we need to work around.
529 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2);
530 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2);
532 /* Fix the transmitted FTS count desired to exit from L0s. */
533 status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL_PLC1);
534 status = (status & PCIE_CORE_CTRL_PLC1_FTS_MASK) |
535 (PCIE_CORE_CTRL_PLC1_FTS_CNT << PCIE_CORE_CTRL_PLC1_FTS_SHIFT);
536 rockchip_pcie_write(rockchip, status, PCIE_CORE_CTRL_PLC1);
538 rockchip_pcie_set_power_limit(rockchip);
540 /* Set RC's clock architecture as common clock */
541 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS);
542 status |= PCIE_RC_CONFIG_LCS_CCC;
543 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS);
545 /* Enable Gen1 training */
546 rockchip_pcie_write(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE,
549 gpiod_set_value(rockchip->ep_gpio, 1);
551 /* 500ms timeout value should be enough for Gen1/2 training */
552 timeout = jiffies + msecs_to_jiffies(500);
555 status = rockchip_pcie_read(rockchip,
556 PCIE_CLIENT_BASIC_STATUS1);
557 if ((status & PCIE_CLIENT_LINK_STATUS_MASK) ==
558 PCIE_CLIENT_LINK_STATUS_UP) {
559 dev_dbg(dev, "PCIe link training gen1 pass!\n");
563 if (time_after(jiffies, timeout)) {
564 dev_err(dev, "PCIe link training gen1 timeout!\n");
572 * Enable retrain for gen2. This should be configured only after
575 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS);
576 status |= PCIE_RC_CONFIG_LCS_RETRAIN_LINK;
577 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS);
579 timeout = jiffies + msecs_to_jiffies(500);
581 status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL);
582 if ((status & PCIE_CORE_PL_CONF_SPEED_MASK) ==
583 PCIE_CORE_PL_CONF_SPEED_5G) {
584 dev_dbg(dev, "PCIe link training gen2 pass!\n");
588 if (time_after(jiffies, timeout)) {
589 dev_dbg(dev, "PCIe link training gen2 timeout, fall back to gen1!\n");
596 /* Check the final link width from negotiated lane counter from MGMT */
597 status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL);
598 status = 0x1 << ((status & PCIE_CORE_PL_CONF_LANE_MASK) >>
599 PCIE_CORE_PL_CONF_LANE_MASK);
600 dev_dbg(dev, "current link width is x%d\n", status);
602 rockchip_pcie_write(rockchip, ROCKCHIP_VENDOR_ID,
603 PCIE_RC_CONFIG_VENDOR);
604 rockchip_pcie_write(rockchip,
605 PCI_CLASS_BRIDGE_PCI << PCIE_RC_CONFIG_SCC_SHIFT,
606 PCIE_RC_CONFIG_RID_CCR);
607 rockchip_pcie_write(rockchip, 0x0, PCIE_RC_BAR_CONF);
609 rockchip_pcie_write(rockchip,
610 (RC_REGION_0_ADDR_TRANS_L + RC_REGION_0_PASS_BITS),
611 PCIE_CORE_OB_REGION_ADDR0);
612 rockchip_pcie_write(rockchip, RC_REGION_0_ADDR_TRANS_H,
613 PCIE_CORE_OB_REGION_ADDR1);
614 rockchip_pcie_write(rockchip, 0x0080000a, PCIE_CORE_OB_REGION_DESC0);
615 rockchip_pcie_write(rockchip, 0x0, PCIE_CORE_OB_REGION_DESC1);
620 static irqreturn_t rockchip_pcie_subsys_irq_handler(int irq, void *arg)
622 struct rockchip_pcie *rockchip = arg;
623 struct device *dev = rockchip->dev;
627 reg = rockchip_pcie_read(rockchip, PCIE_CLIENT_INT_STATUS);
628 if (reg & PCIE_CLIENT_INT_LOCAL) {
629 dev_dbg(dev, "local interrupt received\n");
630 sub_reg = rockchip_pcie_read(rockchip, PCIE_CORE_INT_STATUS);
631 if (sub_reg & PCIE_CORE_INT_PRFPE)
632 dev_dbg(dev, "parity error detected while reading from the PNP receive FIFO RAM\n");
634 if (sub_reg & PCIE_CORE_INT_CRFPE)
635 dev_dbg(dev, "parity error detected while reading from the Completion Receive FIFO RAM\n");
637 if (sub_reg & PCIE_CORE_INT_RRPE)
638 dev_dbg(dev, "parity error detected while reading from replay buffer RAM\n");
640 if (sub_reg & PCIE_CORE_INT_PRFO)
641 dev_dbg(dev, "overflow occurred in the PNP receive FIFO\n");
643 if (sub_reg & PCIE_CORE_INT_CRFO)
644 dev_dbg(dev, "overflow occurred in the completion receive FIFO\n");
646 if (sub_reg & PCIE_CORE_INT_RT)
647 dev_dbg(dev, "replay timer timed out\n");
649 if (sub_reg & PCIE_CORE_INT_RTR)
650 dev_dbg(dev, "replay timer rolled over after 4 transmissions of the same TLP\n");
652 if (sub_reg & PCIE_CORE_INT_PE)
653 dev_dbg(dev, "phy error detected on receive side\n");
655 if (sub_reg & PCIE_CORE_INT_MTR)
656 dev_dbg(dev, "malformed TLP received from the link\n");
658 if (sub_reg & PCIE_CORE_INT_UCR)
659 dev_dbg(dev, "malformed TLP received from the link\n");
661 if (sub_reg & PCIE_CORE_INT_FCE)
662 dev_dbg(dev, "an error was observed in the flow control advertisements from the other side\n");
664 if (sub_reg & PCIE_CORE_INT_CT)
665 dev_dbg(dev, "a request timed out waiting for completion\n");
667 if (sub_reg & PCIE_CORE_INT_UTC)
668 dev_dbg(dev, "unmapped TC error\n");
670 if (sub_reg & PCIE_CORE_INT_MMVC)
671 dev_dbg(dev, "MSI mask register changes\n");
673 rockchip_pcie_write(rockchip, sub_reg, PCIE_CORE_INT_STATUS);
674 } else if (reg & PCIE_CLIENT_INT_PHY) {
675 dev_dbg(dev, "phy link changes\n");
676 rockchip_pcie_update_txcredit_mui(rockchip);
677 rockchip_pcie_clr_bw_int(rockchip);
680 rockchip_pcie_write(rockchip, reg & PCIE_CLIENT_INT_LOCAL,
681 PCIE_CLIENT_INT_STATUS);
686 static irqreturn_t rockchip_pcie_client_irq_handler(int irq, void *arg)
688 struct rockchip_pcie *rockchip = arg;
689 struct device *dev = rockchip->dev;
692 reg = rockchip_pcie_read(rockchip, PCIE_CLIENT_INT_STATUS);
693 if (reg & PCIE_CLIENT_INT_LEGACY_DONE)
694 dev_dbg(dev, "legacy done interrupt received\n");
696 if (reg & PCIE_CLIENT_INT_MSG)
697 dev_dbg(dev, "message done interrupt received\n");
699 if (reg & PCIE_CLIENT_INT_HOT_RST)
700 dev_dbg(dev, "hot reset interrupt received\n");
702 if (reg & PCIE_CLIENT_INT_DPA)
703 dev_dbg(dev, "dpa interrupt received\n");
705 if (reg & PCIE_CLIENT_INT_FATAL_ERR)
706 dev_dbg(dev, "fatal error interrupt received\n");
708 if (reg & PCIE_CLIENT_INT_NFATAL_ERR)
709 dev_dbg(dev, "no fatal error interrupt received\n");
711 if (reg & PCIE_CLIENT_INT_CORR_ERR)
712 dev_dbg(dev, "correctable error interrupt received\n");
714 if (reg & PCIE_CLIENT_INT_PHY)
715 dev_dbg(dev, "phy interrupt received\n");
717 rockchip_pcie_write(rockchip, reg & (PCIE_CLIENT_INT_LEGACY_DONE |
718 PCIE_CLIENT_INT_MSG | PCIE_CLIENT_INT_HOT_RST |
719 PCIE_CLIENT_INT_DPA | PCIE_CLIENT_INT_FATAL_ERR |
720 PCIE_CLIENT_INT_NFATAL_ERR |
721 PCIE_CLIENT_INT_CORR_ERR |
722 PCIE_CLIENT_INT_PHY),
723 PCIE_CLIENT_INT_STATUS);
728 static void rockchip_pcie_legacy_int_handler(struct irq_desc *desc)
730 struct irq_chip *chip = irq_desc_get_chip(desc);
731 struct rockchip_pcie *rockchip = irq_desc_get_handler_data(desc);
732 struct device *dev = rockchip->dev;
737 chained_irq_enter(chip, desc);
739 reg = rockchip_pcie_read(rockchip, PCIE_CLIENT_INT_STATUS);
740 reg = (reg & PCIE_CLIENT_INTR_MASK) >> PCIE_CLIENT_INTR_SHIFT;
743 hwirq = ffs(reg) - 1;
746 virq = irq_find_mapping(rockchip->irq_domain, hwirq);
748 generic_handle_irq(virq);
750 dev_err(dev, "unexpected IRQ, INT%d\n", hwirq);
753 chained_irq_exit(chip, desc);
758 * rockchip_pcie_parse_dt - Parse Device Tree
759 * @rockchip: PCIe port information
761 * Return: '0' on success and error value on failure
763 static int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip)
765 struct device *dev = rockchip->dev;
766 struct platform_device *pdev = to_platform_device(dev);
767 struct device_node *node = dev->of_node;
768 struct resource *regs;
772 regs = platform_get_resource_byname(pdev,
775 rockchip->reg_base = devm_ioremap_resource(dev, regs);
776 if (IS_ERR(rockchip->reg_base))
777 return PTR_ERR(rockchip->reg_base);
779 regs = platform_get_resource_byname(pdev,
782 rockchip->apb_base = devm_ioremap_resource(dev, regs);
783 if (IS_ERR(rockchip->apb_base))
784 return PTR_ERR(rockchip->apb_base);
786 rockchip->phy = devm_phy_get(dev, "pcie-phy");
787 if (IS_ERR(rockchip->phy)) {
788 if (PTR_ERR(rockchip->phy) != -EPROBE_DEFER)
789 dev_err(dev, "missing phy\n");
790 return PTR_ERR(rockchip->phy);
794 err = of_property_read_u32(node, "num-lanes", &rockchip->lanes);
795 if (!err && (rockchip->lanes == 0 ||
796 rockchip->lanes == 3 ||
797 rockchip->lanes > 4)) {
798 dev_warn(dev, "invalid num-lanes, default to use one lane\n");
802 rockchip->core_rst = devm_reset_control_get(dev, "core");
803 if (IS_ERR(rockchip->core_rst)) {
804 if (PTR_ERR(rockchip->core_rst) != -EPROBE_DEFER)
805 dev_err(dev, "missing core reset property in node\n");
806 return PTR_ERR(rockchip->core_rst);
809 rockchip->mgmt_rst = devm_reset_control_get(dev, "mgmt");
810 if (IS_ERR(rockchip->mgmt_rst)) {
811 if (PTR_ERR(rockchip->mgmt_rst) != -EPROBE_DEFER)
812 dev_err(dev, "missing mgmt reset property in node\n");
813 return PTR_ERR(rockchip->mgmt_rst);
816 rockchip->mgmt_sticky_rst = devm_reset_control_get(dev, "mgmt-sticky");
817 if (IS_ERR(rockchip->mgmt_sticky_rst)) {
818 if (PTR_ERR(rockchip->mgmt_sticky_rst) != -EPROBE_DEFER)
819 dev_err(dev, "missing mgmt-sticky reset property in node\n");
820 return PTR_ERR(rockchip->mgmt_sticky_rst);
823 rockchip->pipe_rst = devm_reset_control_get(dev, "pipe");
824 if (IS_ERR(rockchip->pipe_rst)) {
825 if (PTR_ERR(rockchip->pipe_rst) != -EPROBE_DEFER)
826 dev_err(dev, "missing pipe reset property in node\n");
827 return PTR_ERR(rockchip->pipe_rst);
830 rockchip->ep_gpio = devm_gpiod_get(dev, "ep", GPIOD_OUT_HIGH);
831 if (IS_ERR(rockchip->ep_gpio)) {
832 dev_err(dev, "missing ep-gpios property in node\n");
833 return PTR_ERR(rockchip->ep_gpio);
836 rockchip->aclk_pcie = devm_clk_get(dev, "aclk");
837 if (IS_ERR(rockchip->aclk_pcie)) {
838 dev_err(dev, "aclk clock not found\n");
839 return PTR_ERR(rockchip->aclk_pcie);
842 rockchip->aclk_perf_pcie = devm_clk_get(dev, "aclk-perf");
843 if (IS_ERR(rockchip->aclk_perf_pcie)) {
844 dev_err(dev, "aclk_perf clock not found\n");
845 return PTR_ERR(rockchip->aclk_perf_pcie);
848 rockchip->hclk_pcie = devm_clk_get(dev, "hclk");
849 if (IS_ERR(rockchip->hclk_pcie)) {
850 dev_err(dev, "hclk clock not found\n");
851 return PTR_ERR(rockchip->hclk_pcie);
854 rockchip->clk_pcie_pm = devm_clk_get(dev, "pm");
855 if (IS_ERR(rockchip->clk_pcie_pm)) {
856 dev_err(dev, "pm clock not found\n");
857 return PTR_ERR(rockchip->clk_pcie_pm);
860 irq = platform_get_irq_byname(pdev, "sys");
862 dev_err(dev, "missing sys IRQ resource\n");
866 err = devm_request_irq(dev, irq, rockchip_pcie_subsys_irq_handler,
867 IRQF_SHARED, "pcie-sys", rockchip);
869 dev_err(dev, "failed to request PCIe subsystem IRQ\n");
873 irq = platform_get_irq_byname(pdev, "legacy");
875 dev_err(dev, "missing legacy IRQ resource\n");
879 irq_set_chained_handler_and_data(irq,
880 rockchip_pcie_legacy_int_handler,
883 irq = platform_get_irq_byname(pdev, "client");
885 dev_err(dev, "missing client IRQ resource\n");
889 err = devm_request_irq(dev, irq, rockchip_pcie_client_irq_handler,
890 IRQF_SHARED, "pcie-client", rockchip);
892 dev_err(dev, "failed to request PCIe client IRQ\n");
896 rockchip->vpcie3v3 = devm_regulator_get_optional(dev, "vpcie3v3");
897 if (IS_ERR(rockchip->vpcie3v3)) {
898 if (PTR_ERR(rockchip->vpcie3v3) == -EPROBE_DEFER)
899 return -EPROBE_DEFER;
900 dev_info(dev, "no vpcie3v3 regulator found\n");
903 rockchip->vpcie1v8 = devm_regulator_get_optional(dev, "vpcie1v8");
904 if (IS_ERR(rockchip->vpcie1v8)) {
905 if (PTR_ERR(rockchip->vpcie1v8) == -EPROBE_DEFER)
906 return -EPROBE_DEFER;
907 dev_info(dev, "no vpcie1v8 regulator found\n");
910 rockchip->vpcie0v9 = devm_regulator_get_optional(dev, "vpcie0v9");
911 if (IS_ERR(rockchip->vpcie0v9)) {
912 if (PTR_ERR(rockchip->vpcie0v9) == -EPROBE_DEFER)
913 return -EPROBE_DEFER;
914 dev_info(dev, "no vpcie0v9 regulator found\n");
920 static int rockchip_pcie_set_vpcie(struct rockchip_pcie *rockchip)
922 struct device *dev = rockchip->dev;
925 if (!IS_ERR(rockchip->vpcie3v3)) {
926 err = regulator_enable(rockchip->vpcie3v3);
928 dev_err(dev, "fail to enable vpcie3v3 regulator\n");
933 if (!IS_ERR(rockchip->vpcie1v8)) {
934 err = regulator_enable(rockchip->vpcie1v8);
936 dev_err(dev, "fail to enable vpcie1v8 regulator\n");
937 goto err_disable_3v3;
941 if (!IS_ERR(rockchip->vpcie0v9)) {
942 err = regulator_enable(rockchip->vpcie0v9);
944 dev_err(dev, "fail to enable vpcie0v9 regulator\n");
945 goto err_disable_1v8;
952 if (!IS_ERR(rockchip->vpcie1v8))
953 regulator_disable(rockchip->vpcie1v8);
955 if (!IS_ERR(rockchip->vpcie3v3))
956 regulator_disable(rockchip->vpcie3v3);
961 static void rockchip_pcie_enable_interrupts(struct rockchip_pcie *rockchip)
963 rockchip_pcie_write(rockchip, (PCIE_CLIENT_INT_CLI << 16) &
964 (~PCIE_CLIENT_INT_CLI), PCIE_CLIENT_INT_MASK);
965 rockchip_pcie_write(rockchip, (u32)(~PCIE_CORE_INT),
968 rockchip_pcie_enable_bw_int(rockchip);
971 static int rockchip_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
972 irq_hw_number_t hwirq)
974 irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
975 irq_set_chip_data(irq, domain->host_data);
980 static const struct irq_domain_ops intx_domain_ops = {
981 .map = rockchip_pcie_intx_map,
984 static int rockchip_pcie_init_irq_domain(struct rockchip_pcie *rockchip)
986 struct device *dev = rockchip->dev;
987 struct device_node *intc = of_get_next_child(dev->of_node, NULL);
990 dev_err(dev, "missing child interrupt-controller node\n");
994 rockchip->irq_domain = irq_domain_add_linear(intc, 4,
995 &intx_domain_ops, rockchip);
996 if (!rockchip->irq_domain) {
997 dev_err(dev, "failed to get a INTx IRQ domain\n");
1004 static int rockchip_pcie_prog_ob_atu(struct rockchip_pcie *rockchip,
1005 int region_no, int type, u8 num_pass_bits,
1006 u32 lower_addr, u32 upper_addr)
1013 if (region_no >= MAX_AXI_WRAPPER_REGION_NUM)
1015 if (num_pass_bits + 1 < 8)
1017 if (num_pass_bits > 63)
1019 if (region_no == 0) {
1020 if (AXI_REGION_0_SIZE < (2ULL << num_pass_bits))
1023 if (region_no != 0) {
1024 if (AXI_REGION_SIZE < (2ULL << num_pass_bits))
1028 aw_offset = (region_no << OB_REG_SIZE_SHIFT);
1030 ob_addr_0 = num_pass_bits & PCIE_CORE_OB_REGION_ADDR0_NUM_BITS;
1031 ob_addr_0 |= lower_addr & PCIE_CORE_OB_REGION_ADDR0_LO_ADDR;
1032 ob_addr_1 = upper_addr;
1033 ob_desc_0 = (1 << 23 | type);
1035 rockchip_pcie_write(rockchip, ob_addr_0,
1036 PCIE_CORE_OB_REGION_ADDR0 + aw_offset);
1037 rockchip_pcie_write(rockchip, ob_addr_1,
1038 PCIE_CORE_OB_REGION_ADDR1 + aw_offset);
1039 rockchip_pcie_write(rockchip, ob_desc_0,
1040 PCIE_CORE_OB_REGION_DESC0 + aw_offset);
1041 rockchip_pcie_write(rockchip, 0,
1042 PCIE_CORE_OB_REGION_DESC1 + aw_offset);
1047 static int rockchip_pcie_prog_ib_atu(struct rockchip_pcie *rockchip,
1048 int region_no, u8 num_pass_bits,
1049 u32 lower_addr, u32 upper_addr)
1055 if (region_no > MAX_AXI_IB_ROOTPORT_REGION_NUM)
1057 if (num_pass_bits + 1 < MIN_AXI_ADDR_BITS_PASSED)
1059 if (num_pass_bits > 63)
1062 aw_offset = (region_no << IB_ROOT_PORT_REG_SIZE_SHIFT);
1064 ib_addr_0 = num_pass_bits & PCIE_CORE_IB_REGION_ADDR0_NUM_BITS;
1065 ib_addr_0 |= (lower_addr << 8) & PCIE_CORE_IB_REGION_ADDR0_LO_ADDR;
1066 ib_addr_1 = upper_addr;
1068 rockchip_pcie_write(rockchip, ib_addr_0, PCIE_RP_IB_ADDR0 + aw_offset);
1069 rockchip_pcie_write(rockchip, ib_addr_1, PCIE_RP_IB_ADDR1 + aw_offset);
1074 static int rockchip_pcie_probe(struct platform_device *pdev)
1076 struct rockchip_pcie *rockchip;
1077 struct device *dev = &pdev->dev;
1078 struct pci_bus *bus, *child;
1079 struct resource_entry *win;
1080 resource_size_t io_base;
1081 struct resource *mem;
1082 struct resource *io;
1083 phys_addr_t io_bus_addr = 0;
1085 phys_addr_t mem_bus_addr = 0;
1096 rockchip = devm_kzalloc(dev, sizeof(*rockchip), GFP_KERNEL);
1100 rockchip->dev = dev;
1102 err = rockchip_pcie_parse_dt(rockchip);
1106 err = clk_prepare_enable(rockchip->aclk_pcie);
1108 dev_err(dev, "unable to enable aclk_pcie clock\n");
1112 err = clk_prepare_enable(rockchip->aclk_perf_pcie);
1114 dev_err(dev, "unable to enable aclk_perf_pcie clock\n");
1115 goto err_aclk_perf_pcie;
1118 err = clk_prepare_enable(rockchip->hclk_pcie);
1120 dev_err(dev, "unable to enable hclk_pcie clock\n");
1124 err = clk_prepare_enable(rockchip->clk_pcie_pm);
1126 dev_err(dev, "unable to enable hclk_pcie clock\n");
1130 err = rockchip_pcie_set_vpcie(rockchip);
1132 dev_err(dev, "failed to set vpcie regulator\n");
1136 err = rockchip_pcie_init_port(rockchip);
1140 platform_set_drvdata(pdev, rockchip);
1142 rockchip_pcie_enable_interrupts(rockchip);
1144 err = rockchip_pcie_init_irq_domain(rockchip);
1148 err = of_pci_get_host_bridge_resources(dev->of_node, 0, 0xff,
1153 err = devm_request_pci_bus_resources(dev, &res);
1157 /* Get the I/O and memory ranges from DT */
1159 resource_list_for_each_entry(win, &res) {
1160 switch (resource_type(win->res)) {
1164 io_size = resource_size(io);
1165 io_bus_addr = io->start - win->offset;
1166 err = pci_remap_iospace(io, io_base);
1168 dev_warn(dev, "error %d: failed to map resource %pR\n",
1173 case IORESOURCE_MEM:
1176 mem_size = resource_size(mem);
1177 mem_bus_addr = mem->start - win->offset;
1179 case IORESOURCE_BUS:
1180 rockchip->root_bus_nr = win->res->start;
1188 for (reg_no = 0; reg_no < (mem_size >> 20); reg_no++) {
1189 err = rockchip_pcie_prog_ob_atu(rockchip, reg_no + 1,
1190 AXI_WRAPPER_MEM_WRITE,
1196 dev_err(dev, "program RC mem outbound ATU failed\n");
1202 err = rockchip_pcie_prog_ib_atu(rockchip, 2, 32 - 1, 0x0, 0);
1204 dev_err(dev, "program RC mem inbound ATU failed\n");
1208 offset = mem_size >> 20;
1211 for (reg_no = 0; reg_no < (io_size >> 20); reg_no++) {
1212 err = rockchip_pcie_prog_ob_atu(rockchip,
1213 reg_no + 1 + offset,
1214 AXI_WRAPPER_IO_WRITE,
1220 dev_err(dev, "program RC io outbound ATU failed\n");
1226 bus = pci_scan_root_bus(&pdev->dev, 0, &rockchip_pcie_ops, rockchip, &res);
1232 pci_bus_size_bridges(bus);
1233 pci_bus_assign_resources(bus);
1234 list_for_each_entry(child, &bus->children, node)
1235 pcie_bus_configure_settings(child);
1237 pci_bus_add_devices(bus);
1239 dev_warn(dev, "only 32-bit config accesses supported; smaller writes may corrupt adjacent RW1C fields\n");
1244 if (!IS_ERR(rockchip->vpcie3v3))
1245 regulator_disable(rockchip->vpcie3v3);
1246 if (!IS_ERR(rockchip->vpcie1v8))
1247 regulator_disable(rockchip->vpcie1v8);
1248 if (!IS_ERR(rockchip->vpcie0v9))
1249 regulator_disable(rockchip->vpcie0v9);
1251 clk_disable_unprepare(rockchip->clk_pcie_pm);
1253 clk_disable_unprepare(rockchip->hclk_pcie);
1255 clk_disable_unprepare(rockchip->aclk_perf_pcie);
1257 clk_disable_unprepare(rockchip->aclk_pcie);
1262 static const struct of_device_id rockchip_pcie_of_match[] = {
1263 { .compatible = "rockchip,rk3399-pcie", },
1267 static struct platform_driver rockchip_pcie_driver = {
1269 .name = "rockchip-pcie",
1270 .of_match_table = rockchip_pcie_of_match,
1272 .probe = rockchip_pcie_probe,
1275 builtin_platform_driver(rockchip_pcie_driver);