2 * Rockchip AXI PCIe host controller driver
4 * Copyright (c) 2016 Rockchip, Inc.
6 * Author: Shawn Lin <shawn.lin@rock-chips.com>
7 * Wenrui Li <wenrui.li@rock-chips.com>
9 * Bits taken from Synopsys Designware Host controller driver and
10 * ARM PCI Host generic driver.
12 * This program is free software: you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation, either version 2 of the License, or
15 * (at your option) any later version.
18 #include <linux/clk.h>
19 #include <linux/delay.h>
20 #include <linux/gpio/consumer.h>
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
23 #include <linux/irq.h>
24 #include <linux/irqchip/chained_irq.h>
25 #include <linux/irqdomain.h>
26 #include <linux/kernel.h>
27 #include <linux/mfd/syscon.h>
28 #include <linux/of_address.h>
29 #include <linux/of_device.h>
30 #include <linux/of_pci.h>
31 #include <linux/of_platform.h>
32 #include <linux/of_irq.h>
33 #include <linux/pci.h>
34 #include <linux/pci_ids.h>
35 #include <linux/phy/phy.h>
36 #include <linux/platform_device.h>
37 #include <linux/reset.h>
38 #include <linux/regmap.h>
41 * The upper 16 bits of PCIE_CLIENT_CONFIG are a write mask for the lower 16
42 * bits. This allows atomic updates of the register without locking.
44 #define HIWORD_UPDATE(mask, val) (((mask) << 16) | (val))
45 #define HIWORD_UPDATE_BIT(val) HIWORD_UPDATE(val, val)
47 #define ENCODE_LANES(x) ((((x) >> 1) & 3) << 4)
49 #define PCIE_CLIENT_BASE 0x0
50 #define PCIE_CLIENT_CONFIG (PCIE_CLIENT_BASE + 0x00)
51 #define PCIE_CLIENT_CONF_ENABLE HIWORD_UPDATE_BIT(0x0001)
52 #define PCIE_CLIENT_LINK_TRAIN_ENABLE HIWORD_UPDATE_BIT(0x0002)
53 #define PCIE_CLIENT_ARI_ENABLE HIWORD_UPDATE_BIT(0x0008)
54 #define PCIE_CLIENT_CONF_LANE_NUM(x) HIWORD_UPDATE(0x0030, ENCODE_LANES(x))
55 #define PCIE_CLIENT_MODE_RC HIWORD_UPDATE_BIT(0x0040)
56 #define PCIE_CLIENT_GEN_SEL_1 HIWORD_UPDATE(0x0080, 0)
57 #define PCIE_CLIENT_GEN_SEL_2 HIWORD_UPDATE_BIT(0x0080)
58 #define PCIE_CLIENT_BASIC_STATUS1 (PCIE_CLIENT_BASE + 0x48)
59 #define PCIE_CLIENT_LINK_STATUS_UP 0x00300000
60 #define PCIE_CLIENT_LINK_STATUS_MASK 0x00300000
61 #define PCIE_CLIENT_INT_MASK (PCIE_CLIENT_BASE + 0x4c)
62 #define PCIE_CLIENT_INT_STATUS (PCIE_CLIENT_BASE + 0x50)
63 #define PCIE_CLIENT_INTR_MASK GENMASK(8, 5)
64 #define PCIE_CLIENT_INTR_SHIFT 5
65 #define PCIE_CLIENT_INT_LEGACY_DONE BIT(15)
66 #define PCIE_CLIENT_INT_MSG BIT(14)
67 #define PCIE_CLIENT_INT_HOT_RST BIT(13)
68 #define PCIE_CLIENT_INT_DPA BIT(12)
69 #define PCIE_CLIENT_INT_FATAL_ERR BIT(11)
70 #define PCIE_CLIENT_INT_NFATAL_ERR BIT(10)
71 #define PCIE_CLIENT_INT_CORR_ERR BIT(9)
72 #define PCIE_CLIENT_INT_INTD BIT(8)
73 #define PCIE_CLIENT_INT_INTC BIT(7)
74 #define PCIE_CLIENT_INT_INTB BIT(6)
75 #define PCIE_CLIENT_INT_INTA BIT(5)
76 #define PCIE_CLIENT_INT_LOCAL BIT(4)
77 #define PCIE_CLIENT_INT_UDMA BIT(3)
78 #define PCIE_CLIENT_INT_PHY BIT(2)
79 #define PCIE_CLIENT_INT_HOT_PLUG BIT(1)
80 #define PCIE_CLIENT_INT_PWR_STCG BIT(0)
82 #define PCIE_CLIENT_INT_LEGACY \
83 (PCIE_CLIENT_INT_INTA | PCIE_CLIENT_INT_INTB | \
84 PCIE_CLIENT_INT_INTC | PCIE_CLIENT_INT_INTD)
86 #define PCIE_CLIENT_INT_CLI \
87 (PCIE_CLIENT_INT_CORR_ERR | PCIE_CLIENT_INT_NFATAL_ERR | \
88 PCIE_CLIENT_INT_FATAL_ERR | PCIE_CLIENT_INT_DPA | \
89 PCIE_CLIENT_INT_HOT_RST | PCIE_CLIENT_INT_MSG | \
90 PCIE_CLIENT_INT_LEGACY_DONE | PCIE_CLIENT_INT_LEGACY | \
93 #define PCIE_CORE_CTRL_MGMT_BASE 0x900000
94 #define PCIE_CORE_CTRL (PCIE_CORE_CTRL_MGMT_BASE + 0x000)
95 #define PCIE_CORE_PL_CONF_SPEED_5G 0x00000008
96 #define PCIE_CORE_PL_CONF_SPEED_MASK 0x00000018
97 #define PCIE_CORE_PL_CONF_LANE_MASK 0x00000006
98 #define PCIE_CORE_PL_CONF_LANE_SHIFT 1
99 #define PCIE_CORE_CTRL_PLC1 (PCIE_CORE_CTRL_MGMT_BASE + 0x004)
100 #define PCIE_CORE_CTRL_PLC1_FTS_MASK GENMASK(23, 8)
101 #define PCIE_CORE_CTRL_PLC1_FTS_SHIFT 8
102 #define PCIE_CORE_CTRL_PLC1_FTS_CNT 0xffff
103 #define PCIE_CORE_TXCREDIT_CFG1 (PCIE_CORE_CTRL_MGMT_BASE + 0x020)
104 #define PCIE_CORE_TXCREDIT_CFG1_MUI_MASK 0xFFFF0000
105 #define PCIE_CORE_TXCREDIT_CFG1_MUI_SHIFT 16
106 #define PCIE_CORE_TXCREDIT_CFG1_MUI_ENCODE(x) \
107 (((x) >> 3) << PCIE_CORE_TXCREDIT_CFG1_MUI_SHIFT)
108 #define PCIE_CORE_INT_STATUS (PCIE_CORE_CTRL_MGMT_BASE + 0x20c)
109 #define PCIE_CORE_INT_PRFPE BIT(0)
110 #define PCIE_CORE_INT_CRFPE BIT(1)
111 #define PCIE_CORE_INT_RRPE BIT(2)
112 #define PCIE_CORE_INT_PRFO BIT(3)
113 #define PCIE_CORE_INT_CRFO BIT(4)
114 #define PCIE_CORE_INT_RT BIT(5)
115 #define PCIE_CORE_INT_RTR BIT(6)
116 #define PCIE_CORE_INT_PE BIT(7)
117 #define PCIE_CORE_INT_MTR BIT(8)
118 #define PCIE_CORE_INT_UCR BIT(9)
119 #define PCIE_CORE_INT_FCE BIT(10)
120 #define PCIE_CORE_INT_CT BIT(11)
121 #define PCIE_CORE_INT_UTC BIT(18)
122 #define PCIE_CORE_INT_MMVC BIT(19)
123 #define PCIE_CORE_INT_MASK (PCIE_CORE_CTRL_MGMT_BASE + 0x210)
124 #define PCIE_RC_BAR_CONF (PCIE_CORE_CTRL_MGMT_BASE + 0x300)
126 #define PCIE_CORE_INT \
127 (PCIE_CORE_INT_PRFPE | PCIE_CORE_INT_CRFPE | \
128 PCIE_CORE_INT_RRPE | PCIE_CORE_INT_CRFO | \
129 PCIE_CORE_INT_RT | PCIE_CORE_INT_RTR | \
130 PCIE_CORE_INT_PE | PCIE_CORE_INT_MTR | \
131 PCIE_CORE_INT_UCR | PCIE_CORE_INT_FCE | \
132 PCIE_CORE_INT_CT | PCIE_CORE_INT_UTC | \
135 #define PCIE_RC_CONFIG_BASE 0xa00000
136 #define PCIE_RC_CONFIG_VENDOR (PCIE_RC_CONFIG_BASE + 0x00)
137 #define PCIE_RC_CONFIG_RID_CCR (PCIE_RC_CONFIG_BASE + 0x08)
138 #define PCIE_RC_CONFIG_SCC_SHIFT 16
139 #define PCIE_RC_CONFIG_DCR (PCIE_RC_CONFIG_BASE + 0xc4)
140 #define PCIE_RC_CONFIG_DCR_CSPL_SHIFT 18
141 #define PCIE_RC_CONFIG_DCR_CSPL_LIMIT 0xff
142 #define PCIE_RC_CONFIG_DCR_CPLS_SHIFT 26
143 #define PCIE_RC_CONFIG_LINK_CAP (PCIE_RC_CONFIG_BASE + 0xcc)
144 #define PCIE_RC_CONFIG_LINK_CAP_L0S BIT(10)
145 #define PCIE_RC_CONFIG_LCS (PCIE_RC_CONFIG_BASE + 0xd0)
146 #define PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2 (PCIE_RC_CONFIG_BASE + 0x90c)
147 #define PCIE_RC_CONFIG_THP_CAP (PCIE_RC_CONFIG_BASE + 0x274)
148 #define PCIE_RC_CONFIG_THP_CAP_NEXT_MASK GENMASK(31, 20)
150 #define PCIE_CORE_AXI_CONF_BASE 0xc00000
151 #define PCIE_CORE_OB_REGION_ADDR0 (PCIE_CORE_AXI_CONF_BASE + 0x0)
152 #define PCIE_CORE_OB_REGION_ADDR0_NUM_BITS 0x3f
153 #define PCIE_CORE_OB_REGION_ADDR0_LO_ADDR 0xffffff00
154 #define PCIE_CORE_OB_REGION_ADDR1 (PCIE_CORE_AXI_CONF_BASE + 0x4)
155 #define PCIE_CORE_OB_REGION_DESC0 (PCIE_CORE_AXI_CONF_BASE + 0x8)
156 #define PCIE_CORE_OB_REGION_DESC1 (PCIE_CORE_AXI_CONF_BASE + 0xc)
158 #define PCIE_CORE_AXI_INBOUND_BASE 0xc00800
159 #define PCIE_RP_IB_ADDR0 (PCIE_CORE_AXI_INBOUND_BASE + 0x0)
160 #define PCIE_CORE_IB_REGION_ADDR0_NUM_BITS 0x3f
161 #define PCIE_CORE_IB_REGION_ADDR0_LO_ADDR 0xffffff00
162 #define PCIE_RP_IB_ADDR1 (PCIE_CORE_AXI_INBOUND_BASE + 0x4)
164 /* Size of one AXI Region (not Region 0) */
165 #define AXI_REGION_SIZE BIT(20)
166 /* Size of Region 0, equal to sum of sizes of other regions */
167 #define AXI_REGION_0_SIZE (32 * (0x1 << 20))
168 #define OB_REG_SIZE_SHIFT 5
169 #define IB_ROOT_PORT_REG_SIZE_SHIFT 3
170 #define AXI_WRAPPER_IO_WRITE 0x6
171 #define AXI_WRAPPER_MEM_WRITE 0x2
173 #define MAX_AXI_IB_ROOTPORT_REGION_NUM 3
174 #define MIN_AXI_ADDR_BITS_PASSED 8
175 #define ROCKCHIP_VENDOR_ID 0x1d87
176 #define PCIE_ECAM_BUS(x) (((x) & 0xff) << 20)
177 #define PCIE_ECAM_DEV(x) (((x) & 0x1f) << 15)
178 #define PCIE_ECAM_FUNC(x) (((x) & 0x7) << 12)
179 #define PCIE_ECAM_REG(x) (((x) & 0xfff) << 0)
180 #define PCIE_ECAM_ADDR(bus, dev, func, reg) \
181 (PCIE_ECAM_BUS(bus) | PCIE_ECAM_DEV(dev) | \
182 PCIE_ECAM_FUNC(func) | PCIE_ECAM_REG(reg))
184 #define RC_REGION_0_ADDR_TRANS_H 0x00000000
185 #define RC_REGION_0_ADDR_TRANS_L 0x00000000
186 #define RC_REGION_0_PASS_BITS (25 - 1)
187 #define MAX_AXI_WRAPPER_REGION_NUM 33
189 struct rockchip_pcie {
190 void __iomem *reg_base; /* DT axi-base */
191 void __iomem *apb_base; /* DT apb-base */
193 struct reset_control *core_rst;
194 struct reset_control *mgmt_rst;
195 struct reset_control *mgmt_sticky_rst;
196 struct reset_control *pipe_rst;
197 struct reset_control *pm_rst;
198 struct reset_control *aclk_rst;
199 struct reset_control *pclk_rst;
200 struct clk *aclk_pcie;
201 struct clk *aclk_perf_pcie;
202 struct clk *hclk_pcie;
203 struct clk *clk_pcie_pm;
204 struct regulator *vpcie3v3; /* 3.3V power supply */
205 struct regulator *vpcie1v8; /* 1.8V power supply */
206 struct regulator *vpcie0v9; /* 0.9V power supply */
207 struct gpio_desc *ep_gpio;
212 struct irq_domain *irq_domain;
215 static u32 rockchip_pcie_read(struct rockchip_pcie *rockchip, u32 reg)
217 return readl(rockchip->apb_base + reg);
220 static void rockchip_pcie_write(struct rockchip_pcie *rockchip, u32 val,
223 writel(val, rockchip->apb_base + reg);
226 static void rockchip_pcie_enable_bw_int(struct rockchip_pcie *rockchip)
230 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS);
231 status |= (PCI_EXP_LNKCTL_LBMIE | PCI_EXP_LNKCTL_LABIE);
232 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS);
235 static void rockchip_pcie_clr_bw_int(struct rockchip_pcie *rockchip)
239 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS);
240 status |= (PCI_EXP_LNKSTA_LBMS | PCI_EXP_LNKSTA_LABS) << 16;
241 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS);
244 static void rockchip_pcie_update_txcredit_mui(struct rockchip_pcie *rockchip)
248 /* Update Tx credit maximum update interval */
249 val = rockchip_pcie_read(rockchip, PCIE_CORE_TXCREDIT_CFG1);
250 val &= ~PCIE_CORE_TXCREDIT_CFG1_MUI_MASK;
251 val |= PCIE_CORE_TXCREDIT_CFG1_MUI_ENCODE(24000); /* ns */
252 rockchip_pcie_write(rockchip, val, PCIE_CORE_TXCREDIT_CFG1);
255 static int rockchip_pcie_valid_device(struct rockchip_pcie *rockchip,
256 struct pci_bus *bus, int dev)
258 /* access only one slot on each root port */
259 if (bus->number == rockchip->root_bus_nr && dev > 0)
263 * do not read more than one device on the bus directly attached
264 * to RC's downstream side.
266 if (bus->primary == rockchip->root_bus_nr && dev > 0)
272 static int rockchip_pcie_rd_own_conf(struct rockchip_pcie *rockchip,
273 int where, int size, u32 *val)
275 void __iomem *addr = rockchip->apb_base + PCIE_RC_CONFIG_BASE + where;
277 if (!IS_ALIGNED((uintptr_t)addr, size)) {
279 return PCIBIOS_BAD_REGISTER_NUMBER;
284 } else if (size == 2) {
286 } else if (size == 1) {
290 return PCIBIOS_BAD_REGISTER_NUMBER;
292 return PCIBIOS_SUCCESSFUL;
295 static int rockchip_pcie_wr_own_conf(struct rockchip_pcie *rockchip,
296 int where, int size, u32 val)
298 u32 mask, tmp, offset;
300 offset = where & ~0x3;
303 writel(val, rockchip->apb_base + PCIE_RC_CONFIG_BASE + offset);
304 return PCIBIOS_SUCCESSFUL;
307 mask = ~(((1 << (size * 8)) - 1) << ((where & 0x3) * 8));
310 * N.B. This read/modify/write isn't safe in general because it can
311 * corrupt RW1C bits in adjacent registers. But the hardware
312 * doesn't support smaller writes.
314 tmp = readl(rockchip->apb_base + PCIE_RC_CONFIG_BASE + offset) & mask;
315 tmp |= val << ((where & 0x3) * 8);
316 writel(tmp, rockchip->apb_base + PCIE_RC_CONFIG_BASE + offset);
318 return PCIBIOS_SUCCESSFUL;
321 static int rockchip_pcie_rd_other_conf(struct rockchip_pcie *rockchip,
322 struct pci_bus *bus, u32 devfn,
323 int where, int size, u32 *val)
327 busdev = PCIE_ECAM_ADDR(bus->number, PCI_SLOT(devfn),
328 PCI_FUNC(devfn), where);
330 if (!IS_ALIGNED(busdev, size)) {
332 return PCIBIOS_BAD_REGISTER_NUMBER;
336 *val = readl(rockchip->reg_base + busdev);
337 } else if (size == 2) {
338 *val = readw(rockchip->reg_base + busdev);
339 } else if (size == 1) {
340 *val = readb(rockchip->reg_base + busdev);
343 return PCIBIOS_BAD_REGISTER_NUMBER;
345 return PCIBIOS_SUCCESSFUL;
348 static int rockchip_pcie_wr_other_conf(struct rockchip_pcie *rockchip,
349 struct pci_bus *bus, u32 devfn,
350 int where, int size, u32 val)
354 busdev = PCIE_ECAM_ADDR(bus->number, PCI_SLOT(devfn),
355 PCI_FUNC(devfn), where);
356 if (!IS_ALIGNED(busdev, size))
357 return PCIBIOS_BAD_REGISTER_NUMBER;
360 writel(val, rockchip->reg_base + busdev);
362 writew(val, rockchip->reg_base + busdev);
364 writeb(val, rockchip->reg_base + busdev);
366 return PCIBIOS_BAD_REGISTER_NUMBER;
368 return PCIBIOS_SUCCESSFUL;
371 static int rockchip_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
374 struct rockchip_pcie *rockchip = bus->sysdata;
376 if (!rockchip_pcie_valid_device(rockchip, bus, PCI_SLOT(devfn))) {
378 return PCIBIOS_DEVICE_NOT_FOUND;
381 if (bus->number == rockchip->root_bus_nr)
382 return rockchip_pcie_rd_own_conf(rockchip, where, size, val);
384 return rockchip_pcie_rd_other_conf(rockchip, bus, devfn, where, size, val);
387 static int rockchip_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
388 int where, int size, u32 val)
390 struct rockchip_pcie *rockchip = bus->sysdata;
392 if (!rockchip_pcie_valid_device(rockchip, bus, PCI_SLOT(devfn)))
393 return PCIBIOS_DEVICE_NOT_FOUND;
395 if (bus->number == rockchip->root_bus_nr)
396 return rockchip_pcie_wr_own_conf(rockchip, where, size, val);
398 return rockchip_pcie_wr_other_conf(rockchip, bus, devfn, where, size, val);
401 static struct pci_ops rockchip_pcie_ops = {
402 .read = rockchip_pcie_rd_conf,
403 .write = rockchip_pcie_wr_conf,
406 static void rockchip_pcie_set_power_limit(struct rockchip_pcie *rockchip)
408 u32 status, curr, scale, power;
410 if (IS_ERR(rockchip->vpcie3v3))
414 * Set RC's captured slot power limit and scale if
415 * vpcie3v3 available. The default values are both zero
416 * which means the software should set these two according
417 * to the actual power supply.
419 curr = regulator_get_current_limit(rockchip->vpcie3v3);
421 scale = 3; /* 0.001x */
422 curr = curr / 1000; /* convert to mA */
423 power = (curr * 3300) / 1000; /* milliwatt */
424 while (power > PCIE_RC_CONFIG_DCR_CSPL_LIMIT) {
426 dev_warn(rockchip->dev, "invalid power supply\n");
433 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_DCR);
434 status |= (power << PCIE_RC_CONFIG_DCR_CSPL_SHIFT) |
435 (scale << PCIE_RC_CONFIG_DCR_CPLS_SHIFT);
436 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_DCR);
441 * rockchip_pcie_init_port - Initialize hardware
442 * @rockchip: PCIe port information
444 static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
446 struct device *dev = rockchip->dev;
449 unsigned long timeout;
451 gpiod_set_value(rockchip->ep_gpio, 0);
453 err = reset_control_assert(rockchip->aclk_rst);
455 dev_err(dev, "assert aclk_rst err %d\n", err);
459 err = reset_control_assert(rockchip->pclk_rst);
461 dev_err(dev, "assert pclk_rst err %d\n", err);
465 err = reset_control_assert(rockchip->pm_rst);
467 dev_err(dev, "assert pm_rst err %d\n", err);
473 err = reset_control_deassert(rockchip->pm_rst);
475 dev_err(dev, "deassert pm_rst err %d\n", err);
479 err = reset_control_deassert(rockchip->aclk_rst);
481 dev_err(dev, "deassert mgmt_sticky_rst err %d\n", err);
485 err = reset_control_deassert(rockchip->pclk_rst);
487 dev_err(dev, "deassert mgmt_sticky_rst err %d\n", err);
491 err = phy_init(rockchip->phy);
493 dev_err(dev, "fail to init phy, err %d\n", err);
497 err = reset_control_assert(rockchip->core_rst);
499 dev_err(dev, "assert core_rst err %d\n", err);
503 err = reset_control_assert(rockchip->mgmt_rst);
505 dev_err(dev, "assert mgmt_rst err %d\n", err);
509 err = reset_control_assert(rockchip->mgmt_sticky_rst);
511 dev_err(dev, "assert mgmt_sticky_rst err %d\n", err);
515 err = reset_control_assert(rockchip->pipe_rst);
517 dev_err(dev, "assert pipe_rst err %d\n", err);
521 if (rockchip->link_gen == 2)
522 rockchip_pcie_write(rockchip, PCIE_CLIENT_GEN_SEL_2,
525 rockchip_pcie_write(rockchip, PCIE_CLIENT_GEN_SEL_1,
528 rockchip_pcie_write(rockchip,
529 PCIE_CLIENT_CONF_ENABLE |
530 PCIE_CLIENT_LINK_TRAIN_ENABLE |
531 PCIE_CLIENT_ARI_ENABLE |
532 PCIE_CLIENT_CONF_LANE_NUM(rockchip->lanes) |
536 err = phy_power_on(rockchip->phy);
538 dev_err(dev, "fail to power on phy, err %d\n", err);
543 * Please don't reorder the deassert sequence of the following
546 err = reset_control_deassert(rockchip->mgmt_sticky_rst);
548 dev_err(dev, "deassert mgmt_sticky_rst err %d\n", err);
552 err = reset_control_deassert(rockchip->core_rst);
554 dev_err(dev, "deassert core_rst err %d\n", err);
558 err = reset_control_deassert(rockchip->mgmt_rst);
560 dev_err(dev, "deassert mgmt_rst err %d\n", err);
564 err = reset_control_deassert(rockchip->pipe_rst);
566 dev_err(dev, "deassert pipe_rst err %d\n", err);
570 /* Fix the transmitted FTS count desired to exit from L0s. */
571 status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL_PLC1);
572 status = (status & ~PCIE_CORE_CTRL_PLC1_FTS_MASK) |
573 (PCIE_CORE_CTRL_PLC1_FTS_CNT << PCIE_CORE_CTRL_PLC1_FTS_SHIFT);
574 rockchip_pcie_write(rockchip, status, PCIE_CORE_CTRL_PLC1);
576 rockchip_pcie_set_power_limit(rockchip);
578 /* Set RC's clock architecture as common clock */
579 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS);
580 status |= PCI_EXP_LNKCTL_CCC;
581 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS);
583 /* Enable Gen1 training */
584 rockchip_pcie_write(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE,
587 gpiod_set_value(rockchip->ep_gpio, 1);
589 /* 500ms timeout value should be enough for Gen1/2 training */
590 timeout = jiffies + msecs_to_jiffies(500);
593 status = rockchip_pcie_read(rockchip,
594 PCIE_CLIENT_BASIC_STATUS1);
595 if ((status & PCIE_CLIENT_LINK_STATUS_MASK) ==
596 PCIE_CLIENT_LINK_STATUS_UP) {
597 dev_dbg(dev, "PCIe link training gen1 pass!\n");
601 if (time_after(jiffies, timeout)) {
602 dev_err(dev, "PCIe link training gen1 timeout!\n");
609 if (rockchip->link_gen == 2) {
611 * Enable retrain for gen2. This should be configured only after
614 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS);
615 status |= PCI_EXP_LNKCTL_RL;
616 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS);
618 timeout = jiffies + msecs_to_jiffies(500);
620 status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL);
621 if ((status & PCIE_CORE_PL_CONF_SPEED_MASK) ==
622 PCIE_CORE_PL_CONF_SPEED_5G) {
623 dev_dbg(dev, "PCIe link training gen2 pass!\n");
627 if (time_after(jiffies, timeout)) {
628 dev_dbg(dev, "PCIe link training gen2 timeout, fall back to gen1!\n");
636 /* Check the final link width from negotiated lane counter from MGMT */
637 status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL);
638 status = 0x1 << ((status & PCIE_CORE_PL_CONF_LANE_MASK) >>
639 PCIE_CORE_PL_CONF_LANE_SHIFT);
640 dev_dbg(dev, "current link width is x%d\n", status);
642 rockchip_pcie_write(rockchip, ROCKCHIP_VENDOR_ID,
643 PCIE_RC_CONFIG_VENDOR);
644 rockchip_pcie_write(rockchip,
645 PCI_CLASS_BRIDGE_PCI << PCIE_RC_CONFIG_SCC_SHIFT,
646 PCIE_RC_CONFIG_RID_CCR);
648 /* Clear THP cap's next cap pointer to remove L1 substate cap */
649 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_THP_CAP);
650 status &= ~PCIE_RC_CONFIG_THP_CAP_NEXT_MASK;
651 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_THP_CAP);
653 /* Clear L0s from RC's link cap */
654 if (of_property_read_bool(dev->of_node, "quirk,apsm-no-l0s")) {
655 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LINK_CAP);
656 status &= ~PCIE_RC_CONFIG_LINK_CAP_L0S;
657 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LINK_CAP);
660 rockchip_pcie_write(rockchip, 0x0, PCIE_RC_BAR_CONF);
662 rockchip_pcie_write(rockchip,
663 (RC_REGION_0_ADDR_TRANS_L + RC_REGION_0_PASS_BITS),
664 PCIE_CORE_OB_REGION_ADDR0);
665 rockchip_pcie_write(rockchip, RC_REGION_0_ADDR_TRANS_H,
666 PCIE_CORE_OB_REGION_ADDR1);
667 rockchip_pcie_write(rockchip, 0x0080000a, PCIE_CORE_OB_REGION_DESC0);
668 rockchip_pcie_write(rockchip, 0x0, PCIE_CORE_OB_REGION_DESC1);
673 static irqreturn_t rockchip_pcie_subsys_irq_handler(int irq, void *arg)
675 struct rockchip_pcie *rockchip = arg;
676 struct device *dev = rockchip->dev;
680 reg = rockchip_pcie_read(rockchip, PCIE_CLIENT_INT_STATUS);
681 if (reg & PCIE_CLIENT_INT_LOCAL) {
682 dev_dbg(dev, "local interrupt received\n");
683 sub_reg = rockchip_pcie_read(rockchip, PCIE_CORE_INT_STATUS);
684 if (sub_reg & PCIE_CORE_INT_PRFPE)
685 dev_dbg(dev, "parity error detected while reading from the PNP receive FIFO RAM\n");
687 if (sub_reg & PCIE_CORE_INT_CRFPE)
688 dev_dbg(dev, "parity error detected while reading from the Completion Receive FIFO RAM\n");
690 if (sub_reg & PCIE_CORE_INT_RRPE)
691 dev_dbg(dev, "parity error detected while reading from replay buffer RAM\n");
693 if (sub_reg & PCIE_CORE_INT_PRFO)
694 dev_dbg(dev, "overflow occurred in the PNP receive FIFO\n");
696 if (sub_reg & PCIE_CORE_INT_CRFO)
697 dev_dbg(dev, "overflow occurred in the completion receive FIFO\n");
699 if (sub_reg & PCIE_CORE_INT_RT)
700 dev_dbg(dev, "replay timer timed out\n");
702 if (sub_reg & PCIE_CORE_INT_RTR)
703 dev_dbg(dev, "replay timer rolled over after 4 transmissions of the same TLP\n");
705 if (sub_reg & PCIE_CORE_INT_PE)
706 dev_dbg(dev, "phy error detected on receive side\n");
708 if (sub_reg & PCIE_CORE_INT_MTR)
709 dev_dbg(dev, "malformed TLP received from the link\n");
711 if (sub_reg & PCIE_CORE_INT_UCR)
712 dev_dbg(dev, "malformed TLP received from the link\n");
714 if (sub_reg & PCIE_CORE_INT_FCE)
715 dev_dbg(dev, "an error was observed in the flow control advertisements from the other side\n");
717 if (sub_reg & PCIE_CORE_INT_CT)
718 dev_dbg(dev, "a request timed out waiting for completion\n");
720 if (sub_reg & PCIE_CORE_INT_UTC)
721 dev_dbg(dev, "unmapped TC error\n");
723 if (sub_reg & PCIE_CORE_INT_MMVC)
724 dev_dbg(dev, "MSI mask register changes\n");
726 rockchip_pcie_write(rockchip, sub_reg, PCIE_CORE_INT_STATUS);
727 } else if (reg & PCIE_CLIENT_INT_PHY) {
728 dev_dbg(dev, "phy link changes\n");
729 rockchip_pcie_update_txcredit_mui(rockchip);
730 rockchip_pcie_clr_bw_int(rockchip);
733 rockchip_pcie_write(rockchip, reg & PCIE_CLIENT_INT_LOCAL,
734 PCIE_CLIENT_INT_STATUS);
739 static irqreturn_t rockchip_pcie_client_irq_handler(int irq, void *arg)
741 struct rockchip_pcie *rockchip = arg;
742 struct device *dev = rockchip->dev;
745 reg = rockchip_pcie_read(rockchip, PCIE_CLIENT_INT_STATUS);
746 if (reg & PCIE_CLIENT_INT_LEGACY_DONE)
747 dev_dbg(dev, "legacy done interrupt received\n");
749 if (reg & PCIE_CLIENT_INT_MSG)
750 dev_dbg(dev, "message done interrupt received\n");
752 if (reg & PCIE_CLIENT_INT_HOT_RST)
753 dev_dbg(dev, "hot reset interrupt received\n");
755 if (reg & PCIE_CLIENT_INT_DPA)
756 dev_dbg(dev, "dpa interrupt received\n");
758 if (reg & PCIE_CLIENT_INT_FATAL_ERR)
759 dev_dbg(dev, "fatal error interrupt received\n");
761 if (reg & PCIE_CLIENT_INT_NFATAL_ERR)
762 dev_dbg(dev, "no fatal error interrupt received\n");
764 if (reg & PCIE_CLIENT_INT_CORR_ERR)
765 dev_dbg(dev, "correctable error interrupt received\n");
767 if (reg & PCIE_CLIENT_INT_PHY)
768 dev_dbg(dev, "phy interrupt received\n");
770 rockchip_pcie_write(rockchip, reg & (PCIE_CLIENT_INT_LEGACY_DONE |
771 PCIE_CLIENT_INT_MSG | PCIE_CLIENT_INT_HOT_RST |
772 PCIE_CLIENT_INT_DPA | PCIE_CLIENT_INT_FATAL_ERR |
773 PCIE_CLIENT_INT_NFATAL_ERR |
774 PCIE_CLIENT_INT_CORR_ERR |
775 PCIE_CLIENT_INT_PHY),
776 PCIE_CLIENT_INT_STATUS);
781 static void rockchip_pcie_legacy_int_handler(struct irq_desc *desc)
783 struct irq_chip *chip = irq_desc_get_chip(desc);
784 struct rockchip_pcie *rockchip = irq_desc_get_handler_data(desc);
785 struct device *dev = rockchip->dev;
790 chained_irq_enter(chip, desc);
792 reg = rockchip_pcie_read(rockchip, PCIE_CLIENT_INT_STATUS);
793 reg = (reg & PCIE_CLIENT_INTR_MASK) >> PCIE_CLIENT_INTR_SHIFT;
796 hwirq = ffs(reg) - 1;
799 virq = irq_find_mapping(rockchip->irq_domain, hwirq);
801 generic_handle_irq(virq);
803 dev_err(dev, "unexpected IRQ, INT%d\n", hwirq);
806 chained_irq_exit(chip, desc);
811 * rockchip_pcie_parse_dt - Parse Device Tree
812 * @rockchip: PCIe port information
814 * Return: '0' on success and error value on failure
816 static int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip)
818 struct device *dev = rockchip->dev;
819 struct platform_device *pdev = to_platform_device(dev);
820 struct device_node *node = dev->of_node;
821 struct resource *regs;
825 regs = platform_get_resource_byname(pdev,
828 rockchip->reg_base = devm_ioremap_resource(dev, regs);
829 if (IS_ERR(rockchip->reg_base))
830 return PTR_ERR(rockchip->reg_base);
832 regs = platform_get_resource_byname(pdev,
835 rockchip->apb_base = devm_ioremap_resource(dev, regs);
836 if (IS_ERR(rockchip->apb_base))
837 return PTR_ERR(rockchip->apb_base);
839 rockchip->phy = devm_phy_get(dev, "pcie-phy");
840 if (IS_ERR(rockchip->phy)) {
841 if (PTR_ERR(rockchip->phy) != -EPROBE_DEFER)
842 dev_err(dev, "missing phy\n");
843 return PTR_ERR(rockchip->phy);
847 err = of_property_read_u32(node, "num-lanes", &rockchip->lanes);
848 if (!err && (rockchip->lanes == 0 ||
849 rockchip->lanes == 3 ||
850 rockchip->lanes > 4)) {
851 dev_warn(dev, "invalid num-lanes, default to use one lane\n");
855 rockchip->link_gen = of_pci_get_max_link_speed(node);
856 if (rockchip->link_gen < 0 || rockchip->link_gen > 2)
857 rockchip->link_gen = 2;
859 rockchip->core_rst = devm_reset_control_get(dev, "core");
860 if (IS_ERR(rockchip->core_rst)) {
861 if (PTR_ERR(rockchip->core_rst) != -EPROBE_DEFER)
862 dev_err(dev, "missing core reset property in node\n");
863 return PTR_ERR(rockchip->core_rst);
866 rockchip->mgmt_rst = devm_reset_control_get(dev, "mgmt");
867 if (IS_ERR(rockchip->mgmt_rst)) {
868 if (PTR_ERR(rockchip->mgmt_rst) != -EPROBE_DEFER)
869 dev_err(dev, "missing mgmt reset property in node\n");
870 return PTR_ERR(rockchip->mgmt_rst);
873 rockchip->mgmt_sticky_rst = devm_reset_control_get(dev, "mgmt-sticky");
874 if (IS_ERR(rockchip->mgmt_sticky_rst)) {
875 if (PTR_ERR(rockchip->mgmt_sticky_rst) != -EPROBE_DEFER)
876 dev_err(dev, "missing mgmt-sticky reset property in node\n");
877 return PTR_ERR(rockchip->mgmt_sticky_rst);
880 rockchip->pipe_rst = devm_reset_control_get(dev, "pipe");
881 if (IS_ERR(rockchip->pipe_rst)) {
882 if (PTR_ERR(rockchip->pipe_rst) != -EPROBE_DEFER)
883 dev_err(dev, "missing pipe reset property in node\n");
884 return PTR_ERR(rockchip->pipe_rst);
887 rockchip->pm_rst = devm_reset_control_get(dev, "pm");
888 if (IS_ERR(rockchip->pm_rst)) {
889 if (PTR_ERR(rockchip->pm_rst) != -EPROBE_DEFER)
890 dev_err(dev, "missing pm reset property in node\n");
891 return PTR_ERR(rockchip->pm_rst);
894 rockchip->pclk_rst = devm_reset_control_get(dev, "pclk");
895 if (IS_ERR(rockchip->pclk_rst)) {
896 if (PTR_ERR(rockchip->pclk_rst) != -EPROBE_DEFER)
897 dev_err(dev, "missing pclk reset property in node\n");
898 return PTR_ERR(rockchip->pclk_rst);
901 rockchip->aclk_rst = devm_reset_control_get(dev, "aclk");
902 if (IS_ERR(rockchip->aclk_rst)) {
903 if (PTR_ERR(rockchip->aclk_rst) != -EPROBE_DEFER)
904 dev_err(dev, "missing aclk reset property in node\n");
905 return PTR_ERR(rockchip->aclk_rst);
908 rockchip->ep_gpio = devm_gpiod_get(dev, "ep", GPIOD_OUT_HIGH);
909 if (IS_ERR(rockchip->ep_gpio)) {
910 dev_err(dev, "missing ep-gpios property in node\n");
911 return PTR_ERR(rockchip->ep_gpio);
914 rockchip->aclk_pcie = devm_clk_get(dev, "aclk");
915 if (IS_ERR(rockchip->aclk_pcie)) {
916 dev_err(dev, "aclk clock not found\n");
917 return PTR_ERR(rockchip->aclk_pcie);
920 rockchip->aclk_perf_pcie = devm_clk_get(dev, "aclk-perf");
921 if (IS_ERR(rockchip->aclk_perf_pcie)) {
922 dev_err(dev, "aclk_perf clock not found\n");
923 return PTR_ERR(rockchip->aclk_perf_pcie);
926 rockchip->hclk_pcie = devm_clk_get(dev, "hclk");
927 if (IS_ERR(rockchip->hclk_pcie)) {
928 dev_err(dev, "hclk clock not found\n");
929 return PTR_ERR(rockchip->hclk_pcie);
932 rockchip->clk_pcie_pm = devm_clk_get(dev, "pm");
933 if (IS_ERR(rockchip->clk_pcie_pm)) {
934 dev_err(dev, "pm clock not found\n");
935 return PTR_ERR(rockchip->clk_pcie_pm);
938 irq = platform_get_irq_byname(pdev, "sys");
940 dev_err(dev, "missing sys IRQ resource\n");
944 err = devm_request_irq(dev, irq, rockchip_pcie_subsys_irq_handler,
945 IRQF_SHARED, "pcie-sys", rockchip);
947 dev_err(dev, "failed to request PCIe subsystem IRQ\n");
951 irq = platform_get_irq_byname(pdev, "legacy");
953 dev_err(dev, "missing legacy IRQ resource\n");
957 irq_set_chained_handler_and_data(irq,
958 rockchip_pcie_legacy_int_handler,
961 irq = platform_get_irq_byname(pdev, "client");
963 dev_err(dev, "missing client IRQ resource\n");
967 err = devm_request_irq(dev, irq, rockchip_pcie_client_irq_handler,
968 IRQF_SHARED, "pcie-client", rockchip);
970 dev_err(dev, "failed to request PCIe client IRQ\n");
974 rockchip->vpcie3v3 = devm_regulator_get_optional(dev, "vpcie3v3");
975 if (IS_ERR(rockchip->vpcie3v3)) {
976 if (PTR_ERR(rockchip->vpcie3v3) == -EPROBE_DEFER)
977 return -EPROBE_DEFER;
978 dev_info(dev, "no vpcie3v3 regulator found\n");
981 rockchip->vpcie1v8 = devm_regulator_get_optional(dev, "vpcie1v8");
982 if (IS_ERR(rockchip->vpcie1v8)) {
983 if (PTR_ERR(rockchip->vpcie1v8) == -EPROBE_DEFER)
984 return -EPROBE_DEFER;
985 dev_info(dev, "no vpcie1v8 regulator found\n");
988 rockchip->vpcie0v9 = devm_regulator_get_optional(dev, "vpcie0v9");
989 if (IS_ERR(rockchip->vpcie0v9)) {
990 if (PTR_ERR(rockchip->vpcie0v9) == -EPROBE_DEFER)
991 return -EPROBE_DEFER;
992 dev_info(dev, "no vpcie0v9 regulator found\n");
998 static int rockchip_pcie_set_vpcie(struct rockchip_pcie *rockchip)
1000 struct device *dev = rockchip->dev;
1003 if (!IS_ERR(rockchip->vpcie3v3)) {
1004 err = regulator_enable(rockchip->vpcie3v3);
1006 dev_err(dev, "fail to enable vpcie3v3 regulator\n");
1011 if (!IS_ERR(rockchip->vpcie1v8)) {
1012 err = regulator_enable(rockchip->vpcie1v8);
1014 dev_err(dev, "fail to enable vpcie1v8 regulator\n");
1015 goto err_disable_3v3;
1019 if (!IS_ERR(rockchip->vpcie0v9)) {
1020 err = regulator_enable(rockchip->vpcie0v9);
1022 dev_err(dev, "fail to enable vpcie0v9 regulator\n");
1023 goto err_disable_1v8;
1030 if (!IS_ERR(rockchip->vpcie1v8))
1031 regulator_disable(rockchip->vpcie1v8);
1033 if (!IS_ERR(rockchip->vpcie3v3))
1034 regulator_disable(rockchip->vpcie3v3);
1039 static void rockchip_pcie_enable_interrupts(struct rockchip_pcie *rockchip)
1041 rockchip_pcie_write(rockchip, (PCIE_CLIENT_INT_CLI << 16) &
1042 (~PCIE_CLIENT_INT_CLI), PCIE_CLIENT_INT_MASK);
1043 rockchip_pcie_write(rockchip, (u32)(~PCIE_CORE_INT),
1044 PCIE_CORE_INT_MASK);
1046 rockchip_pcie_enable_bw_int(rockchip);
1049 static int rockchip_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
1050 irq_hw_number_t hwirq)
1052 irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
1053 irq_set_chip_data(irq, domain->host_data);
1058 static const struct irq_domain_ops intx_domain_ops = {
1059 .map = rockchip_pcie_intx_map,
1062 static int rockchip_pcie_init_irq_domain(struct rockchip_pcie *rockchip)
1064 struct device *dev = rockchip->dev;
1065 struct device_node *intc = of_get_next_child(dev->of_node, NULL);
1068 dev_err(dev, "missing child interrupt-controller node\n");
1072 rockchip->irq_domain = irq_domain_add_linear(intc, 4,
1073 &intx_domain_ops, rockchip);
1074 if (!rockchip->irq_domain) {
1075 dev_err(dev, "failed to get a INTx IRQ domain\n");
1082 static int rockchip_pcie_prog_ob_atu(struct rockchip_pcie *rockchip,
1083 int region_no, int type, u8 num_pass_bits,
1084 u32 lower_addr, u32 upper_addr)
1091 if (region_no >= MAX_AXI_WRAPPER_REGION_NUM)
1093 if (num_pass_bits + 1 < 8)
1095 if (num_pass_bits > 63)
1097 if (region_no == 0) {
1098 if (AXI_REGION_0_SIZE < (2ULL << num_pass_bits))
1101 if (region_no != 0) {
1102 if (AXI_REGION_SIZE < (2ULL << num_pass_bits))
1106 aw_offset = (region_no << OB_REG_SIZE_SHIFT);
1108 ob_addr_0 = num_pass_bits & PCIE_CORE_OB_REGION_ADDR0_NUM_BITS;
1109 ob_addr_0 |= lower_addr & PCIE_CORE_OB_REGION_ADDR0_LO_ADDR;
1110 ob_addr_1 = upper_addr;
1111 ob_desc_0 = (1 << 23 | type);
1113 rockchip_pcie_write(rockchip, ob_addr_0,
1114 PCIE_CORE_OB_REGION_ADDR0 + aw_offset);
1115 rockchip_pcie_write(rockchip, ob_addr_1,
1116 PCIE_CORE_OB_REGION_ADDR1 + aw_offset);
1117 rockchip_pcie_write(rockchip, ob_desc_0,
1118 PCIE_CORE_OB_REGION_DESC0 + aw_offset);
1119 rockchip_pcie_write(rockchip, 0,
1120 PCIE_CORE_OB_REGION_DESC1 + aw_offset);
1125 static int rockchip_pcie_prog_ib_atu(struct rockchip_pcie *rockchip,
1126 int region_no, u8 num_pass_bits,
1127 u32 lower_addr, u32 upper_addr)
1133 if (region_no > MAX_AXI_IB_ROOTPORT_REGION_NUM)
1135 if (num_pass_bits + 1 < MIN_AXI_ADDR_BITS_PASSED)
1137 if (num_pass_bits > 63)
1140 aw_offset = (region_no << IB_ROOT_PORT_REG_SIZE_SHIFT);
1142 ib_addr_0 = num_pass_bits & PCIE_CORE_IB_REGION_ADDR0_NUM_BITS;
1143 ib_addr_0 |= (lower_addr << 8) & PCIE_CORE_IB_REGION_ADDR0_LO_ADDR;
1144 ib_addr_1 = upper_addr;
1146 rockchip_pcie_write(rockchip, ib_addr_0, PCIE_RP_IB_ADDR0 + aw_offset);
1147 rockchip_pcie_write(rockchip, ib_addr_1, PCIE_RP_IB_ADDR1 + aw_offset);
1152 static int rockchip_pcie_probe(struct platform_device *pdev)
1154 struct rockchip_pcie *rockchip;
1155 struct device *dev = &pdev->dev;
1156 struct pci_bus *bus, *child;
1157 struct resource_entry *win;
1158 resource_size_t io_base;
1159 struct resource *mem;
1160 struct resource *io;
1161 phys_addr_t io_bus_addr = 0;
1163 phys_addr_t mem_bus_addr = 0;
1174 rockchip = devm_kzalloc(dev, sizeof(*rockchip), GFP_KERNEL);
1178 rockchip->dev = dev;
1180 err = rockchip_pcie_parse_dt(rockchip);
1184 err = clk_prepare_enable(rockchip->aclk_pcie);
1186 dev_err(dev, "unable to enable aclk_pcie clock\n");
1190 err = clk_prepare_enable(rockchip->aclk_perf_pcie);
1192 dev_err(dev, "unable to enable aclk_perf_pcie clock\n");
1193 goto err_aclk_perf_pcie;
1196 err = clk_prepare_enable(rockchip->hclk_pcie);
1198 dev_err(dev, "unable to enable hclk_pcie clock\n");
1202 err = clk_prepare_enable(rockchip->clk_pcie_pm);
1204 dev_err(dev, "unable to enable hclk_pcie clock\n");
1208 err = rockchip_pcie_set_vpcie(rockchip);
1210 dev_err(dev, "failed to set vpcie regulator\n");
1214 err = rockchip_pcie_init_port(rockchip);
1218 platform_set_drvdata(pdev, rockchip);
1220 rockchip_pcie_enable_interrupts(rockchip);
1222 err = rockchip_pcie_init_irq_domain(rockchip);
1226 err = of_pci_get_host_bridge_resources(dev->of_node, 0, 0xff,
1231 err = devm_request_pci_bus_resources(dev, &res);
1235 /* Get the I/O and memory ranges from DT */
1237 resource_list_for_each_entry(win, &res) {
1238 switch (resource_type(win->res)) {
1242 io_size = resource_size(io);
1243 io_bus_addr = io->start - win->offset;
1244 err = pci_remap_iospace(io, io_base);
1246 dev_warn(dev, "error %d: failed to map resource %pR\n",
1251 case IORESOURCE_MEM:
1254 mem_size = resource_size(mem);
1255 mem_bus_addr = mem->start - win->offset;
1257 case IORESOURCE_BUS:
1258 rockchip->root_bus_nr = win->res->start;
1266 for (reg_no = 0; reg_no < (mem_size >> 20); reg_no++) {
1267 err = rockchip_pcie_prog_ob_atu(rockchip, reg_no + 1,
1268 AXI_WRAPPER_MEM_WRITE,
1274 dev_err(dev, "program RC mem outbound ATU failed\n");
1280 err = rockchip_pcie_prog_ib_atu(rockchip, 2, 32 - 1, 0x0, 0);
1282 dev_err(dev, "program RC mem inbound ATU failed\n");
1286 offset = mem_size >> 20;
1289 for (reg_no = 0; reg_no < (io_size >> 20); reg_no++) {
1290 err = rockchip_pcie_prog_ob_atu(rockchip,
1291 reg_no + 1 + offset,
1292 AXI_WRAPPER_IO_WRITE,
1298 dev_err(dev, "program RC io outbound ATU failed\n");
1304 bus = pci_scan_root_bus(&pdev->dev, 0, &rockchip_pcie_ops, rockchip, &res);
1310 pci_bus_size_bridges(bus);
1311 pci_bus_assign_resources(bus);
1312 list_for_each_entry(child, &bus->children, node)
1313 pcie_bus_configure_settings(child);
1315 pci_bus_add_devices(bus);
1317 dev_warn(dev, "only 32-bit config accesses supported; smaller writes may corrupt adjacent RW1C fields\n");
1322 if (!IS_ERR(rockchip->vpcie3v3))
1323 regulator_disable(rockchip->vpcie3v3);
1324 if (!IS_ERR(rockchip->vpcie1v8))
1325 regulator_disable(rockchip->vpcie1v8);
1326 if (!IS_ERR(rockchip->vpcie0v9))
1327 regulator_disable(rockchip->vpcie0v9);
1329 clk_disable_unprepare(rockchip->clk_pcie_pm);
1331 clk_disable_unprepare(rockchip->hclk_pcie);
1333 clk_disable_unprepare(rockchip->aclk_perf_pcie);
1335 clk_disable_unprepare(rockchip->aclk_pcie);
1340 static const struct of_device_id rockchip_pcie_of_match[] = {
1341 { .compatible = "rockchip,rk3399-pcie", },
1345 static struct platform_driver rockchip_pcie_driver = {
1347 .name = "rockchip-pcie",
1348 .of_match_table = rockchip_pcie_of_match,
1350 .probe = rockchip_pcie_probe,
1353 builtin_platform_driver(rockchip_pcie_driver);