2 * Rockchip AXI PCIe host controller driver
4 * Copyright (c) 2016 Rockchip, Inc.
6 * Author: Shawn Lin <shawn.lin@rock-chips.com>
7 * Wenrui Li <wenrui.li@rock-chips.com>
9 * Bits taken from Synopsys Designware Host controller driver and
10 * ARM PCI Host generic driver.
12 * This program is free software: you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation, either version 2 of the License, or
15 * (at your option) any later version.
18 #include <linux/clk.h>
19 #include <linux/delay.h>
20 #include <linux/gpio/consumer.h>
21 #include <linux/init.h>
22 #include <linux/interrupt.h>
23 #include <linux/irq.h>
24 #include <linux/irqchip/chained_irq.h>
25 #include <linux/irqdomain.h>
26 #include <linux/kernel.h>
27 #include <linux/mfd/syscon.h>
28 #include <linux/of_address.h>
29 #include <linux/of_device.h>
30 #include <linux/of_pci.h>
31 #include <linux/of_platform.h>
32 #include <linux/of_irq.h>
33 #include <linux/pci.h>
34 #include <linux/pci_ids.h>
35 #include <linux/phy/phy.h>
36 #include <linux/platform_device.h>
37 #include <linux/reset.h>
38 #include <linux/regmap.h>
41 * The upper 16 bits of PCIE_CLIENT_CONFIG are a write mask for the lower 16
42 * bits. This allows atomic updates of the register without locking.
44 #define HIWORD_UPDATE(mask, val) (((mask) << 16) | (val))
45 #define HIWORD_UPDATE_BIT(val) HIWORD_UPDATE(val, val)
47 #define ENCODE_LANES(x) ((((x) >> 1) & 3) << 4)
49 #define PCIE_CLIENT_BASE 0x0
50 #define PCIE_CLIENT_CONFIG (PCIE_CLIENT_BASE + 0x00)
51 #define PCIE_CLIENT_CONF_ENABLE HIWORD_UPDATE_BIT(0x0001)
52 #define PCIE_CLIENT_LINK_TRAIN_ENABLE HIWORD_UPDATE_BIT(0x0002)
53 #define PCIE_CLIENT_ARI_ENABLE HIWORD_UPDATE_BIT(0x0008)
54 #define PCIE_CLIENT_CONF_LANE_NUM(x) HIWORD_UPDATE(0x0030, ENCODE_LANES(x))
55 #define PCIE_CLIENT_MODE_RC HIWORD_UPDATE_BIT(0x0040)
56 #define PCIE_CLIENT_GEN_SEL_1 HIWORD_UPDATE(0x0080, 0)
57 #define PCIE_CLIENT_GEN_SEL_2 HIWORD_UPDATE_BIT(0x0080)
58 #define PCIE_CLIENT_BASIC_STATUS1 (PCIE_CLIENT_BASE + 0x48)
59 #define PCIE_CLIENT_LINK_STATUS_UP 0x00300000
60 #define PCIE_CLIENT_LINK_STATUS_MASK 0x00300000
61 #define PCIE_CLIENT_INT_MASK (PCIE_CLIENT_BASE + 0x4c)
62 #define PCIE_CLIENT_INT_STATUS (PCIE_CLIENT_BASE + 0x50)
63 #define PCIE_CLIENT_INTR_MASK GENMASK(8, 5)
64 #define PCIE_CLIENT_INTR_SHIFT 5
65 #define PCIE_CLIENT_INT_LEGACY_DONE BIT(15)
66 #define PCIE_CLIENT_INT_MSG BIT(14)
67 #define PCIE_CLIENT_INT_HOT_RST BIT(13)
68 #define PCIE_CLIENT_INT_DPA BIT(12)
69 #define PCIE_CLIENT_INT_FATAL_ERR BIT(11)
70 #define PCIE_CLIENT_INT_NFATAL_ERR BIT(10)
71 #define PCIE_CLIENT_INT_CORR_ERR BIT(9)
72 #define PCIE_CLIENT_INT_INTD BIT(8)
73 #define PCIE_CLIENT_INT_INTC BIT(7)
74 #define PCIE_CLIENT_INT_INTB BIT(6)
75 #define PCIE_CLIENT_INT_INTA BIT(5)
76 #define PCIE_CLIENT_INT_LOCAL BIT(4)
77 #define PCIE_CLIENT_INT_UDMA BIT(3)
78 #define PCIE_CLIENT_INT_PHY BIT(2)
79 #define PCIE_CLIENT_INT_HOT_PLUG BIT(1)
80 #define PCIE_CLIENT_INT_PWR_STCG BIT(0)
82 #define PCIE_CLIENT_INT_LEGACY \
83 (PCIE_CLIENT_INT_INTA | PCIE_CLIENT_INT_INTB | \
84 PCIE_CLIENT_INT_INTC | PCIE_CLIENT_INT_INTD)
86 #define PCIE_CLIENT_INT_CLI \
87 (PCIE_CLIENT_INT_CORR_ERR | PCIE_CLIENT_INT_NFATAL_ERR | \
88 PCIE_CLIENT_INT_FATAL_ERR | PCIE_CLIENT_INT_DPA | \
89 PCIE_CLIENT_INT_HOT_RST | PCIE_CLIENT_INT_MSG | \
90 PCIE_CLIENT_INT_LEGACY_DONE | PCIE_CLIENT_INT_LEGACY | \
93 #define PCIE_CORE_CTRL_MGMT_BASE 0x900000
94 #define PCIE_CORE_CTRL (PCIE_CORE_CTRL_MGMT_BASE + 0x000)
95 #define PCIE_CORE_PL_CONF_SPEED_5G 0x00000008
96 #define PCIE_CORE_PL_CONF_SPEED_MASK 0x00000018
97 #define PCIE_CORE_PL_CONF_LANE_MASK 0x00000006
98 #define PCIE_CORE_PL_CONF_LANE_SHIFT 1
99 #define PCIE_CORE_CTRL_PLC1 (PCIE_CORE_CTRL_MGMT_BASE + 0x004)
100 #define PCIE_CORE_CTRL_PLC1_FTS_MASK GENMASK(23, 8)
101 #define PCIE_CORE_CTRL_PLC1_FTS_SHIFT 8
102 #define PCIE_CORE_CTRL_PLC1_FTS_CNT 0xffff
103 #define PCIE_CORE_TXCREDIT_CFG1 (PCIE_CORE_CTRL_MGMT_BASE + 0x020)
104 #define PCIE_CORE_TXCREDIT_CFG1_MUI_MASK 0xFFFF0000
105 #define PCIE_CORE_TXCREDIT_CFG1_MUI_SHIFT 16
106 #define PCIE_CORE_TXCREDIT_CFG1_MUI_ENCODE(x) \
107 (((x) >> 3) << PCIE_CORE_TXCREDIT_CFG1_MUI_SHIFT)
108 #define PCIE_CORE_INT_STATUS (PCIE_CORE_CTRL_MGMT_BASE + 0x20c)
109 #define PCIE_CORE_INT_PRFPE BIT(0)
110 #define PCIE_CORE_INT_CRFPE BIT(1)
111 #define PCIE_CORE_INT_RRPE BIT(2)
112 #define PCIE_CORE_INT_PRFO BIT(3)
113 #define PCIE_CORE_INT_CRFO BIT(4)
114 #define PCIE_CORE_INT_RT BIT(5)
115 #define PCIE_CORE_INT_RTR BIT(6)
116 #define PCIE_CORE_INT_PE BIT(7)
117 #define PCIE_CORE_INT_MTR BIT(8)
118 #define PCIE_CORE_INT_UCR BIT(9)
119 #define PCIE_CORE_INT_FCE BIT(10)
120 #define PCIE_CORE_INT_CT BIT(11)
121 #define PCIE_CORE_INT_UTC BIT(18)
122 #define PCIE_CORE_INT_MMVC BIT(19)
123 #define PCIE_CORE_INT_MASK (PCIE_CORE_CTRL_MGMT_BASE + 0x210)
124 #define PCIE_RC_BAR_CONF (PCIE_CORE_CTRL_MGMT_BASE + 0x300)
126 #define PCIE_CORE_INT \
127 (PCIE_CORE_INT_PRFPE | PCIE_CORE_INT_CRFPE | \
128 PCIE_CORE_INT_RRPE | PCIE_CORE_INT_CRFO | \
129 PCIE_CORE_INT_RT | PCIE_CORE_INT_RTR | \
130 PCIE_CORE_INT_PE | PCIE_CORE_INT_MTR | \
131 PCIE_CORE_INT_UCR | PCIE_CORE_INT_FCE | \
132 PCIE_CORE_INT_CT | PCIE_CORE_INT_UTC | \
135 #define PCIE_RC_CONFIG_BASE 0xa00000
136 #define PCIE_RC_CONFIG_VENDOR (PCIE_RC_CONFIG_BASE + 0x00)
137 #define PCIE_RC_CONFIG_RID_CCR (PCIE_RC_CONFIG_BASE + 0x08)
138 #define PCIE_RC_CONFIG_SCC_SHIFT 16
139 #define PCIE_RC_CONFIG_DCR (PCIE_RC_CONFIG_BASE + 0xc4)
140 #define PCIE_RC_CONFIG_DCR_CSPL_SHIFT 18
141 #define PCIE_RC_CONFIG_DCR_CSPL_LIMIT 0xff
142 #define PCIE_RC_CONFIG_DCR_CPLS_SHIFT 26
143 #define PCIE_RC_CONFIG_LINK_CAP (PCIE_RC_CONFIG_BASE + 0xcc)
144 #define PCIE_RC_CONFIG_LINK_CAP_L0S BIT(10)
145 #define PCIE_RC_CONFIG_LCS (PCIE_RC_CONFIG_BASE + 0xd0)
146 #define PCIE_RC_CONFIG_L1_SUBSTATE_CTRL2 (PCIE_RC_CONFIG_BASE + 0x90c)
147 #define PCIE_RC_CONFIG_THP_CAP (PCIE_RC_CONFIG_BASE + 0x274)
148 #define PCIE_RC_CONFIG_THP_CAP_NEXT_MASK GENMASK(31, 20)
150 #define PCIE_CORE_AXI_CONF_BASE 0xc00000
151 #define PCIE_CORE_OB_REGION_ADDR0 (PCIE_CORE_AXI_CONF_BASE + 0x0)
152 #define PCIE_CORE_OB_REGION_ADDR0_NUM_BITS 0x3f
153 #define PCIE_CORE_OB_REGION_ADDR0_LO_ADDR 0xffffff00
154 #define PCIE_CORE_OB_REGION_ADDR1 (PCIE_CORE_AXI_CONF_BASE + 0x4)
155 #define PCIE_CORE_OB_REGION_DESC0 (PCIE_CORE_AXI_CONF_BASE + 0x8)
156 #define PCIE_CORE_OB_REGION_DESC1 (PCIE_CORE_AXI_CONF_BASE + 0xc)
158 #define PCIE_CORE_AXI_INBOUND_BASE 0xc00800
159 #define PCIE_RP_IB_ADDR0 (PCIE_CORE_AXI_INBOUND_BASE + 0x0)
160 #define PCIE_CORE_IB_REGION_ADDR0_NUM_BITS 0x3f
161 #define PCIE_CORE_IB_REGION_ADDR0_LO_ADDR 0xffffff00
162 #define PCIE_RP_IB_ADDR1 (PCIE_CORE_AXI_INBOUND_BASE + 0x4)
164 /* Size of one AXI Region (not Region 0) */
165 #define AXI_REGION_SIZE BIT(20)
166 /* Size of Region 0, equal to sum of sizes of other regions */
167 #define AXI_REGION_0_SIZE (32 * (0x1 << 20))
168 #define OB_REG_SIZE_SHIFT 5
169 #define IB_ROOT_PORT_REG_SIZE_SHIFT 3
170 #define AXI_WRAPPER_IO_WRITE 0x6
171 #define AXI_WRAPPER_MEM_WRITE 0x2
173 #define MAX_AXI_IB_ROOTPORT_REGION_NUM 3
174 #define MIN_AXI_ADDR_BITS_PASSED 8
175 #define ROCKCHIP_VENDOR_ID 0x1d87
176 #define PCIE_ECAM_BUS(x) (((x) & 0xff) << 20)
177 #define PCIE_ECAM_DEV(x) (((x) & 0x1f) << 15)
178 #define PCIE_ECAM_FUNC(x) (((x) & 0x7) << 12)
179 #define PCIE_ECAM_REG(x) (((x) & 0xfff) << 0)
180 #define PCIE_ECAM_ADDR(bus, dev, func, reg) \
181 (PCIE_ECAM_BUS(bus) | PCIE_ECAM_DEV(dev) | \
182 PCIE_ECAM_FUNC(func) | PCIE_ECAM_REG(reg))
184 #define RC_REGION_0_ADDR_TRANS_H 0x00000000
185 #define RC_REGION_0_ADDR_TRANS_L 0x00000000
186 #define RC_REGION_0_PASS_BITS (25 - 1)
187 #define MAX_AXI_WRAPPER_REGION_NUM 33
189 struct rockchip_pcie {
190 void __iomem *reg_base; /* DT axi-base */
191 void __iomem *apb_base; /* DT apb-base */
193 struct reset_control *core_rst;
194 struct reset_control *mgmt_rst;
195 struct reset_control *mgmt_sticky_rst;
196 struct reset_control *pipe_rst;
197 struct reset_control *pm_rst;
198 struct reset_control *aclk_rst;
199 struct reset_control *pclk_rst;
200 struct clk *aclk_pcie;
201 struct clk *aclk_perf_pcie;
202 struct clk *hclk_pcie;
203 struct clk *clk_pcie_pm;
204 struct regulator *vpcie3v3; /* 3.3V power supply */
205 struct regulator *vpcie1v8; /* 1.8V power supply */
206 struct regulator *vpcie0v9; /* 0.9V power supply */
207 struct gpio_desc *ep_gpio;
212 struct irq_domain *irq_domain;
215 phys_addr_t io_bus_addr;
217 phys_addr_t mem_bus_addr;
220 static u32 rockchip_pcie_read(struct rockchip_pcie *rockchip, u32 reg)
222 return readl(rockchip->apb_base + reg);
225 static void rockchip_pcie_write(struct rockchip_pcie *rockchip, u32 val,
228 writel(val, rockchip->apb_base + reg);
231 static void rockchip_pcie_enable_bw_int(struct rockchip_pcie *rockchip)
235 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS);
236 status |= (PCI_EXP_LNKCTL_LBMIE | PCI_EXP_LNKCTL_LABIE);
237 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS);
240 static void rockchip_pcie_clr_bw_int(struct rockchip_pcie *rockchip)
244 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS);
245 status |= (PCI_EXP_LNKSTA_LBMS | PCI_EXP_LNKSTA_LABS) << 16;
246 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS);
249 static void rockchip_pcie_update_txcredit_mui(struct rockchip_pcie *rockchip)
253 /* Update Tx credit maximum update interval */
254 val = rockchip_pcie_read(rockchip, PCIE_CORE_TXCREDIT_CFG1);
255 val &= ~PCIE_CORE_TXCREDIT_CFG1_MUI_MASK;
256 val |= PCIE_CORE_TXCREDIT_CFG1_MUI_ENCODE(24000); /* ns */
257 rockchip_pcie_write(rockchip, val, PCIE_CORE_TXCREDIT_CFG1);
260 static int rockchip_pcie_valid_device(struct rockchip_pcie *rockchip,
261 struct pci_bus *bus, int dev)
263 /* access only one slot on each root port */
264 if (bus->number == rockchip->root_bus_nr && dev > 0)
268 * do not read more than one device on the bus directly attached
269 * to RC's downstream side.
271 if (bus->primary == rockchip->root_bus_nr && dev > 0)
277 static int rockchip_pcie_rd_own_conf(struct rockchip_pcie *rockchip,
278 int where, int size, u32 *val)
280 void __iomem *addr = rockchip->apb_base + PCIE_RC_CONFIG_BASE + where;
282 if (!IS_ALIGNED((uintptr_t)addr, size)) {
284 return PCIBIOS_BAD_REGISTER_NUMBER;
289 } else if (size == 2) {
291 } else if (size == 1) {
295 return PCIBIOS_BAD_REGISTER_NUMBER;
297 return PCIBIOS_SUCCESSFUL;
300 static int rockchip_pcie_wr_own_conf(struct rockchip_pcie *rockchip,
301 int where, int size, u32 val)
303 u32 mask, tmp, offset;
305 offset = where & ~0x3;
308 writel(val, rockchip->apb_base + PCIE_RC_CONFIG_BASE + offset);
309 return PCIBIOS_SUCCESSFUL;
312 mask = ~(((1 << (size * 8)) - 1) << ((where & 0x3) * 8));
315 * N.B. This read/modify/write isn't safe in general because it can
316 * corrupt RW1C bits in adjacent registers. But the hardware
317 * doesn't support smaller writes.
319 tmp = readl(rockchip->apb_base + PCIE_RC_CONFIG_BASE + offset) & mask;
320 tmp |= val << ((where & 0x3) * 8);
321 writel(tmp, rockchip->apb_base + PCIE_RC_CONFIG_BASE + offset);
323 return PCIBIOS_SUCCESSFUL;
326 static int rockchip_pcie_rd_other_conf(struct rockchip_pcie *rockchip,
327 struct pci_bus *bus, u32 devfn,
328 int where, int size, u32 *val)
332 busdev = PCIE_ECAM_ADDR(bus->number, PCI_SLOT(devfn),
333 PCI_FUNC(devfn), where);
335 if (!IS_ALIGNED(busdev, size)) {
337 return PCIBIOS_BAD_REGISTER_NUMBER;
341 *val = readl(rockchip->reg_base + busdev);
342 } else if (size == 2) {
343 *val = readw(rockchip->reg_base + busdev);
344 } else if (size == 1) {
345 *val = readb(rockchip->reg_base + busdev);
348 return PCIBIOS_BAD_REGISTER_NUMBER;
350 return PCIBIOS_SUCCESSFUL;
353 static int rockchip_pcie_wr_other_conf(struct rockchip_pcie *rockchip,
354 struct pci_bus *bus, u32 devfn,
355 int where, int size, u32 val)
359 busdev = PCIE_ECAM_ADDR(bus->number, PCI_SLOT(devfn),
360 PCI_FUNC(devfn), where);
361 if (!IS_ALIGNED(busdev, size))
362 return PCIBIOS_BAD_REGISTER_NUMBER;
365 writel(val, rockchip->reg_base + busdev);
367 writew(val, rockchip->reg_base + busdev);
369 writeb(val, rockchip->reg_base + busdev);
371 return PCIBIOS_BAD_REGISTER_NUMBER;
373 return PCIBIOS_SUCCESSFUL;
376 static int rockchip_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
379 struct rockchip_pcie *rockchip = bus->sysdata;
381 if (!rockchip_pcie_valid_device(rockchip, bus, PCI_SLOT(devfn))) {
383 return PCIBIOS_DEVICE_NOT_FOUND;
386 if (bus->number == rockchip->root_bus_nr)
387 return rockchip_pcie_rd_own_conf(rockchip, where, size, val);
389 return rockchip_pcie_rd_other_conf(rockchip, bus, devfn, where, size, val);
392 static int rockchip_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
393 int where, int size, u32 val)
395 struct rockchip_pcie *rockchip = bus->sysdata;
397 if (!rockchip_pcie_valid_device(rockchip, bus, PCI_SLOT(devfn)))
398 return PCIBIOS_DEVICE_NOT_FOUND;
400 if (bus->number == rockchip->root_bus_nr)
401 return rockchip_pcie_wr_own_conf(rockchip, where, size, val);
403 return rockchip_pcie_wr_other_conf(rockchip, bus, devfn, where, size, val);
406 static struct pci_ops rockchip_pcie_ops = {
407 .read = rockchip_pcie_rd_conf,
408 .write = rockchip_pcie_wr_conf,
411 static void rockchip_pcie_set_power_limit(struct rockchip_pcie *rockchip)
413 u32 status, curr, scale, power;
415 if (IS_ERR(rockchip->vpcie3v3))
419 * Set RC's captured slot power limit and scale if
420 * vpcie3v3 available. The default values are both zero
421 * which means the software should set these two according
422 * to the actual power supply.
424 curr = regulator_get_current_limit(rockchip->vpcie3v3);
426 scale = 3; /* 0.001x */
427 curr = curr / 1000; /* convert to mA */
428 power = (curr * 3300) / 1000; /* milliwatt */
429 while (power > PCIE_RC_CONFIG_DCR_CSPL_LIMIT) {
431 dev_warn(rockchip->dev, "invalid power supply\n");
438 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_DCR);
439 status |= (power << PCIE_RC_CONFIG_DCR_CSPL_SHIFT) |
440 (scale << PCIE_RC_CONFIG_DCR_CPLS_SHIFT);
441 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_DCR);
446 * rockchip_pcie_init_port - Initialize hardware
447 * @rockchip: PCIe port information
449 static int rockchip_pcie_init_port(struct rockchip_pcie *rockchip)
451 struct device *dev = rockchip->dev;
454 unsigned long timeout;
456 gpiod_set_value(rockchip->ep_gpio, 0);
458 err = reset_control_assert(rockchip->aclk_rst);
460 dev_err(dev, "assert aclk_rst err %d\n", err);
464 err = reset_control_assert(rockchip->pclk_rst);
466 dev_err(dev, "assert pclk_rst err %d\n", err);
470 err = reset_control_assert(rockchip->pm_rst);
472 dev_err(dev, "assert pm_rst err %d\n", err);
476 err = phy_init(rockchip->phy);
478 dev_err(dev, "fail to init phy, err %d\n", err);
482 err = reset_control_assert(rockchip->core_rst);
484 dev_err(dev, "assert core_rst err %d\n", err);
488 err = reset_control_assert(rockchip->mgmt_rst);
490 dev_err(dev, "assert mgmt_rst err %d\n", err);
494 err = reset_control_assert(rockchip->mgmt_sticky_rst);
496 dev_err(dev, "assert mgmt_sticky_rst err %d\n", err);
500 err = reset_control_assert(rockchip->pipe_rst);
502 dev_err(dev, "assert pipe_rst err %d\n", err);
508 err = reset_control_deassert(rockchip->pm_rst);
510 dev_err(dev, "deassert pm_rst err %d\n", err);
514 err = reset_control_deassert(rockchip->aclk_rst);
516 dev_err(dev, "deassert aclk_rst err %d\n", err);
520 err = reset_control_deassert(rockchip->pclk_rst);
522 dev_err(dev, "deassert pclk_rst err %d\n", err);
526 if (rockchip->link_gen == 2)
527 rockchip_pcie_write(rockchip, PCIE_CLIENT_GEN_SEL_2,
530 rockchip_pcie_write(rockchip, PCIE_CLIENT_GEN_SEL_1,
533 rockchip_pcie_write(rockchip,
534 PCIE_CLIENT_CONF_ENABLE |
535 PCIE_CLIENT_LINK_TRAIN_ENABLE |
536 PCIE_CLIENT_ARI_ENABLE |
537 PCIE_CLIENT_CONF_LANE_NUM(rockchip->lanes) |
541 err = phy_power_on(rockchip->phy);
543 dev_err(dev, "fail to power on phy, err %d\n", err);
548 * Please don't reorder the deassert sequence of the following
551 err = reset_control_deassert(rockchip->mgmt_sticky_rst);
553 dev_err(dev, "deassert mgmt_sticky_rst err %d\n", err);
557 err = reset_control_deassert(rockchip->core_rst);
559 dev_err(dev, "deassert core_rst err %d\n", err);
563 err = reset_control_deassert(rockchip->mgmt_rst);
565 dev_err(dev, "deassert mgmt_rst err %d\n", err);
569 err = reset_control_deassert(rockchip->pipe_rst);
571 dev_err(dev, "deassert pipe_rst err %d\n", err);
575 /* Fix the transmitted FTS count desired to exit from L0s. */
576 status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL_PLC1);
577 status = (status & ~PCIE_CORE_CTRL_PLC1_FTS_MASK) |
578 (PCIE_CORE_CTRL_PLC1_FTS_CNT << PCIE_CORE_CTRL_PLC1_FTS_SHIFT);
579 rockchip_pcie_write(rockchip, status, PCIE_CORE_CTRL_PLC1);
581 rockchip_pcie_set_power_limit(rockchip);
583 /* Set RC's clock architecture as common clock */
584 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS);
585 status |= PCI_EXP_LNKCTL_CCC;
586 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS);
588 /* Enable Gen1 training */
589 rockchip_pcie_write(rockchip, PCIE_CLIENT_LINK_TRAIN_ENABLE,
592 gpiod_set_value(rockchip->ep_gpio, 1);
594 /* 500ms timeout value should be enough for Gen1/2 training */
595 timeout = jiffies + msecs_to_jiffies(500);
598 status = rockchip_pcie_read(rockchip,
599 PCIE_CLIENT_BASIC_STATUS1);
600 if ((status & PCIE_CLIENT_LINK_STATUS_MASK) ==
601 PCIE_CLIENT_LINK_STATUS_UP) {
602 dev_dbg(dev, "PCIe link training gen1 pass!\n");
606 if (time_after(jiffies, timeout)) {
607 dev_err(dev, "PCIe link training gen1 timeout!\n");
614 if (rockchip->link_gen == 2) {
616 * Enable retrain for gen2. This should be configured only after
619 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LCS);
620 status |= PCI_EXP_LNKCTL_RL;
621 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LCS);
623 timeout = jiffies + msecs_to_jiffies(500);
625 status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL);
626 if ((status & PCIE_CORE_PL_CONF_SPEED_MASK) ==
627 PCIE_CORE_PL_CONF_SPEED_5G) {
628 dev_dbg(dev, "PCIe link training gen2 pass!\n");
632 if (time_after(jiffies, timeout)) {
633 dev_dbg(dev, "PCIe link training gen2 timeout, fall back to gen1!\n");
641 /* Check the final link width from negotiated lane counter from MGMT */
642 status = rockchip_pcie_read(rockchip, PCIE_CORE_CTRL);
643 status = 0x1 << ((status & PCIE_CORE_PL_CONF_LANE_MASK) >>
644 PCIE_CORE_PL_CONF_LANE_SHIFT);
645 dev_dbg(dev, "current link width is x%d\n", status);
647 rockchip_pcie_write(rockchip, ROCKCHIP_VENDOR_ID,
648 PCIE_RC_CONFIG_VENDOR);
649 rockchip_pcie_write(rockchip,
650 PCI_CLASS_BRIDGE_PCI << PCIE_RC_CONFIG_SCC_SHIFT,
651 PCIE_RC_CONFIG_RID_CCR);
653 /* Clear THP cap's next cap pointer to remove L1 substate cap */
654 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_THP_CAP);
655 status &= ~PCIE_RC_CONFIG_THP_CAP_NEXT_MASK;
656 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_THP_CAP);
658 /* Clear L0s from RC's link cap */
659 if (of_property_read_bool(dev->of_node, "quirk,apsm-no-l0s")) {
660 status = rockchip_pcie_read(rockchip, PCIE_RC_CONFIG_LINK_CAP);
661 status &= ~PCIE_RC_CONFIG_LINK_CAP_L0S;
662 rockchip_pcie_write(rockchip, status, PCIE_RC_CONFIG_LINK_CAP);
665 rockchip_pcie_write(rockchip, 0x0, PCIE_RC_BAR_CONF);
667 rockchip_pcie_write(rockchip,
668 (RC_REGION_0_ADDR_TRANS_L + RC_REGION_0_PASS_BITS),
669 PCIE_CORE_OB_REGION_ADDR0);
670 rockchip_pcie_write(rockchip, RC_REGION_0_ADDR_TRANS_H,
671 PCIE_CORE_OB_REGION_ADDR1);
672 rockchip_pcie_write(rockchip, 0x0080000a, PCIE_CORE_OB_REGION_DESC0);
673 rockchip_pcie_write(rockchip, 0x0, PCIE_CORE_OB_REGION_DESC1);
678 static irqreturn_t rockchip_pcie_subsys_irq_handler(int irq, void *arg)
680 struct rockchip_pcie *rockchip = arg;
681 struct device *dev = rockchip->dev;
685 reg = rockchip_pcie_read(rockchip, PCIE_CLIENT_INT_STATUS);
686 if (reg & PCIE_CLIENT_INT_LOCAL) {
687 dev_dbg(dev, "local interrupt received\n");
688 sub_reg = rockchip_pcie_read(rockchip, PCIE_CORE_INT_STATUS);
689 if (sub_reg & PCIE_CORE_INT_PRFPE)
690 dev_dbg(dev, "parity error detected while reading from the PNP receive FIFO RAM\n");
692 if (sub_reg & PCIE_CORE_INT_CRFPE)
693 dev_dbg(dev, "parity error detected while reading from the Completion Receive FIFO RAM\n");
695 if (sub_reg & PCIE_CORE_INT_RRPE)
696 dev_dbg(dev, "parity error detected while reading from replay buffer RAM\n");
698 if (sub_reg & PCIE_CORE_INT_PRFO)
699 dev_dbg(dev, "overflow occurred in the PNP receive FIFO\n");
701 if (sub_reg & PCIE_CORE_INT_CRFO)
702 dev_dbg(dev, "overflow occurred in the completion receive FIFO\n");
704 if (sub_reg & PCIE_CORE_INT_RT)
705 dev_dbg(dev, "replay timer timed out\n");
707 if (sub_reg & PCIE_CORE_INT_RTR)
708 dev_dbg(dev, "replay timer rolled over after 4 transmissions of the same TLP\n");
710 if (sub_reg & PCIE_CORE_INT_PE)
711 dev_dbg(dev, "phy error detected on receive side\n");
713 if (sub_reg & PCIE_CORE_INT_MTR)
714 dev_dbg(dev, "malformed TLP received from the link\n");
716 if (sub_reg & PCIE_CORE_INT_UCR)
717 dev_dbg(dev, "malformed TLP received from the link\n");
719 if (sub_reg & PCIE_CORE_INT_FCE)
720 dev_dbg(dev, "an error was observed in the flow control advertisements from the other side\n");
722 if (sub_reg & PCIE_CORE_INT_CT)
723 dev_dbg(dev, "a request timed out waiting for completion\n");
725 if (sub_reg & PCIE_CORE_INT_UTC)
726 dev_dbg(dev, "unmapped TC error\n");
728 if (sub_reg & PCIE_CORE_INT_MMVC)
729 dev_dbg(dev, "MSI mask register changes\n");
731 rockchip_pcie_write(rockchip, sub_reg, PCIE_CORE_INT_STATUS);
732 } else if (reg & PCIE_CLIENT_INT_PHY) {
733 dev_dbg(dev, "phy link changes\n");
734 rockchip_pcie_update_txcredit_mui(rockchip);
735 rockchip_pcie_clr_bw_int(rockchip);
738 rockchip_pcie_write(rockchip, reg & PCIE_CLIENT_INT_LOCAL,
739 PCIE_CLIENT_INT_STATUS);
744 static irqreturn_t rockchip_pcie_client_irq_handler(int irq, void *arg)
746 struct rockchip_pcie *rockchip = arg;
747 struct device *dev = rockchip->dev;
750 reg = rockchip_pcie_read(rockchip, PCIE_CLIENT_INT_STATUS);
751 if (reg & PCIE_CLIENT_INT_LEGACY_DONE)
752 dev_dbg(dev, "legacy done interrupt received\n");
754 if (reg & PCIE_CLIENT_INT_MSG)
755 dev_dbg(dev, "message done interrupt received\n");
757 if (reg & PCIE_CLIENT_INT_HOT_RST)
758 dev_dbg(dev, "hot reset interrupt received\n");
760 if (reg & PCIE_CLIENT_INT_DPA)
761 dev_dbg(dev, "dpa interrupt received\n");
763 if (reg & PCIE_CLIENT_INT_FATAL_ERR)
764 dev_dbg(dev, "fatal error interrupt received\n");
766 if (reg & PCIE_CLIENT_INT_NFATAL_ERR)
767 dev_dbg(dev, "no fatal error interrupt received\n");
769 if (reg & PCIE_CLIENT_INT_CORR_ERR)
770 dev_dbg(dev, "correctable error interrupt received\n");
772 if (reg & PCIE_CLIENT_INT_PHY)
773 dev_dbg(dev, "phy interrupt received\n");
775 rockchip_pcie_write(rockchip, reg & (PCIE_CLIENT_INT_LEGACY_DONE |
776 PCIE_CLIENT_INT_MSG | PCIE_CLIENT_INT_HOT_RST |
777 PCIE_CLIENT_INT_DPA | PCIE_CLIENT_INT_FATAL_ERR |
778 PCIE_CLIENT_INT_NFATAL_ERR |
779 PCIE_CLIENT_INT_CORR_ERR |
780 PCIE_CLIENT_INT_PHY),
781 PCIE_CLIENT_INT_STATUS);
786 static void rockchip_pcie_legacy_int_handler(struct irq_desc *desc)
788 struct irq_chip *chip = irq_desc_get_chip(desc);
789 struct rockchip_pcie *rockchip = irq_desc_get_handler_data(desc);
790 struct device *dev = rockchip->dev;
795 chained_irq_enter(chip, desc);
797 reg = rockchip_pcie_read(rockchip, PCIE_CLIENT_INT_STATUS);
798 reg = (reg & PCIE_CLIENT_INTR_MASK) >> PCIE_CLIENT_INTR_SHIFT;
801 hwirq = ffs(reg) - 1;
804 virq = irq_find_mapping(rockchip->irq_domain, hwirq);
806 generic_handle_irq(virq);
808 dev_err(dev, "unexpected IRQ, INT%d\n", hwirq);
811 chained_irq_exit(chip, desc);
816 * rockchip_pcie_parse_dt - Parse Device Tree
817 * @rockchip: PCIe port information
819 * Return: '0' on success and error value on failure
821 static int rockchip_pcie_parse_dt(struct rockchip_pcie *rockchip)
823 struct device *dev = rockchip->dev;
824 struct platform_device *pdev = to_platform_device(dev);
825 struct device_node *node = dev->of_node;
826 struct resource *regs;
830 regs = platform_get_resource_byname(pdev,
833 rockchip->reg_base = devm_ioremap_resource(dev, regs);
834 if (IS_ERR(rockchip->reg_base))
835 return PTR_ERR(rockchip->reg_base);
837 regs = platform_get_resource_byname(pdev,
840 rockchip->apb_base = devm_ioremap_resource(dev, regs);
841 if (IS_ERR(rockchip->apb_base))
842 return PTR_ERR(rockchip->apb_base);
844 rockchip->phy = devm_phy_get(dev, "pcie-phy");
845 if (IS_ERR(rockchip->phy)) {
846 if (PTR_ERR(rockchip->phy) != -EPROBE_DEFER)
847 dev_err(dev, "missing phy\n");
848 return PTR_ERR(rockchip->phy);
852 err = of_property_read_u32(node, "num-lanes", &rockchip->lanes);
853 if (!err && (rockchip->lanes == 0 ||
854 rockchip->lanes == 3 ||
855 rockchip->lanes > 4)) {
856 dev_warn(dev, "invalid num-lanes, default to use one lane\n");
860 rockchip->link_gen = of_pci_get_max_link_speed(node);
861 if (rockchip->link_gen < 0 || rockchip->link_gen > 2)
862 rockchip->link_gen = 2;
864 rockchip->core_rst = devm_reset_control_get(dev, "core");
865 if (IS_ERR(rockchip->core_rst)) {
866 if (PTR_ERR(rockchip->core_rst) != -EPROBE_DEFER)
867 dev_err(dev, "missing core reset property in node\n");
868 return PTR_ERR(rockchip->core_rst);
871 rockchip->mgmt_rst = devm_reset_control_get(dev, "mgmt");
872 if (IS_ERR(rockchip->mgmt_rst)) {
873 if (PTR_ERR(rockchip->mgmt_rst) != -EPROBE_DEFER)
874 dev_err(dev, "missing mgmt reset property in node\n");
875 return PTR_ERR(rockchip->mgmt_rst);
878 rockchip->mgmt_sticky_rst = devm_reset_control_get(dev, "mgmt-sticky");
879 if (IS_ERR(rockchip->mgmt_sticky_rst)) {
880 if (PTR_ERR(rockchip->mgmt_sticky_rst) != -EPROBE_DEFER)
881 dev_err(dev, "missing mgmt-sticky reset property in node\n");
882 return PTR_ERR(rockchip->mgmt_sticky_rst);
885 rockchip->pipe_rst = devm_reset_control_get(dev, "pipe");
886 if (IS_ERR(rockchip->pipe_rst)) {
887 if (PTR_ERR(rockchip->pipe_rst) != -EPROBE_DEFER)
888 dev_err(dev, "missing pipe reset property in node\n");
889 return PTR_ERR(rockchip->pipe_rst);
892 rockchip->pm_rst = devm_reset_control_get(dev, "pm");
893 if (IS_ERR(rockchip->pm_rst)) {
894 if (PTR_ERR(rockchip->pm_rst) != -EPROBE_DEFER)
895 dev_err(dev, "missing pm reset property in node\n");
896 return PTR_ERR(rockchip->pm_rst);
899 rockchip->pclk_rst = devm_reset_control_get(dev, "pclk");
900 if (IS_ERR(rockchip->pclk_rst)) {
901 if (PTR_ERR(rockchip->pclk_rst) != -EPROBE_DEFER)
902 dev_err(dev, "missing pclk reset property in node\n");
903 return PTR_ERR(rockchip->pclk_rst);
906 rockchip->aclk_rst = devm_reset_control_get(dev, "aclk");
907 if (IS_ERR(rockchip->aclk_rst)) {
908 if (PTR_ERR(rockchip->aclk_rst) != -EPROBE_DEFER)
909 dev_err(dev, "missing aclk reset property in node\n");
910 return PTR_ERR(rockchip->aclk_rst);
913 rockchip->ep_gpio = devm_gpiod_get(dev, "ep", GPIOD_OUT_HIGH);
914 if (IS_ERR(rockchip->ep_gpio)) {
915 dev_err(dev, "missing ep-gpios property in node\n");
916 return PTR_ERR(rockchip->ep_gpio);
919 rockchip->aclk_pcie = devm_clk_get(dev, "aclk");
920 if (IS_ERR(rockchip->aclk_pcie)) {
921 dev_err(dev, "aclk clock not found\n");
922 return PTR_ERR(rockchip->aclk_pcie);
925 rockchip->aclk_perf_pcie = devm_clk_get(dev, "aclk-perf");
926 if (IS_ERR(rockchip->aclk_perf_pcie)) {
927 dev_err(dev, "aclk_perf clock not found\n");
928 return PTR_ERR(rockchip->aclk_perf_pcie);
931 rockchip->hclk_pcie = devm_clk_get(dev, "hclk");
932 if (IS_ERR(rockchip->hclk_pcie)) {
933 dev_err(dev, "hclk clock not found\n");
934 return PTR_ERR(rockchip->hclk_pcie);
937 rockchip->clk_pcie_pm = devm_clk_get(dev, "pm");
938 if (IS_ERR(rockchip->clk_pcie_pm)) {
939 dev_err(dev, "pm clock not found\n");
940 return PTR_ERR(rockchip->clk_pcie_pm);
943 irq = platform_get_irq_byname(pdev, "sys");
945 dev_err(dev, "missing sys IRQ resource\n");
949 err = devm_request_irq(dev, irq, rockchip_pcie_subsys_irq_handler,
950 IRQF_SHARED, "pcie-sys", rockchip);
952 dev_err(dev, "failed to request PCIe subsystem IRQ\n");
956 irq = platform_get_irq_byname(pdev, "legacy");
958 dev_err(dev, "missing legacy IRQ resource\n");
962 irq_set_chained_handler_and_data(irq,
963 rockchip_pcie_legacy_int_handler,
966 irq = platform_get_irq_byname(pdev, "client");
968 dev_err(dev, "missing client IRQ resource\n");
972 err = devm_request_irq(dev, irq, rockchip_pcie_client_irq_handler,
973 IRQF_SHARED, "pcie-client", rockchip);
975 dev_err(dev, "failed to request PCIe client IRQ\n");
979 rockchip->vpcie3v3 = devm_regulator_get_optional(dev, "vpcie3v3");
980 if (IS_ERR(rockchip->vpcie3v3)) {
981 if (PTR_ERR(rockchip->vpcie3v3) == -EPROBE_DEFER)
982 return -EPROBE_DEFER;
983 dev_info(dev, "no vpcie3v3 regulator found\n");
986 rockchip->vpcie1v8 = devm_regulator_get_optional(dev, "vpcie1v8");
987 if (IS_ERR(rockchip->vpcie1v8)) {
988 if (PTR_ERR(rockchip->vpcie1v8) == -EPROBE_DEFER)
989 return -EPROBE_DEFER;
990 dev_info(dev, "no vpcie1v8 regulator found\n");
993 rockchip->vpcie0v9 = devm_regulator_get_optional(dev, "vpcie0v9");
994 if (IS_ERR(rockchip->vpcie0v9)) {
995 if (PTR_ERR(rockchip->vpcie0v9) == -EPROBE_DEFER)
996 return -EPROBE_DEFER;
997 dev_info(dev, "no vpcie0v9 regulator found\n");
1003 static int rockchip_pcie_set_vpcie(struct rockchip_pcie *rockchip)
1005 struct device *dev = rockchip->dev;
1008 if (!IS_ERR(rockchip->vpcie3v3)) {
1009 err = regulator_enable(rockchip->vpcie3v3);
1011 dev_err(dev, "fail to enable vpcie3v3 regulator\n");
1016 if (!IS_ERR(rockchip->vpcie1v8)) {
1017 err = regulator_enable(rockchip->vpcie1v8);
1019 dev_err(dev, "fail to enable vpcie1v8 regulator\n");
1020 goto err_disable_3v3;
1024 if (!IS_ERR(rockchip->vpcie0v9)) {
1025 err = regulator_enable(rockchip->vpcie0v9);
1027 dev_err(dev, "fail to enable vpcie0v9 regulator\n");
1028 goto err_disable_1v8;
1035 if (!IS_ERR(rockchip->vpcie1v8))
1036 regulator_disable(rockchip->vpcie1v8);
1038 if (!IS_ERR(rockchip->vpcie3v3))
1039 regulator_disable(rockchip->vpcie3v3);
1044 static void rockchip_pcie_enable_interrupts(struct rockchip_pcie *rockchip)
1046 rockchip_pcie_write(rockchip, (PCIE_CLIENT_INT_CLI << 16) &
1047 (~PCIE_CLIENT_INT_CLI), PCIE_CLIENT_INT_MASK);
1048 rockchip_pcie_write(rockchip, (u32)(~PCIE_CORE_INT),
1049 PCIE_CORE_INT_MASK);
1051 rockchip_pcie_enable_bw_int(rockchip);
1054 static int rockchip_pcie_intx_map(struct irq_domain *domain, unsigned int irq,
1055 irq_hw_number_t hwirq)
1057 irq_set_chip_and_handler(irq, &dummy_irq_chip, handle_simple_irq);
1058 irq_set_chip_data(irq, domain->host_data);
1063 static const struct irq_domain_ops intx_domain_ops = {
1064 .map = rockchip_pcie_intx_map,
1067 static int rockchip_pcie_init_irq_domain(struct rockchip_pcie *rockchip)
1069 struct device *dev = rockchip->dev;
1070 struct device_node *intc = of_get_next_child(dev->of_node, NULL);
1073 dev_err(dev, "missing child interrupt-controller node\n");
1077 rockchip->irq_domain = irq_domain_add_linear(intc, 4,
1078 &intx_domain_ops, rockchip);
1079 if (!rockchip->irq_domain) {
1080 dev_err(dev, "failed to get a INTx IRQ domain\n");
1087 static int rockchip_pcie_prog_ob_atu(struct rockchip_pcie *rockchip,
1088 int region_no, int type, u8 num_pass_bits,
1089 u32 lower_addr, u32 upper_addr)
1096 if (region_no >= MAX_AXI_WRAPPER_REGION_NUM)
1098 if (num_pass_bits + 1 < 8)
1100 if (num_pass_bits > 63)
1102 if (region_no == 0) {
1103 if (AXI_REGION_0_SIZE < (2ULL << num_pass_bits))
1106 if (region_no != 0) {
1107 if (AXI_REGION_SIZE < (2ULL << num_pass_bits))
1111 aw_offset = (region_no << OB_REG_SIZE_SHIFT);
1113 ob_addr_0 = num_pass_bits & PCIE_CORE_OB_REGION_ADDR0_NUM_BITS;
1114 ob_addr_0 |= lower_addr & PCIE_CORE_OB_REGION_ADDR0_LO_ADDR;
1115 ob_addr_1 = upper_addr;
1116 ob_desc_0 = (1 << 23 | type);
1118 rockchip_pcie_write(rockchip, ob_addr_0,
1119 PCIE_CORE_OB_REGION_ADDR0 + aw_offset);
1120 rockchip_pcie_write(rockchip, ob_addr_1,
1121 PCIE_CORE_OB_REGION_ADDR1 + aw_offset);
1122 rockchip_pcie_write(rockchip, ob_desc_0,
1123 PCIE_CORE_OB_REGION_DESC0 + aw_offset);
1124 rockchip_pcie_write(rockchip, 0,
1125 PCIE_CORE_OB_REGION_DESC1 + aw_offset);
1130 static int rockchip_pcie_prog_ib_atu(struct rockchip_pcie *rockchip,
1131 int region_no, u8 num_pass_bits,
1132 u32 lower_addr, u32 upper_addr)
1138 if (region_no > MAX_AXI_IB_ROOTPORT_REGION_NUM)
1140 if (num_pass_bits + 1 < MIN_AXI_ADDR_BITS_PASSED)
1142 if (num_pass_bits > 63)
1145 aw_offset = (region_no << IB_ROOT_PORT_REG_SIZE_SHIFT);
1147 ib_addr_0 = num_pass_bits & PCIE_CORE_IB_REGION_ADDR0_NUM_BITS;
1148 ib_addr_0 |= (lower_addr << 8) & PCIE_CORE_IB_REGION_ADDR0_LO_ADDR;
1149 ib_addr_1 = upper_addr;
1151 rockchip_pcie_write(rockchip, ib_addr_0, PCIE_RP_IB_ADDR0 + aw_offset);
1152 rockchip_pcie_write(rockchip, ib_addr_1, PCIE_RP_IB_ADDR1 + aw_offset);
1157 static int rockchip_cfg_atu(struct rockchip_pcie *rockchip)
1163 for (reg_no = 0; reg_no < (rockchip->mem_size >> 20); reg_no++) {
1164 err = rockchip_pcie_prog_ob_atu(rockchip, reg_no + 1,
1165 AXI_WRAPPER_MEM_WRITE,
1167 rockchip->mem_bus_addr +
1171 dev_err(rockchip->dev,
1172 "program RC mem outbound ATU failed\n");
1177 err = rockchip_pcie_prog_ib_atu(rockchip, 2, 32 - 1, 0x0, 0);
1179 dev_err(rockchip->dev, "program RC mem inbound ATU failed\n");
1183 offset = rockchip->mem_size >> 20;
1184 for (reg_no = 0; reg_no < (rockchip->io_size >> 20); reg_no++) {
1185 err = rockchip_pcie_prog_ob_atu(rockchip,
1186 reg_no + 1 + offset,
1187 AXI_WRAPPER_IO_WRITE,
1189 rockchip->io_bus_addr +
1193 dev_err(rockchip->dev,
1194 "program RC io outbound ATU failed\n");
1201 static int rockchip_pcie_probe(struct platform_device *pdev)
1203 struct rockchip_pcie *rockchip;
1204 struct device *dev = &pdev->dev;
1205 struct pci_bus *bus, *child;
1206 struct resource_entry *win;
1207 resource_size_t io_base;
1208 struct resource *mem;
1209 struct resource *io;
1217 rockchip = devm_kzalloc(dev, sizeof(*rockchip), GFP_KERNEL);
1221 rockchip->dev = dev;
1223 err = rockchip_pcie_parse_dt(rockchip);
1227 err = clk_prepare_enable(rockchip->aclk_pcie);
1229 dev_err(dev, "unable to enable aclk_pcie clock\n");
1233 err = clk_prepare_enable(rockchip->aclk_perf_pcie);
1235 dev_err(dev, "unable to enable aclk_perf_pcie clock\n");
1236 goto err_aclk_perf_pcie;
1239 err = clk_prepare_enable(rockchip->hclk_pcie);
1241 dev_err(dev, "unable to enable hclk_pcie clock\n");
1245 err = clk_prepare_enable(rockchip->clk_pcie_pm);
1247 dev_err(dev, "unable to enable hclk_pcie clock\n");
1251 err = rockchip_pcie_set_vpcie(rockchip);
1253 dev_err(dev, "failed to set vpcie regulator\n");
1257 err = rockchip_pcie_init_port(rockchip);
1261 platform_set_drvdata(pdev, rockchip);
1263 rockchip_pcie_enable_interrupts(rockchip);
1265 err = rockchip_pcie_init_irq_domain(rockchip);
1269 err = of_pci_get_host_bridge_resources(dev->of_node, 0, 0xff,
1274 err = devm_request_pci_bus_resources(dev, &res);
1278 /* Get the I/O and memory ranges from DT */
1279 resource_list_for_each_entry(win, &res) {
1280 switch (resource_type(win->res)) {
1284 rockchip->io_size = resource_size(io);
1285 rockchip->io_bus_addr = io->start - win->offset;
1286 err = pci_remap_iospace(io, io_base);
1288 dev_warn(dev, "error %d: failed to map resource %pR\n",
1293 case IORESOURCE_MEM:
1296 rockchip->mem_size = resource_size(mem);
1297 rockchip->mem_bus_addr = mem->start - win->offset;
1299 case IORESOURCE_BUS:
1300 rockchip->root_bus_nr = win->res->start;
1307 err = rockchip_cfg_atu(rockchip);
1310 bus = pci_scan_root_bus(&pdev->dev, 0, &rockchip_pcie_ops, rockchip, &res);
1316 pci_bus_size_bridges(bus);
1317 pci_bus_assign_resources(bus);
1318 list_for_each_entry(child, &bus->children, node)
1319 pcie_bus_configure_settings(child);
1321 pci_bus_add_devices(bus);
1323 dev_warn(dev, "only 32-bit config accesses supported; smaller writes may corrupt adjacent RW1C fields\n");
1328 if (!IS_ERR(rockchip->vpcie3v3))
1329 regulator_disable(rockchip->vpcie3v3);
1330 if (!IS_ERR(rockchip->vpcie1v8))
1331 regulator_disable(rockchip->vpcie1v8);
1332 if (!IS_ERR(rockchip->vpcie0v9))
1333 regulator_disable(rockchip->vpcie0v9);
1335 clk_disable_unprepare(rockchip->clk_pcie_pm);
1337 clk_disable_unprepare(rockchip->hclk_pcie);
1339 clk_disable_unprepare(rockchip->aclk_perf_pcie);
1341 clk_disable_unprepare(rockchip->aclk_pcie);
1346 static const struct of_device_id rockchip_pcie_of_match[] = {
1347 { .compatible = "rockchip,rk3399-pcie", },
1351 static struct platform_driver rockchip_pcie_driver = {
1353 .name = "rockchip-pcie",
1354 .of_match_table = rockchip_pcie_of_match,
1356 .probe = rockchip_pcie_probe,
1359 builtin_platform_driver(rockchip_pcie_driver);