2 * Synopsys Designware PCIe host controller driver
4 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
7 * Author: Jingoo Han <jg1.han@samsung.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/irq.h>
15 #include <linux/irqdomain.h>
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/msi.h>
19 #include <linux/of_address.h>
20 #include <linux/of_pci.h>
21 #include <linux/pci.h>
22 #include <linux/pci_regs.h>
23 #include <linux/types.h>
25 #include "pcie-designware.h"
27 /* Synopsis specific PCIE configuration registers */
28 #define PCIE_PORT_LINK_CONTROL 0x710
29 #define PORT_LINK_MODE_MASK (0x3f << 16)
30 #define PORT_LINK_MODE_1_LANES (0x1 << 16)
31 #define PORT_LINK_MODE_2_LANES (0x3 << 16)
32 #define PORT_LINK_MODE_4_LANES (0x7 << 16)
34 #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
35 #define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
36 #define PORT_LOGIC_LINK_WIDTH_MASK (0x1ff << 8)
37 #define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8)
38 #define PORT_LOGIC_LINK_WIDTH_2_LANES (0x2 << 8)
39 #define PORT_LOGIC_LINK_WIDTH_4_LANES (0x4 << 8)
41 #define PCIE_MSI_ADDR_LO 0x820
42 #define PCIE_MSI_ADDR_HI 0x824
43 #define PCIE_MSI_INTR0_ENABLE 0x828
44 #define PCIE_MSI_INTR0_MASK 0x82C
45 #define PCIE_MSI_INTR0_STATUS 0x830
47 #define PCIE_ATU_VIEWPORT 0x900
48 #define PCIE_ATU_REGION_INBOUND (0x1 << 31)
49 #define PCIE_ATU_REGION_OUTBOUND (0x0 << 31)
50 #define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
51 #define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
52 #define PCIE_ATU_CR1 0x904
53 #define PCIE_ATU_TYPE_MEM (0x0 << 0)
54 #define PCIE_ATU_TYPE_IO (0x2 << 0)
55 #define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
56 #define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
57 #define PCIE_ATU_CR2 0x908
58 #define PCIE_ATU_ENABLE (0x1 << 31)
59 #define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
60 #define PCIE_ATU_LOWER_BASE 0x90C
61 #define PCIE_ATU_UPPER_BASE 0x910
62 #define PCIE_ATU_LIMIT 0x914
63 #define PCIE_ATU_LOWER_TARGET 0x918
64 #define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
65 #define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
66 #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
67 #define PCIE_ATU_UPPER_TARGET 0x91C
69 static struct hw_pci dw_pci;
71 static unsigned long global_io_offset;
73 static inline struct pcie_port *sys_to_pcie(struct pci_sys_data *sys)
75 return sys->private_data;
78 int dw_pcie_cfg_read(void __iomem *addr, int where, int size, u32 *val)
83 *val = (*val >> (8 * (where & 3))) & 0xff;
85 *val = (*val >> (8 * (where & 3))) & 0xffff;
87 return PCIBIOS_BAD_REGISTER_NUMBER;
89 return PCIBIOS_SUCCESSFUL;
92 int dw_pcie_cfg_write(void __iomem *addr, int where, int size, u32 val)
97 writew(val, addr + (where & 2));
99 writeb(val, addr + (where & 3));
101 return PCIBIOS_BAD_REGISTER_NUMBER;
103 return PCIBIOS_SUCCESSFUL;
106 static inline void dw_pcie_readl_rc(struct pcie_port *pp, u32 reg, u32 *val)
108 if (pp->ops->readl_rc)
109 pp->ops->readl_rc(pp, pp->dbi_base + reg, val);
111 *val = readl(pp->dbi_base + reg);
114 static inline void dw_pcie_writel_rc(struct pcie_port *pp, u32 val, u32 reg)
116 if (pp->ops->writel_rc)
117 pp->ops->writel_rc(pp, val, pp->dbi_base + reg);
119 writel(val, pp->dbi_base + reg);
122 static int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
127 if (pp->ops->rd_own_conf)
128 ret = pp->ops->rd_own_conf(pp, where, size, val);
130 ret = dw_pcie_cfg_read(pp->dbi_base + (where & ~0x3), where,
136 static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
141 if (pp->ops->wr_own_conf)
142 ret = pp->ops->wr_own_conf(pp, where, size, val);
144 ret = dw_pcie_cfg_write(pp->dbi_base + (where & ~0x3), where,
150 static struct irq_chip dw_msi_irq_chip = {
152 .irq_enable = unmask_msi_irq,
153 .irq_disable = mask_msi_irq,
154 .irq_mask = mask_msi_irq,
155 .irq_unmask = unmask_msi_irq,
158 /* MSI int handler */
159 irqreturn_t dw_handle_msi_irq(struct pcie_port *pp)
163 irqreturn_t ret = IRQ_NONE;
165 for (i = 0; i < MAX_MSI_CTRLS; i++) {
166 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_STATUS + i * 12, 4,
171 while ((pos = find_next_bit(&val, 32, pos)) != 32) {
172 irq = irq_find_mapping(pp->irq_domain,
174 dw_pcie_wr_own_conf(pp,
175 PCIE_MSI_INTR0_STATUS + i * 12,
177 generic_handle_irq(irq);
186 void dw_pcie_msi_init(struct pcie_port *pp)
188 pp->msi_data = __get_free_pages(GFP_KERNEL, 0);
190 /* program the msi_data */
191 dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_LO, 4,
192 virt_to_phys((void *)pp->msi_data));
193 dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4, 0);
196 static int find_valid_pos0(struct pcie_port *pp, int msgvec, int pos, int *pos0)
201 pos = find_next_zero_bit(pp->msi_irq_in_use,
203 /*if you have reached to the end then get out from here.*/
204 if (pos == MAX_MSI_IRQS)
207 * Check if this position is at correct offset.nvec is always a
208 * power of two. pos0 must be nvec bit aligned.
211 pos += msgvec - (pos % msgvec);
220 static void clear_irq_range(struct pcie_port *pp, unsigned int irq_base,
221 unsigned int nvec, unsigned int pos)
223 unsigned int i, res, bit, val;
225 for (i = 0; i < nvec; i++) {
226 irq_set_msi_desc_off(irq_base, i, NULL);
227 clear_bit(pos + i, pp->msi_irq_in_use);
228 /* Disable corresponding interrupt on MSI controller */
229 res = ((pos + i) / 32) * 12;
230 bit = (pos + i) % 32;
231 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val);
233 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val);
237 static int assign_irq(int no_irqs, struct msi_desc *desc, int *pos)
239 int res, bit, irq, pos0, pos1, i;
241 struct pcie_port *pp = sys_to_pcie(desc->dev->bus->sysdata);
248 pos0 = find_first_zero_bit(pp->msi_irq_in_use,
250 if (pos0 % no_irqs) {
251 if (find_valid_pos0(pp, no_irqs, pos0, &pos0))
255 pos1 = find_next_bit(pp->msi_irq_in_use,
257 /* there must be nvec number of consecutive free bits */
258 while ((pos1 - pos0) < no_irqs) {
259 if (find_valid_pos0(pp, no_irqs, pos1, &pos0))
261 pos1 = find_next_bit(pp->msi_irq_in_use,
266 irq = irq_find_mapping(pp->irq_domain, pos0);
271 * irq_create_mapping (called from dw_pcie_host_init) pre-allocates
272 * descs so there is no need to allocate descs here. We can therefore
273 * assume that if irq_find_mapping above returns non-zero, then the
274 * descs are also successfully allocated.
277 for (i = 0; i < no_irqs; i++) {
278 if (irq_set_msi_desc_off(irq, i, desc) != 0) {
279 clear_irq_range(pp, irq, i, pos0);
282 set_bit(pos0 + i, pp->msi_irq_in_use);
283 /*Enable corresponding interrupt in MSI interrupt controller */
284 res = ((pos0 + i) / 32) * 12;
285 bit = (pos0 + i) % 32;
286 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val);
288 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val);
299 static void clear_irq(unsigned int irq)
301 unsigned int pos, nvec;
302 struct msi_desc *msi;
303 struct pcie_port *pp;
304 struct irq_data *data = irq_get_irq_data(irq);
306 /* get the port structure */
307 msi = irq_data_get_msi(data);
308 pp = sys_to_pcie(msi->dev->bus->sysdata);
314 /* undo what was done in assign_irq */
316 nvec = 1 << msi->msi_attrib.multiple;
318 clear_irq_range(pp, irq, nvec, pos);
320 /* all irqs cleared; reset attributes */
322 msi->msi_attrib.multiple = 0;
325 static int dw_msi_setup_irq(struct msi_chip *chip, struct pci_dev *pdev,
326 struct msi_desc *desc)
328 int irq, pos, msgvec;
331 struct pcie_port *pp = sys_to_pcie(pdev->bus->sysdata);
338 pci_read_config_word(pdev, desc->msi_attrib.pos+PCI_MSI_FLAGS,
340 msgvec = (msg_ctr&PCI_MSI_FLAGS_QSIZE) >> 4;
342 msgvec = (msg_ctr & PCI_MSI_FLAGS_QMASK) >> 1;
346 irq = assign_irq((1 << msgvec), desc, &pos);
351 * write_msi_msg() will update PCI_MSI_FLAGS so there is
352 * no need to explicitly call pci_write_config_word().
354 desc->msi_attrib.multiple = msgvec;
356 msg.address_lo = virt_to_phys((void *)pp->msi_data);
357 msg.address_hi = 0x0;
359 write_msi_msg(irq, &msg);
364 static void dw_msi_teardown_irq(struct msi_chip *chip, unsigned int irq)
369 static struct msi_chip dw_pcie_msi_chip = {
370 .setup_irq = dw_msi_setup_irq,
371 .teardown_irq = dw_msi_teardown_irq,
374 int dw_pcie_link_up(struct pcie_port *pp)
376 if (pp->ops->link_up)
377 return pp->ops->link_up(pp);
382 static int dw_pcie_msi_map(struct irq_domain *domain, unsigned int irq,
383 irq_hw_number_t hwirq)
385 irq_set_chip_and_handler(irq, &dw_msi_irq_chip, handle_simple_irq);
386 irq_set_chip_data(irq, domain->host_data);
387 set_irq_flags(irq, IRQF_VALID);
392 static const struct irq_domain_ops msi_domain_ops = {
393 .map = dw_pcie_msi_map,
396 int __init dw_pcie_host_init(struct pcie_port *pp)
398 struct device_node *np = pp->dev->of_node;
399 struct of_pci_range range;
400 struct of_pci_range_parser parser;
404 if (of_pci_range_parser_init(&parser, np)) {
405 dev_err(pp->dev, "missing ranges property\n");
409 /* Get the I/O and memory ranges from DT */
410 for_each_of_pci_range(&parser, &range) {
411 unsigned long restype = range.flags & IORESOURCE_TYPE_BITS;
412 if (restype == IORESOURCE_IO) {
413 of_pci_range_to_resource(&range, np, &pp->io);
415 pp->io.start = max_t(resource_size_t,
417 range.pci_addr + global_io_offset);
418 pp->io.end = min_t(resource_size_t,
420 range.pci_addr + range.size
422 pp->config.io_size = resource_size(&pp->io);
423 pp->config.io_bus_addr = range.pci_addr;
424 pp->io_base = range.cpu_addr;
426 if (restype == IORESOURCE_MEM) {
427 of_pci_range_to_resource(&range, np, &pp->mem);
428 pp->mem.name = "MEM";
429 pp->config.mem_size = resource_size(&pp->mem);
430 pp->config.mem_bus_addr = range.pci_addr;
433 of_pci_range_to_resource(&range, np, &pp->cfg);
434 pp->config.cfg0_size = resource_size(&pp->cfg)/2;
435 pp->config.cfg1_size = resource_size(&pp->cfg)/2;
440 pp->dbi_base = devm_ioremap(pp->dev, pp->cfg.start,
441 resource_size(&pp->cfg));
443 dev_err(pp->dev, "error with ioremap\n");
448 pp->cfg0_base = pp->cfg.start;
449 pp->cfg1_base = pp->cfg.start + pp->config.cfg0_size;
450 pp->mem_base = pp->mem.start;
452 pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base,
453 pp->config.cfg0_size);
454 if (!pp->va_cfg0_base) {
455 dev_err(pp->dev, "error with ioremap in function\n");
458 pp->va_cfg1_base = devm_ioremap(pp->dev, pp->cfg1_base,
459 pp->config.cfg1_size);
460 if (!pp->va_cfg1_base) {
461 dev_err(pp->dev, "error with ioremap\n");
465 if (of_property_read_u32(np, "num-lanes", &pp->lanes)) {
466 dev_err(pp->dev, "Failed to parse the number of lanes\n");
470 if (IS_ENABLED(CONFIG_PCI_MSI)) {
471 pp->irq_domain = irq_domain_add_linear(pp->dev->of_node,
472 MAX_MSI_IRQS, &msi_domain_ops,
474 if (!pp->irq_domain) {
475 dev_err(pp->dev, "irq domain init failed\n");
479 for (i = 0; i < MAX_MSI_IRQS; i++)
480 irq_create_mapping(pp->irq_domain, i);
483 if (pp->ops->host_init)
484 pp->ops->host_init(pp);
486 dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
488 /* program correct class for RC */
489 dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI);
491 dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val);
492 val |= PORT_LOGIC_SPEED_CHANGE;
493 dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val);
495 dw_pci.nr_controllers = 1;
496 dw_pci.private_data = (void **)&pp;
498 pci_common_init_dev(pp->dev, &dw_pci);
499 pci_assign_unassigned_resources();
500 #ifdef CONFIG_PCI_DOMAINS
507 static void dw_pcie_prog_viewport_cfg0(struct pcie_port *pp, u32 busdev)
509 /* Program viewport 0 : OUTBOUND : CFG0 */
510 dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
512 dw_pcie_writel_rc(pp, pp->cfg0_base, PCIE_ATU_LOWER_BASE);
513 dw_pcie_writel_rc(pp, (pp->cfg0_base >> 32), PCIE_ATU_UPPER_BASE);
514 dw_pcie_writel_rc(pp, pp->cfg0_base + pp->config.cfg0_size - 1,
516 dw_pcie_writel_rc(pp, busdev, PCIE_ATU_LOWER_TARGET);
517 dw_pcie_writel_rc(pp, 0, PCIE_ATU_UPPER_TARGET);
518 dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_CFG0, PCIE_ATU_CR1);
519 dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
522 static void dw_pcie_prog_viewport_cfg1(struct pcie_port *pp, u32 busdev)
524 /* Program viewport 1 : OUTBOUND : CFG1 */
525 dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
527 dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_CFG1, PCIE_ATU_CR1);
528 dw_pcie_writel_rc(pp, pp->cfg1_base, PCIE_ATU_LOWER_BASE);
529 dw_pcie_writel_rc(pp, (pp->cfg1_base >> 32), PCIE_ATU_UPPER_BASE);
530 dw_pcie_writel_rc(pp, pp->cfg1_base + pp->config.cfg1_size - 1,
532 dw_pcie_writel_rc(pp, busdev, PCIE_ATU_LOWER_TARGET);
533 dw_pcie_writel_rc(pp, 0, PCIE_ATU_UPPER_TARGET);
534 dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
537 static void dw_pcie_prog_viewport_mem_outbound(struct pcie_port *pp)
539 /* Program viewport 0 : OUTBOUND : MEM */
540 dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
542 dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_MEM, PCIE_ATU_CR1);
543 dw_pcie_writel_rc(pp, pp->mem_base, PCIE_ATU_LOWER_BASE);
544 dw_pcie_writel_rc(pp, (pp->mem_base >> 32), PCIE_ATU_UPPER_BASE);
545 dw_pcie_writel_rc(pp, pp->mem_base + pp->config.mem_size - 1,
547 dw_pcie_writel_rc(pp, pp->config.mem_bus_addr, PCIE_ATU_LOWER_TARGET);
548 dw_pcie_writel_rc(pp, upper_32_bits(pp->config.mem_bus_addr),
549 PCIE_ATU_UPPER_TARGET);
550 dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
553 static void dw_pcie_prog_viewport_io_outbound(struct pcie_port *pp)
555 /* Program viewport 1 : OUTBOUND : IO */
556 dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
558 dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_IO, PCIE_ATU_CR1);
559 dw_pcie_writel_rc(pp, pp->io_base, PCIE_ATU_LOWER_BASE);
560 dw_pcie_writel_rc(pp, (pp->io_base >> 32), PCIE_ATU_UPPER_BASE);
561 dw_pcie_writel_rc(pp, pp->io_base + pp->config.io_size - 1,
563 dw_pcie_writel_rc(pp, pp->config.io_bus_addr, PCIE_ATU_LOWER_TARGET);
564 dw_pcie_writel_rc(pp, upper_32_bits(pp->config.io_bus_addr),
565 PCIE_ATU_UPPER_TARGET);
566 dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
569 static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
570 u32 devfn, int where, int size, u32 *val)
572 int ret = PCIBIOS_SUCCESSFUL;
575 busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
576 PCIE_ATU_FUNC(PCI_FUNC(devfn));
577 address = where & ~0x3;
579 if (bus->parent->number == pp->root_bus_nr) {
580 dw_pcie_prog_viewport_cfg0(pp, busdev);
581 ret = dw_pcie_cfg_read(pp->va_cfg0_base + address, where, size,
583 dw_pcie_prog_viewport_mem_outbound(pp);
585 dw_pcie_prog_viewport_cfg1(pp, busdev);
586 ret = dw_pcie_cfg_read(pp->va_cfg1_base + address, where, size,
588 dw_pcie_prog_viewport_io_outbound(pp);
594 static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
595 u32 devfn, int where, int size, u32 val)
597 int ret = PCIBIOS_SUCCESSFUL;
600 busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
601 PCIE_ATU_FUNC(PCI_FUNC(devfn));
602 address = where & ~0x3;
604 if (bus->parent->number == pp->root_bus_nr) {
605 dw_pcie_prog_viewport_cfg0(pp, busdev);
606 ret = dw_pcie_cfg_write(pp->va_cfg0_base + address, where, size,
608 dw_pcie_prog_viewport_mem_outbound(pp);
610 dw_pcie_prog_viewport_cfg1(pp, busdev);
611 ret = dw_pcie_cfg_write(pp->va_cfg1_base + address, where, size,
613 dw_pcie_prog_viewport_io_outbound(pp);
619 static int dw_pcie_valid_config(struct pcie_port *pp,
620 struct pci_bus *bus, int dev)
622 /* If there is no link, then there is no device */
623 if (bus->number != pp->root_bus_nr) {
624 if (!dw_pcie_link_up(pp))
628 /* access only one slot on each root port */
629 if (bus->number == pp->root_bus_nr && dev > 0)
633 * do not read more than one device on the bus directly attached
634 * to RC's (Virtual Bridge's) DS side.
636 if (bus->primary == pp->root_bus_nr && dev > 0)
642 static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
645 struct pcie_port *pp = sys_to_pcie(bus->sysdata);
653 if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) {
655 return PCIBIOS_DEVICE_NOT_FOUND;
658 if (bus->number != pp->root_bus_nr)
659 ret = dw_pcie_rd_other_conf(pp, bus, devfn,
662 ret = dw_pcie_rd_own_conf(pp, where, size, val);
667 static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
668 int where, int size, u32 val)
670 struct pcie_port *pp = sys_to_pcie(bus->sysdata);
678 if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0)
679 return PCIBIOS_DEVICE_NOT_FOUND;
681 if (bus->number != pp->root_bus_nr)
682 ret = dw_pcie_wr_other_conf(pp, bus, devfn,
685 ret = dw_pcie_wr_own_conf(pp, where, size, val);
690 static struct pci_ops dw_pcie_ops = {
691 .read = dw_pcie_rd_conf,
692 .write = dw_pcie_wr_conf,
695 static int dw_pcie_setup(int nr, struct pci_sys_data *sys)
697 struct pcie_port *pp;
699 pp = sys_to_pcie(sys);
704 if (global_io_offset < SZ_1M && pp->config.io_size > 0) {
705 sys->io_offset = global_io_offset - pp->config.io_bus_addr;
706 pci_ioremap_io(global_io_offset, pp->io_base);
707 global_io_offset += SZ_64K;
708 pci_add_resource_offset(&sys->resources, &pp->io,
712 sys->mem_offset = pp->mem.start - pp->config.mem_bus_addr;
713 pci_add_resource_offset(&sys->resources, &pp->mem, sys->mem_offset);
718 static struct pci_bus *dw_pcie_scan_bus(int nr, struct pci_sys_data *sys)
721 struct pcie_port *pp = sys_to_pcie(sys);
724 pp->root_bus_nr = sys->busnr;
725 bus = pci_scan_root_bus(pp->dev, sys->busnr, &dw_pcie_ops,
726 sys, &sys->resources);
735 static int dw_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
737 struct pcie_port *pp = sys_to_pcie(dev->bus->sysdata);
740 irq = of_irq_parse_and_map_pci(dev, slot, pin);
747 static void dw_pcie_add_bus(struct pci_bus *bus)
749 if (IS_ENABLED(CONFIG_PCI_MSI)) {
750 struct pcie_port *pp = sys_to_pcie(bus->sysdata);
752 dw_pcie_msi_chip.dev = pp->dev;
753 bus->msi = &dw_pcie_msi_chip;
757 static struct hw_pci dw_pci = {
758 .setup = dw_pcie_setup,
759 .scan = dw_pcie_scan_bus,
760 .map_irq = dw_pcie_map_irq,
761 .add_bus = dw_pcie_add_bus,
764 void dw_pcie_setup_rc(struct pcie_port *pp)
766 struct pcie_port_info *config = &pp->config;
771 /* set the number of lanes */
772 dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL, &val);
773 val &= ~PORT_LINK_MODE_MASK;
776 val |= PORT_LINK_MODE_1_LANES;
779 val |= PORT_LINK_MODE_2_LANES;
782 val |= PORT_LINK_MODE_4_LANES;
785 dw_pcie_writel_rc(pp, val, PCIE_PORT_LINK_CONTROL);
787 /* set link width speed control register */
788 dw_pcie_readl_rc(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, &val);
789 val &= ~PORT_LOGIC_LINK_WIDTH_MASK;
792 val |= PORT_LOGIC_LINK_WIDTH_1_LANES;
795 val |= PORT_LOGIC_LINK_WIDTH_2_LANES;
798 val |= PORT_LOGIC_LINK_WIDTH_4_LANES;
801 dw_pcie_writel_rc(pp, val, PCIE_LINK_WIDTH_SPEED_CONTROL);
804 dw_pcie_writel_rc(pp, 0x00000004, PCI_BASE_ADDRESS_0);
805 dw_pcie_writel_rc(pp, 0x00000000, PCI_BASE_ADDRESS_1);
807 /* setup interrupt pins */
808 dw_pcie_readl_rc(pp, PCI_INTERRUPT_LINE, &val);
811 dw_pcie_writel_rc(pp, val, PCI_INTERRUPT_LINE);
813 /* setup bus numbers */
814 dw_pcie_readl_rc(pp, PCI_PRIMARY_BUS, &val);
817 dw_pcie_writel_rc(pp, val, PCI_PRIMARY_BUS);
819 /* setup memory base, memory limit */
820 membase = ((u32)pp->mem_base & 0xfff00000) >> 16;
821 memlimit = (config->mem_size + (u32)pp->mem_base) & 0xfff00000;
822 val = memlimit | membase;
823 dw_pcie_writel_rc(pp, val, PCI_MEMORY_BASE);
825 /* setup command register */
826 dw_pcie_readl_rc(pp, PCI_COMMAND, &val);
828 val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
829 PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
830 dw_pcie_writel_rc(pp, val, PCI_COMMAND);
833 MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
834 MODULE_DESCRIPTION("Designware PCIe host controller driver");
835 MODULE_LICENSE("GPL v2");