2 * Synopsys Designware PCIe host controller driver
4 * Copyright (C) 2013 Samsung Electronics Co., Ltd.
5 * http://www.samsung.com
7 * Author: Jingoo Han <jg1.han@samsung.com>
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 #include <linux/irq.h>
15 #include <linux/irqdomain.h>
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/msi.h>
19 #include <linux/of_address.h>
20 #include <linux/pci.h>
21 #include <linux/pci_regs.h>
22 #include <linux/types.h>
24 #include "pcie-designware.h"
26 /* Synopsis specific PCIE configuration registers */
27 #define PCIE_PORT_LINK_CONTROL 0x710
28 #define PORT_LINK_MODE_MASK (0x3f << 16)
29 #define PORT_LINK_MODE_1_LANES (0x1 << 16)
30 #define PORT_LINK_MODE_2_LANES (0x3 << 16)
31 #define PORT_LINK_MODE_4_LANES (0x7 << 16)
33 #define PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C
34 #define PORT_LOGIC_SPEED_CHANGE (0x1 << 17)
35 #define PORT_LOGIC_LINK_WIDTH_MASK (0x1ff << 8)
36 #define PORT_LOGIC_LINK_WIDTH_1_LANES (0x1 << 8)
37 #define PORT_LOGIC_LINK_WIDTH_2_LANES (0x2 << 8)
38 #define PORT_LOGIC_LINK_WIDTH_4_LANES (0x4 << 8)
40 #define PCIE_MSI_ADDR_LO 0x820
41 #define PCIE_MSI_ADDR_HI 0x824
42 #define PCIE_MSI_INTR0_ENABLE 0x828
43 #define PCIE_MSI_INTR0_MASK 0x82C
44 #define PCIE_MSI_INTR0_STATUS 0x830
46 #define PCIE_ATU_VIEWPORT 0x900
47 #define PCIE_ATU_REGION_INBOUND (0x1 << 31)
48 #define PCIE_ATU_REGION_OUTBOUND (0x0 << 31)
49 #define PCIE_ATU_REGION_INDEX1 (0x1 << 0)
50 #define PCIE_ATU_REGION_INDEX0 (0x0 << 0)
51 #define PCIE_ATU_CR1 0x904
52 #define PCIE_ATU_TYPE_MEM (0x0 << 0)
53 #define PCIE_ATU_TYPE_IO (0x2 << 0)
54 #define PCIE_ATU_TYPE_CFG0 (0x4 << 0)
55 #define PCIE_ATU_TYPE_CFG1 (0x5 << 0)
56 #define PCIE_ATU_CR2 0x908
57 #define PCIE_ATU_ENABLE (0x1 << 31)
58 #define PCIE_ATU_BAR_MODE_ENABLE (0x1 << 30)
59 #define PCIE_ATU_LOWER_BASE 0x90C
60 #define PCIE_ATU_UPPER_BASE 0x910
61 #define PCIE_ATU_LIMIT 0x914
62 #define PCIE_ATU_LOWER_TARGET 0x918
63 #define PCIE_ATU_BUS(x) (((x) & 0xff) << 24)
64 #define PCIE_ATU_DEV(x) (((x) & 0x1f) << 19)
65 #define PCIE_ATU_FUNC(x) (((x) & 0x7) << 16)
66 #define PCIE_ATU_UPPER_TARGET 0x91C
68 static struct hw_pci dw_pci;
70 static unsigned long global_io_offset;
72 static inline struct pcie_port *sys_to_pcie(struct pci_sys_data *sys)
74 return sys->private_data;
77 int cfg_read(void __iomem *addr, int where, int size, u32 *val)
82 *val = (*val >> (8 * (where & 3))) & 0xff;
84 *val = (*val >> (8 * (where & 3))) & 0xffff;
86 return PCIBIOS_BAD_REGISTER_NUMBER;
88 return PCIBIOS_SUCCESSFUL;
91 int cfg_write(void __iomem *addr, int where, int size, u32 val)
96 writew(val, addr + (where & 2));
98 writeb(val, addr + (where & 3));
100 return PCIBIOS_BAD_REGISTER_NUMBER;
102 return PCIBIOS_SUCCESSFUL;
105 static inline void dw_pcie_readl_rc(struct pcie_port *pp, u32 reg, u32 *val)
107 if (pp->ops->readl_rc)
108 pp->ops->readl_rc(pp, pp->dbi_base + reg, val);
110 *val = readl(pp->dbi_base + reg);
113 static inline void dw_pcie_writel_rc(struct pcie_port *pp, u32 val, u32 reg)
115 if (pp->ops->writel_rc)
116 pp->ops->writel_rc(pp, val, pp->dbi_base + reg);
118 writel(val, pp->dbi_base + reg);
121 static int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size,
126 if (pp->ops->rd_own_conf)
127 ret = pp->ops->rd_own_conf(pp, where, size, val);
129 ret = cfg_read(pp->dbi_base + (where & ~0x3), where, size, val);
134 static int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size,
139 if (pp->ops->wr_own_conf)
140 ret = pp->ops->wr_own_conf(pp, where, size, val);
142 ret = cfg_write(pp->dbi_base + (where & ~0x3), where, size,
148 static struct irq_chip dw_msi_irq_chip = {
150 .irq_enable = unmask_msi_irq,
151 .irq_disable = mask_msi_irq,
152 .irq_mask = mask_msi_irq,
153 .irq_unmask = unmask_msi_irq,
156 /* MSI int handler */
157 void dw_handle_msi_irq(struct pcie_port *pp)
162 for (i = 0; i < MAX_MSI_CTRLS; i++) {
163 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_STATUS + i * 12, 4,
167 while ((pos = find_next_bit(&val, 32, pos)) != 32) {
168 irq = irq_find_mapping(pp->irq_domain,
170 generic_handle_irq(irq);
174 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_STATUS + i * 12, 4, val);
178 void dw_pcie_msi_init(struct pcie_port *pp)
180 pp->msi_data = __get_free_pages(GFP_KERNEL, 0);
182 /* program the msi_data */
183 dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_LO, 4,
184 virt_to_phys((void *)pp->msi_data));
185 dw_pcie_wr_own_conf(pp, PCIE_MSI_ADDR_HI, 4, 0);
188 static int find_valid_pos0(struct pcie_port *pp, int msgvec, int pos, int *pos0)
193 pos = find_next_zero_bit(pp->msi_irq_in_use,
195 /*if you have reached to the end then get out from here.*/
196 if (pos == MAX_MSI_IRQS)
199 * Check if this position is at correct offset.nvec is always a
200 * power of two. pos0 must be nvec bit alligned.
203 pos += msgvec - (pos % msgvec);
212 static int assign_irq(int no_irqs, struct msi_desc *desc, int *pos)
214 int res, bit, irq, pos0, pos1, i;
216 struct pcie_port *pp = sys_to_pcie(desc->dev->bus->sysdata);
223 pos0 = find_first_zero_bit(pp->msi_irq_in_use,
225 if (pos0 % no_irqs) {
226 if (find_valid_pos0(pp, no_irqs, pos0, &pos0))
230 pos1 = find_next_bit(pp->msi_irq_in_use,
232 /* there must be nvec number of consecutive free bits */
233 while ((pos1 - pos0) < no_irqs) {
234 if (find_valid_pos0(pp, no_irqs, pos1, &pos0))
236 pos1 = find_next_bit(pp->msi_irq_in_use,
241 irq = irq_find_mapping(pp->irq_domain, pos0);
246 while (i < no_irqs) {
247 set_bit(pos0 + i, pp->msi_irq_in_use);
248 irq_alloc_descs((irq + i), (irq + i), 1, 0);
249 irq_set_msi_desc(irq + i, desc);
250 /*Enable corresponding interrupt in MSI interrupt controller */
251 res = ((pos0 + i) / 32) * 12;
252 bit = (pos0 + i) % 32;
253 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val);
255 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val);
267 static void clear_irq(unsigned int irq)
269 int res, bit, val, pos;
270 struct irq_desc *desc;
271 struct msi_desc *msi;
272 struct pcie_port *pp;
273 struct irq_data *data = irq_get_irq_data(irq);
275 /* get the port structure */
276 desc = irq_to_desc(irq);
277 msi = irq_desc_get_msi_desc(desc);
278 pp = sys_to_pcie(msi->dev->bus->sysdata);
288 clear_bit(pos, pp->msi_irq_in_use);
290 /* Disable corresponding interrupt on MSI interrupt controller */
291 res = (pos / 32) * 12;
293 dw_pcie_rd_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, &val);
295 dw_pcie_wr_own_conf(pp, PCIE_MSI_INTR0_ENABLE + res, 4, val);
298 static int dw_msi_setup_irq(struct msi_chip *chip, struct pci_dev *pdev,
299 struct msi_desc *desc)
301 int irq, pos, msgvec;
304 struct pcie_port *pp = sys_to_pcie(pdev->bus->sysdata);
311 pci_read_config_word(pdev, desc->msi_attrib.pos+PCI_MSI_FLAGS,
313 msgvec = (msg_ctr&PCI_MSI_FLAGS_QSIZE) >> 4;
315 msgvec = (msg_ctr & PCI_MSI_FLAGS_QMASK) >> 1;
319 irq = assign_irq((1 << msgvec), desc, &pos);
323 msg_ctr &= ~PCI_MSI_FLAGS_QSIZE;
324 msg_ctr |= msgvec << 4;
325 pci_write_config_word(pdev, desc->msi_attrib.pos + PCI_MSI_FLAGS,
327 desc->msi_attrib.multiple = msgvec;
329 msg.address_lo = virt_to_phys((void *)pp->msi_data);
330 msg.address_hi = 0x0;
332 write_msi_msg(irq, &msg);
337 static void dw_msi_teardown_irq(struct msi_chip *chip, unsigned int irq)
342 static struct msi_chip dw_pcie_msi_chip = {
343 .setup_irq = dw_msi_setup_irq,
344 .teardown_irq = dw_msi_teardown_irq,
347 int dw_pcie_link_up(struct pcie_port *pp)
349 if (pp->ops->link_up)
350 return pp->ops->link_up(pp);
355 static int dw_pcie_msi_map(struct irq_domain *domain, unsigned int irq,
356 irq_hw_number_t hwirq)
358 irq_set_chip_and_handler(irq, &dw_msi_irq_chip, handle_simple_irq);
359 irq_set_chip_data(irq, domain->host_data);
360 set_irq_flags(irq, IRQF_VALID);
365 static const struct irq_domain_ops msi_domain_ops = {
366 .map = dw_pcie_msi_map,
369 int __init dw_pcie_host_init(struct pcie_port *pp)
371 struct device_node *np = pp->dev->of_node;
372 struct of_pci_range range;
373 struct of_pci_range_parser parser;
377 if (of_pci_range_parser_init(&parser, np)) {
378 dev_err(pp->dev, "missing ranges property\n");
382 /* Get the I/O and memory ranges from DT */
383 for_each_of_pci_range(&parser, &range) {
384 unsigned long restype = range.flags & IORESOURCE_TYPE_BITS;
385 if (restype == IORESOURCE_IO) {
386 of_pci_range_to_resource(&range, np, &pp->io);
388 pp->io.start = max_t(resource_size_t,
390 range.pci_addr + global_io_offset);
391 pp->io.end = min_t(resource_size_t,
393 range.pci_addr + range.size
395 pp->config.io_size = resource_size(&pp->io);
396 pp->config.io_bus_addr = range.pci_addr;
398 if (restype == IORESOURCE_MEM) {
399 of_pci_range_to_resource(&range, np, &pp->mem);
400 pp->mem.name = "MEM";
401 pp->config.mem_size = resource_size(&pp->mem);
402 pp->config.mem_bus_addr = range.pci_addr;
405 of_pci_range_to_resource(&range, np, &pp->cfg);
406 pp->config.cfg0_size = resource_size(&pp->cfg)/2;
407 pp->config.cfg1_size = resource_size(&pp->cfg)/2;
412 pp->dbi_base = devm_ioremap(pp->dev, pp->cfg.start,
413 resource_size(&pp->cfg));
415 dev_err(pp->dev, "error with ioremap\n");
420 pp->cfg0_base = pp->cfg.start;
421 pp->cfg1_base = pp->cfg.start + pp->config.cfg0_size;
422 pp->io_base = pp->io.start;
423 pp->mem_base = pp->mem.start;
425 pp->va_cfg0_base = devm_ioremap(pp->dev, pp->cfg0_base,
426 pp->config.cfg0_size);
427 if (!pp->va_cfg0_base) {
428 dev_err(pp->dev, "error with ioremap in function\n");
431 pp->va_cfg1_base = devm_ioremap(pp->dev, pp->cfg1_base,
432 pp->config.cfg1_size);
433 if (!pp->va_cfg1_base) {
434 dev_err(pp->dev, "error with ioremap\n");
438 if (of_property_read_u32(np, "num-lanes", &pp->lanes)) {
439 dev_err(pp->dev, "Failed to parse the number of lanes\n");
443 if (IS_ENABLED(CONFIG_PCI_MSI)) {
444 pp->irq_domain = irq_domain_add_linear(pp->dev->of_node,
445 MAX_MSI_IRQS, &msi_domain_ops,
447 if (!pp->irq_domain) {
448 dev_err(pp->dev, "irq domain init failed\n");
452 for (i = 0; i < MAX_MSI_IRQS; i++)
453 irq_create_mapping(pp->irq_domain, i);
456 if (pp->ops->host_init)
457 pp->ops->host_init(pp);
459 dw_pcie_wr_own_conf(pp, PCI_BASE_ADDRESS_0, 4, 0);
461 /* program correct class for RC */
462 dw_pcie_wr_own_conf(pp, PCI_CLASS_DEVICE, 2, PCI_CLASS_BRIDGE_PCI);
464 dw_pcie_rd_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, &val);
465 val |= PORT_LOGIC_SPEED_CHANGE;
466 dw_pcie_wr_own_conf(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, 4, val);
468 dw_pci.nr_controllers = 1;
469 dw_pci.private_data = (void **)&pp;
471 pci_common_init(&dw_pci);
472 pci_assign_unassigned_resources();
473 #ifdef CONFIG_PCI_DOMAINS
480 static void dw_pcie_prog_viewport_cfg0(struct pcie_port *pp, u32 busdev)
482 /* Program viewport 0 : OUTBOUND : CFG0 */
483 dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
485 dw_pcie_writel_rc(pp, pp->cfg0_base, PCIE_ATU_LOWER_BASE);
486 dw_pcie_writel_rc(pp, (pp->cfg0_base >> 32), PCIE_ATU_UPPER_BASE);
487 dw_pcie_writel_rc(pp, pp->cfg0_base + pp->config.cfg0_size - 1,
489 dw_pcie_writel_rc(pp, busdev, PCIE_ATU_LOWER_TARGET);
490 dw_pcie_writel_rc(pp, 0, PCIE_ATU_UPPER_TARGET);
491 dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_CFG0, PCIE_ATU_CR1);
492 dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
495 static void dw_pcie_prog_viewport_cfg1(struct pcie_port *pp, u32 busdev)
497 /* Program viewport 1 : OUTBOUND : CFG1 */
498 dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
500 dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_CFG1, PCIE_ATU_CR1);
501 dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
502 dw_pcie_writel_rc(pp, pp->cfg1_base, PCIE_ATU_LOWER_BASE);
503 dw_pcie_writel_rc(pp, (pp->cfg1_base >> 32), PCIE_ATU_UPPER_BASE);
504 dw_pcie_writel_rc(pp, pp->cfg1_base + pp->config.cfg1_size - 1,
506 dw_pcie_writel_rc(pp, busdev, PCIE_ATU_LOWER_TARGET);
507 dw_pcie_writel_rc(pp, 0, PCIE_ATU_UPPER_TARGET);
510 static void dw_pcie_prog_viewport_mem_outbound(struct pcie_port *pp)
512 /* Program viewport 0 : OUTBOUND : MEM */
513 dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX0,
515 dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_MEM, PCIE_ATU_CR1);
516 dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
517 dw_pcie_writel_rc(pp, pp->mem_base, PCIE_ATU_LOWER_BASE);
518 dw_pcie_writel_rc(pp, (pp->mem_base >> 32), PCIE_ATU_UPPER_BASE);
519 dw_pcie_writel_rc(pp, pp->mem_base + pp->config.mem_size - 1,
521 dw_pcie_writel_rc(pp, pp->config.mem_bus_addr, PCIE_ATU_LOWER_TARGET);
522 dw_pcie_writel_rc(pp, upper_32_bits(pp->config.mem_bus_addr),
523 PCIE_ATU_UPPER_TARGET);
526 static void dw_pcie_prog_viewport_io_outbound(struct pcie_port *pp)
528 /* Program viewport 1 : OUTBOUND : IO */
529 dw_pcie_writel_rc(pp, PCIE_ATU_REGION_OUTBOUND | PCIE_ATU_REGION_INDEX1,
531 dw_pcie_writel_rc(pp, PCIE_ATU_TYPE_IO, PCIE_ATU_CR1);
532 dw_pcie_writel_rc(pp, PCIE_ATU_ENABLE, PCIE_ATU_CR2);
533 dw_pcie_writel_rc(pp, pp->io_base, PCIE_ATU_LOWER_BASE);
534 dw_pcie_writel_rc(pp, (pp->io_base >> 32), PCIE_ATU_UPPER_BASE);
535 dw_pcie_writel_rc(pp, pp->io_base + pp->config.io_size - 1,
537 dw_pcie_writel_rc(pp, pp->config.io_bus_addr, PCIE_ATU_LOWER_TARGET);
538 dw_pcie_writel_rc(pp, upper_32_bits(pp->config.io_bus_addr),
539 PCIE_ATU_UPPER_TARGET);
542 static int dw_pcie_rd_other_conf(struct pcie_port *pp, struct pci_bus *bus,
543 u32 devfn, int where, int size, u32 *val)
545 int ret = PCIBIOS_SUCCESSFUL;
548 busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
549 PCIE_ATU_FUNC(PCI_FUNC(devfn));
550 address = where & ~0x3;
552 if (bus->parent->number == pp->root_bus_nr) {
553 dw_pcie_prog_viewport_cfg0(pp, busdev);
554 ret = cfg_read(pp->va_cfg0_base + address, where, size, val);
555 dw_pcie_prog_viewport_mem_outbound(pp);
557 dw_pcie_prog_viewport_cfg1(pp, busdev);
558 ret = cfg_read(pp->va_cfg1_base + address, where, size, val);
559 dw_pcie_prog_viewport_io_outbound(pp);
565 static int dw_pcie_wr_other_conf(struct pcie_port *pp, struct pci_bus *bus,
566 u32 devfn, int where, int size, u32 val)
568 int ret = PCIBIOS_SUCCESSFUL;
571 busdev = PCIE_ATU_BUS(bus->number) | PCIE_ATU_DEV(PCI_SLOT(devfn)) |
572 PCIE_ATU_FUNC(PCI_FUNC(devfn));
573 address = where & ~0x3;
575 if (bus->parent->number == pp->root_bus_nr) {
576 dw_pcie_prog_viewport_cfg0(pp, busdev);
577 ret = cfg_write(pp->va_cfg0_base + address, where, size, val);
578 dw_pcie_prog_viewport_mem_outbound(pp);
580 dw_pcie_prog_viewport_cfg1(pp, busdev);
581 ret = cfg_write(pp->va_cfg1_base + address, where, size, val);
582 dw_pcie_prog_viewport_io_outbound(pp);
589 static int dw_pcie_valid_config(struct pcie_port *pp,
590 struct pci_bus *bus, int dev)
592 /* If there is no link, then there is no device */
593 if (bus->number != pp->root_bus_nr) {
594 if (!dw_pcie_link_up(pp))
598 /* access only one slot on each root port */
599 if (bus->number == pp->root_bus_nr && dev > 0)
603 * do not read more than one device on the bus directly attached
604 * to RC's (Virtual Bridge's) DS side.
606 if (bus->primary == pp->root_bus_nr && dev > 0)
612 static int dw_pcie_rd_conf(struct pci_bus *bus, u32 devfn, int where,
615 struct pcie_port *pp = sys_to_pcie(bus->sysdata);
624 if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0) {
626 return PCIBIOS_DEVICE_NOT_FOUND;
629 spin_lock_irqsave(&pp->conf_lock, flags);
630 if (bus->number != pp->root_bus_nr)
631 ret = dw_pcie_rd_other_conf(pp, bus, devfn,
634 ret = dw_pcie_rd_own_conf(pp, where, size, val);
635 spin_unlock_irqrestore(&pp->conf_lock, flags);
640 static int dw_pcie_wr_conf(struct pci_bus *bus, u32 devfn,
641 int where, int size, u32 val)
643 struct pcie_port *pp = sys_to_pcie(bus->sysdata);
652 if (dw_pcie_valid_config(pp, bus, PCI_SLOT(devfn)) == 0)
653 return PCIBIOS_DEVICE_NOT_FOUND;
655 spin_lock_irqsave(&pp->conf_lock, flags);
656 if (bus->number != pp->root_bus_nr)
657 ret = dw_pcie_wr_other_conf(pp, bus, devfn,
660 ret = dw_pcie_wr_own_conf(pp, where, size, val);
661 spin_unlock_irqrestore(&pp->conf_lock, flags);
666 static struct pci_ops dw_pcie_ops = {
667 .read = dw_pcie_rd_conf,
668 .write = dw_pcie_wr_conf,
671 static int dw_pcie_setup(int nr, struct pci_sys_data *sys)
673 struct pcie_port *pp;
675 pp = sys_to_pcie(sys);
680 if (global_io_offset < SZ_1M && pp->config.io_size > 0) {
681 sys->io_offset = global_io_offset - pp->config.io_bus_addr;
682 pci_ioremap_io(sys->io_offset, pp->io.start);
683 global_io_offset += SZ_64K;
684 pci_add_resource_offset(&sys->resources, &pp->io,
688 sys->mem_offset = pp->mem.start - pp->config.mem_bus_addr;
689 pci_add_resource_offset(&sys->resources, &pp->mem, sys->mem_offset);
694 static struct pci_bus *dw_pcie_scan_bus(int nr, struct pci_sys_data *sys)
697 struct pcie_port *pp = sys_to_pcie(sys);
700 pp->root_bus_nr = sys->busnr;
701 bus = pci_scan_root_bus(NULL, sys->busnr, &dw_pcie_ops,
702 sys, &sys->resources);
711 static int dw_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
713 struct pcie_port *pp = sys_to_pcie(dev->bus->sysdata);
718 static void dw_pcie_add_bus(struct pci_bus *bus)
720 if (IS_ENABLED(CONFIG_PCI_MSI)) {
721 struct pcie_port *pp = sys_to_pcie(bus->sysdata);
723 dw_pcie_msi_chip.dev = pp->dev;
724 bus->msi = &dw_pcie_msi_chip;
728 static struct hw_pci dw_pci = {
729 .setup = dw_pcie_setup,
730 .scan = dw_pcie_scan_bus,
731 .map_irq = dw_pcie_map_irq,
732 .add_bus = dw_pcie_add_bus,
735 void dw_pcie_setup_rc(struct pcie_port *pp)
737 struct pcie_port_info *config = &pp->config;
742 /* set the number of lines as 4 */
743 dw_pcie_readl_rc(pp, PCIE_PORT_LINK_CONTROL, &val);
744 val &= ~PORT_LINK_MODE_MASK;
747 val |= PORT_LINK_MODE_1_LANES;
750 val |= PORT_LINK_MODE_2_LANES;
753 val |= PORT_LINK_MODE_4_LANES;
756 dw_pcie_writel_rc(pp, val, PCIE_PORT_LINK_CONTROL);
758 /* set link width speed control register */
759 dw_pcie_readl_rc(pp, PCIE_LINK_WIDTH_SPEED_CONTROL, &val);
760 val &= ~PORT_LOGIC_LINK_WIDTH_MASK;
763 val |= PORT_LOGIC_LINK_WIDTH_1_LANES;
766 val |= PORT_LOGIC_LINK_WIDTH_2_LANES;
769 val |= PORT_LOGIC_LINK_WIDTH_4_LANES;
772 dw_pcie_writel_rc(pp, val, PCIE_LINK_WIDTH_SPEED_CONTROL);
775 dw_pcie_writel_rc(pp, 0x00000004, PCI_BASE_ADDRESS_0);
776 dw_pcie_writel_rc(pp, 0x00000004, PCI_BASE_ADDRESS_1);
778 /* setup interrupt pins */
779 dw_pcie_readl_rc(pp, PCI_INTERRUPT_LINE, &val);
782 dw_pcie_writel_rc(pp, val, PCI_INTERRUPT_LINE);
784 /* setup bus numbers */
785 dw_pcie_readl_rc(pp, PCI_PRIMARY_BUS, &val);
788 dw_pcie_writel_rc(pp, val, PCI_PRIMARY_BUS);
790 /* setup memory base, memory limit */
791 membase = ((u32)pp->mem_base & 0xfff00000) >> 16;
792 memlimit = (config->mem_size + (u32)pp->mem_base) & 0xfff00000;
793 val = memlimit | membase;
794 dw_pcie_writel_rc(pp, val, PCI_MEMORY_BASE);
796 /* setup command register */
797 dw_pcie_readl_rc(pp, PCI_COMMAND, &val);
799 val |= PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
800 PCI_COMMAND_MASTER | PCI_COMMAND_SERR;
801 dw_pcie_writel_rc(pp, val, PCI_COMMAND);
804 MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>");
805 MODULE_DESCRIPTION("Designware PCIe host controller driver");
806 MODULE_LICENSE("GPL v2");