2 * pci-rcar-gen2: internal PCI bus support
4 * Copyright (C) 2013 Renesas Solutions Corp.
5 * Copyright (C) 2013 Cogent Embedded, Inc.
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
12 #include <linux/delay.h>
13 #include <linux/init.h>
14 #include <linux/interrupt.h>
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/pci.h>
19 #include <linux/platform_device.h>
20 #include <linux/slab.h>
22 /* AHB-PCI Bridge PCI communication registers */
23 #define RCAR_AHBPCI_PCICOM_OFFSET 0x800
25 #define RCAR_PCIAHB_WIN1_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x00)
26 #define RCAR_PCIAHB_WIN2_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x04)
27 #define RCAR_PCIAHB_PREFETCH0 0x0
28 #define RCAR_PCIAHB_PREFETCH4 0x1
29 #define RCAR_PCIAHB_PREFETCH8 0x2
30 #define RCAR_PCIAHB_PREFETCH16 0x3
32 #define RCAR_AHBPCI_WIN1_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x10)
33 #define RCAR_AHBPCI_WIN2_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x14)
34 #define RCAR_AHBPCI_WIN_CTR_MEM (3 << 1)
35 #define RCAR_AHBPCI_WIN_CTR_CFG (5 << 1)
36 #define RCAR_AHBPCI_WIN1_HOST (1 << 30)
37 #define RCAR_AHBPCI_WIN1_DEVICE (1 << 31)
39 #define RCAR_PCI_INT_ENABLE_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x20)
40 #define RCAR_PCI_INT_STATUS_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x24)
41 #define RCAR_PCI_INT_A (1 << 16)
42 #define RCAR_PCI_INT_B (1 << 17)
43 #define RCAR_PCI_INT_PME (1 << 19)
45 #define RCAR_AHB_BUS_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x30)
46 #define RCAR_AHB_BUS_MMODE_HTRANS (1 << 0)
47 #define RCAR_AHB_BUS_MMODE_BYTE_BURST (1 << 1)
48 #define RCAR_AHB_BUS_MMODE_WR_INCR (1 << 2)
49 #define RCAR_AHB_BUS_MMODE_HBUS_REQ (1 << 7)
50 #define RCAR_AHB_BUS_SMODE_READYCTR (1 << 17)
51 #define RCAR_AHB_BUS_MODE (RCAR_AHB_BUS_MMODE_HTRANS | \
52 RCAR_AHB_BUS_MMODE_BYTE_BURST | \
53 RCAR_AHB_BUS_MMODE_WR_INCR | \
54 RCAR_AHB_BUS_MMODE_HBUS_REQ | \
55 RCAR_AHB_BUS_SMODE_READYCTR)
57 #define RCAR_USBCTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x34)
58 #define RCAR_USBCTR_USBH_RST (1 << 0)
59 #define RCAR_USBCTR_PCICLK_MASK (1 << 1)
60 #define RCAR_USBCTR_PLL_RST (1 << 2)
61 #define RCAR_USBCTR_DIRPD (1 << 8)
62 #define RCAR_USBCTR_PCIAHB_WIN2_EN (1 << 9)
63 #define RCAR_USBCTR_PCIAHB_WIN1_256M (0 << 10)
64 #define RCAR_USBCTR_PCIAHB_WIN1_512M (1 << 10)
65 #define RCAR_USBCTR_PCIAHB_WIN1_1G (2 << 10)
66 #define RCAR_USBCTR_PCIAHB_WIN1_2G (3 << 10)
67 #define RCAR_USBCTR_PCIAHB_WIN1_MASK (3 << 10)
69 #define RCAR_PCI_ARBITER_CTR_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x40)
70 #define RCAR_PCI_ARBITER_PCIREQ0 (1 << 0)
71 #define RCAR_PCI_ARBITER_PCIREQ1 (1 << 1)
72 #define RCAR_PCI_ARBITER_PCIBP_MODE (1 << 12)
74 #define RCAR_PCI_UNIT_REV_REG (RCAR_AHBPCI_PCICOM_OFFSET + 0x48)
76 /* Number of internal PCI controllers */
77 #define RCAR_PCI_NR_CONTROLLERS 3
79 struct rcar_pci_priv {
81 struct resource io_res;
82 struct resource mem_res;
83 struct resource *cfg_res;
87 /* PCI configuration space operations */
88 static void __iomem *rcar_pci_cfg_base(struct pci_bus *bus, unsigned int devfn,
91 struct pci_sys_data *sys = bus->sysdata;
92 struct rcar_pci_priv *priv = sys->private_data;
95 if (sys->busnr != bus->number || PCI_FUNC(devfn))
98 /* Only one EHCI/OHCI device built-in */
99 slot = PCI_SLOT(devfn);
103 val = slot ? RCAR_AHBPCI_WIN1_DEVICE | RCAR_AHBPCI_WIN_CTR_CFG :
104 RCAR_AHBPCI_WIN1_HOST | RCAR_AHBPCI_WIN_CTR_CFG;
106 iowrite32(val, priv->reg + RCAR_AHBPCI_WIN1_CTR_REG);
107 return priv->reg + (slot >> 1) * 0x100 + where;
110 static int rcar_pci_read_config(struct pci_bus *bus, unsigned int devfn,
111 int where, int size, u32 *val)
113 void __iomem *reg = rcar_pci_cfg_base(bus, devfn, where);
116 return PCIBIOS_DEVICE_NOT_FOUND;
123 *val = ioread16(reg);
126 *val = ioread32(reg);
130 return PCIBIOS_SUCCESSFUL;
133 static int rcar_pci_write_config(struct pci_bus *bus, unsigned int devfn,
134 int where, int size, u32 val)
136 void __iomem *reg = rcar_pci_cfg_base(bus, devfn, where);
139 return PCIBIOS_DEVICE_NOT_FOUND;
153 return PCIBIOS_SUCCESSFUL;
156 /* PCI interrupt mapping */
157 static int __init rcar_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin)
159 struct pci_sys_data *sys = dev->bus->sysdata;
160 struct rcar_pci_priv *priv = sys->private_data;
165 /* PCI host controller setup */
166 static int __init rcar_pci_setup(int nr, struct pci_sys_data *sys)
168 struct rcar_pci_priv *priv = sys->private_data;
169 void __iomem *reg = priv->reg;
172 val = ioread32(reg + RCAR_PCI_UNIT_REV_REG);
173 pr_info("PCI: bus%u revision %x\n", sys->busnr, val);
175 /* Disable Direct Power Down State and assert reset */
176 val = ioread32(reg + RCAR_USBCTR_REG) & ~RCAR_USBCTR_DIRPD;
177 val |= RCAR_USBCTR_USBH_RST | RCAR_USBCTR_PLL_RST;
178 iowrite32(val, reg + RCAR_USBCTR_REG);
181 /* De-assert reset and set PCIAHB window1 size to 1GB */
182 val &= ~(RCAR_USBCTR_PCIAHB_WIN1_MASK | RCAR_USBCTR_PCICLK_MASK |
183 RCAR_USBCTR_USBH_RST | RCAR_USBCTR_PLL_RST);
184 iowrite32(val | RCAR_USBCTR_PCIAHB_WIN1_1G, reg + RCAR_USBCTR_REG);
186 /* Configure AHB master and slave modes */
187 iowrite32(RCAR_AHB_BUS_MODE, reg + RCAR_AHB_BUS_CTR_REG);
189 /* Configure PCI arbiter */
190 val = ioread32(reg + RCAR_PCI_ARBITER_CTR_REG);
191 val |= RCAR_PCI_ARBITER_PCIREQ0 | RCAR_PCI_ARBITER_PCIREQ1 |
192 RCAR_PCI_ARBITER_PCIBP_MODE;
193 iowrite32(val, reg + RCAR_PCI_ARBITER_CTR_REG);
195 /* PCI-AHB mapping: 0x40000000-0x80000000 */
196 iowrite32(0x40000000 | RCAR_PCIAHB_PREFETCH16,
197 reg + RCAR_PCIAHB_WIN1_CTR_REG);
199 /* AHB-PCI mapping: OHCI/EHCI registers */
200 val = priv->mem_res.start | RCAR_AHBPCI_WIN_CTR_MEM;
201 iowrite32(val, reg + RCAR_AHBPCI_WIN2_CTR_REG);
203 /* Enable AHB-PCI bridge PCI configuration access */
204 iowrite32(RCAR_AHBPCI_WIN1_HOST | RCAR_AHBPCI_WIN_CTR_CFG,
205 reg + RCAR_AHBPCI_WIN1_CTR_REG);
206 /* Set PCI-AHB Window1 address */
207 iowrite32(0x40000000 | PCI_BASE_ADDRESS_MEM_PREFETCH,
208 reg + PCI_BASE_ADDRESS_1);
209 /* Set AHB-PCI bridge PCI communication area address */
210 val = priv->cfg_res->start + RCAR_AHBPCI_PCICOM_OFFSET;
211 iowrite32(val, reg + PCI_BASE_ADDRESS_0);
213 val = ioread32(reg + PCI_COMMAND);
214 val |= PCI_COMMAND_SERR | PCI_COMMAND_PARITY |
215 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER;
216 iowrite32(val, reg + PCI_COMMAND);
218 /* Enable PCI interrupts */
219 iowrite32(RCAR_PCI_INT_A | RCAR_PCI_INT_B | RCAR_PCI_INT_PME,
220 reg + RCAR_PCI_INT_ENABLE_REG);
222 /* Add PCI resources */
223 pci_add_resource(&sys->resources, &priv->io_res);
224 pci_add_resource(&sys->resources, &priv->mem_res);
229 static struct pci_ops rcar_pci_ops = {
230 .read = rcar_pci_read_config,
231 .write = rcar_pci_write_config,
234 static struct hw_pci rcar_hw_pci __initdata = {
235 .map_irq = rcar_pci_map_irq,
236 .ops = &rcar_pci_ops,
237 .setup = rcar_pci_setup,
240 static int rcar_pci_count __initdata;
242 static int __init rcar_pci_add_controller(struct rcar_pci_priv *priv)
247 if (rcar_hw_pci.nr_controllers < rcar_pci_count)
250 /* (Re)allocate private data pointer array if needed */
251 count = rcar_pci_count + RCAR_PCI_NR_CONTROLLERS;
252 private_data = kzalloc(count * sizeof(void *), GFP_KERNEL);
256 rcar_pci_count = count;
257 if (rcar_hw_pci.private_data) {
258 memcpy(private_data, rcar_hw_pci.private_data,
259 rcar_hw_pci.nr_controllers * sizeof(void *));
260 kfree(rcar_hw_pci.private_data);
263 rcar_hw_pci.private_data = private_data;
266 /* Add private data pointer to the array */
267 rcar_hw_pci.private_data[rcar_hw_pci.nr_controllers++] = priv;
271 static int __init rcar_pci_probe(struct platform_device *pdev)
273 struct resource *cfg_res, *mem_res;
274 struct rcar_pci_priv *priv;
277 cfg_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
278 reg = devm_ioremap_resource(&pdev->dev, cfg_res);
282 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
283 if (!mem_res || !mem_res->start)
286 priv = devm_kzalloc(&pdev->dev,
287 sizeof(struct rcar_pci_priv), GFP_KERNEL);
291 priv->mem_res = *mem_res;
293 * The controller does not support/use port I/O,
294 * so setup a dummy port I/O region here.
296 priv->io_res.start = priv->mem_res.start;
297 priv->io_res.end = priv->mem_res.end;
298 priv->io_res.flags = IORESOURCE_IO;
300 priv->cfg_res = cfg_res;
302 priv->irq = platform_get_irq(pdev, 0);
305 return rcar_pci_add_controller(priv);
308 static struct platform_driver rcar_pci_driver = {
310 .name = "pci-rcar-gen2",
314 static int __init rcar_pci_init(void)
318 retval = platform_driver_probe(&rcar_pci_driver, rcar_pci_probe);
320 pci_common_init(&rcar_hw_pci);
322 /* Private data pointer array is not needed any more */
323 kfree(rcar_hw_pci.private_data);
324 rcar_hw_pci.private_data = NULL;
329 subsys_initcall(rcar_pci_init);
331 MODULE_LICENSE("GPL v2");
332 MODULE_DESCRIPTION("Renesas R-Car Gen2 internal PCI");
333 MODULE_AUTHOR("Valentine Barshak <valentine.barshak@cogentembedded.com>");