2 * This file is part of wl1271
4 * Copyright (C) 2008-2010 Nokia Corporation
6 * Contact: Luciano Coelho <luciano.coelho@nokia.com>
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
24 #include <linux/gpio.h>
26 #include "wl1271_acx.h"
27 #include "wl1271_reg.h"
28 #include "wl1271_boot.h"
29 #include "wl1271_io.h"
30 #include "wl1271_event.h"
32 static struct wl1271_partition_set part_table[PART_TABLE_LEN] = {
39 .start = REGISTERS_BASE,
58 .start = REGISTERS_BASE,
91 static void wl1271_boot_set_ecpu_ctrl(struct wl1271 *wl, u32 flag)
95 /* 10.5.0 run the firmware (I) */
96 cpu_ctrl = wl1271_read32(wl, ACX_REG_ECPU_CONTROL);
98 /* 10.5.1 run the firmware (II) */
100 wl1271_write32(wl, ACX_REG_ECPU_CONTROL, cpu_ctrl);
103 static void wl1271_boot_fw_version(struct wl1271 *wl)
105 struct wl1271_static_data static_data;
107 wl1271_read(wl, wl->cmd_box_addr, &static_data, sizeof(static_data),
110 strncpy(wl->chip.fw_ver, static_data.fw_version,
111 sizeof(wl->chip.fw_ver));
113 /* make sure the string is NULL-terminated */
114 wl->chip.fw_ver[sizeof(wl->chip.fw_ver) - 1] = '\0';
117 static int wl1271_boot_upload_firmware_chunk(struct wl1271 *wl, void *buf,
118 size_t fw_data_len, u32 dest)
120 struct wl1271_partition_set partition;
121 int addr, chunk_num, partition_limit;
124 /* whal_FwCtrl_LoadFwImageSm() */
126 wl1271_debug(DEBUG_BOOT, "starting firmware upload");
128 wl1271_debug(DEBUG_BOOT, "fw_data_len %zd chunk_size %d",
129 fw_data_len, CHUNK_SIZE);
131 if ((fw_data_len % 4) != 0) {
132 wl1271_error("firmware length not multiple of four");
136 chunk = kmalloc(CHUNK_SIZE, GFP_KERNEL);
138 wl1271_error("allocation for firmware upload chunk failed");
142 memcpy(&partition, &part_table[PART_DOWN], sizeof(partition));
143 partition.mem.start = dest;
144 wl1271_set_partition(wl, &partition);
146 /* 10.1 set partition limit and chunk num */
148 partition_limit = part_table[PART_DOWN].mem.size;
150 while (chunk_num < fw_data_len / CHUNK_SIZE) {
151 /* 10.2 update partition, if needed */
152 addr = dest + (chunk_num + 2) * CHUNK_SIZE;
153 if (addr > partition_limit) {
154 addr = dest + chunk_num * CHUNK_SIZE;
155 partition_limit = chunk_num * CHUNK_SIZE +
156 part_table[PART_DOWN].mem.size;
157 partition.mem.start = addr;
158 wl1271_set_partition(wl, &partition);
161 /* 10.3 upload the chunk */
162 addr = dest + chunk_num * CHUNK_SIZE;
163 p = buf + chunk_num * CHUNK_SIZE;
164 memcpy(chunk, p, CHUNK_SIZE);
165 wl1271_debug(DEBUG_BOOT, "uploading fw chunk 0x%p to 0x%x",
167 wl1271_write(wl, addr, chunk, CHUNK_SIZE, false);
172 /* 10.4 upload the last chunk */
173 addr = dest + chunk_num * CHUNK_SIZE;
174 p = buf + chunk_num * CHUNK_SIZE;
175 memcpy(chunk, p, fw_data_len % CHUNK_SIZE);
176 wl1271_debug(DEBUG_BOOT, "uploading fw last chunk (%zd B) 0x%p to 0x%x",
177 fw_data_len % CHUNK_SIZE, p, addr);
178 wl1271_write(wl, addr, chunk, fw_data_len % CHUNK_SIZE, false);
184 static int wl1271_boot_upload_firmware(struct wl1271 *wl)
186 u32 chunks, addr, len;
191 chunks = be32_to_cpup((__be32 *) fw);
194 wl1271_debug(DEBUG_BOOT, "firmware chunks to be uploaded: %u", chunks);
197 addr = be32_to_cpup((__be32 *) fw);
199 len = be32_to_cpup((__be32 *) fw);
203 wl1271_info("firmware chunk too long: %u", len);
206 wl1271_debug(DEBUG_BOOT, "chunk %d addr 0x%x len %u",
208 ret = wl1271_boot_upload_firmware_chunk(wl, fw, len, addr);
217 static int wl1271_boot_upload_nvs(struct wl1271 *wl)
219 size_t nvs_len, burst_len;
222 u8 *nvs_ptr, *nvs_aligned;
227 /* only the first part of the NVS needs to be uploaded */
228 nvs_len = sizeof(wl->nvs->nvs);
229 nvs_ptr = (u8 *)wl->nvs->nvs;
231 /* update current MAC address to NVS */
232 nvs_ptr[11] = wl->mac_addr[0];
233 nvs_ptr[10] = wl->mac_addr[1];
234 nvs_ptr[6] = wl->mac_addr[2];
235 nvs_ptr[5] = wl->mac_addr[3];
236 nvs_ptr[4] = wl->mac_addr[4];
237 nvs_ptr[3] = wl->mac_addr[5];
240 * Layout before the actual NVS tables:
241 * 1 byte : burst length.
242 * 2 bytes: destination address.
243 * n bytes: data to burst copy.
245 * This is ended by a 0 length, then the NVS tables.
248 /* FIXME: Do we need to check here whether the LSB is 1? */
250 burst_len = nvs_ptr[0];
251 dest_addr = (nvs_ptr[1] & 0xfe) | ((u32)(nvs_ptr[2] << 8));
253 /* FIXME: Due to our new wl1271_translate_reg_addr function,
254 we need to add the REGISTER_BASE to the destination */
255 dest_addr += REGISTERS_BASE;
257 /* We move our pointer to the data */
260 for (i = 0; i < burst_len; i++) {
261 val = (nvs_ptr[0] | (nvs_ptr[1] << 8)
262 | (nvs_ptr[2] << 16) | (nvs_ptr[3] << 24));
264 wl1271_debug(DEBUG_BOOT,
265 "nvs burst write 0x%x: 0x%x",
267 wl1271_write32(wl, dest_addr, val);
275 * We've reached the first zero length, the first NVS table
276 * is 7 bytes further.
279 nvs_len -= nvs_ptr - (u8 *)wl->nvs->nvs;
280 nvs_len = ALIGN(nvs_len, 4);
282 /* FIXME: The driver sets the partition here, but this is not needed,
283 since it sets to the same one as currently in use */
284 /* Now we must set the partition correctly */
285 wl1271_set_partition(wl, &part_table[PART_WORK]);
287 /* Copy the NVS tables to a new block to ensure alignment */
288 /* FIXME: We jump 3 more bytes before uploading the NVS. It seems
289 that our NVS files have three extra zeros here. I'm not sure whether
290 the problem is in our NVS generation or we should really jumpt these
294 nvs_aligned = kmemdup(nvs_ptr, nvs_len, GFP_KERNEL); if
295 (!nvs_aligned) return -ENOMEM;
297 /* And finally we upload the NVS tables */
298 /* FIXME: In wl1271, we upload everything at once.
299 No endianness handling needed here?! The ref driver doesn't do
300 anything about it at this point */
301 wl1271_write(wl, CMD_MBOX_ADDRESS, nvs_aligned, nvs_len, false);
307 static void wl1271_boot_enable_interrupts(struct wl1271 *wl)
309 wl1271_enable_interrupts(wl);
310 wl1271_write32(wl, ACX_REG_INTERRUPT_MASK,
311 WL1271_ACX_INTR_ALL & ~(WL1271_INTR_MASK));
312 wl1271_write32(wl, HI_CFG, HI_CFG_DEF_VAL);
315 static int wl1271_boot_soft_reset(struct wl1271 *wl)
317 unsigned long timeout;
320 /* perform soft reset */
321 wl1271_write32(wl, ACX_REG_SLV_SOFT_RESET, ACX_SLV_SOFT_RESET_BIT);
323 /* SOFT_RESET is self clearing */
324 timeout = jiffies + usecs_to_jiffies(SOFT_RESET_MAX_TIME);
326 boot_data = wl1271_read32(wl, ACX_REG_SLV_SOFT_RESET);
327 wl1271_debug(DEBUG_BOOT, "soft reset bootdata 0x%x", boot_data);
328 if ((boot_data & ACX_SLV_SOFT_RESET_BIT) == 0)
331 if (time_after(jiffies, timeout)) {
332 /* 1.2 check pWhalBus->uSelfClearTime if the
333 * timeout was reached */
334 wl1271_error("soft reset timeout");
338 udelay(SOFT_RESET_STALL_TIME);
342 wl1271_write32(wl, ENABLE, 0x0);
344 /* disable auto calibration on start*/
345 wl1271_write32(wl, SPARE_A2, 0xffff);
350 static int wl1271_boot_run_firmware(struct wl1271 *wl)
355 wl1271_boot_set_ecpu_ctrl(wl, ECPU_CONTROL_HALT);
357 chip_id = wl1271_read32(wl, CHIP_ID_B);
359 wl1271_debug(DEBUG_BOOT, "chip id after firmware boot: 0x%x", chip_id);
361 if (chip_id != wl->chip.id) {
362 wl1271_error("chip id doesn't match after firmware boot");
366 /* wait for init to complete */
368 while (loop++ < INIT_LOOP) {
369 udelay(INIT_LOOP_DELAY);
370 intr = wl1271_read32(wl, ACX_REG_INTERRUPT_NO_CLEAR);
372 if (intr == 0xffffffff) {
373 wl1271_error("error reading hardware complete "
377 /* check that ACX_INTR_INIT_COMPLETE is enabled */
378 else if (intr & WL1271_ACX_INTR_INIT_COMPLETE) {
379 wl1271_write32(wl, ACX_REG_INTERRUPT_ACK,
380 WL1271_ACX_INTR_INIT_COMPLETE);
385 if (loop > INIT_LOOP) {
386 wl1271_error("timeout waiting for the hardware to "
387 "complete initialization");
391 /* get hardware config command mail box */
392 wl->cmd_box_addr = wl1271_read32(wl, REG_COMMAND_MAILBOX_PTR);
394 /* get hardware config event mail box */
395 wl->event_box_addr = wl1271_read32(wl, REG_EVENT_MAILBOX_PTR);
397 /* set the working partition to its "running" mode offset */
398 wl1271_set_partition(wl, &part_table[PART_WORK]);
400 wl1271_debug(DEBUG_MAILBOX, "cmd_box_addr 0x%x event_box_addr 0x%x",
401 wl->cmd_box_addr, wl->event_box_addr);
403 wl1271_boot_fw_version(wl);
406 * in case of full asynchronous mode the firmware event must be
407 * ready to receive event from the command mailbox
410 /* unmask required mbox events */
411 wl->event_mask = BSS_LOSE_EVENT_ID |
412 SCAN_COMPLETE_EVENT_ID |
414 JOIN_EVENT_COMPLETE_ID |
415 DISCONNECT_EVENT_COMPLETE_ID |
416 RSSI_SNR_TRIGGER_0_EVENT_ID;
418 ret = wl1271_event_unmask(wl);
420 wl1271_error("EVENT mask setting failed");
424 wl1271_event_mbox_config(wl);
426 /* firmware startup completed */
430 static int wl1271_boot_write_irq_polarity(struct wl1271 *wl)
434 polarity = wl1271_top_reg_read(wl, OCP_REG_POLARITY);
436 /* We use HIGH polarity, so unset the LOW bit */
437 polarity &= ~POLARITY_LOW;
438 wl1271_top_reg_write(wl, OCP_REG_POLARITY, polarity);
443 int wl1271_boot(struct wl1271 *wl)
448 if (REF_CLOCK == 0 || REF_CLOCK == 2 || REF_CLOCK == 4)
449 /* ref clk: 19.2/38.4/38.4-XTAL */
451 else if (REF_CLOCK == 1 || REF_CLOCK == 3)
455 if (REF_CLOCK != 0) {
457 /* Set clock type (open drain) */
458 val = wl1271_top_reg_read(wl, OCP_REG_CLK_TYPE);
459 val &= FREF_CLK_TYPE_BITS;
460 wl1271_top_reg_write(wl, OCP_REG_CLK_TYPE, val);
462 /* Set clock pull mode (no pull) */
463 val = wl1271_top_reg_read(wl, OCP_REG_CLK_PULL);
465 wl1271_top_reg_write(wl, OCP_REG_CLK_PULL, val);
468 /* Set clock polarity */
469 val = wl1271_top_reg_read(wl, OCP_REG_CLK_POLARITY);
470 val &= FREF_CLK_POLARITY_BITS;
471 val |= CLK_REQ_OUTN_SEL;
472 wl1271_top_reg_write(wl, OCP_REG_CLK_POLARITY, val);
475 wl1271_write32(wl, PLL_PARAMETERS, clk);
477 pause = wl1271_read32(wl, PLL_PARAMETERS);
479 wl1271_debug(DEBUG_BOOT, "pause1 0x%x", pause);
481 pause &= ~(WU_COUNTER_PAUSE_VAL); /* FIXME: This should probably be
482 * WU_COUNTER_PAUSE_VAL instead of
483 * 0x3ff (magic number ). How does
485 pause |= WU_COUNTER_PAUSE_VAL;
486 wl1271_write32(wl, WU_COUNTER_PAUSE, pause);
488 /* Continue the ELP wake up sequence */
489 wl1271_write32(wl, WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL);
492 wl1271_set_partition(wl, &part_table[PART_DRPW]);
494 /* Read-modify-write DRPW_SCRATCH_START register (see next state)
495 to be used by DRPw FW. The RTRIM value will be added by the FW
496 before taking DRPw out of reset */
498 wl1271_debug(DEBUG_BOOT, "DRPW_SCRATCH_START %08x", DRPW_SCRATCH_START);
499 clk = wl1271_read32(wl, DRPW_SCRATCH_START);
501 wl1271_debug(DEBUG_BOOT, "clk2 0x%x", clk);
504 clk |= (REF_CLOCK << 1) << 4;
505 wl1271_write32(wl, DRPW_SCRATCH_START, clk);
507 wl1271_set_partition(wl, &part_table[PART_WORK]);
509 /* Disable interrupts */
510 wl1271_write32(wl, ACX_REG_INTERRUPT_MASK, WL1271_ACX_INTR_ALL);
512 ret = wl1271_boot_soft_reset(wl);
516 /* 2. start processing NVS file */
517 ret = wl1271_boot_upload_nvs(wl);
521 /* write firmware's last address (ie. it's length) to
522 * ACX_EEPROMLESS_IND_REG */
523 wl1271_debug(DEBUG_BOOT, "ACX_EEPROMLESS_IND_REG");
525 wl1271_write32(wl, ACX_EEPROMLESS_IND_REG, ACX_EEPROMLESS_IND_REG);
527 tmp = wl1271_read32(wl, CHIP_ID_B);
529 wl1271_debug(DEBUG_BOOT, "chip id 0x%x", tmp);
531 /* 6. read the EEPROM parameters */
532 tmp = wl1271_read32(wl, SCR_PAD2);
534 ret = wl1271_boot_write_irq_polarity(wl);
538 /* FIXME: Need to check whether this is really what we want */
539 wl1271_write32(wl, ACX_REG_INTERRUPT_MASK,
540 WL1271_ACX_ALL_EVENTS_VECTOR);
542 /* WL1271: The reference driver skips steps 7 to 10 (jumps directly
545 ret = wl1271_boot_upload_firmware(wl);
549 /* 10.5 start firmware */
550 ret = wl1271_boot_run_firmware(wl);
554 /* Enable firmware interrupts now */
555 wl1271_boot_enable_interrupts(wl);
557 /* set the wl1271 default filters */
558 wl->rx_config = WL1271_DEFAULT_RX_CONFIG;
559 wl->rx_filter = WL1271_DEFAULT_RX_FILTER;
561 wl1271_event_mbox_config(wl);