2 * This file is part of wl1271
4 * Copyright (C) 2008-2009 Nokia Corporation
6 * Contact: Luciano Coelho <luciano.coelho@nokia.com>
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License
10 * version 2 as published by the Free Software Foundation.
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
24 #include <linux/gpio.h>
26 #include "wl1271_acx.h"
27 #include "wl1271_reg.h"
28 #include "wl1271_boot.h"
29 #include "wl1271_spi.h"
30 #include "wl1271_io.h"
31 #include "wl1271_event.h"
33 static struct wl1271_partition_set part_table[PART_TABLE_LEN] = {
40 .start = REGISTERS_BASE,
59 .start = REGISTERS_BASE,
92 static void wl1271_boot_set_ecpu_ctrl(struct wl1271 *wl, u32 flag)
96 /* 10.5.0 run the firmware (I) */
97 cpu_ctrl = wl1271_read32(wl, ACX_REG_ECPU_CONTROL);
99 /* 10.5.1 run the firmware (II) */
101 wl1271_write32(wl, ACX_REG_ECPU_CONTROL, cpu_ctrl);
104 static void wl1271_boot_fw_version(struct wl1271 *wl)
106 struct wl1271_static_data static_data;
108 wl1271_read(wl, wl->cmd_box_addr, &static_data, sizeof(static_data),
111 strncpy(wl->chip.fw_ver, static_data.fw_version,
112 sizeof(wl->chip.fw_ver));
114 /* make sure the string is NULL-terminated */
115 wl->chip.fw_ver[sizeof(wl->chip.fw_ver) - 1] = '\0';
118 static int wl1271_boot_upload_firmware_chunk(struct wl1271 *wl, void *buf,
119 size_t fw_data_len, u32 dest)
121 struct wl1271_partition_set partition;
122 int addr, chunk_num, partition_limit;
125 /* whal_FwCtrl_LoadFwImageSm() */
127 wl1271_debug(DEBUG_BOOT, "starting firmware upload");
129 wl1271_debug(DEBUG_BOOT, "fw_data_len %zd chunk_size %d",
130 fw_data_len, CHUNK_SIZE);
132 if ((fw_data_len % 4) != 0) {
133 wl1271_error("firmware length not multiple of four");
137 chunk = kmalloc(CHUNK_SIZE, GFP_KERNEL);
139 wl1271_error("allocation for firmware upload chunk failed");
143 memcpy(&partition, &part_table[PART_DOWN], sizeof(partition));
144 partition.mem.start = dest;
145 wl1271_set_partition(wl, &partition);
147 /* 10.1 set partition limit and chunk num */
149 partition_limit = part_table[PART_DOWN].mem.size;
151 while (chunk_num < fw_data_len / CHUNK_SIZE) {
152 /* 10.2 update partition, if needed */
153 addr = dest + (chunk_num + 2) * CHUNK_SIZE;
154 if (addr > partition_limit) {
155 addr = dest + chunk_num * CHUNK_SIZE;
156 partition_limit = chunk_num * CHUNK_SIZE +
157 part_table[PART_DOWN].mem.size;
158 partition.mem.start = addr;
159 wl1271_set_partition(wl, &partition);
162 /* 10.3 upload the chunk */
163 addr = dest + chunk_num * CHUNK_SIZE;
164 p = buf + chunk_num * CHUNK_SIZE;
165 memcpy(chunk, p, CHUNK_SIZE);
166 wl1271_debug(DEBUG_BOOT, "uploading fw chunk 0x%p to 0x%x",
168 wl1271_write(wl, addr, chunk, CHUNK_SIZE, false);
173 /* 10.4 upload the last chunk */
174 addr = dest + chunk_num * CHUNK_SIZE;
175 p = buf + chunk_num * CHUNK_SIZE;
176 memcpy(chunk, p, fw_data_len % CHUNK_SIZE);
177 wl1271_debug(DEBUG_BOOT, "uploading fw last chunk (%zd B) 0x%p to 0x%x",
178 fw_data_len % CHUNK_SIZE, p, addr);
179 wl1271_write(wl, addr, chunk, fw_data_len % CHUNK_SIZE, false);
185 static int wl1271_boot_upload_firmware(struct wl1271 *wl)
187 u32 chunks, addr, len;
192 chunks = be32_to_cpup((__be32 *) fw);
195 wl1271_debug(DEBUG_BOOT, "firmware chunks to be uploaded: %u", chunks);
198 addr = be32_to_cpup((__be32 *) fw);
200 len = be32_to_cpup((__be32 *) fw);
204 wl1271_info("firmware chunk too long: %u", len);
207 wl1271_debug(DEBUG_BOOT, "chunk %d addr 0x%x len %u",
209 ret = wl1271_boot_upload_firmware_chunk(wl, fw, len, addr);
218 static int wl1271_boot_upload_nvs(struct wl1271 *wl)
220 size_t nvs_len, burst_len;
223 u8 *nvs_ptr, *nvs_aligned;
228 /* only the first part of the NVS needs to be uploaded */
229 nvs_len = sizeof(wl->nvs->nvs);
230 nvs_ptr = (u8 *)wl->nvs->nvs;
233 * Layout before the actual NVS tables:
234 * 1 byte : burst length.
235 * 2 bytes: destination address.
236 * n bytes: data to burst copy.
238 * This is ended by a 0 length, then the NVS tables.
241 /* FIXME: Do we need to check here whether the LSB is 1? */
243 burst_len = nvs_ptr[0];
244 dest_addr = (nvs_ptr[1] & 0xfe) | ((u32)(nvs_ptr[2] << 8));
246 /* FIXME: Due to our new wl1271_translate_reg_addr function,
247 we need to add the REGISTER_BASE to the destination */
248 dest_addr += REGISTERS_BASE;
250 /* We move our pointer to the data */
253 for (i = 0; i < burst_len; i++) {
254 val = (nvs_ptr[0] | (nvs_ptr[1] << 8)
255 | (nvs_ptr[2] << 16) | (nvs_ptr[3] << 24));
257 wl1271_debug(DEBUG_BOOT,
258 "nvs burst write 0x%x: 0x%x",
260 wl1271_write32(wl, dest_addr, val);
268 * We've reached the first zero length, the first NVS table
269 * is 7 bytes further.
272 nvs_len -= nvs_ptr - (u8 *)wl->nvs->nvs;
273 nvs_len = ALIGN(nvs_len, 4);
275 /* FIXME: The driver sets the partition here, but this is not needed,
276 since it sets to the same one as currently in use */
277 /* Now we must set the partition correctly */
278 wl1271_set_partition(wl, &part_table[PART_WORK]);
280 /* Copy the NVS tables to a new block to ensure alignment */
281 /* FIXME: We jump 3 more bytes before uploading the NVS. It seems
282 that our NVS files have three extra zeros here. I'm not sure whether
283 the problem is in our NVS generation or we should really jumpt these
287 nvs_aligned = kmemdup(nvs_ptr, nvs_len, GFP_KERNEL); if
288 (!nvs_aligned) return -ENOMEM;
290 /* And finally we upload the NVS tables */
291 /* FIXME: In wl1271, we upload everything at once.
292 No endianness handling needed here?! The ref driver doesn't do
293 anything about it at this point */
294 wl1271_write(wl, CMD_MBOX_ADDRESS, nvs_aligned, nvs_len, false);
300 static void wl1271_boot_enable_interrupts(struct wl1271 *wl)
303 wl1271_write32(wl, ACX_REG_INTERRUPT_MASK,
304 WL1271_ACX_INTR_ALL & ~(WL1271_INTR_MASK));
305 wl1271_write32(wl, HI_CFG, HI_CFG_DEF_VAL);
308 static int wl1271_boot_soft_reset(struct wl1271 *wl)
310 unsigned long timeout;
313 /* perform soft reset */
314 wl1271_write32(wl, ACX_REG_SLV_SOFT_RESET, ACX_SLV_SOFT_RESET_BIT);
316 /* SOFT_RESET is self clearing */
317 timeout = jiffies + usecs_to_jiffies(SOFT_RESET_MAX_TIME);
319 boot_data = wl1271_read32(wl, ACX_REG_SLV_SOFT_RESET);
320 wl1271_debug(DEBUG_BOOT, "soft reset bootdata 0x%x", boot_data);
321 if ((boot_data & ACX_SLV_SOFT_RESET_BIT) == 0)
324 if (time_after(jiffies, timeout)) {
325 /* 1.2 check pWhalBus->uSelfClearTime if the
326 * timeout was reached */
327 wl1271_error("soft reset timeout");
331 udelay(SOFT_RESET_STALL_TIME);
335 wl1271_write32(wl, ENABLE, 0x0);
337 /* disable auto calibration on start*/
338 wl1271_write32(wl, SPARE_A2, 0xffff);
343 static int wl1271_boot_run_firmware(struct wl1271 *wl)
346 u32 chip_id, interrupt;
348 wl1271_boot_set_ecpu_ctrl(wl, ECPU_CONTROL_HALT);
350 chip_id = wl1271_read32(wl, CHIP_ID_B);
352 wl1271_debug(DEBUG_BOOT, "chip id after firmware boot: 0x%x", chip_id);
354 if (chip_id != wl->chip.id) {
355 wl1271_error("chip id doesn't match after firmware boot");
359 /* wait for init to complete */
361 while (loop++ < INIT_LOOP) {
362 udelay(INIT_LOOP_DELAY);
363 interrupt = wl1271_read32(wl, ACX_REG_INTERRUPT_NO_CLEAR);
365 if (interrupt == 0xffffffff) {
366 wl1271_error("error reading hardware complete "
370 /* check that ACX_INTR_INIT_COMPLETE is enabled */
371 else if (interrupt & WL1271_ACX_INTR_INIT_COMPLETE) {
372 wl1271_write32(wl, ACX_REG_INTERRUPT_ACK,
373 WL1271_ACX_INTR_INIT_COMPLETE);
378 if (loop > INIT_LOOP) {
379 wl1271_error("timeout waiting for the hardware to "
380 "complete initialization");
384 /* get hardware config command mail box */
385 wl->cmd_box_addr = wl1271_read32(wl, REG_COMMAND_MAILBOX_PTR);
387 /* get hardware config event mail box */
388 wl->event_box_addr = wl1271_read32(wl, REG_EVENT_MAILBOX_PTR);
390 /* set the working partition to its "running" mode offset */
391 wl1271_set_partition(wl, &part_table[PART_WORK]);
393 wl1271_debug(DEBUG_MAILBOX, "cmd_box_addr 0x%x event_box_addr 0x%x",
394 wl->cmd_box_addr, wl->event_box_addr);
396 wl1271_boot_fw_version(wl);
399 * in case of full asynchronous mode the firmware event must be
400 * ready to receive event from the command mailbox
403 /* unmask required mbox events */
404 wl->event_mask = BSS_LOSE_EVENT_ID |
405 SCAN_COMPLETE_EVENT_ID |
408 ret = wl1271_event_unmask(wl);
410 wl1271_error("EVENT mask setting failed");
414 wl1271_event_mbox_config(wl);
416 /* firmware startup completed */
420 static int wl1271_boot_write_irq_polarity(struct wl1271 *wl)
424 polarity = wl1271_top_reg_read(wl, OCP_REG_POLARITY);
426 /* We use HIGH polarity, so unset the LOW bit */
427 polarity &= ~POLARITY_LOW;
428 wl1271_top_reg_write(wl, OCP_REG_POLARITY, polarity);
433 int wl1271_boot(struct wl1271 *wl)
438 if (REF_CLOCK == 0 || REF_CLOCK == 2 || REF_CLOCK == 4)
439 /* ref clk: 19.2/38.4/38.4-XTAL */
441 else if (REF_CLOCK == 1 || REF_CLOCK == 3)
445 if (REF_CLOCK != 0) {
448 val = wl1271_top_reg_read(wl, OCP_REG_CLK_TYPE);
449 val &= FREF_CLK_TYPE_BITS;
451 wl1271_top_reg_write(wl, OCP_REG_CLK_TYPE, val);
454 /* Set clock polarity */
455 val = wl1271_top_reg_read(wl, OCP_REG_CLK_POLARITY);
456 val &= FREF_CLK_POLARITY_BITS;
457 val |= CLK_REQ_OUTN_SEL;
458 wl1271_top_reg_write(wl, OCP_REG_CLK_POLARITY, val);
461 wl1271_write32(wl, PLL_PARAMETERS, clk);
463 pause = wl1271_read32(wl, PLL_PARAMETERS);
465 wl1271_debug(DEBUG_BOOT, "pause1 0x%x", pause);
467 pause &= ~(WU_COUNTER_PAUSE_VAL); /* FIXME: This should probably be
468 * WU_COUNTER_PAUSE_VAL instead of
469 * 0x3ff (magic number ). How does
471 pause |= WU_COUNTER_PAUSE_VAL;
472 wl1271_write32(wl, WU_COUNTER_PAUSE, pause);
474 /* Continue the ELP wake up sequence */
475 wl1271_write32(wl, WELP_ARM_COMMAND, WELP_ARM_COMMAND_VAL);
478 wl1271_set_partition(wl, &part_table[PART_DRPW]);
480 /* Read-modify-write DRPW_SCRATCH_START register (see next state)
481 to be used by DRPw FW. The RTRIM value will be added by the FW
482 before taking DRPw out of reset */
484 wl1271_debug(DEBUG_BOOT, "DRPW_SCRATCH_START %08x", DRPW_SCRATCH_START);
485 clk = wl1271_read32(wl, DRPW_SCRATCH_START);
487 wl1271_debug(DEBUG_BOOT, "clk2 0x%x", clk);
490 clk |= (REF_CLOCK << 1) << 4;
491 wl1271_write32(wl, DRPW_SCRATCH_START, clk);
493 wl1271_set_partition(wl, &part_table[PART_WORK]);
495 /* Disable interrupts */
496 wl1271_write32(wl, ACX_REG_INTERRUPT_MASK, WL1271_ACX_INTR_ALL);
498 ret = wl1271_boot_soft_reset(wl);
502 /* 2. start processing NVS file */
503 ret = wl1271_boot_upload_nvs(wl);
507 /* write firmware's last address (ie. it's length) to
508 * ACX_EEPROMLESS_IND_REG */
509 wl1271_debug(DEBUG_BOOT, "ACX_EEPROMLESS_IND_REG");
511 wl1271_write32(wl, ACX_EEPROMLESS_IND_REG, ACX_EEPROMLESS_IND_REG);
513 tmp = wl1271_read32(wl, CHIP_ID_B);
515 wl1271_debug(DEBUG_BOOT, "chip id 0x%x", tmp);
517 /* 6. read the EEPROM parameters */
518 tmp = wl1271_read32(wl, SCR_PAD2);
520 ret = wl1271_boot_write_irq_polarity(wl);
524 /* FIXME: Need to check whether this is really what we want */
525 wl1271_write32(wl, ACX_REG_INTERRUPT_MASK,
526 WL1271_ACX_ALL_EVENTS_VECTOR);
528 /* WL1271: The reference driver skips steps 7 to 10 (jumps directly
531 ret = wl1271_boot_upload_firmware(wl);
535 /* 10.5 start firmware */
536 ret = wl1271_boot_run_firmware(wl);
540 /* Enable firmware interrupts now */
541 wl1271_boot_enable_interrupts(wl);
543 /* set the wl1271 default filters */
544 wl->rx_config = WL1271_DEFAULT_RX_CONFIG;
545 wl->rx_filter = WL1271_DEFAULT_RX_FILTER;
547 wl1271_event_mbox_config(wl);