2 * This file is part of wlcore
4 * Copyright (C) 2011 Texas Instruments Inc.
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License
8 * version 2 as published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
25 #include <linux/platform_device.h>
30 /* The maximum number of Tx descriptors in all chip families */
31 #define WLCORE_MAX_TX_DESCRIPTORS 32
33 /* forward declaration */
34 struct wl1271_tx_hw_descr;
38 int (*identify_chip)(struct wl1271 *wl);
39 int (*identify_fw)(struct wl1271 *wl);
40 int (*boot)(struct wl1271 *wl);
41 void (*trigger_cmd)(struct wl1271 *wl, int cmd_box_addr,
42 void *buf, size_t len);
43 void (*ack_event)(struct wl1271 *wl);
44 u32 (*calc_tx_blocks)(struct wl1271 *wl, u32 len, u32 spare_blks);
45 void (*set_tx_desc_blocks)(struct wl1271 *wl,
46 struct wl1271_tx_hw_descr *desc,
47 u32 blks, u32 spare_blks);
48 void (*set_tx_desc_data_len)(struct wl1271 *wl,
49 struct wl1271_tx_hw_descr *desc,
51 enum wl_rx_buf_align (*get_rx_buf_align)(struct wl1271 *wl,
53 void (*prepare_read)(struct wl1271 *wl, u32 rx_desc, u32 len);
54 u32 (*get_rx_packet_len)(struct wl1271 *wl, void *rx_data,
56 void (*tx_delayed_compl)(struct wl1271 *wl);
57 void (*tx_immediate_compl)(struct wl1271 *wl);
58 int (*hw_init)(struct wl1271 *wl);
59 int (*init_vif)(struct wl1271 *wl, struct wl12xx_vif *wlvif);
60 u32 (*sta_get_ap_rate_mask)(struct wl1271 *wl,
61 struct wl12xx_vif *wlvif);
62 s8 (*get_pg_ver)(struct wl1271 *wl);
63 void (*get_mac)(struct wl1271 *wl);
66 enum wlcore_partitions {
71 PART_TOP_PRCM_ELP_SOC,
77 struct wlcore_partition {
82 struct wlcore_partition_set {
83 struct wlcore_partition mem;
84 struct wlcore_partition reg;
85 struct wlcore_partition mem2;
86 struct wlcore_partition mem3;
89 enum wlcore_registers {
90 /* register addresses, used with partition translation */
92 REG_INTERRUPT_NO_CLEAR,
94 REG_COMMAND_MAILBOX_PTR,
95 REG_EVENT_MAILBOX_PTR,
100 REG_CMD_MBOX_ADDRESS,
102 /* data access memory addresses, used with partition translation */
106 /* raw data access memory addresses */
107 REG_RAW_FW_STATUS_ADDR,
113 struct ieee80211_hw *hw;
114 bool mac80211_registered;
120 struct wl1271_if_operations *if_ops;
122 void (*set_power)(bool enable);
128 enum wl1271_state state;
129 enum wl12xx_fw_type fw_type;
136 struct wlcore_partition_set curr_part;
138 struct wl1271_chip chip;
149 /* address read from the fuse ROM */
153 /* we have up to 2 MAC addresses */
154 struct mac_address addresses[2];
158 unsigned long links_map[BITS_TO_LONGS(WL12XX_MAX_LINKS)];
159 unsigned long roles_map[BITS_TO_LONGS(WL12XX_MAX_ROLES)];
160 unsigned long roc_map[BITS_TO_LONGS(WL12XX_MAX_ROLES)];
161 unsigned long rate_policies_map[
162 BITS_TO_LONGS(WL12XX_MAX_RATE_POLICIES)];
164 struct list_head wlvif_list;
169 struct wl1271_acx_mem_map *target_mem_map;
171 /* Accounting for allocated / available TX blocks on HW */
173 u32 tx_blocks_available;
174 u32 tx_allocated_blocks;
175 u32 tx_results_count;
177 /* Accounting for allocated / available Tx packets in HW */
178 u32 tx_pkts_freed[NUM_TX_QUEUES];
179 u32 tx_allocated_pkts[NUM_TX_QUEUES];
181 /* Transmitted TX packets counter for chipset interface */
182 u32 tx_packets_count;
184 /* Time-offset between host and chipset clocks */
187 /* Frames scheduled for transmission, not handled yet */
188 int tx_queue_count[NUM_TX_QUEUES];
189 long stopped_queues_map;
191 /* Frames received, not handled yet by mac80211 */
192 struct sk_buff_head deferred_rx_queue;
194 /* Frames sent, not returned yet to mac80211 */
195 struct sk_buff_head deferred_tx_queue;
197 struct work_struct tx_work;
198 struct workqueue_struct *freezable_wq;
200 /* Pending TX frames */
201 unsigned long tx_frames_map[BITS_TO_LONGS(WLCORE_MAX_TX_DESCRIPTORS)];
202 struct sk_buff *tx_frames[WLCORE_MAX_TX_DESCRIPTORS];
208 /* Rx memory pool address */
209 struct wl1271_rx_mem_pool_addr rx_mem_pool_addr;
211 /* Intermediate buffer, used for packet aggregation */
214 /* Reusable dummy packet template */
215 struct sk_buff *dummy_packet;
217 /* Network stack work */
218 struct work_struct netstack_work;
223 /* Number of valid bytes in the FW log buffer */
226 /* Sysfs FW log entry readers wait queue */
227 wait_queue_head_t fwlog_waitq;
229 /* Hardware recovery work */
230 struct work_struct recovery_work;
232 /* Pointer that holds DMA-friendly block for the mailbox */
233 struct event_mailbox *mbox;
235 /* The mbox event mask */
238 /* Mailbox pointers */
241 /* Are we currently scanning */
242 struct ieee80211_vif *scan_vif;
243 struct wl1271_scan scan;
244 struct delayed_work scan_complete_work;
248 /* The current band */
249 enum ieee80211_band band;
251 struct completion *elp_compl;
252 struct delayed_work elp_work;
257 struct wl1271_stats stats;
261 u32 buffer_busyword[WL1271_BUSY_WORD_CNT];
263 struct wl_fw_status *fw_status;
264 struct wl1271_tx_hw_res_if *tx_res_if;
266 /* Current chipset configuration */
267 struct wlcore_conf conf;
273 /* Most recently reported noise in dBm */
276 /* bands supported by this instance of wl12xx */
277 struct ieee80211_supported_band bands[IEEE80211_NUM_BANDS];
282 * wowlan trigger was configured during suspend.
283 * (currently, only "ANY" trigger is supported)
286 bool irq_wake_enabled;
289 * AP-mode - links indexed by HLID. The global and broadcast links
292 struct wl1271_link links[WL12XX_MAX_LINKS];
294 /* AP-mode - a bitmap of links currently in PS mode according to FW */
297 /* AP-mode - a bitmap of links currently in PS mode in mac80211 */
298 unsigned long ap_ps_map;
300 /* Quirks of specific hardware revisions */
303 /* Platform limitations */
304 unsigned int platform_quirks;
306 /* number of currently active RX BA sessions */
307 int ba_rx_session_count;
309 /* AP-mode - number of currently connected stations */
310 int active_sta_count;
312 /* last wlvif we transmitted from */
313 struct wl12xx_vif *last_wlvif;
315 /* work to fire when Tx is stuck */
316 struct delayed_work tx_watchdog_work;
318 struct wlcore_ops *ops;
319 /* pointer to the lower driver partition table */
320 const struct wlcore_partition_set *ptable;
321 /* pointer to the lower driver register table */
323 /* name of the firmwares to load - for PLT, single role, multi-role */
324 const char *plt_fw_name;
325 const char *sr_fw_name;
326 const char *mr_fw_name;
328 /* per-chip-family private structure */
331 /* number of TX descriptors the HW supports. */
334 /* spare Tx blocks for normal/GEM operating modes */
338 /* translate HW Tx rates to standard rate-indices */
339 const u8 **band_rate_to_idx;
341 /* size of table for HW rates that can be received from chip */
342 u8 hw_tx_rate_tbl_size;
344 /* this HW rate and below are considered HT rates for this chip */
347 /* HW HT (11n) capabilities */
348 struct ieee80211_sta_ht_cap ht_cap;
350 /* size of the private FW status data */
351 size_t fw_status_priv_len;
354 int __devinit wlcore_probe(struct wl1271 *wl, struct platform_device *pdev);
355 int __devexit wlcore_remove(struct platform_device *pdev);
356 struct ieee80211_hw *wlcore_alloc_hw(size_t priv_size);
357 int wlcore_free_hw(struct wl1271 *wl);
359 /* Firmware image load chunk size */
360 #define CHUNK_SIZE 16384
364 /* Each RX/TX transaction requires an end-of-transaction transfer */
365 #define WLCORE_QUIRK_END_OF_TRANSACTION BIT(0)
367 /* wl127x and SPI don't support SDIO block size alignment */
368 #define WLCORE_QUIRK_TX_BLOCKSIZE_ALIGN BIT(2)
370 /* means aggregated Rx packets are aligned to a SDIO block */
371 #define WLCORE_QUIRK_RX_BLOCKSIZE_ALIGN BIT(3)
373 /* Older firmwares did not implement the FW logger over bus feature */
374 #define WLCORE_QUIRK_FWLOG_NOT_IMPLEMENTED BIT(4)
376 /* Older firmwares use an old NVS format */
377 #define WLCORE_QUIRK_LEGACY_NVS BIT(5)
379 /* Some firmwares may not support ELP */
380 #define WLCORE_QUIRK_NO_ELP BIT(6)
382 /* TODO: move to the lower drivers when all usages are abstracted */
383 #define CHIP_ID_1271_PG10 (0x4030101)
384 #define CHIP_ID_1271_PG20 (0x4030111)
385 #define CHIP_ID_1283_PG10 (0x05030101)
386 #define CHIP_ID_1283_PG20 (0x05030111)
388 /* TODO: move all these common registers and values elsewhere */
389 #define HW_ACCESS_ELP_CTRL_REG 0x1FFFC
391 /* ELP register commands */
392 #define ELPCTRL_WAKE_UP 0x1
393 #define ELPCTRL_WAKE_UP_WLAN_READY 0x5
394 #define ELPCTRL_SLEEP 0x0
395 /* ELP WLAN_READY bit */
396 #define ELPCTRL_WLAN_READY 0x2
398 /*************************************************************************
400 Interrupt Trigger Register (Host -> WiLink)
402 **************************************************************************/
404 /* Hardware to Embedded CPU Interrupts - first 32-bit register set */
407 * The host sets this bit to inform the Wlan
408 * FW that a TX packet is in the XFER
411 #define INTR_TRIG_TX_PROC0 BIT(2)
414 * The host sets this bit to inform the FW
415 * that it read a packet from RX XFER
418 #define INTR_TRIG_RX_PROC0 BIT(3)
420 #define INTR_TRIG_DEBUG_ACK BIT(4)
422 #define INTR_TRIG_STATE_CHANGED BIT(5)
424 /* Hardware to Embedded CPU Interrupts - second 32-bit register set */
427 * The host sets this bit to inform the FW
428 * that it read a packet from RX XFER
431 #define INTR_TRIG_RX_PROC1 BIT(17)
434 * The host sets this bit to inform the Wlan
435 * hardware that a TX packet is in the XFER
438 #define INTR_TRIG_TX_PROC1 BIT(18)
440 #define ACX_SLV_SOFT_RESET_BIT BIT(1)
441 #define SOFT_RESET_MAX_TIME 1000000
442 #define SOFT_RESET_STALL_TIME 1000
444 #define ECPU_CONTROL_HALT 0x00000101
446 #define WELP_ARM_COMMAND_VAL 0x4
448 #endif /* __WLCORE_H__ */