1 /******************************************************************************
3 * Copyright(c) 2009-2012 Realtek Corporation.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
18 * The full GNU General Public License is included in this distribution in the
19 * file called LICENSE.
21 * Contact Information:
22 * wlanfae <wlanfae@realtek.com>
23 * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
24 * Hsinchu 300, Taiwan.
26 * Larry Finger <Larry.Finger@lwfinger.net>
28 *****************************************************************************/
36 #include <linux/export.h>
37 #include <linux/kmemleak.h>
38 #include <linux/module.h>
40 MODULE_AUTHOR("lizhaoming <chaoming_li@realsil.com.cn>");
41 MODULE_AUTHOR("Realtek WlanFAE <wlanfae@realtek.com>");
42 MODULE_AUTHOR("Larry Finger <Larry.FInger@lwfinger.net>");
43 MODULE_LICENSE("GPL");
44 MODULE_DESCRIPTION("PCI basic driver for rtlwifi");
46 static const u16 pcibridge_vendors[PCI_BRIDGE_VENDOR_MAX] = {
53 static const u8 ac_to_hwq[] = {
60 static u8 _rtl_mac_to_hwqueue(struct ieee80211_hw *hw,
63 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
64 __le16 fc = rtl_get_fc(skb);
65 u8 queue_index = skb_get_queue_mapping(skb);
67 if (unlikely(ieee80211_is_beacon(fc)))
69 if (ieee80211_is_mgmt(fc) || ieee80211_is_ctl(fc))
71 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
72 if (ieee80211_is_nullfunc(fc))
75 return ac_to_hwq[queue_index];
78 /* Update PCI dependent default settings*/
79 static void _rtl_pci_update_default_setting(struct ieee80211_hw *hw)
81 struct rtl_priv *rtlpriv = rtl_priv(hw);
82 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
83 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
84 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
85 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
88 ppsc->reg_rfps_level = 0;
89 ppsc->support_aspm = false;
91 /*Update PCI ASPM setting */
92 ppsc->const_amdpci_aspm = rtlpci->const_amdpci_aspm;
93 switch (rtlpci->const_pci_aspm) {
99 /*ASPM dynamically enabled/disable. */
100 ppsc->reg_rfps_level |= RT_RF_LPS_LEVEL_ASPM;
104 /*ASPM with Clock Req dynamically enabled/disable. */
105 ppsc->reg_rfps_level |= (RT_RF_LPS_LEVEL_ASPM |
106 RT_RF_OFF_LEVL_CLK_REQ);
111 * Always enable ASPM and Clock Req
112 * from initialization to halt.
114 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM);
115 ppsc->reg_rfps_level |= (RT_RF_PS_LEVEL_ALWAYS_ASPM |
116 RT_RF_OFF_LEVL_CLK_REQ);
121 * Always enable ASPM without Clock Req
122 * from initialization to halt.
124 ppsc->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM |
125 RT_RF_OFF_LEVL_CLK_REQ);
126 ppsc->reg_rfps_level |= RT_RF_PS_LEVEL_ALWAYS_ASPM;
130 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
132 /*Update Radio OFF setting */
133 switch (rtlpci->const_hwsw_rfoff_d3) {
135 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
136 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
140 if (ppsc->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
141 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
142 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
146 ppsc->reg_rfps_level |= RT_RF_OFF_LEVL_PCI_D3;
150 /*Set HW definition to determine if it supports ASPM. */
151 switch (rtlpci->const_support_pciaspm) {
153 /*Not support ASPM. */
154 bool support_aspm = false;
155 ppsc->support_aspm = support_aspm;
160 bool support_aspm = true;
161 bool support_backdoor = true;
162 ppsc->support_aspm = support_aspm;
164 /*if (priv->oem_id == RT_CID_TOSHIBA &&
165 !priv->ndis_adapter.amd_l1_patch)
166 support_backdoor = false; */
168 ppsc->support_backdoor = support_backdoor;
173 /*ASPM value set by chipset. */
174 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL) {
175 bool support_aspm = true;
176 ppsc->support_aspm = support_aspm;
180 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
181 "switch case not processed\n");
185 /* toshiba aspm issue, toshiba will set aspm selfly
186 * so we should not set aspm in driver */
187 pci_read_config_byte(rtlpci->pdev, 0x80, &init_aspm);
188 if (rtlpriv->rtlhal.hw_type == HARDWARE_TYPE_RTL8192SE &&
190 ppsc->support_aspm = false;
193 static bool _rtl_pci_platform_switch_device_pci_aspm(
194 struct ieee80211_hw *hw,
197 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
198 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
200 if (rtlhal->hw_type != HARDWARE_TYPE_RTL8192SE)
203 pci_write_config_byte(rtlpci->pdev, 0x80, value);
208 /*When we set 0x01 to enable clk request. Set 0x0 to disable clk req.*/
209 static void _rtl_pci_switch_clk_req(struct ieee80211_hw *hw, u8 value)
211 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
212 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
214 pci_write_config_byte(rtlpci->pdev, 0x81, value);
216 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE)
220 /*Disable RTL8192SE ASPM & Disable Pci Bridge ASPM*/
221 static void rtl_pci_disable_aspm(struct ieee80211_hw *hw)
223 struct rtl_priv *rtlpriv = rtl_priv(hw);
224 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
225 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
226 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
227 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
228 u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
229 /*Retrieve original configuration settings. */
230 u8 linkctrl_reg = pcipriv->ndis_adapter.linkctrl_reg;
231 u16 pcibridge_linkctrlreg = pcipriv->ndis_adapter.
232 pcibridge_linkctrlreg;
236 if (!ppsc->support_aspm)
239 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
240 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
241 "PCI(Bridge) UNKNOWN\n");
246 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
247 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
248 _rtl_pci_switch_clk_req(hw, 0x0);
251 /*for promising device will in L0 state after an I/O. */
252 pci_read_config_byte(rtlpci->pdev, 0x80, &tmp_u1b);
254 /*Set corresponding value. */
255 aspmlevel |= BIT(0) | BIT(1);
256 linkctrl_reg &= ~aspmlevel;
257 pcibridge_linkctrlreg &= ~(BIT(0) | BIT(1));
259 _rtl_pci_platform_switch_device_pci_aspm(hw, linkctrl_reg);
262 /*4 Disable Pci Bridge ASPM */
263 pci_write_config_byte(rtlpci->pdev, (num4bytes << 2),
264 pcibridge_linkctrlreg);
270 *Enable RTL8192SE ASPM & Enable Pci Bridge ASPM for
271 *power saving We should follow the sequence to enable
272 *RTL8192SE first then enable Pci Bridge ASPM
273 *or the system will show bluescreen.
275 static void rtl_pci_enable_aspm(struct ieee80211_hw *hw)
277 struct rtl_priv *rtlpriv = rtl_priv(hw);
278 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
279 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
280 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
281 u8 pcibridge_vendor = pcipriv->ndis_adapter.pcibridge_vendor;
282 u8 num4bytes = pcipriv->ndis_adapter.num4bytes;
284 u8 u_pcibridge_aspmsetting;
285 u8 u_device_aspmsetting;
287 if (!ppsc->support_aspm)
290 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
291 RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
292 "PCI(Bridge) UNKNOWN\n");
296 /*4 Enable Pci Bridge ASPM */
298 u_pcibridge_aspmsetting =
299 pcipriv->ndis_adapter.pcibridge_linkctrlreg |
300 rtlpci->const_hostpci_aspm_setting;
302 if (pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL)
303 u_pcibridge_aspmsetting &= ~BIT(0);
305 pci_write_config_byte(rtlpci->pdev, (num4bytes << 2),
306 u_pcibridge_aspmsetting);
308 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
309 "PlatformEnableASPM(): Write reg[%x] = %x\n",
310 (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10),
311 u_pcibridge_aspmsetting);
315 /*Get ASPM level (with/without Clock Req) */
316 aspmlevel = rtlpci->const_devicepci_aspm_setting;
317 u_device_aspmsetting = pcipriv->ndis_adapter.linkctrl_reg;
319 /*_rtl_pci_platform_switch_device_pci_aspm(dev,*/
320 /*(priv->ndis_adapter.linkctrl_reg | ASPMLevel)); */
322 u_device_aspmsetting |= aspmlevel;
324 _rtl_pci_platform_switch_device_pci_aspm(hw, u_device_aspmsetting);
326 if (ppsc->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
327 _rtl_pci_switch_clk_req(hw, (ppsc->reg_rfps_level &
328 RT_RF_OFF_LEVL_CLK_REQ) ? 1 : 0);
329 RT_SET_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_CLK_REQ);
334 static bool rtl_pci_get_amd_l1_patch(struct ieee80211_hw *hw)
336 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
342 pci_write_config_byte(rtlpci->pdev, 0xe0, 0xa0);
344 pci_read_config_byte(rtlpci->pdev, 0xe0, &offset_e0);
346 if (offset_e0 == 0xA0) {
347 pci_read_config_dword(rtlpci->pdev, 0xe4, &offset_e4);
348 if (offset_e4 & BIT(23))
355 static bool rtl_pci_check_buddy_priv(struct ieee80211_hw *hw,
356 struct rtl_priv **buddy_priv)
358 struct rtl_priv *rtlpriv = rtl_priv(hw);
359 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
360 bool find_buddy_priv = false;
361 struct rtl_priv *tpriv = NULL;
362 struct rtl_pci_priv *tpcipriv = NULL;
364 if (!list_empty(&rtlpriv->glb_var->glb_priv_list)) {
365 list_for_each_entry(tpriv, &rtlpriv->glb_var->glb_priv_list,
368 tpcipriv = (struct rtl_pci_priv *)tpriv->priv;
369 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
370 "pcipriv->ndis_adapter.funcnumber %x\n",
371 pcipriv->ndis_adapter.funcnumber);
372 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
373 "tpcipriv->ndis_adapter.funcnumber %x\n",
374 tpcipriv->ndis_adapter.funcnumber);
376 if ((pcipriv->ndis_adapter.busnumber ==
377 tpcipriv->ndis_adapter.busnumber) &&
378 (pcipriv->ndis_adapter.devnumber ==
379 tpcipriv->ndis_adapter.devnumber) &&
380 (pcipriv->ndis_adapter.funcnumber !=
381 tpcipriv->ndis_adapter.funcnumber)) {
382 find_buddy_priv = true;
389 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
390 "find_buddy_priv %d\n", find_buddy_priv);
395 return find_buddy_priv;
398 static void rtl_pci_get_linkcontrol_field(struct ieee80211_hw *hw)
400 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
401 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
402 u8 capabilityoffset = pcipriv->ndis_adapter.pcibridge_pciehdr_offset;
406 num4bbytes = (capabilityoffset + 0x10) / 4;
408 /*Read Link Control Register */
409 pci_read_config_byte(rtlpci->pdev, (num4bbytes << 2), &linkctrl_reg);
411 pcipriv->ndis_adapter.pcibridge_linkctrlreg = linkctrl_reg;
414 static void rtl_pci_parse_configuration(struct pci_dev *pdev,
415 struct ieee80211_hw *hw)
417 struct rtl_priv *rtlpriv = rtl_priv(hw);
418 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
423 /*Link Control Register */
424 pcie_capability_read_word(pdev, PCI_EXP_LNKCTL, &linkctrl_reg);
425 pcipriv->ndis_adapter.linkctrl_reg = (u8)linkctrl_reg;
427 RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "Link Control Register =%x\n",
428 pcipriv->ndis_adapter.linkctrl_reg);
430 pci_read_config_byte(pdev, 0x98, &tmp);
432 pci_write_config_byte(pdev, 0x98, tmp);
435 pci_write_config_byte(pdev, 0x70f, tmp);
438 static void rtl_pci_init_aspm(struct ieee80211_hw *hw)
440 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
442 _rtl_pci_update_default_setting(hw);
444 if (ppsc->reg_rfps_level & RT_RF_PS_LEVEL_ALWAYS_ASPM) {
445 /*Always enable ASPM & Clock Req. */
446 rtl_pci_enable_aspm(hw);
447 RT_SET_PS_LEVEL(ppsc, RT_RF_PS_LEVEL_ALWAYS_ASPM);
452 static void _rtl_pci_io_handler_init(struct device *dev,
453 struct ieee80211_hw *hw)
455 struct rtl_priv *rtlpriv = rtl_priv(hw);
457 rtlpriv->io.dev = dev;
459 rtlpriv->io.write8_async = pci_write8_async;
460 rtlpriv->io.write16_async = pci_write16_async;
461 rtlpriv->io.write32_async = pci_write32_async;
463 rtlpriv->io.read8_sync = pci_read8_sync;
464 rtlpriv->io.read16_sync = pci_read16_sync;
465 rtlpriv->io.read32_sync = pci_read32_sync;
469 static bool _rtl_update_earlymode_info(struct ieee80211_hw *hw,
470 struct sk_buff *skb, struct rtl_tcb_desc *tcb_desc, u8 tid)
472 struct rtl_priv *rtlpriv = rtl_priv(hw);
473 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
474 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
475 struct sk_buff *next_skb;
476 u8 additionlen = FCS_LEN;
478 /* here open is 4, wep/tkip is 8, aes is 12*/
479 if (info->control.hw_key)
480 additionlen += info->control.hw_key->icv_len;
482 /* The most skb num is 6 */
483 tcb_desc->empkt_num = 0;
484 spin_lock_bh(&rtlpriv->locks.waitq_lock);
485 skb_queue_walk(&rtlpriv->mac80211.skb_waitq[tid], next_skb) {
486 struct ieee80211_tx_info *next_info;
488 next_info = IEEE80211_SKB_CB(next_skb);
489 if (next_info->flags & IEEE80211_TX_CTL_AMPDU) {
490 tcb_desc->empkt_len[tcb_desc->empkt_num] =
491 next_skb->len + additionlen;
492 tcb_desc->empkt_num++;
497 if (skb_queue_is_last(&rtlpriv->mac80211.skb_waitq[tid],
501 if (tcb_desc->empkt_num >= rtlhal->max_earlymode_num)
504 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
509 /* just for early mode now */
510 static void _rtl_pci_tx_chk_waitq(struct ieee80211_hw *hw)
512 struct rtl_priv *rtlpriv = rtl_priv(hw);
513 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
514 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
515 struct sk_buff *skb = NULL;
516 struct ieee80211_tx_info *info = NULL;
517 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
520 if (!rtlpriv->rtlhal.earlymode_enable)
523 if (rtlpriv->dm.supp_phymode_switch &&
524 (rtlpriv->easy_concurrent_ctl.switch_in_process ||
525 (rtlpriv->buddy_priv &&
526 rtlpriv->buddy_priv->easy_concurrent_ctl.switch_in_process)))
528 /* we juse use em for BE/BK/VI/VO */
529 for (tid = 7; tid >= 0; tid--) {
530 u8 hw_queue = ac_to_hwq[rtl_tid_to_ac(tid)];
531 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[hw_queue];
532 while (!mac->act_scanning &&
533 rtlpriv->psc.rfpwr_state == ERFON) {
534 struct rtl_tcb_desc tcb_desc;
535 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
537 spin_lock_bh(&rtlpriv->locks.waitq_lock);
538 if (!skb_queue_empty(&mac->skb_waitq[tid]) &&
539 (ring->entries - skb_queue_len(&ring->queue) >
540 rtlhal->max_earlymode_num)) {
541 skb = skb_dequeue(&mac->skb_waitq[tid]);
543 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
546 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
548 /* Some macaddr can't do early mode. like
549 * multicast/broadcast/no_qos data */
550 info = IEEE80211_SKB_CB(skb);
551 if (info->flags & IEEE80211_TX_CTL_AMPDU)
552 _rtl_update_earlymode_info(hw, skb,
555 rtlpriv->intf_ops->adapter_tx(hw, NULL, skb, &tcb_desc);
561 static void _rtl_pci_tx_isr(struct ieee80211_hw *hw, int prio)
563 struct rtl_priv *rtlpriv = rtl_priv(hw);
564 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
566 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
568 while (skb_queue_len(&ring->queue)) {
569 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
571 struct ieee80211_tx_info *info;
575 u8 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) entry, true,
578 /*beacon packet will only use the first
579 *descriptor by defaut, and the own may not
580 *be cleared by the hardware
584 ring->idx = (ring->idx + 1) % ring->entries;
586 skb = __skb_dequeue(&ring->queue);
587 pci_unmap_single(rtlpci->pdev,
589 get_desc((u8 *) entry, true,
590 HW_DESC_TXBUFF_ADDR),
591 skb->len, PCI_DMA_TODEVICE);
593 /* remove early mode header */
594 if (rtlpriv->rtlhal.earlymode_enable)
595 skb_pull(skb, EM_HDR_LEN);
597 RT_TRACE(rtlpriv, (COMP_INTR | COMP_SEND), DBG_TRACE,
598 "new ring->idx:%d, free: skb_queue_len:%d, free: seq:%x\n",
600 skb_queue_len(&ring->queue),
601 *(u16 *) (skb->data + 22));
603 if (prio == TXCMD_QUEUE) {
609 /* for sw LPS, just after NULL skb send out, we can
610 * sure AP knows we are sleeping, we should not let
613 fc = rtl_get_fc(skb);
614 if (ieee80211_is_nullfunc(fc)) {
615 if (ieee80211_has_pm(fc)) {
616 rtlpriv->mac80211.offchan_delay = true;
617 rtlpriv->psc.state_inap = true;
619 rtlpriv->psc.state_inap = false;
622 if (ieee80211_is_action(fc)) {
623 struct ieee80211_mgmt *action_frame =
624 (struct ieee80211_mgmt *)skb->data;
625 if (action_frame->u.action.u.ht_smps.action ==
626 WLAN_HT_ACTION_SMPS) {
632 /* update tid tx pkt num */
633 tid = rtl_get_tid(skb);
635 rtlpriv->link_info.tidtx_inperiod[tid]++;
637 info = IEEE80211_SKB_CB(skb);
638 ieee80211_tx_info_clear_status(info);
640 info->flags |= IEEE80211_TX_STAT_ACK;
641 /*info->status.rates[0].count = 1; */
643 ieee80211_tx_status_irqsafe(hw, skb);
645 if ((ring->entries - skb_queue_len(&ring->queue))
648 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
649 "more desc left, wake skb_queue@%d, ring->idx = %d, skb_queue_len = 0x%d\n",
651 skb_queue_len(&ring->queue));
653 ieee80211_wake_queue(hw,
654 skb_get_queue_mapping
661 if (((rtlpriv->link_info.num_rx_inperiod +
662 rtlpriv->link_info.num_tx_inperiod) > 8) ||
663 (rtlpriv->link_info.num_rx_inperiod > 2)) {
664 rtlpriv->enter_ps = false;
665 schedule_work(&rtlpriv->works.lps_change_work);
669 static void _rtl_receive_one(struct ieee80211_hw *hw, struct sk_buff *skb,
670 struct ieee80211_rx_status rx_status)
672 struct rtl_priv *rtlpriv = rtl_priv(hw);
673 struct ieee80211_hdr *hdr = rtl_get_hdr(skb);
674 __le16 fc = rtl_get_fc(skb);
675 bool unicast = false;
676 struct sk_buff *uskb = NULL;
680 memcpy(IEEE80211_SKB_RXCB(skb), &rx_status, sizeof(rx_status));
682 if (is_broadcast_ether_addr(hdr->addr1)) {
684 } else if (is_multicast_ether_addr(hdr->addr1)) {
688 rtlpriv->stats.rxbytesunicast += skb->len;
691 if (ieee80211_is_data(fc)) {
692 rtlpriv->cfg->ops->led_control(hw, LED_CTL_RX);
695 rtlpriv->link_info.num_rx_inperiod++;
698 /* static bcn for roaming */
699 rtl_beacon_statistic(hw, skb);
700 rtl_p2p_info(hw, (void *)skb->data, skb->len);
703 rtl_swlps_beacon(hw, (void *)skb->data, skb->len);
704 rtl_recognize_peer(hw, (void *)skb->data, skb->len);
705 if ((rtlpriv->mac80211.opmode == NL80211_IFTYPE_AP) &&
706 (rtlpriv->rtlhal.current_bandtype == BAND_ON_2_4G) &&
707 (ieee80211_is_beacon(fc) || ieee80211_is_probe_resp(fc)))
710 if (unlikely(!rtl_action_proc(hw, skb, false)))
713 uskb = dev_alloc_skb(skb->len + 128);
715 return; /* exit if allocation failed */
716 memcpy(IEEE80211_SKB_RXCB(uskb), &rx_status, sizeof(rx_status));
717 pdata = (u8 *)skb_put(uskb, skb->len);
718 memcpy(pdata, skb->data, skb->len);
720 ieee80211_rx_irqsafe(hw, uskb);
723 static void _rtl_pci_rx_interrupt(struct ieee80211_hw *hw)
725 struct rtl_priv *rtlpriv = rtl_priv(hw);
726 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
727 int rx_queue_idx = RTL_PCI_RX_MPDU_QUEUE;
729 struct ieee80211_rx_status rx_status = { 0 };
730 unsigned int count = rtlpci->rxringcount;
735 struct rtl_stats stats = {
739 int index = rtlpci->rx_ring[rx_queue_idx].idx;
744 struct rtl_rx_desc *pdesc = &rtlpci->rx_ring[rx_queue_idx].desc[
747 struct sk_buff *skb = rtlpci->rx_ring[rx_queue_idx].rx_buf[
749 struct sk_buff *new_skb = NULL;
751 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) pdesc,
754 /*wait data to be filled by hardware */
758 rtlpriv->cfg->ops->query_rx_desc(hw, &stats,
762 if (stats.crc || stats.hwerror)
765 new_skb = dev_alloc_skb(rtlpci->rxbuffersize);
766 if (unlikely(!new_skb)) {
767 RT_TRACE(rtlpriv, (COMP_INTR | COMP_RECV), DBG_DMESG,
768 "can't alloc skb for rx\n");
771 kmemleak_not_leak(new_skb);
773 pci_unmap_single(rtlpci->pdev,
774 *((dma_addr_t *) skb->cb),
775 rtlpci->rxbuffersize,
778 skb_put(skb, rtlpriv->cfg->ops->get_desc((u8 *) pdesc, false,
780 skb_reserve(skb, stats.rx_drvinfo_size + stats.rx_bufshift);
783 * NOTICE This can not be use for mac80211,
784 * this is done in mac80211 code,
785 * if you done here sec DHCP will fail
786 * skb_trim(skb, skb->len - 4);
789 _rtl_receive_one(hw, skb, rx_status);
791 if (((rtlpriv->link_info.num_rx_inperiod +
792 rtlpriv->link_info.num_tx_inperiod) > 8) ||
793 (rtlpriv->link_info.num_rx_inperiod > 2)) {
794 rtlpriv->enter_ps = false;
795 schedule_work(&rtlpriv->works.lps_change_work);
798 dev_kfree_skb_any(skb);
801 rtlpci->rx_ring[rx_queue_idx].rx_buf[index] = skb;
802 *((dma_addr_t *) skb->cb) =
803 pci_map_single(rtlpci->pdev, skb_tail_pointer(skb),
804 rtlpci->rxbuffersize,
808 bufferaddress = (*((dma_addr_t *)skb->cb));
809 if (pci_dma_mapping_error(rtlpci->pdev, bufferaddress))
812 rtlpriv->cfg->ops->set_desc((u8 *) pdesc, false,
814 (u8 *)&bufferaddress);
815 rtlpriv->cfg->ops->set_desc((u8 *)pdesc, false,
817 (u8 *)&rtlpci->rxbuffersize);
819 if (index == rtlpci->rxringcount - 1)
820 rtlpriv->cfg->ops->set_desc((u8 *)pdesc, false,
824 rtlpriv->cfg->ops->set_desc((u8 *)pdesc, false, HW_DESC_RXOWN,
827 index = (index + 1) % rtlpci->rxringcount;
830 rtlpci->rx_ring[rx_queue_idx].idx = index;
833 static irqreturn_t _rtl_pci_interrupt(int irq, void *dev_id)
835 struct ieee80211_hw *hw = dev_id;
836 struct rtl_priv *rtlpriv = rtl_priv(hw);
837 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
841 irqreturn_t ret = IRQ_HANDLED;
843 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
845 /*read ISR: 4/8bytes */
846 rtlpriv->cfg->ops->interrupt_recognized(hw, &inta, &intb);
848 /*Shared IRQ or HW disappared */
849 if (!inta || inta == 0xffff) {
854 /*<1> beacon related */
855 if (inta & rtlpriv->cfg->maps[RTL_IMR_TBDOK]) {
856 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
857 "beacon ok interrupt!\n");
860 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_TBDER])) {
861 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
862 "beacon err interrupt!\n");
865 if (inta & rtlpriv->cfg->maps[RTL_IMR_BDOK]) {
866 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, "beacon interrupt!\n");
869 if (inta & rtlpriv->cfg->maps[RTL_IMR_BCNINT]) {
870 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
871 "prepare beacon for interrupt!\n");
872 tasklet_schedule(&rtlpriv->works.irq_prepare_bcn_tasklet);
876 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_TXFOVW]))
877 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, "IMR_TXFOVW!\n");
879 if (inta & rtlpriv->cfg->maps[RTL_IMR_MGNTDOK]) {
880 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
881 "Manage ok interrupt!\n");
882 _rtl_pci_tx_isr(hw, MGNT_QUEUE);
885 if (inta & rtlpriv->cfg->maps[RTL_IMR_HIGHDOK]) {
886 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
887 "HIGH_QUEUE ok interrupt!\n");
888 _rtl_pci_tx_isr(hw, HIGH_QUEUE);
891 if (inta & rtlpriv->cfg->maps[RTL_IMR_BKDOK]) {
892 rtlpriv->link_info.num_tx_inperiod++;
894 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
895 "BK Tx OK interrupt!\n");
896 _rtl_pci_tx_isr(hw, BK_QUEUE);
899 if (inta & rtlpriv->cfg->maps[RTL_IMR_BEDOK]) {
900 rtlpriv->link_info.num_tx_inperiod++;
902 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
903 "BE TX OK interrupt!\n");
904 _rtl_pci_tx_isr(hw, BE_QUEUE);
907 if (inta & rtlpriv->cfg->maps[RTL_IMR_VIDOK]) {
908 rtlpriv->link_info.num_tx_inperiod++;
910 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
911 "VI TX OK interrupt!\n");
912 _rtl_pci_tx_isr(hw, VI_QUEUE);
915 if (inta & rtlpriv->cfg->maps[RTL_IMR_VODOK]) {
916 rtlpriv->link_info.num_tx_inperiod++;
918 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
919 "Vo TX OK interrupt!\n");
920 _rtl_pci_tx_isr(hw, VO_QUEUE);
923 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192SE) {
924 if (inta & rtlpriv->cfg->maps[RTL_IMR_COMDOK]) {
925 rtlpriv->link_info.num_tx_inperiod++;
927 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
928 "CMD TX OK interrupt!\n");
929 _rtl_pci_tx_isr(hw, TXCMD_QUEUE);
934 if (inta & rtlpriv->cfg->maps[RTL_IMR_ROK]) {
935 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE, "Rx ok interrupt!\n");
936 _rtl_pci_rx_interrupt(hw);
939 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_RDU])) {
940 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
941 "rx descriptor unavailable!\n");
942 _rtl_pci_rx_interrupt(hw);
945 if (unlikely(inta & rtlpriv->cfg->maps[RTL_IMR_RXFOVW])) {
946 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING, "rx overflow !\n");
947 _rtl_pci_rx_interrupt(hw);
951 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8723AE) {
952 if (inta & rtlpriv->cfg->maps[RTL_IMR_C2HCMD]) {
953 RT_TRACE(rtlpriv, COMP_INTR, DBG_TRACE,
954 "firmware interrupt!\n");
955 queue_delayed_work(rtlpriv->works.rtl_wq,
956 &rtlpriv->works.fwevt_wq, 0);
960 if (rtlpriv->rtlhal.earlymode_enable)
961 tasklet_schedule(&rtlpriv->works.irq_tasklet);
964 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
968 static void _rtl_pci_irq_tasklet(struct ieee80211_hw *hw)
970 _rtl_pci_tx_chk_waitq(hw);
973 static void _rtl_pci_prepare_bcn_tasklet(struct ieee80211_hw *hw)
975 struct rtl_priv *rtlpriv = rtl_priv(hw);
976 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
977 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
978 struct rtl8192_tx_ring *ring = NULL;
979 struct ieee80211_hdr *hdr = NULL;
980 struct ieee80211_tx_info *info = NULL;
981 struct sk_buff *pskb = NULL;
982 struct rtl_tx_desc *pdesc = NULL;
983 struct rtl_tcb_desc tcb_desc;
986 memset(&tcb_desc, 0, sizeof(struct rtl_tcb_desc));
987 ring = &rtlpci->tx_ring[BEACON_QUEUE];
988 pskb = __skb_dequeue(&ring->queue);
990 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
991 pci_unmap_single(rtlpci->pdev, rtlpriv->cfg->ops->get_desc(
992 (u8 *) entry, true, HW_DESC_TXBUFF_ADDR),
993 pskb->len, PCI_DMA_TODEVICE);
997 /*NB: the beacon data buffer must be 32-bit aligned. */
998 pskb = ieee80211_beacon_get(hw, mac->vif);
1001 hdr = rtl_get_hdr(pskb);
1002 info = IEEE80211_SKB_CB(pskb);
1003 pdesc = &ring->desc[0];
1004 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *) pdesc,
1005 info, NULL, pskb, BEACON_QUEUE, &tcb_desc);
1007 __skb_queue_tail(&ring->queue, pskb);
1009 rtlpriv->cfg->ops->set_desc((u8 *) pdesc, true, HW_DESC_OWN,
1015 static void _rtl_pci_init_trx_var(struct ieee80211_hw *hw)
1017 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1020 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1021 rtlpci->txringcount[i] = RT_TXDESC_NUM;
1024 *we just alloc 2 desc for beacon queue,
1025 *because we just need first desc in hw beacon.
1027 rtlpci->txringcount[BEACON_QUEUE] = 2;
1030 *BE queue need more descriptor for performance
1031 *consideration or, No more tx desc will happen,
1032 *and may cause mac80211 mem leakage.
1034 rtlpci->txringcount[BE_QUEUE] = RT_TXDESC_NUM_BE_QUEUE;
1036 rtlpci->rxbuffersize = 9100; /*2048/1024; */
1037 rtlpci->rxringcount = RTL_PCI_MAX_RX_COUNT; /*64; */
1040 static void _rtl_pci_init_struct(struct ieee80211_hw *hw,
1041 struct pci_dev *pdev)
1043 struct rtl_priv *rtlpriv = rtl_priv(hw);
1044 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1045 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1046 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1048 rtlpci->up_first_time = true;
1049 rtlpci->being_init_adapter = false;
1052 rtlpci->pdev = pdev;
1054 /*Tx/Rx related var */
1055 _rtl_pci_init_trx_var(hw);
1057 /*IBSS*/ mac->beacon_interval = 100;
1060 mac->min_space_cfg = 0;
1061 mac->max_mss_density = 0;
1062 /*set sane AMPDU defaults */
1063 mac->current_ampdu_density = 7;
1064 mac->current_ampdu_factor = 3;
1067 rtlpci->acm_method = eAcmWay2_SW;
1070 tasklet_init(&rtlpriv->works.irq_tasklet,
1071 (void (*)(unsigned long))_rtl_pci_irq_tasklet,
1073 tasklet_init(&rtlpriv->works.irq_prepare_bcn_tasklet,
1074 (void (*)(unsigned long))_rtl_pci_prepare_bcn_tasklet,
1076 INIT_WORK(&rtlpriv->works.lps_change_work,
1077 rtl_lps_change_work_callback);
1080 static int _rtl_pci_init_tx_ring(struct ieee80211_hw *hw,
1081 unsigned int prio, unsigned int entries)
1083 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1084 struct rtl_priv *rtlpriv = rtl_priv(hw);
1085 struct rtl_tx_desc *ring;
1087 u32 nextdescaddress;
1090 ring = pci_alloc_consistent(rtlpci->pdev,
1091 sizeof(*ring) * entries, &dma);
1093 if (!ring || (unsigned long)ring & 0xFF) {
1094 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1095 "Cannot allocate TX ring (prio = %d)\n", prio);
1099 memset(ring, 0, sizeof(*ring) * entries);
1100 rtlpci->tx_ring[prio].desc = ring;
1101 rtlpci->tx_ring[prio].dma = dma;
1102 rtlpci->tx_ring[prio].idx = 0;
1103 rtlpci->tx_ring[prio].entries = entries;
1104 skb_queue_head_init(&rtlpci->tx_ring[prio].queue);
1106 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "queue:%d, ring_addr:%p\n",
1109 for (i = 0; i < entries; i++) {
1110 nextdescaddress = (u32) dma +
1111 ((i + 1) % entries) *
1114 rtlpriv->cfg->ops->set_desc((u8 *)&(ring[i]),
1115 true, HW_DESC_TX_NEXTDESC_ADDR,
1116 (u8 *)&nextdescaddress);
1122 static int _rtl_pci_init_rx_ring(struct ieee80211_hw *hw)
1124 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1125 struct rtl_priv *rtlpriv = rtl_priv(hw);
1126 struct rtl_rx_desc *entry = NULL;
1127 int i, rx_queue_idx;
1131 *rx_queue_idx 0:RX_MPDU_QUEUE
1132 *rx_queue_idx 1:RX_CMD_QUEUE
1134 for (rx_queue_idx = 0; rx_queue_idx < RTL_PCI_MAX_RX_QUEUE;
1136 rtlpci->rx_ring[rx_queue_idx].desc =
1137 pci_alloc_consistent(rtlpci->pdev,
1138 sizeof(*rtlpci->rx_ring[rx_queue_idx].
1139 desc) * rtlpci->rxringcount,
1140 &rtlpci->rx_ring[rx_queue_idx].dma);
1142 if (!rtlpci->rx_ring[rx_queue_idx].desc ||
1143 (unsigned long)rtlpci->rx_ring[rx_queue_idx].desc & 0xFF) {
1144 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1145 "Cannot allocate RX ring\n");
1149 memset(rtlpci->rx_ring[rx_queue_idx].desc, 0,
1150 sizeof(*rtlpci->rx_ring[rx_queue_idx].desc) *
1151 rtlpci->rxringcount);
1153 rtlpci->rx_ring[rx_queue_idx].idx = 0;
1155 /* If amsdu_8k is disabled, set buffersize to 4096. This
1156 * change will reduce memory fragmentation.
1158 if (rtlpci->rxbuffersize > 4096 &&
1159 rtlpriv->rtlhal.disable_amsdu_8k)
1160 rtlpci->rxbuffersize = 4096;
1162 for (i = 0; i < rtlpci->rxringcount; i++) {
1163 struct sk_buff *skb =
1164 dev_alloc_skb(rtlpci->rxbuffersize);
1168 kmemleak_not_leak(skb);
1169 entry = &rtlpci->rx_ring[rx_queue_idx].desc[i];
1171 /*skb->dev = dev; */
1173 rtlpci->rx_ring[rx_queue_idx].rx_buf[i] = skb;
1176 *just set skb->cb to mapping addr
1177 *for pci_unmap_single use
1179 *((dma_addr_t *) skb->cb) =
1180 pci_map_single(rtlpci->pdev, skb_tail_pointer(skb),
1181 rtlpci->rxbuffersize,
1182 PCI_DMA_FROMDEVICE);
1184 bufferaddress = (*((dma_addr_t *)skb->cb));
1185 if (pci_dma_mapping_error(rtlpci->pdev, bufferaddress)) {
1186 dev_kfree_skb_any(skb);
1189 rtlpriv->cfg->ops->set_desc((u8 *)entry, false,
1190 HW_DESC_RXBUFF_ADDR,
1191 (u8 *)&bufferaddress);
1192 rtlpriv->cfg->ops->set_desc((u8 *)entry, false,
1196 rtlpriv->cfg->ops->set_desc((u8 *) entry, false,
1201 rtlpriv->cfg->ops->set_desc((u8 *) entry, false,
1202 HW_DESC_RXERO, &tmp_one);
1207 static void _rtl_pci_free_tx_ring(struct ieee80211_hw *hw,
1210 struct rtl_priv *rtlpriv = rtl_priv(hw);
1211 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1212 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[prio];
1214 while (skb_queue_len(&ring->queue)) {
1215 struct rtl_tx_desc *entry = &ring->desc[ring->idx];
1216 struct sk_buff *skb = __skb_dequeue(&ring->queue);
1218 pci_unmap_single(rtlpci->pdev,
1220 ops->get_desc((u8 *) entry, true,
1221 HW_DESC_TXBUFF_ADDR),
1222 skb->len, PCI_DMA_TODEVICE);
1224 ring->idx = (ring->idx + 1) % ring->entries;
1228 pci_free_consistent(rtlpci->pdev,
1229 sizeof(*ring->desc) * ring->entries,
1230 ring->desc, ring->dma);
1235 static void _rtl_pci_free_rx_ring(struct rtl_pci *rtlpci)
1237 int i, rx_queue_idx;
1239 /*rx_queue_idx 0:RX_MPDU_QUEUE */
1240 /*rx_queue_idx 1:RX_CMD_QUEUE */
1241 for (rx_queue_idx = 0; rx_queue_idx < RTL_PCI_MAX_RX_QUEUE;
1243 for (i = 0; i < rtlpci->rxringcount; i++) {
1244 struct sk_buff *skb =
1245 rtlpci->rx_ring[rx_queue_idx].rx_buf[i];
1249 pci_unmap_single(rtlpci->pdev,
1250 *((dma_addr_t *) skb->cb),
1251 rtlpci->rxbuffersize,
1252 PCI_DMA_FROMDEVICE);
1256 if (rtlpci->rx_ring[rx_queue_idx].desc) {
1257 pci_free_consistent(rtlpci->pdev,
1258 sizeof(*rtlpci->rx_ring[rx_queue_idx].
1259 desc) * rtlpci->rxringcount,
1260 rtlpci->rx_ring[rx_queue_idx].desc,
1261 rtlpci->rx_ring[rx_queue_idx].dma);
1262 rtlpci->rx_ring[rx_queue_idx].desc = NULL;
1267 static int _rtl_pci_init_trx_ring(struct ieee80211_hw *hw)
1269 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1273 ret = _rtl_pci_init_rx_ring(hw);
1277 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1278 ret = _rtl_pci_init_tx_ring(hw, i,
1279 rtlpci->txringcount[i]);
1281 goto err_free_rings;
1287 _rtl_pci_free_rx_ring(rtlpci);
1289 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1290 if (rtlpci->tx_ring[i].desc)
1291 _rtl_pci_free_tx_ring(hw, i);
1296 static int _rtl_pci_deinit_trx_ring(struct ieee80211_hw *hw)
1298 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1302 _rtl_pci_free_rx_ring(rtlpci);
1305 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++)
1306 _rtl_pci_free_tx_ring(hw, i);
1311 int rtl_pci_reset_trx_ring(struct ieee80211_hw *hw)
1313 struct rtl_priv *rtlpriv = rtl_priv(hw);
1314 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1315 int i, rx_queue_idx;
1316 unsigned long flags;
1319 /*rx_queue_idx 0:RX_MPDU_QUEUE */
1320 /*rx_queue_idx 1:RX_CMD_QUEUE */
1321 for (rx_queue_idx = 0; rx_queue_idx < RTL_PCI_MAX_RX_QUEUE;
1324 *force the rx_ring[RX_MPDU_QUEUE/
1325 *RX_CMD_QUEUE].idx to the first one
1327 if (rtlpci->rx_ring[rx_queue_idx].desc) {
1328 struct rtl_rx_desc *entry = NULL;
1330 for (i = 0; i < rtlpci->rxringcount; i++) {
1331 entry = &rtlpci->rx_ring[rx_queue_idx].desc[i];
1332 rtlpriv->cfg->ops->set_desc((u8 *) entry,
1337 rtlpci->rx_ring[rx_queue_idx].idx = 0;
1342 *after reset, release previous pending packet,
1343 *and force the tx idx to the first one
1345 for (i = 0; i < RTL_PCI_MAX_TX_QUEUE_COUNT; i++) {
1346 if (rtlpci->tx_ring[i].desc) {
1347 struct rtl8192_tx_ring *ring = &rtlpci->tx_ring[i];
1349 while (skb_queue_len(&ring->queue)) {
1350 struct rtl_tx_desc *entry;
1351 struct sk_buff *skb;
1353 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock,
1355 entry = &ring->desc[ring->idx];
1356 skb = __skb_dequeue(&ring->queue);
1357 pci_unmap_single(rtlpci->pdev,
1362 HW_DESC_TXBUFF_ADDR),
1363 skb->len, PCI_DMA_TODEVICE);
1364 ring->idx = (ring->idx + 1) % ring->entries;
1365 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock,
1376 static bool rtl_pci_tx_chk_waitq_insert(struct ieee80211_hw *hw,
1377 struct ieee80211_sta *sta,
1378 struct sk_buff *skb)
1380 struct rtl_priv *rtlpriv = rtl_priv(hw);
1381 struct rtl_sta_info *sta_entry = NULL;
1382 u8 tid = rtl_get_tid(skb);
1383 __le16 fc = rtl_get_fc(skb);
1387 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
1389 if (!rtlpriv->rtlhal.earlymode_enable)
1391 if (ieee80211_is_nullfunc(fc))
1393 if (ieee80211_is_qos_nullfunc(fc))
1395 if (ieee80211_is_pspoll(fc))
1397 if (sta_entry->tids[tid].agg.agg_state != RTL_AGG_OPERATIONAL)
1399 if (_rtl_mac_to_hwqueue(hw, skb) > VO_QUEUE)
1404 /* maybe every tid should be checked */
1405 if (!rtlpriv->link_info.higher_busytxtraffic[tid])
1408 spin_lock_bh(&rtlpriv->locks.waitq_lock);
1409 skb_queue_tail(&rtlpriv->mac80211.skb_waitq[tid], skb);
1410 spin_unlock_bh(&rtlpriv->locks.waitq_lock);
1415 static int rtl_pci_tx(struct ieee80211_hw *hw,
1416 struct ieee80211_sta *sta,
1417 struct sk_buff *skb,
1418 struct rtl_tcb_desc *ptcb_desc)
1420 struct rtl_priv *rtlpriv = rtl_priv(hw);
1421 struct rtl_sta_info *sta_entry = NULL;
1422 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
1423 struct rtl8192_tx_ring *ring;
1424 struct rtl_tx_desc *pdesc;
1426 u8 hw_queue = _rtl_mac_to_hwqueue(hw, skb);
1427 unsigned long flags;
1428 struct ieee80211_hdr *hdr = rtl_get_hdr(skb);
1429 __le16 fc = rtl_get_fc(skb);
1430 u8 *pda_addr = hdr->addr1;
1431 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1438 if (ieee80211_is_mgmt(fc))
1439 rtl_tx_mgmt_proc(hw, skb);
1441 if (rtlpriv->psc.sw_ps_enabled) {
1442 if (ieee80211_is_data(fc) && !ieee80211_is_nullfunc(fc) &&
1443 !ieee80211_has_pm(fc))
1444 hdr->frame_control |= cpu_to_le16(IEEE80211_FCTL_PM);
1447 rtl_action_proc(hw, skb, true);
1449 if (is_multicast_ether_addr(pda_addr))
1450 rtlpriv->stats.txbytesmulticast += skb->len;
1451 else if (is_broadcast_ether_addr(pda_addr))
1452 rtlpriv->stats.txbytesbroadcast += skb->len;
1454 rtlpriv->stats.txbytesunicast += skb->len;
1456 spin_lock_irqsave(&rtlpriv->locks.irq_th_lock, flags);
1457 ring = &rtlpci->tx_ring[hw_queue];
1458 if (hw_queue != BEACON_QUEUE)
1459 idx = (ring->idx + skb_queue_len(&ring->queue)) %
1464 pdesc = &ring->desc[idx];
1465 own = (u8) rtlpriv->cfg->ops->get_desc((u8 *) pdesc,
1468 if ((own == 1) && (hw_queue != BEACON_QUEUE)) {
1469 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1470 "No more TX desc@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%d\n",
1471 hw_queue, ring->idx, idx,
1472 skb_queue_len(&ring->queue));
1474 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1478 if (ieee80211_is_data_qos(fc)) {
1479 tid = rtl_get_tid(skb);
1481 sta_entry = (struct rtl_sta_info *)sta->drv_priv;
1482 seq_number = (le16_to_cpu(hdr->seq_ctrl) &
1483 IEEE80211_SCTL_SEQ) >> 4;
1486 if (!ieee80211_has_morefrags(hdr->frame_control))
1487 sta_entry->tids[tid].seq_number = seq_number;
1491 if (ieee80211_is_data(fc))
1492 rtlpriv->cfg->ops->led_control(hw, LED_CTL_TX);
1494 rtlpriv->cfg->ops->fill_tx_desc(hw, hdr, (u8 *)pdesc,
1495 info, sta, skb, hw_queue, ptcb_desc);
1497 __skb_queue_tail(&ring->queue, skb);
1499 rtlpriv->cfg->ops->set_desc((u8 *)pdesc, true,
1500 HW_DESC_OWN, &temp_one);
1503 if ((ring->entries - skb_queue_len(&ring->queue)) < 2 &&
1504 hw_queue != BEACON_QUEUE) {
1506 RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD,
1507 "less desc left, stop skb_queue@%d, ring->idx = %d, idx = %d, skb_queue_len = 0x%d\n",
1508 hw_queue, ring->idx, idx,
1509 skb_queue_len(&ring->queue));
1511 ieee80211_stop_queue(hw, skb_get_queue_mapping(skb));
1514 spin_unlock_irqrestore(&rtlpriv->locks.irq_th_lock, flags);
1516 rtlpriv->cfg->ops->tx_polling(hw, hw_queue);
1521 static void rtl_pci_flush(struct ieee80211_hw *hw, bool drop)
1523 struct rtl_priv *rtlpriv = rtl_priv(hw);
1524 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1525 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1526 struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
1529 struct rtl8192_tx_ring *ring;
1534 for (queue_id = RTL_PCI_MAX_TX_QUEUE_COUNT - 1; queue_id >= 0;) {
1536 ring = &pcipriv->dev.tx_ring[queue_id];
1537 queue_len = skb_queue_len(&ring->queue);
1538 if (queue_len == 0 || queue_id == BEACON_QUEUE ||
1539 queue_id == TXCMD_QUEUE) {
1547 /* we just wait 1s for all queues */
1548 if (rtlpriv->psc.rfpwr_state == ERFOFF ||
1549 is_hal_stop(rtlhal) || i >= 200)
1554 static void rtl_pci_deinit(struct ieee80211_hw *hw)
1556 struct rtl_priv *rtlpriv = rtl_priv(hw);
1557 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1559 _rtl_pci_deinit_trx_ring(hw);
1561 synchronize_irq(rtlpci->pdev->irq);
1562 tasklet_kill(&rtlpriv->works.irq_tasklet);
1563 cancel_work_sync(&rtlpriv->works.lps_change_work);
1565 flush_workqueue(rtlpriv->works.rtl_wq);
1566 destroy_workqueue(rtlpriv->works.rtl_wq);
1570 static int rtl_pci_init(struct ieee80211_hw *hw, struct pci_dev *pdev)
1572 struct rtl_priv *rtlpriv = rtl_priv(hw);
1575 _rtl_pci_init_struct(hw, pdev);
1577 err = _rtl_pci_init_trx_ring(hw);
1579 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1580 "tx ring initialization failed\n");
1587 static int rtl_pci_start(struct ieee80211_hw *hw)
1589 struct rtl_priv *rtlpriv = rtl_priv(hw);
1590 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1591 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1592 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1596 rtl_pci_reset_trx_ring(hw);
1598 rtlpci->driver_is_goingto_unload = false;
1599 err = rtlpriv->cfg->ops->hw_init(hw);
1601 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1602 "Failed to config hardware!\n");
1606 rtlpriv->cfg->ops->enable_interrupt(hw);
1607 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD, "enable_interrupt OK\n");
1609 rtl_init_rx_config(hw);
1611 /*should be after adapter start and interrupt enable. */
1612 set_hal_start(rtlhal);
1614 RT_CLEAR_PS_LEVEL(ppsc, RT_RF_OFF_LEVL_HALT_NIC);
1616 rtlpci->up_first_time = false;
1618 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG, "OK\n");
1622 static void rtl_pci_stop(struct ieee80211_hw *hw)
1624 struct rtl_priv *rtlpriv = rtl_priv(hw);
1625 struct rtl_pci *rtlpci = rtl_pcidev(rtl_pcipriv(hw));
1626 struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
1627 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1628 unsigned long flags;
1629 u8 RFInProgressTimeOut = 0;
1632 *should be before disable interrupt&adapter
1633 *and will do it immediately.
1635 set_hal_stop(rtlhal);
1637 rtlpriv->cfg->ops->disable_interrupt(hw);
1638 cancel_work_sync(&rtlpriv->works.lps_change_work);
1640 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1641 while (ppsc->rfchange_inprogress) {
1642 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1643 if (RFInProgressTimeOut > 100) {
1644 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1648 RFInProgressTimeOut++;
1649 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1651 ppsc->rfchange_inprogress = true;
1652 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1654 rtlpci->driver_is_goingto_unload = true;
1655 rtlpriv->cfg->ops->hw_disable(hw);
1656 /* some things are not needed if firmware not available */
1657 if (!rtlpriv->max_fw_size)
1659 rtlpriv->cfg->ops->led_control(hw, LED_CTL_POWER_OFF);
1661 spin_lock_irqsave(&rtlpriv->locks.rf_ps_lock, flags);
1662 ppsc->rfchange_inprogress = false;
1663 spin_unlock_irqrestore(&rtlpriv->locks.rf_ps_lock, flags);
1665 rtl_pci_enable_aspm(hw);
1668 static bool _rtl_pci_find_adapter(struct pci_dev *pdev,
1669 struct ieee80211_hw *hw)
1671 struct rtl_priv *rtlpriv = rtl_priv(hw);
1672 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
1673 struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
1674 struct pci_dev *bridge_pdev = pdev->bus->self;
1681 pcipriv->ndis_adapter.pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN;
1682 venderid = pdev->vendor;
1683 deviceid = pdev->device;
1684 pci_read_config_byte(pdev, 0x8, &revisionid);
1685 pci_read_config_word(pdev, 0x3C, &irqline);
1687 /* PCI ID 0x10ec:0x8192 occurs for both RTL8192E, which uses
1688 * r8192e_pci, and RTL8192SE, which uses this driver. If the
1689 * revision ID is RTL_PCI_REVISION_ID_8192PCIE (0x01), then
1690 * the correct driver is r8192e_pci, thus this routine should
1693 if (deviceid == RTL_PCI_8192SE_DID &&
1694 revisionid == RTL_PCI_REVISION_ID_8192PCIE)
1697 if (deviceid == RTL_PCI_8192_DID ||
1698 deviceid == RTL_PCI_0044_DID ||
1699 deviceid == RTL_PCI_0047_DID ||
1700 deviceid == RTL_PCI_8192SE_DID ||
1701 deviceid == RTL_PCI_8174_DID ||
1702 deviceid == RTL_PCI_8173_DID ||
1703 deviceid == RTL_PCI_8172_DID ||
1704 deviceid == RTL_PCI_8171_DID) {
1705 switch (revisionid) {
1706 case RTL_PCI_REVISION_ID_8192PCIE:
1707 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1708 "8192 PCI-E is found - vid/did=%x/%x\n",
1709 venderid, deviceid);
1710 rtlhal->hw_type = HARDWARE_TYPE_RTL8192E;
1712 case RTL_PCI_REVISION_ID_8192SE:
1713 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1714 "8192SE is found - vid/did=%x/%x\n",
1715 venderid, deviceid);
1716 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1719 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1720 "Err: Unknown device - vid/did=%x/%x\n",
1721 venderid, deviceid);
1722 rtlhal->hw_type = HARDWARE_TYPE_RTL8192SE;
1726 } else if (deviceid == RTL_PCI_8723AE_DID) {
1727 rtlhal->hw_type = HARDWARE_TYPE_RTL8723AE;
1728 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1729 "8723AE PCI-E is found - "
1730 "vid/did=%x/%x\n", venderid, deviceid);
1731 } else if (deviceid == RTL_PCI_8192CET_DID ||
1732 deviceid == RTL_PCI_8192CE_DID ||
1733 deviceid == RTL_PCI_8191CE_DID ||
1734 deviceid == RTL_PCI_8188CE_DID) {
1735 rtlhal->hw_type = HARDWARE_TYPE_RTL8192CE;
1736 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1737 "8192C PCI-E is found - vid/did=%x/%x\n",
1738 venderid, deviceid);
1739 } else if (deviceid == RTL_PCI_8192DE_DID ||
1740 deviceid == RTL_PCI_8192DE_DID2) {
1741 rtlhal->hw_type = HARDWARE_TYPE_RTL8192DE;
1742 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1743 "8192D PCI-E is found - vid/did=%x/%x\n",
1744 venderid, deviceid);
1745 } else if (deviceid == RTL_PCI_8188EE_DID) {
1746 rtlhal->hw_type = HARDWARE_TYPE_RTL8188EE;
1747 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1748 "Find adapter, Hardware type is 8188EE\n");
1750 RT_TRACE(rtlpriv, COMP_ERR, DBG_WARNING,
1751 "Err: Unknown device - vid/did=%x/%x\n",
1752 venderid, deviceid);
1754 rtlhal->hw_type = RTL_DEFAULT_HARDWARE_TYPE;
1757 if (rtlhal->hw_type == HARDWARE_TYPE_RTL8192DE) {
1758 if (revisionid == 0 || revisionid == 1) {
1759 if (revisionid == 0) {
1760 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1761 "Find 92DE MAC0\n");
1762 rtlhal->interfaceindex = 0;
1763 } else if (revisionid == 1) {
1764 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1765 "Find 92DE MAC1\n");
1766 rtlhal->interfaceindex = 1;
1769 RT_TRACE(rtlpriv, COMP_INIT, DBG_LOUD,
1770 "Unknown device - VendorID/DeviceID=%x/%x, Revision=%x\n",
1771 venderid, deviceid, revisionid);
1772 rtlhal->interfaceindex = 0;
1776 pcipriv->ndis_adapter.busnumber = pdev->bus->number;
1777 pcipriv->ndis_adapter.devnumber = PCI_SLOT(pdev->devfn);
1778 pcipriv->ndis_adapter.funcnumber = PCI_FUNC(pdev->devfn);
1780 /* some ARM have no bridge_pdev and will crash here
1781 * so we should check if bridge_pdev is NULL
1784 /*find bridge info if available */
1785 pcipriv->ndis_adapter.pcibridge_vendorid = bridge_pdev->vendor;
1786 for (tmp = 0; tmp < PCI_BRIDGE_VENDOR_MAX; tmp++) {
1787 if (bridge_pdev->vendor == pcibridge_vendors[tmp]) {
1788 pcipriv->ndis_adapter.pcibridge_vendor = tmp;
1789 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1790 "Pci Bridge Vendor is found index: %d\n",
1797 if (pcipriv->ndis_adapter.pcibridge_vendor !=
1798 PCI_BRIDGE_VENDOR_UNKNOWN) {
1799 pcipriv->ndis_adapter.pcibridge_busnum =
1800 bridge_pdev->bus->number;
1801 pcipriv->ndis_adapter.pcibridge_devnum =
1802 PCI_SLOT(bridge_pdev->devfn);
1803 pcipriv->ndis_adapter.pcibridge_funcnum =
1804 PCI_FUNC(bridge_pdev->devfn);
1805 pcipriv->ndis_adapter.pcibridge_pciehdr_offset =
1806 pci_pcie_cap(bridge_pdev);
1807 pcipriv->ndis_adapter.num4bytes =
1808 (pcipriv->ndis_adapter.pcibridge_pciehdr_offset + 0x10) / 4;
1810 rtl_pci_get_linkcontrol_field(hw);
1812 if (pcipriv->ndis_adapter.pcibridge_vendor ==
1813 PCI_BRIDGE_VENDOR_AMD) {
1814 pcipriv->ndis_adapter.amd_l1_patch =
1815 rtl_pci_get_amd_l1_patch(hw);
1819 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1820 "pcidev busnumber:devnumber:funcnumber:vendor:link_ctl %d:%d:%d:%x:%x\n",
1821 pcipriv->ndis_adapter.busnumber,
1822 pcipriv->ndis_adapter.devnumber,
1823 pcipriv->ndis_adapter.funcnumber,
1824 pdev->vendor, pcipriv->ndis_adapter.linkctrl_reg);
1826 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1827 "pci_bridge busnumber:devnumber:funcnumber:vendor:pcie_cap:link_ctl_reg:amd %d:%d:%d:%x:%x:%x:%x\n",
1828 pcipriv->ndis_adapter.pcibridge_busnum,
1829 pcipriv->ndis_adapter.pcibridge_devnum,
1830 pcipriv->ndis_adapter.pcibridge_funcnum,
1831 pcibridge_vendors[pcipriv->ndis_adapter.pcibridge_vendor],
1832 pcipriv->ndis_adapter.pcibridge_pciehdr_offset,
1833 pcipriv->ndis_adapter.pcibridge_linkctrlreg,
1834 pcipriv->ndis_adapter.amd_l1_patch);
1836 rtl_pci_parse_configuration(pdev, hw);
1837 list_add_tail(&rtlpriv->list, &rtlpriv->glb_var->glb_priv_list);
1842 int rtl_pci_probe(struct pci_dev *pdev,
1843 const struct pci_device_id *id)
1845 struct ieee80211_hw *hw = NULL;
1847 struct rtl_priv *rtlpriv = NULL;
1848 struct rtl_pci_priv *pcipriv = NULL;
1849 struct rtl_pci *rtlpci;
1850 unsigned long pmem_start, pmem_len, pmem_flags;
1853 err = pci_enable_device(pdev);
1855 RT_ASSERT(false, "%s : Cannot enable new PCI device\n",
1860 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
1861 if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) {
1863 "Unable to obtain 32bit DMA for consistent allocations\n");
1869 pci_set_master(pdev);
1871 hw = ieee80211_alloc_hw(sizeof(struct rtl_pci_priv) +
1872 sizeof(struct rtl_priv), &rtl_ops);
1875 "%s : ieee80211 alloc failed\n", pci_name(pdev));
1880 SET_IEEE80211_DEV(hw, &pdev->dev);
1881 pci_set_drvdata(pdev, hw);
1885 pcipriv = (void *)rtlpriv->priv;
1886 pcipriv->dev.pdev = pdev;
1887 init_completion(&rtlpriv->firmware_loading_complete);
1889 /* init cfg & intf_ops */
1890 rtlpriv->rtlhal.interface = INTF_PCI;
1891 rtlpriv->cfg = (struct rtl_hal_cfg *)(id->driver_data);
1892 rtlpriv->intf_ops = &rtl_pci_ops;
1893 rtlpriv->glb_var = &rtl_global_var;
1896 *init dbgp flags before all
1897 *other functions, because we will
1898 *use it in other funtions like
1899 *RT_TRACE/RT_PRINT/RTL_PRINT_DATA
1900 *you can not use these macro
1903 rtl_dbgp_flag_init(hw);
1906 err = pci_request_regions(pdev, KBUILD_MODNAME);
1908 RT_ASSERT(false, "Can't obtain PCI resources\n");
1912 pmem_start = pci_resource_start(pdev, rtlpriv->cfg->bar_id);
1913 pmem_len = pci_resource_len(pdev, rtlpriv->cfg->bar_id);
1914 pmem_flags = pci_resource_flags(pdev, rtlpriv->cfg->bar_id);
1916 /*shared mem start */
1917 rtlpriv->io.pci_mem_start =
1918 (unsigned long)pci_iomap(pdev,
1919 rtlpriv->cfg->bar_id, pmem_len);
1920 if (rtlpriv->io.pci_mem_start == 0) {
1921 RT_ASSERT(false, "Can't map PCI mem\n");
1926 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1927 "mem mapped space: start: 0x%08lx len:%08lx flags:%08lx, after map:0x%08lx\n",
1928 pmem_start, pmem_len, pmem_flags,
1929 rtlpriv->io.pci_mem_start);
1931 /* Disable Clk Request */
1932 pci_write_config_byte(pdev, 0x81, 0);
1934 pci_write_config_byte(pdev, 0x44, 0);
1935 pci_write_config_byte(pdev, 0x04, 0x06);
1936 pci_write_config_byte(pdev, 0x04, 0x07);
1939 if (!_rtl_pci_find_adapter(pdev, hw)) {
1944 /* Init IO handler */
1945 _rtl_pci_io_handler_init(&pdev->dev, hw);
1947 /*like read eeprom and so on */
1948 rtlpriv->cfg->ops->read_eeprom_info(hw);
1951 rtl_pci_init_aspm(hw);
1953 /* Init mac80211 sw */
1954 err = rtl_init_core(hw);
1956 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1957 "Can't allocate sw for mac80211\n");
1962 err = rtl_pci_init(hw, pdev);
1964 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Failed to init PCI\n");
1968 if (rtlpriv->cfg->ops->init_sw_vars(hw)) {
1969 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Can't init_sw_vars\n");
1974 rtlpriv->cfg->ops->init_sw_leds(hw);
1976 err = sysfs_create_group(&pdev->dev.kobj, &rtl_attribute_group);
1978 RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG,
1979 "failed to create sysfs device attributes\n");
1983 rtlpci = rtl_pcidev(pcipriv);
1984 err = request_irq(rtlpci->pdev->irq, &_rtl_pci_interrupt,
1985 IRQF_SHARED, KBUILD_MODNAME, hw);
1987 RT_TRACE(rtlpriv, COMP_INIT, DBG_DMESG,
1988 "%s: failed to register IRQ handler\n",
1989 wiphy_name(hw->wiphy));
1992 rtlpci->irq_alloc = 1;
1997 rtl_deinit_core(hw);
1999 if (rtlpriv->io.pci_mem_start != 0)
2000 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
2003 pci_release_regions(pdev);
2004 complete(&rtlpriv->firmware_loading_complete);
2008 ieee80211_free_hw(hw);
2009 pci_disable_device(pdev);
2014 EXPORT_SYMBOL(rtl_pci_probe);
2016 void rtl_pci_disconnect(struct pci_dev *pdev)
2018 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2019 struct rtl_pci_priv *pcipriv = rtl_pcipriv(hw);
2020 struct rtl_priv *rtlpriv = rtl_priv(hw);
2021 struct rtl_pci *rtlpci = rtl_pcidev(pcipriv);
2022 struct rtl_mac *rtlmac = rtl_mac(rtlpriv);
2024 /* just in case driver is removed before firmware callback */
2025 wait_for_completion(&rtlpriv->firmware_loading_complete);
2026 clear_bit(RTL_STATUS_INTERFACE_START, &rtlpriv->status);
2028 sysfs_remove_group(&pdev->dev.kobj, &rtl_attribute_group);
2030 /*ieee80211_unregister_hw will call ops_stop */
2031 if (rtlmac->mac80211_registered == 1) {
2032 ieee80211_unregister_hw(hw);
2033 rtlmac->mac80211_registered = 0;
2035 rtl_deinit_deferred_work(hw);
2036 rtlpriv->intf_ops->adapter_stop(hw);
2038 rtlpriv->cfg->ops->disable_interrupt(hw);
2041 rtl_deinit_rfkill(hw);
2044 rtl_deinit_core(hw);
2045 rtlpriv->cfg->ops->deinit_sw_vars(hw);
2047 if (rtlpci->irq_alloc) {
2048 synchronize_irq(rtlpci->pdev->irq);
2049 free_irq(rtlpci->pdev->irq, hw);
2050 rtlpci->irq_alloc = 0;
2053 list_del(&rtlpriv->list);
2054 if (rtlpriv->io.pci_mem_start != 0) {
2055 pci_iounmap(pdev, (void __iomem *)rtlpriv->io.pci_mem_start);
2056 pci_release_regions(pdev);
2059 pci_disable_device(pdev);
2061 rtl_pci_disable_aspm(hw);
2063 ieee80211_free_hw(hw);
2065 EXPORT_SYMBOL(rtl_pci_disconnect);
2067 #ifdef CONFIG_PM_SLEEP
2068 /***************************************
2069 kernel pci power state define:
2070 PCI_D0 ((pci_power_t __force) 0)
2071 PCI_D1 ((pci_power_t __force) 1)
2072 PCI_D2 ((pci_power_t __force) 2)
2073 PCI_D3hot ((pci_power_t __force) 3)
2074 PCI_D3cold ((pci_power_t __force) 4)
2075 PCI_UNKNOWN ((pci_power_t __force) 5)
2077 This function is called when system
2078 goes into suspend state mac80211 will
2079 call rtl_mac_stop() from the mac80211
2080 suspend function first, So there is
2081 no need to call hw_disable here.
2082 ****************************************/
2083 int rtl_pci_suspend(struct device *dev)
2085 struct pci_dev *pdev = to_pci_dev(dev);
2086 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2087 struct rtl_priv *rtlpriv = rtl_priv(hw);
2089 rtlpriv->cfg->ops->hw_suspend(hw);
2090 rtl_deinit_rfkill(hw);
2094 EXPORT_SYMBOL(rtl_pci_suspend);
2096 int rtl_pci_resume(struct device *dev)
2098 struct pci_dev *pdev = to_pci_dev(dev);
2099 struct ieee80211_hw *hw = pci_get_drvdata(pdev);
2100 struct rtl_priv *rtlpriv = rtl_priv(hw);
2102 rtlpriv->cfg->ops->hw_resume(hw);
2103 rtl_init_rfkill(hw);
2106 EXPORT_SYMBOL(rtl_pci_resume);
2107 #endif /* CONFIG_PM_SLEEP */
2109 struct rtl_intf_ops rtl_pci_ops = {
2110 .read_efuse_byte = read_efuse_byte,
2111 .adapter_start = rtl_pci_start,
2112 .adapter_stop = rtl_pci_stop,
2113 .check_buddy_priv = rtl_pci_check_buddy_priv,
2114 .adapter_tx = rtl_pci_tx,
2115 .flush = rtl_pci_flush,
2116 .reset_trx_ring = rtl_pci_reset_trx_ring,
2117 .waitq_insert = rtl_pci_tx_chk_waitq_insert,
2119 .disable_aspm = rtl_pci_disable_aspm,
2120 .enable_aspm = rtl_pci_enable_aspm,