drivers/net/wireless/rtl8723bs/hal/OUTSRC/odm.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  *
  19  ******************************************************************************/
  20
  21 //============================================================
  22 // include files
  23 //============================================================
  24
  25 #include "odm_precomp.h"
  26
  27
  28 const u2Byte dB_Invert_Table[8][12] = {
  29         {       1,              1,              1,              2,              2,              2,              2,              3,              3,              3,              4,              4},
  30         {       4,              5,              6,              6,              7,              8,              9,              10,             11,             13,             14,             16},
  31         {       18,             20,             22,             25,             28,             32,             35,             40,             45,             50,             56,             63},
  32         {       71,             79,             89,             100,    112,    126,    141,    158,    178,    200,    224,    251},
  33         {       282,    316,    355,    398,    447,    501,    562,    631,    708,    794,    891,    1000},
  34         {       1122,   1259,   1413,   1585,   1778,   1995,   2239,   2512,   2818,   3162,   3548,   3981},
  35         {       4467,   5012,   5623,   6310,   7079,   7943,   8913,   10000,  11220,  12589,  14125,  15849},
  36         {       17783,  19953,  22387,  25119,  28184,  31623,  35481,  39811,  44668,  50119,  56234,  65535}};
  37
  38
  39 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
  40 static u4Byte edca_setting_UL[HT_IOT_PEER_MAX] =
  41 // UNKNOWN              REALTEK_90      REALTEK_92SE    BROADCOM                RALINK          ATHEROS         CISCO           MERU        MARVELL     92U_AP          SELF_AP(DownLink/Tx)
  42 { 0x5e4322,             0xa44f,                 0x5e4322,               0x5ea32b,               0x5ea422,       0x5ea322,       0x3ea430,       0x5ea42b, 0x5ea44f,     0x5e4322,       0x5e4322};
  43
  44
  45 static u4Byte edca_setting_DL[HT_IOT_PEER_MAX] =
  46 // UNKNOWN              REALTEK_90      REALTEK_92SE    BROADCOM                RALINK          ATHEROS         CISCO           MERU,       MARVELL     92U_AP          SELF_AP(UpLink/Rx)
  47 { 0xa44f,               0x5ea44f,       0x5e4322,               0x5ea42b,               0xa44f,                 0xa630,                 0x5ea630,       0x5ea42b, 0xa44f,               0xa42b,         0xa42b};
  48
  49 static u4Byte edca_setting_DL_GMode[HT_IOT_PEER_MAX] =
  50 // UNKNOWN              REALTEK_90      REALTEK_92SE    BROADCOM                RALINK          ATHEROS         CISCO           MERU,       MARVELL     92U_AP          SELF_AP
  51 { 0x4322,               0xa44f,                 0x5e4322,               0xa42b,                         0x5e4322,       0x4322,                 0xa42b,         0x5ea42b, 0xa44f,               0x5e4322,       0x5ea42b};
  52
  53
  54 //============================================================
  55 // EDCA Paramter for AP/ADSL   by Mingzhi 2011-11-22
  56 //============================================================
  57 #elif (DM_ODM_SUPPORT_TYPE &ODM_ADSL)
  58 enum qos_prio { BK, BE, VI, VO, VI_AG, VO_AG };
  59
  60 static const struct ParaRecord rtl_ap_EDCA[] =
  61 {
  62 //ACM,AIFSN, ECWmin, ECWmax, TXOplimit
  63      {0,     7,      4,      10,     0},            //BK
  64      {0,     3,      4,      6,      0},             //BE
  65      {0,     1,      3,      4,      188},         //VI
  66      {0,     1,      2,      3,      102},         //VO
  67      {0,     1,      3,      4,      94},          //VI_AG
  68      {0,     1,      2,      3,      47},          //VO_AG
  69 };
  70
  71 static const struct ParaRecord rtl_sta_EDCA[] =
  72 {
  73 //ACM,AIFSN, ECWmin, ECWmax, TXOplimit
  74      {0,     7,      4,      10,     0},
  75      {0,     3,      4,      10,     0},
  76      {0,     2,      3,      4,      188},
  77      {0,     2,      2,      3,      102},
  78      {0,     2,      3,      4,      94},
  79      {0,     2,      2,      3,      47},
  80 };
  81 #endif
  82
  83 //============================================================
  84 // Global var
  85 //============================================================
  86
  87 u4Byte  OFDMSwingTable[OFDM_TABLE_SIZE] = {
  88         0x7f8001fe,     // 0, +6.0dB
  89         0x788001e2,     // 1, +5.5dB
  90         0x71c001c7,     // 2, +5.0dB
  91         0x6b8001ae,     // 3, +4.5dB
  92         0x65400195,     // 4, +4.0dB
  93         0x5fc0017f,     // 5, +3.5dB
  94         0x5a400169,     // 6, +3.0dB
  95         0x55400155,     // 7, +2.5dB
  96         0x50800142,     // 8, +2.0dB
  97         0x4c000130,     // 9, +1.5dB
  98         0x47c0011f,     // 10, +1.0dB
  99         0x43c0010f,     // 11, +0.5dB
 100         0x40000100,     // 12, +0dB
 101         0x3c8000f2,     // 13, -0.5dB
 102         0x390000e4,     // 14, -1.0dB
 103         0x35c000d7,     // 15, -1.5dB
 104         0x32c000cb,     // 16, -2.0dB
 105         0x300000c0,     // 17, -2.5dB
 106         0x2d4000b5,     // 18, -3.0dB
 107         0x2ac000ab,     // 19, -3.5dB
 108         0x288000a2,     // 20, -4.0dB
 109         0x26000098,     // 21, -4.5dB
 110         0x24000090,     // 22, -5.0dB
 111         0x22000088,     // 23, -5.5dB
 112         0x20000080,     // 24, -6.0dB
 113         0x1e400079,     // 25, -6.5dB
 114         0x1c800072,     // 26, -7.0dB
 115         0x1b00006c,     // 27. -7.5dB
 116         0x19800066,     // 28, -8.0dB
 117         0x18000060,     // 29, -8.5dB
 118         0x16c0005b,     // 30, -9.0dB
 119         0x15800056,     // 31, -9.5dB
 120         0x14400051,     // 32, -10.0dB
 121         0x1300004c,     // 33, -10.5dB
 122         0x12000048,     // 34, -11.0dB
 123         0x11000044,     // 35, -11.5dB
 124         0x10000040,     // 36, -12.0dB
 125 };
 126
 127 u1Byte  CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8] = {
 128         {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04},       // 0, +0dB
 129         {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04},       // 1, -0.5dB
 130         {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03},       // 2, -1.0dB
 131         {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03},       // 3, -1.5dB
 132         {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03},       // 4, -2.0dB
 133         {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03},       // 5, -2.5dB
 134         {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03},       // 6, -3.0dB
 135         {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03},       // 7, -3.5dB
 136         {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02},       // 8, -4.0dB
 137         {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02},       // 9, -4.5dB
 138         {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02},       // 10, -5.0dB
 139         {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02},       // 11, -5.5dB
 140         {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02},       // 12, -6.0dB <== default
 141         {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02},       // 13, -6.5dB
 142         {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02},       // 14, -7.0dB
 143         {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02},       // 15, -7.5dB
 144         {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01},       // 16, -8.0dB
 145         {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02},       // 17, -8.5dB
 146         {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01},       // 18, -9.0dB
 147         {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},       // 19, -9.5dB
 148         {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},       // 20, -10.0dB
 149         {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01},       // 21, -10.5dB
 150         {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01},       // 22, -11.0dB
 151         {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01},       // 23, -11.5dB
 152         {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01},       // 24, -12.0dB
 153         {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01},       // 25, -12.5dB
 154         {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01},       // 26, -13.0dB
 155         {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01},       // 27, -13.5dB
 156         {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01},       // 28, -14.0dB
 157         {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01},       // 29, -14.5dB
 158         {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01},       // 30, -15.0dB
 159         {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01},       // 31, -15.5dB
 160         {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}        // 32, -16.0dB
 161 };
 162
 163
 164 u1Byte  CCKSwingTable_Ch14[CCK_TABLE_SIZE][8] = {
 165         {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00},       // 0, +0dB
 166         {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00},       // 1, -0.5dB
 167         {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00},       // 2, -1.0dB
 168         {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00},       // 3, -1.5dB
 169         {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00},       // 4, -2.0dB
 170         {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00},       // 5, -2.5dB
 171         {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00},       // 6, -3.0dB
 172         {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00},       // 7, -3.5dB
 173         {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00},       // 8, -4.0dB
 174         {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00},       // 9, -4.5dB
 175         {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00},       // 10, -5.0dB
 176         {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00},       // 11, -5.5dB
 177         {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00},       // 12, -6.0dB  <== default
 178         {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00},       // 13, -6.5dB
 179         {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00},       // 14, -7.0dB
 180         {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00},       // 15, -7.5dB
 181         {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00},       // 16, -8.0dB
 182         {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00},       // 17, -8.5dB
 183         {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00},       // 18, -9.0dB
 184         {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},       // 19, -9.5dB
 185         {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},       // 20, -10.0dB
 186         {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00},       // 21, -10.5dB
 187         {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00},       // 22, -11.0dB
 188         {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},       // 23, -11.5dB
 189         {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},       // 24, -12.0dB
 190         {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00},       // 25, -12.5dB
 191         {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},       // 26, -13.0dB
 192         {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},       // 27, -13.5dB
 193         {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},       // 28, -14.0dB
 194         {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},       // 29, -14.5dB
 195         {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},       // 30, -15.0dB
 196         {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},       // 31, -15.5dB
 197         {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}        // 32, -16.0dB
 198 };
 199
 200
 201 u4Byte OFDMSwingTable_New[OFDM_TABLE_SIZE] = {
 202         0x0b40002d, // 0,  -15.0dB
 203         0x0c000030, // 1,  -14.5dB
 204         0x0cc00033, // 2,  -14.0dB
 205         0x0d800036, // 3,  -13.5dB
 206         0x0e400039, // 4,  -13.0dB
 207         0x0f00003c, // 5,  -12.5dB
 208         0x10000040, // 6,  -12.0dB
 209         0x11000044, // 7,  -11.5dB
 210         0x12000048, // 8,  -11.0dB
 211         0x1300004c, // 9,  -10.5dB
 212         0x14400051, // 10, -10.0dB
 213         0x15800056, // 11, -9.5dB
 214         0x16c0005b, // 12, -9.0dB
 215         0x18000060, // 13, -8.5dB
 216         0x19800066, // 14, -8.0dB
 217         0x1b00006c, // 15, -7.5dB
 218         0x1c800072, // 16, -7.0dB
 219         0x1e400079, // 17, -6.5dB
 220         0x20000080, // 18, -6.0dB
 221         0x22000088, // 19, -5.5dB
 222         0x24000090, // 20, -5.0dB
 223         0x26000098, // 21, -4.5dB
 224         0x288000a2, // 22, -4.0dB
 225         0x2ac000ab, // 23, -3.5dB
 226         0x2d4000b5, // 24, -3.0dB
 227         0x300000c0, // 25, -2.5dB
 228         0x32c000cb, // 26, -2.0dB
 229         0x35c000d7, // 27, -1.5dB
 230         0x390000e4, // 28, -1.0dB
 231         0x3c8000f2, // 29, -0.5dB
 232         0x40000100, // 30, +0dB
 233         0x43c0010f, // 31, +0.5dB
 234         0x47c0011f, // 32, +1.0dB
 235         0x4c000130, // 33, +1.5dB
 236         0x50800142, // 34, +2.0dB
 237         0x55400155, // 35, +2.5dB
 238         0x5a400169, // 36, +3.0dB
 239         0x5fc0017f, // 37, +3.5dB
 240         0x65400195, // 38, +4.0dB
 241         0x6b8001ae, // 39, +4.5dB
 242         0x71c001c7, // 40, +5.0dB
 243         0x788001e2, // 41, +5.5dB
 244         0x7f8001fe  // 42, +6.0dB
 245 };
 246
 247
 248 u1Byte CCKSwingTable_Ch1_Ch13_New[CCK_TABLE_SIZE][8] = {
 249         {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01},       //  0, -16.0dB
 250         {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01},       //  1, -15.5dB
 251         {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01},       //  2, -15.0dB
 252         {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01},       //  3, -14.5dB
 253         {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01},       //  4, -14.0dB
 254         {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01},       //  5, -13.5dB
 255         {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01},       //  6, -13.0dB
 256         {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01},       //  7, -12.5dB
 257         {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01},       //  8, -12.0dB
 258         {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01},       //  9, -11.5dB
 259         {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01},       // 10, -11.0dB
 260         {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01},       // 11, -10.5dB
 261         {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},       // 12, -10.0dB
 262         {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},       // 13, -9.5dB
 263         {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01},       // 14, -9.0dB
 264         {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02},       // 15, -8.5dB
 265         {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01},       // 16, -8.0dB
 266         {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02},       // 17, -7.5dB
 267         {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02},       // 18, -7.0dB
 268         {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02},       // 19, -6.5dB
 269     {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02},   // 20, -6.0dB
 270         {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02},       // 21, -5.5dB
 271         {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02},       // 22, -5.0dB
 272         {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02},       // 23, -4.5dB
 273         {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02},       // 24, -4.0dB
 274         {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03},       // 25, -3.5dB
 275         {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03},       // 26, -3.0dB
 276         {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03},       // 27, -2.5dB
 277         {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03},       // 28, -2.0dB
 278         {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03},       // 29, -1.5dB
 279         {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03},       // 30, -1.0dB
 280         {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04},       // 31, -0.5dB
 281         {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04}        // 32, +0dB
 282 };
 283
 284
 285 u1Byte CCKSwingTable_Ch14_New[CCK_TABLE_SIZE][8]= {
 286         {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00},       //  0, -16.0dB
 287         {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},       //  1, -15.5dB
 288         {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},       //  2, -15.0dB
 289         {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},       //  3, -14.5dB
 290         {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},       //  4, -14.0dB
 291         {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},       //  5, -13.5dB
 292         {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},       //  6, -13.0dB
 293         {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00},       //  7, -12.5dB
 294         {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},       //  8, -12.0dB
 295         {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},       //  9, -11.5dB
 296         {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00},       // 10, -11.0dB
 297         {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00},       // 11, -10.5dB
 298         {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},       // 12, -10.0dB
 299         {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},       // 13, -9.5dB
 300         {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00},       // 14, -9.0dB
 301         {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00},       // 15, -8.5dB
 302         {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00},       // 16, -8.0dB
 303         {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00},       // 17, -7.5dB
 304         {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00},       // 18, -7.0dB
 305         {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00},       // 19, -6.5dB
 306         {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00},       // 20, -6.0dB
 307         {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00},       // 21, -5.5dB
 308         {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00},       // 22, -5.0dB
 309         {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00},       // 23, -4.5dB
 310         {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00},       // 24, -4.0dB
 311         {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00},       // 25, -3.5dB
 312         {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00},       // 26, -3.0dB
 313         {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00},       // 27, -2.5dB
 314         {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00},       // 28, -2.0dB
 315         {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00},       // 29, -1.5dB
 316         {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00},       // 30, -1.0dB
 317         {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00},       // 31, -0.5dB
 318         {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00}        // 32, +0dB
 319 };
 320
 321 u4Byte TxScalingTable_Jaguar[TXSCALE_TABLE_SIZE] =
 322 {
 323         0x081, // 0,  -12.0dB
 324         0x088, // 1,  -11.5dB
 325         0x090, // 2,  -11.0dB
 326         0x099, // 3,  -10.5dB
 327         0x0A2, // 4,  -10.0dB
 328         0x0AC, // 5,  -9.5dB
 329         0x0B6, // 6,  -9.0dB
 330         0x0C0, // 7,  -8.5dB
 331         0x0CC, // 8,  -8.0dB
 332         0x0D8, // 9,  -7.5dB
 333         0x0E5, // 10, -7.0dB
 334         0x0F2, // 11, -6.5dB
 335         0x101, // 12, -6.0dB
 336         0x110, // 13, -5.5dB
 337         0x120, // 14, -5.0dB
 338         0x131, // 15, -4.5dB
 339         0x143, // 16, -4.0dB
 340         0x156, // 17, -3.5dB
 341         0x16A, // 18, -3.0dB
 342         0x180, // 19, -2.5dB
 343         0x197, // 20, -2.0dB
 344         0x1AF, // 21, -1.5dB
 345         0x1C8, // 22, -1.0dB
 346         0x1E3, // 23, -0.5dB
 347         0x200, // 24, +0  dB
 348         0x21E, // 25, +0.5dB
 349         0x23E, // 26, +1.0dB
 350         0x261, // 27, +1.5dB
 351         0x285, // 28, +2.0dB
 352         0x2AB, // 29, +2.5dB
 353         0x2D3, // 30, +3.0dB
 354         0x2FE, // 31, +3.5dB
 355         0x32B, // 32, +4.0dB
 356         0x35C, // 33, +4.5dB
 357         0x38E, // 34, +5.0dB
 358         0x3C4, // 35, +5.5dB
 359         0x3FE  // 36, +6.0dB
 360 };
 361
 362 #ifdef AP_BUILD_WORKAROUND
 363
 364 unsigned int TxPwrTrk_OFDM_SwingTbl[TxPwrTrk_OFDM_SwingTbl_Len] = {
 365         /*  +6.0dB */ 0x7f8001fe,
 366         /*  +5.5dB */ 0x788001e2,
 367         /*  +5.0dB */ 0x71c001c7,
 368         /*  +4.5dB */ 0x6b8001ae,
 369         /*  +4.0dB */ 0x65400195,
 370         /*  +3.5dB */ 0x5fc0017f,
 371         /*  +3.0dB */ 0x5a400169,
 372         /*  +2.5dB */ 0x55400155,
 373         /*  +2.0dB */ 0x50800142,
 374         /*  +1.5dB */ 0x4c000130,
 375         /*  +1.0dB */ 0x47c0011f,
 376         /*  +0.5dB */ 0x43c0010f,
 377         /*   0.0dB */ 0x40000100,
 378         /*  -0.5dB */ 0x3c8000f2,
 379         /*  -1.0dB */ 0x390000e4,
 380         /*  -1.5dB */ 0x35c000d7,
 381         /*  -2.0dB */ 0x32c000cb,
 382         /*  -2.5dB */ 0x300000c0,
 383         /*  -3.0dB */ 0x2d4000b5,
 384         /*  -3.5dB */ 0x2ac000ab,
 385         /*  -4.0dB */ 0x288000a2,
 386         /*  -4.5dB */ 0x26000098,
 387         /*  -5.0dB */ 0x24000090,
 388         /*  -5.5dB */ 0x22000088,
 389         /*  -6.0dB */ 0x20000080,
 390         /*  -6.5dB */ 0x1a00006c,
 391         /*  -7.0dB */ 0x1c800072,
 392         /*  -7.5dB */ 0x18000060,
 393         /*  -8.0dB */ 0x19800066,
 394         /*  -8.5dB */ 0x15800056,
 395         /*  -9.0dB */ 0x26c0005b,
 396         /*  -9.5dB */ 0x14400051,
 397         /* -10.0dB */ 0x24400051,
 398         /* -10.5dB */ 0x1300004c,
 399         /* -11.0dB */ 0x12000048,
 400         /* -11.5dB */ 0x11000044,
 401         /* -12.0dB */ 0x10000040
 402 };
 403 #endif
 404
 405 //============================================================
 406 // Local Function predefine.
 407 //============================================================
 408
 409 //START------------COMMON INFO RELATED---------------//
 410 VOID
 411 odm_CommonInfoSelfInit(
 412         IN              PDM_ODM_T               pDM_Odm
 413         );
 414
 415 VOID
 416 odm_CommonInfoSelfUpdate(
 417         IN              PDM_ODM_T               pDM_Odm
 418         );
 419
 420 VOID
 421 odm_CmnInfoInit_Debug(
 422         IN              PDM_ODM_T               pDM_Odm
 423         );
 424
 425 VOID
 426 odm_CmnInfoHook_Debug(
 427         IN              PDM_ODM_T               pDM_Odm
 428         );
 429
 430 VOID
 431 odm_CmnInfoUpdate_Debug(
 432         IN              PDM_ODM_T               pDM_Odm
 433         );
 434 VOID
 435 odm_BasicDbgMessage
 436 (
 437         IN              PDM_ODM_T               pDM_Odm
 438         );
 439
 440 //END------------COMMON INFO RELATED---------------//
 441
 442 //START---------------DIG---------------------------//
 443 VOID
 444 odm_FalseAlarmCounterStatistics(
 445         IN              PDM_ODM_T               pDM_Odm
 446         );
 447
 448 VOID
 449 odm_DIGInit(
 450         IN              PDM_ODM_T               pDM_Odm
 451         );
 452
 453 VOID
 454 odm_DIG(
 455         IN              PDM_ODM_T               pDM_Odm
 456         );
 457
 458 BOOLEAN
 459 odm_DigAbort(
 460         IN              PDM_ODM_T               pDM_Odm
 461         );
 462
 463 VOID
 464 odm_CCKPacketDetectionThresh(
 465         IN              PDM_ODM_T               pDM_Odm
 466         );
 467
 468 VOID
 469 odm_AdaptivityInit(
 470         IN              PDM_ODM_T               pDM_Odm
 471 );
 472
 473 VOID
 474 odm_Adaptivity(
 475         IN              PDM_ODM_T               pDM_Odm,
 476         IN              u1Byte                  IGI
 477 );
 478 //END---------------DIG---------------------------//
 479
 480 //START-------BB POWER SAVE-----------------------//
 481 VOID
 482 odm_DynamicBBPowerSavingInit(
 483         IN              PDM_ODM_T               pDM_Odm
 484         );
 485
 486 VOID
 487 odm_DynamicBBPowerSaving(
 488         IN              PDM_ODM_T               pDM_Odm
 489         );
 490
 491 VOID
 492 odm_1R_CCA(
 493         IN              PDM_ODM_T               pDM_Odm
 494         );
 495 //END---------BB POWER SAVE-----------------------//
 496
 497 //START-----------------PSD-----------------------//
 498 #if(DM_ODM_SUPPORT_TYPE & (ODM_WIN))
 499 //============================================================
 500 // Function predefine.
 501 //============================================================
 502 VOID    odm_PathDiversityInit_92C(      IN      PADAPTER        Adapter);
 503 VOID    odm_2TPathDiversityInit_92C(    IN      PADAPTER        Adapter);
 504 VOID    odm_1TPathDiversityInit_92C(    IN      PADAPTER        Adapter);
 505 BOOLEAN odm_IsConnected_92C(IN  PADAPTER        Adapter);
 506 VOID    odm_PathDiversityAfterLink_92C( IN      PADAPTER        Adapter);
 507
 508 VOID
 509 odm_CCKTXPathDiversityCallback(
 510         PRT_TIMER               pTimer
 511         );
 512
 513 VOID
 514 odm_CCKTXPathDiversityWorkItemCallback(
 515     IN PVOID            pContext
 516     );
 517
 518 VOID
 519 odm_PathDivChkAntSwitchCallback(
 520         PRT_TIMER               pTimer
 521         );
 522
 523 VOID
 524 odm_PathDivChkAntSwitchWorkitemCallback(
 525     IN PVOID            pContext
 526     );
 527
 528 VOID    odm_SetRespPath_92C(            IN      PADAPTER        Adapter,        IN      u1Byte  DefaultRespPath);
 529 VOID    odm_OFDMTXPathDiversity_92C(    IN      PADAPTER        Adapter);
 530 VOID    odm_CCKTXPathDiversity_92C(     IN      PADAPTER        Adapter);
 531 VOID    odm_ResetPathDiversity_92C(             IN      PADAPTER        Adapter);
 532
 533 //Start-------------------- RX High Power------------------------//
 534 VOID    odm_RXHPInit(   IN              PDM_ODM_T               pDM_Odm);
 535 VOID    odm_RXHP(       IN              PDM_ODM_T               pDM_Odm);
 536 VOID    odm_Write_RXHP( IN      PDM_ODM_T       pDM_Odm);
 537
 538 VOID    odm_PSD_RXHP(           IN      PDM_ODM_T       pDM_Odm);
 539 VOID    odm_PSD_RXHPCallback(   PRT_TIMER               pTimer);
 540 VOID    odm_PSD_RXHPWorkitemCallback(   IN PVOID            pContext);
 541 //End--------------------- RX High Power -----------------------//
 542
 543 VOID    odm_PathDivInit_92D(    IN      PDM_ODM_T       pDM_Odm);
 544
 545 VOID
 546 odm_SetRespPath_92C(
 547         IN      PADAPTER        Adapter,
 548         IN      u1Byte  DefaultRespPath
 549         );
 550
 551 #endif
 552 //END-------------------PSD-----------------------//
 553
 554 VOID
 555 odm_RefreshRateAdaptiveMaskMP(
 556         IN              PDM_ODM_T               pDM_Odm
 557         );
 558
 559 VOID
 560 odm_RefreshRateAdaptiveMaskCE(
 561         IN              PDM_ODM_T               pDM_Odm
 562         );
 563
 564 VOID
 565 odm_RefreshRateAdaptiveMaskAPADSL(
 566         IN              PDM_ODM_T               pDM_Odm
 567         );
 568
 569 VOID
 570 ODM_DynamicATCSwitch_init(
 571         IN              PDM_ODM_T               pDM_Odm
 572         );
 573
 574 VOID
 575 ODM_DynamicATCSwitch(
 576         IN              PDM_ODM_T               pDM_Odm
 577         );
 578
 579 VOID
 580 odm_Write_CrystalCap(
 581         IN              PDM_ODM_T               pDM_Odm,
 582         IN              u1Byte                  CrystalCap
 583 );
 584
 585 VOID
 586 odm_DynamicTxPowerInit(
 587         IN              PDM_ODM_T               pDM_Odm
 588         );
 589
 590 VOID
 591 odm_DynamicTxPowerRestorePowerIndex(
 592         IN      PDM_ODM_T       pDM_Odm
 593         );
 594
 595 VOID
 596 odm_DynamicTxPowerNIC(
 597         IN      PDM_ODM_T       pDM_Odm
 598         );
 599
 600 #if(DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
 601 VOID
 602 odm_DynamicTxPowerSavePowerIndex(
 603         IN              PDM_ODM_T               pDM_Odm
 604         );
 605
 606 VOID
 607 odm_DynamicTxPowerWritePowerIndex(
 608         IN      PDM_ODM_T       pDM_Odm,
 609         IN      u1Byte          Value);
 610
 611 VOID
 612 odm_DynamicTxPower_92C(
 613         IN      PDM_ODM_T       pDM_Odm
 614         );
 615
 616 VOID
 617 odm_DynamicTxPower_92D(
 618         IN      PDM_ODM_T       pDM_Odm
 619         );
 620
 621 VOID
 622 odm_MPT_DIGCallback(
 623         PRT_TIMER               pTimer
 624 );
 625
 626 VOID
 627 odm_MPT_DIGWorkItemCallback(
 628     IN PVOID            pContext
 629     );
 630 #endif
 631
 632
 633 VOID
 634 odm_RSSIMonitorInit(
 635         IN      PDM_ODM_T       pDM_Odm
 636         );
 637
 638 VOID
 639 odm_RSSIMonitorCheckMP(
 640         IN      PDM_ODM_T       pDM_Odm
 641         );
 642
 643 VOID
 644 odm_RSSIMonitorCheckCE(
 645         IN              PDM_ODM_T               pDM_Odm
 646         );
 647 VOID
 648 odm_RSSIMonitorCheckAP(
 649         IN              PDM_ODM_T               pDM_Odm
 650         );
 651
 652
 653
 654 VOID
 655 odm_RSSIMonitorCheck(
 656         IN              PDM_ODM_T               pDM_Odm
 657         );
 658 VOID
 659 odm_DynamicTxPower(
 660         IN              PDM_ODM_T               pDM_Odm
 661         );
 662
 663 VOID
 664 odm_DynamicTxPowerAP(
 665         IN              PDM_ODM_T               pDM_Odm
 666         );
 667
 668
 669 VOID
 670 odm_SwAntDivInit(
 671         IN              PDM_ODM_T               pDM_Odm
 672         );
 673
 674 VOID
 675 odm_SwAntDivInit_NIC(
 676         IN              PDM_ODM_T               pDM_Odm
 677         );
 678
 679 VOID
 680 odm_SwAntDetectInit(
 681         IN              PDM_ODM_T               pDM_Odm
 682         );
 683
 684 VOID
 685 odm_SwAntDivChkAntSwitch(
 686         IN              PDM_ODM_T               pDM_Odm,
 687         IN              u1Byte                  Step
 688         );
 689
 690 VOID
 691 odm_SwAntDivChkAntSwitchNIC(
 692         IN              PDM_ODM_T               pDM_Odm,
 693         IN              u1Byte          Step
 694         );
 695
 696
 697 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
 698 VOID
 699 odm_SwAntDivChkAntSwitchCallback(
 700         PRT_TIMER               pTimer
 701 );
 702 VOID
 703 odm_SwAntDivChkAntSwitchWorkitemCallback(
 704     IN PVOID            pContext
 705     );
 706 VOID
 707 ODM_UpdateInitRateWorkItemCallback(
 708     IN PVOID            pContext
 709     );
 710 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
 711 VOID odm_SwAntDivChkAntSwitchCallback(void *FunctionContext);
 712 #elif (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
 713 VOID odm_SwAntDivChkAntSwitchCallback(void *FunctionContext);
 714 #endif
 715
 716
 717
 718 VOID
 719 odm_GlobalAdapterCheck(
 720         IN              VOID
 721         );
 722
 723 VOID
 724 odm_RefreshBasicRateMask(
 725         IN              PDM_ODM_T               pDM_Odm
 726         );
 727
 728 VOID
 729 odm_RefreshRateAdaptiveMask(
 730         IN              PDM_ODM_T               pDM_Odm
 731         );
 732
 733 VOID
 734 ODM_TXPowerTrackingCheck(
 735         IN              PDM_ODM_T               pDM_Odm
 736         );
 737
 738 VOID
 739 odm_TXPowerTrackingCheckAP(
 740         IN              PDM_ODM_T               pDM_Odm
 741         );
 742
 743
 744
 745
 746
 747
 748
 749 VOID
 750 odm_RateAdaptiveMaskInit(
 751         IN      PDM_ODM_T       pDM_Odm
 752         );
 753
 754 VOID
 755 odm_TXPowerTrackingThermalMeterInit(
 756         IN      PDM_ODM_T       pDM_Odm
 757         );
 758
 759
 760 VOID
 761 odm_IQCalibrate(
 762                 IN      PDM_ODM_T       pDM_Odm
 763                 );
 764
 765 VOID
 766 odm_TXPowerTrackingInit(
 767         IN      PDM_ODM_T       pDM_Odm
 768         );
 769
 770 VOID
 771 odm_TXPowerTrackingCheckMP(
 772         IN      PDM_ODM_T       pDM_Odm
 773         );
 774
 775
 776 VOID
 777 odm_TXPowerTrackingCheckCE(
 778         IN      PDM_ODM_T       pDM_Odm
 779         );
 780
 781 #if(DM_ODM_SUPPORT_TYPE & (ODM_WIN))
 782
 783 VOID
 784 ODM_RateAdaptiveStateApInit(
 785         IN      PADAPTER        Adapter ,
 786         IN      PRT_WLAN_STA  pEntry
 787         );
 788
 789 VOID
 790 odm_TXPowerTrackingCallbackThermalMeter92C(
 791             IN PADAPTER Adapter
 792             );
 793
 794 VOID
 795 odm_TXPowerTrackingCallbackRXGainThermalMeter92D(
 796         IN PADAPTER     Adapter
 797         );
 798
 799 VOID
 800 odm_TXPowerTrackingCallbackThermalMeter92D(
 801             IN PADAPTER Adapter
 802             );
 803
 804 VOID
 805 odm_TXPowerTrackingDirectCall92C(
 806             IN  PADAPTER                Adapter
 807             );
 808
 809 VOID
 810 odm_TXPowerTrackingThermalMeterCheck(
 811         IN      PADAPTER                Adapter
 812         );
 813
 814 #endif
 815
 816 VOID
 817 odm_EdcaTurboCheck(
 818         IN              PDM_ODM_T               pDM_Odm
 819         );
 820 VOID
 821 ODM_EdcaTurboInit(
 822         IN      PDM_ODM_T               pDM_Odm
 823 );
 824
 825 #if(DM_ODM_SUPPORT_TYPE==ODM_WIN)
 826 VOID
 827 odm_EdcaTurboCheckMP(
 828         IN              PDM_ODM_T               pDM_Odm
 829         );
 830
 831 //check if edca turbo is disabled
 832 BOOLEAN
 833 odm_IsEdcaTurboDisable(
 834         IN      PDM_ODM_T       pDM_Odm
 835 );
 836 //choose edca paramter for special IOT case
 837 VOID
 838 ODM_EdcaParaSelByIot(
 839         IN      PDM_ODM_T       pDM_Odm,
 840         OUT     u4Byte          *EDCA_BE_UL,
 841         OUT u4Byte              *EDCA_BE_DL
 842         );
 843 //check if it is UL or DL
 844 VOID
 845 odm_EdcaChooseTrafficIdx(
 846         IN      PDM_ODM_T               pDM_Odm,
 847         IN      u8Byte                          cur_tx_bytes,
 848         IN      u8Byte                          cur_rx_bytes,
 849         IN      BOOLEAN                 bBiasOnRx,
 850         OUT BOOLEAN             *pbIsCurRDLState
 851         );
 852
 853 #elif (DM_ODM_SUPPORT_TYPE==ODM_CE)
 854 VOID
 855 odm_EdcaTurboCheckCE(
 856         IN              PDM_ODM_T               pDM_Odm
 857         );
 858 #else
 859 VOID
 860 odm_IotEngine(
 861         IN      PDM_ODM_T       pDM_Odm
 862         );
 863
 864 VOID
 865 odm_EdcaParaInit(
 866         IN      PDM_ODM_T       pDM_Odm
 867         );
 868 #endif
 869
 870
 871
 872 #define         RxDefaultAnt1           0x65a9
 873 #define RxDefaultAnt2           0x569a
 874
 875 VOID
 876 odm_InitHybridAntDiv(
 877         IN PDM_ODM_T    pDM_Odm
 878         );
 879
 880 BOOLEAN
 881 odm_StaDefAntSel(
 882         IN PDM_ODM_T    pDM_Odm,
 883         IN u4Byte               OFDM_Ant1_Cnt,
 884         IN u4Byte               OFDM_Ant2_Cnt,
 885         IN u4Byte               CCK_Ant1_Cnt,
 886         IN u4Byte               CCK_Ant2_Cnt,
 887         OUT u1Byte              *pDefAnt
 888         );
 889
 890 VOID
 891 odm_SetRxIdleAnt(
 892         IN      PDM_ODM_T       pDM_Odm,
 893         IN      u1Byte  Ant,
 894         IN   BOOLEAN   bDualPath
 895 );
 896
 897
 898
 899 VOID
 900 odm_HwAntDiv(
 901         IN      PDM_ODM_T       pDM_Odm
 902 );
 903
 904 VOID    odm_PathDiversityInit(IN        PDM_ODM_T       pDM_Odm);
 905 VOID    odm_PathDiversity(      IN      PDM_ODM_T       pDM_Odm);
 906
 907
 908
 909 //============================================================
 910 //3 Export Interface
 911 //============================================================
 912
 913 //
 914 // 2011/09/21 MH Add to describe different team necessary resource allocate??
 915 //
 916 VOID
 917 ODM_DMInit(
 918         IN              PDM_ODM_T               pDM_Odm
 919         )
 920 {
 921
 922         //2012.05.03 Luke: For all IC series
 923         odm_CommonInfoSelfInit(pDM_Odm);
 924         odm_CmnInfoInit_Debug(pDM_Odm);
 925         odm_DIGInit(pDM_Odm);
 926         odm_AdaptivityInit(pDM_Odm);
 927         odm_RateAdaptiveMaskInit(pDM_Odm);
 928         odm_RSSIMonitorInit(pDM_Odm);
 929
 930 #if (RTL8192E_SUPPORT == 1)
 931         if(pDM_Odm->SupportICType==ODM_RTL8192E)
 932         {
 933                 odm_PrimaryCCA_Check_Init(pDM_Odm);
 934         }
 935 #endif
 936
 937 //#if (MP_DRIVER != 1)
 938         if ( *(pDM_Odm->mp_mode) != 1)
 939             odm_PathDiversityInit(pDM_Odm);
 940 //#endif
 941         ODM_EdcaTurboInit(pDM_Odm);
 942
 943         if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
 944         {
 945                 odm_TXPowerTrackingInit(pDM_Odm);
 946 //#if (MP_DRIVER != 1)
 947                 if ( *(pDM_Odm->mp_mode) != 1)
 948                         ODM_AntDivInit(pDM_Odm);
 949 //#endif
 950         }
 951         else if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
 952         {
 953                 odm_DynamicBBPowerSavingInit(pDM_Odm);
 954                 odm_DynamicTxPowerInit(pDM_Odm);
 955                 odm_TXPowerTrackingInit(pDM_Odm);
 956                 //ODM_EdcaTurboInit(pDM_Odm);
 957 //#if (MP_DRIVER != 1)
 958                 if ( *(pDM_Odm->mp_mode) != 1) {
 959                 if(pDM_Odm->SupportICType==ODM_RTL8723A)
 960                         odm_SwAntDivInit(pDM_Odm);
 961                 else if(pDM_Odm->SupportICType & (ODM_RTL8192C|ODM_RTL8192D))
 962                 {
 963                         if(pDM_Odm->AntDivType == HW_ANTDIV)
 964                         odm_InitHybridAntDiv(pDM_Odm);
 965                         else
 966                         odm_SwAntDivInit(pDM_Odm);
 967                 }
 968                 else
 969                         ODM_AntDivInit(pDM_Odm);
 970
 971                 if(pDM_Odm->SupportICType == ODM_RTL8723B)
 972                         odm_SwAntDetectInit(pDM_Odm);
 973                 }
 974 //#endif
 975
 976 //2010.05.30 LukeLee: For CE platform, files in IC subfolders may not be included to be compiled,
 977 // so compile flags must be left here to prevent from compile errors
 978 #if (RTL8188E_SUPPORT == 1)
 979                 if(pDM_Odm->SupportICType==ODM_RTL8188E)
 980                 {
 981                         odm_PrimaryCCA_Init(pDM_Odm);    // Gary
 982                         ODM_RAInfo_Init_all(pDM_Odm);
 983                 }
 984 #endif
 985
 986 //2010.05.30 LukeLee: Following are not incorporated into ODM structure yet.
 987 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
 988                 if(pDM_Odm->SupportICType&ODM_RTL8723A)
 989                         odm_PSDMonitorInit(pDM_Odm);
 990
 991                 if(!(pDM_Odm->SupportICType & (ODM_RTL8723A|ODM_RTL8188E)))
 992                 {
 993                         odm_RXHPInit(pDM_Odm);
 994                 }
 995                 if(pDM_Odm->SupportICType==ODM_RTL8192D)
 996                 {
 997                         odm_PathDivInit_92D(pDM_Odm); //92D Path Div Init   //Neil Chen
 998                 }
 999 #endif
1000         }
1001
1002         ODM_DynamicATCSwitch_init(pDM_Odm);
1003         ODM_ClearTxPowerTrackingState(pDM_Odm);
1004
1005 }
1006
1007 //
1008 // 2011/09/20 MH This is the entry pointer for all team to execute HW out source DM.
1009 // You can not add any dummy function here, be care, you can only use DM structure
1010 // to perform any new ODM_DM.
1011 //
1012 VOID
1013 ODM_DMWatchdog(
1014         IN              PDM_ODM_T               pDM_Odm
1015         )
1016 {
1017         if((pDM_Odm->SupportICType == ODM_RTL8821) && (pDM_Odm->SupportInterface == ODM_ITRF_USB))
1018         {
1019                 if(pDM_Odm->RSSI_Min > 25)
1020                         ODM_Write1Byte(pDM_Odm, 0x4CF, 0x02);
1021                 else if(pDM_Odm->RSSI_Min < 20)
1022                         ODM_Write1Byte(pDM_Odm, 0x4CF, 0x00);
1023         }
1024
1025
1026         odm_CommonInfoSelfUpdate(pDM_Odm);
1027         odm_BasicDbgMessage(pDM_Odm);
1028         odm_FalseAlarmCounterStatistics(pDM_Odm);
1029         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): RSSI=0x%x\n",pDM_Odm->RSSI_Min));
1030
1031         odm_RSSIMonitorCheck(pDM_Odm);
1032
1033 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
1034 //#ifdef CONFIG_PLATFORM_SPRD
1035         //For CE Platform(SPRD or Tablet)
1036         //8723A or 8189ES platform
1037         //NeilChen--2012--08--24--
1038         //Fix Leave LPS issue
1039         if(     (adapter_to_pwrctl(pDM_Odm->Adapter)->pwr_mode != PS_MODE_ACTIVE) // in LPS mode
1040                 //&&(
1041                 //      (pDM_Odm->SupportICType & (ODM_RTL8723A ) )||
1042                 //      (pDM_Odm->SupportICType & (ODM_RTL8188E) &&((pDM_Odm->SupportInterface  == ODM_ITRF_SDIO)) )
1043                 //)
1044         )
1045         {
1046                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("----Step1: odm_DIG is in LPS mode\n"));
1047                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("---Step2: 8723AS is in LPS mode\n"));
1048                         odm_DIGbyRSSI_LPS(pDM_Odm);
1049         }
1050         else
1051 //#endif
1052 #endif
1053         {
1054                 odm_DIG(pDM_Odm);
1055         }
1056
1057         {
1058                 pDIG_T  pDM_DigTable = &pDM_Odm->DM_DigTable;
1059                 odm_Adaptivity(pDM_Odm, pDM_DigTable->CurIGValue);
1060         }
1061         odm_CCKPacketDetectionThresh(pDM_Odm);
1062
1063         if(*(pDM_Odm->pbPowerSaving)==TRUE)
1064                 return;
1065
1066
1067         odm_RefreshRateAdaptiveMask(pDM_Odm);
1068         odm_RefreshBasicRateMask(pDM_Odm);
1069         odm_DynamicBBPowerSaving(pDM_Odm);
1070         odm_EdcaTurboCheck(pDM_Odm);
1071         odm_PathDiversity(pDM_Odm);
1072         ODM_DynamicATCSwitch(pDM_Odm);
1073         odm_DynamicTxPower(pDM_Odm);
1074
1075 #if (RTL8192E_SUPPORT == 1)
1076         if(pDM_Odm->SupportICType==ODM_RTL8192E)
1077                 odm_DynamicPrimaryCCA_Check(pDM_Odm);
1078 #endif
1079          //if(pDM_Odm->SupportICType == ODM_RTL8192E)
1080          //        return;
1081
1082
1083 //#if (MP_DRIVER != 1)
1084 if ( *(pDM_Odm->mp_mode) != 1) {
1085         if(pDM_Odm->SupportICType==ODM_RTL8723A)
1086         {
1087                 odm_SwAntDivChkAntSwitch(pDM_Odm, SWAW_STEP_PEAK);
1088         }
1089         else if(pDM_Odm->SupportICType & (ODM_RTL8192C|ODM_RTL8192D))
1090         {
1091                 if(pDM_Odm->AntDivType == HW_ANTDIV)
1092                         odm_HwAntDiv(pDM_Odm);
1093                 else
1094                         odm_SwAntDivChkAntSwitch(pDM_Odm, SWAW_STEP_PEAK);
1095         }
1096         else
1097                 ODM_AntDiv(pDM_Odm);
1098 }
1099 //#endif
1100
1101         if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
1102         {
1103                 ODM_TXPowerTrackingCheck(pDM_Odm);
1104
1105                 odm_IQCalibrate(pDM_Odm);
1106         }
1107         else if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
1108         {
1109                 ODM_TXPowerTrackingCheck(pDM_Odm);
1110
1111                 //odm_EdcaTurboCheck(pDM_Odm);
1112
1113                 #if( DM_ODM_SUPPORT_TYPE & (ODM_WIN))
1114                 if(!(pDM_Odm->SupportICType & (ODM_RTL8723A|ODM_RTL8188E)))
1115                         odm_RXHP(pDM_Odm);
1116                 #endif
1117
1118         //2010.05.30 LukeLee: For CE platform, files in IC subfolders may not be included to be compiled,
1119         // so compile flags must be left here to prevent from compile errors
1120 #if (RTL8192D_SUPPORT == 1)
1121                 if(pDM_Odm->SupportICType==ODM_RTL8192D)
1122                         ODM_DynamicEarlyMode(pDM_Odm);
1123 #endif
1124                 odm_DynamicBBPowerSaving(pDM_Odm);
1125 #if (RTL8188E_SUPPORT == 1)
1126                 if(pDM_Odm->SupportICType==ODM_RTL8188E)
1127                         odm_DynamicPrimaryCCA(pDM_Odm);
1128 #endif
1129
1130         }
1131         pDM_Odm->PhyDbgInfo.NumQryBeaconPkt = 0;
1132
1133 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
1134         odm_dtc(pDM_Odm);
1135 #endif
1136 }
1137
1138
1139 //
1140 // Init /.. Fixed HW value. Only init time.
1141 //
1142 VOID
1143 ODM_CmnInfoInit(
1144         IN              PDM_ODM_T               pDM_Odm,
1145         IN              ODM_CMNINFO_E   CmnInfo,
1146         IN              u4Byte                  Value
1147         )
1148 {
1149         //
1150         // This section is used for init value
1151         //
1152         switch  (CmnInfo)
1153         {
1154                 //
1155                 // Fixed ODM value.
1156                 //
1157                 case    ODM_CMNINFO_ABILITY:
1158                         pDM_Odm->SupportAbility = (u4Byte)Value;
1159                         break;
1160
1161                 case    ODM_CMNINFO_RF_TYPE:
1162                         pDM_Odm->RFType = (u1Byte)Value;
1163                         break;
1164
1165                 case    ODM_CMNINFO_PLATFORM:
1166                         pDM_Odm->SupportPlatform = (u1Byte)Value;
1167                         break;
1168
1169                 case    ODM_CMNINFO_INTERFACE:
1170                         pDM_Odm->SupportInterface = (u1Byte)Value;
1171                         break;
1172
1173                 case    ODM_CMNINFO_MP_TEST_CHIP:
1174                         pDM_Odm->bIsMPChip= (u1Byte)Value;
1175                         break;
1176
1177                 case    ODM_CMNINFO_IC_TYPE:
1178                         pDM_Odm->SupportICType = Value;
1179                         break;
1180
1181                 case    ODM_CMNINFO_CUT_VER:
1182                         pDM_Odm->CutVersion = (u1Byte)Value;
1183                         break;
1184
1185                 case    ODM_CMNINFO_FAB_VER:
1186                         pDM_Odm->FabVersion = (u1Byte)Value;
1187                         break;
1188
1189                 case    ODM_CMNINFO_RFE_TYPE:
1190                         pDM_Odm->RFEType = (u1Byte)Value;
1191                         break;
1192
1193                 case    ODM_CMNINFO_RF_ANTENNA_TYPE:
1194                         pDM_Odm->AntDivType= (u1Byte)Value;
1195                         break;
1196
1197                 case    ODM_CMNINFO_BOARD_TYPE:
1198                         pDM_Odm->BoardType = (u1Byte)Value;
1199                         break;
1200
1201                 case    ODM_CMNINFO_PACKAGE_TYPE:
1202                         pDM_Odm->PackageType = (u1Byte)Value;
1203                         break;
1204
1205                 case    ODM_CMNINFO_EXT_LNA:
1206                         pDM_Odm->ExtLNA = (u1Byte)Value;
1207                         break;
1208
1209                 case    ODM_CMNINFO_5G_EXT_LNA:
1210                         pDM_Odm->ExtLNA5G = (u1Byte)Value;
1211                         break;
1212
1213                 case    ODM_CMNINFO_EXT_PA:
1214                         pDM_Odm->ExtPA = (u1Byte)Value;
1215                         break;
1216
1217                 case    ODM_CMNINFO_5G_EXT_PA:
1218                         pDM_Odm->ExtPA5G = (u1Byte)Value;
1219                         break;
1220
1221                 case    ODM_CMNINFO_GPA:
1222                         pDM_Odm->TypeGPA= (ODM_TYPE_GPA_E)Value;
1223                         break;
1224                 case    ODM_CMNINFO_APA:
1225                         pDM_Odm->TypeAPA= (ODM_TYPE_APA_E)Value;
1226                         break;
1227                 case    ODM_CMNINFO_GLNA:
1228                         pDM_Odm->TypeGLNA= (ODM_TYPE_GLNA_E)Value;
1229                         break;
1230                 case    ODM_CMNINFO_ALNA:
1231                         pDM_Odm->TypeALNA= (ODM_TYPE_ALNA_E)Value;
1232                         break;
1233
1234                 case    ODM_CMNINFO_EXT_TRSW:
1235                         pDM_Odm->ExtTRSW = (u1Byte)Value;
1236                         break;
1237                 case    ODM_CMNINFO_PATCH_ID:
1238                         pDM_Odm->PatchID = (u1Byte)Value;
1239                         break;
1240                 case    ODM_CMNINFO_BINHCT_TEST:
1241                         pDM_Odm->bInHctTest = (BOOLEAN)Value;
1242                         break;
1243                 case    ODM_CMNINFO_BWIFI_TEST:
1244                         pDM_Odm->bWIFITest = (BOOLEAN)Value;
1245                         break;
1246
1247                 case    ODM_CMNINFO_SMART_CONCURRENT:
1248                         pDM_Odm->bDualMacSmartConcurrent = (BOOLEAN )Value;
1249                         break;
1250
1251                 //To remove the compiler warning, must add an empty default statement to handle the other values.
1252                 default:
1253                         //do nothing
1254                         break;
1255
1256         }
1257
1258 }
1259
1260
1261 VOID
1262 ODM_CmnInfoHook(
1263         IN              PDM_ODM_T               pDM_Odm,
1264         IN              ODM_CMNINFO_E   CmnInfo,
1265         IN              PVOID                   pValue
1266         )
1267 {
1268         //
1269         // Hook call by reference pointer.
1270         //
1271         switch  (CmnInfo)
1272         {
1273                 //
1274                 // Dynamic call by reference pointer.
1275                 //
1276                 case    ODM_CMNINFO_MAC_PHY_MODE:
1277                         pDM_Odm->pMacPhyMode = (u1Byte *)pValue;
1278                         break;
1279
1280                 case    ODM_CMNINFO_TX_UNI:
1281                         pDM_Odm->pNumTxBytesUnicast = (u8Byte *)pValue;
1282                         break;
1283
1284                 case    ODM_CMNINFO_RX_UNI:
1285                         pDM_Odm->pNumRxBytesUnicast = (u8Byte *)pValue;
1286                         break;
1287
1288                 case    ODM_CMNINFO_WM_MODE:
1289                         pDM_Odm->pWirelessMode = (u1Byte *)pValue;
1290                         break;
1291
1292                 case    ODM_CMNINFO_BAND:
1293                         pDM_Odm->pBandType = (u1Byte *)pValue;
1294                         break;
1295
1296                 case    ODM_CMNINFO_SEC_CHNL_OFFSET:
1297                         pDM_Odm->pSecChOffset = (u1Byte *)pValue;
1298                         break;
1299
1300                 case    ODM_CMNINFO_SEC_MODE:
1301                         pDM_Odm->pSecurity = (u1Byte *)pValue;
1302                         break;
1303
1304                 case    ODM_CMNINFO_BW:
1305                         pDM_Odm->pBandWidth = (u1Byte *)pValue;
1306                         break;
1307
1308                 case    ODM_CMNINFO_CHNL:
1309                         pDM_Odm->pChannel = (u1Byte *)pValue;
1310                         break;
1311
1312                 case    ODM_CMNINFO_DMSP_GET_VALUE:
1313                         pDM_Odm->pbGetValueFromOtherMac = (BOOLEAN *)pValue;
1314                         break;
1315
1316                 case    ODM_CMNINFO_BUDDY_ADAPTOR:
1317                         pDM_Odm->pBuddyAdapter = (PADAPTER *)pValue;
1318                         break;
1319
1320                 case    ODM_CMNINFO_DMSP_IS_MASTER:
1321                         pDM_Odm->pbMasterOfDMSP = (BOOLEAN *)pValue;
1322                         break;
1323
1324                 case    ODM_CMNINFO_SCAN:
1325                         pDM_Odm->pbScanInProcess = (BOOLEAN *)pValue;
1326                         break;
1327
1328                 case    ODM_CMNINFO_POWER_SAVING:
1329                         pDM_Odm->pbPowerSaving = (BOOLEAN *)pValue;
1330                         break;
1331
1332                 case    ODM_CMNINFO_ONE_PATH_CCA:
1333                         pDM_Odm->pOnePathCCA = (u1Byte *)pValue;
1334                         break;
1335
1336                 case    ODM_CMNINFO_DRV_STOP:
1337                         pDM_Odm->pbDriverStopped =  (BOOLEAN *)pValue;
1338                         break;
1339
1340                 case    ODM_CMNINFO_PNP_IN:
1341                         pDM_Odm->pbDriverIsGoingToPnpSetPowerSleep =  (BOOLEAN *)pValue;
1342                         break;
1343
1344                 case    ODM_CMNINFO_INIT_ON:
1345                         pDM_Odm->pinit_adpt_in_progress =  (BOOLEAN *)pValue;
1346                         break;
1347
1348                 case    ODM_CMNINFO_ANT_TEST:
1349                         pDM_Odm->pAntennaTest =  (u1Byte *)pValue;
1350                         break;
1351
1352                 case    ODM_CMNINFO_NET_CLOSED:
1353                         pDM_Odm->pbNet_closed = (BOOLEAN *)pValue;
1354                         break;
1355
1356                 case    ODM_CMNINFO_FORCED_RATE:
1357                         pDM_Odm->pForcedDataRate = (pu2Byte)pValue;
1358                         break;
1359
1360                 case  ODM_CMNINFO_FORCED_IGI_LB:
1361                         pDM_Odm->pu1ForcedIgiLb = (u1Byte *)pValue;
1362                         break;
1363
1364                 case    ODM_CMNINFO_MP_MODE:
1365                         pDM_Odm->mp_mode = (u1Byte *)pValue;
1366                         break;
1367
1368                 //case  ODM_CMNINFO_RTSTA_AID:
1369                 //      pDM_Odm->pAidMap =  (u1Byte *)pValue;
1370                 //      break;
1371
1372                 //case  ODM_CMNINFO_BT_COEXIST:
1373                 //      pDM_Odm->BTCoexist = (BOOLEAN *)pValue;
1374
1375                 //case  ODM_CMNINFO_STA_STATUS:
1376                         //pDM_Odm->pODM_StaInfo[] = (PSTA_INFO_T)pValue;
1377                         //break;
1378
1379                 //case  ODM_CMNINFO_PHY_STATUS:
1380                 //      pDM_Odm->pPhyInfo = (ODM_PHY_INFO *)pValue;
1381                 //      break;
1382
1383                 //case  ODM_CMNINFO_MAC_STATUS:
1384                 //      pDM_Odm->pMacInfo = (ODM_MAC_INFO *)pValue;
1385                 //      break;
1386                 //To remove the compiler warning, must add an empty default statement to handle the other values.
1387                 default:
1388                         //do nothing
1389                         break;
1390
1391         }
1392
1393 }
1394
1395
1396 VOID
1397 ODM_CmnInfoPtrArrayHook(
1398         IN              PDM_ODM_T               pDM_Odm,
1399         IN              ODM_CMNINFO_E   CmnInfo,
1400         IN              u2Byte                  Index,
1401         IN              PVOID                   pValue
1402         )
1403 {
1404         //
1405         // Hook call by reference pointer.
1406         //
1407         switch  (CmnInfo)
1408         {
1409                 //
1410                 // Dynamic call by reference pointer.
1411                 //
1412                 case    ODM_CMNINFO_STA_STATUS:
1413                         pDM_Odm->pODM_StaInfo[Index] = (PSTA_INFO_T)pValue;
1414                         break;
1415                 //To remove the compiler warning, must add an empty default statement to handle the other values.
1416                 default:
1417                         //do nothing
1418                         break;
1419         }
1420
1421 }
1422
1423
1424 //
1425 // Update Band/CHannel/.. The values are dynamic but non-per-packet.
1426 //
1427 VOID
1428 ODM_CmnInfoUpdate(
1429         IN              PDM_ODM_T               pDM_Odm,
1430         IN              u4Byte                  CmnInfo,
1431         IN              u8Byte                  Value
1432         )
1433 {
1434         //
1435         // This init variable may be changed in run time.
1436         //
1437         switch  (CmnInfo)
1438         {
1439                 case ODM_CMNINFO_LINK_IN_PROGRESS:
1440                         pDM_Odm->bLinkInProcess = (BOOLEAN)Value;
1441                         break;
1442
1443                 case    ODM_CMNINFO_ABILITY:
1444                         pDM_Odm->SupportAbility = (u4Byte)Value;
1445                         break;
1446
1447                 case    ODM_CMNINFO_RF_TYPE:
1448                         pDM_Odm->RFType = (u1Byte)Value;
1449                         break;
1450
1451                 case    ODM_CMNINFO_WIFI_DIRECT:
1452                         pDM_Odm->bWIFI_Direct = (BOOLEAN)Value;
1453                         break;
1454
1455                 case    ODM_CMNINFO_WIFI_DISPLAY:
1456                         pDM_Odm->bWIFI_Display = (BOOLEAN)Value;
1457                         break;
1458
1459                 case    ODM_CMNINFO_LINK:
1460                         pDM_Odm->bLinked = (BOOLEAN)Value;
1461                         break;
1462
1463                 case    ODM_CMNINFO_STATION_STATE:
1464                         pDM_Odm->bsta_state = (BOOLEAN)Value;
1465                         break;
1466
1467                 case    ODM_CMNINFO_RSSI_MIN:
1468                         pDM_Odm->RSSI_Min= (u1Byte)Value;
1469                         break;
1470
1471                 case    ODM_CMNINFO_DBG_COMP:
1472                         pDM_Odm->DebugComponents = Value;
1473                         break;
1474
1475                 case    ODM_CMNINFO_DBG_LEVEL:
1476                         pDM_Odm->DebugLevel = (u4Byte)Value;
1477                         break;
1478                 case    ODM_CMNINFO_RA_THRESHOLD_HIGH:
1479                         pDM_Odm->RateAdaptive.HighRSSIThresh = (u1Byte)Value;
1480                         break;
1481
1482                 case    ODM_CMNINFO_RA_THRESHOLD_LOW:
1483                         pDM_Odm->RateAdaptive.LowRSSIThresh = (u1Byte)Value;
1484                         break;
1485                 // The following is for BT HS mode and BT coexist mechanism.
1486                 case ODM_CMNINFO_BT_DISABLED:
1487                         pDM_Odm->bBtDisabled = (BOOLEAN)Value;
1488                         break;
1489
1490                 case ODM_CMNINFO_BT_HS_CONNECT_PROCESS:
1491                         pDM_Odm->bBtConnectProcess = (BOOLEAN)Value;
1492                         break;
1493
1494                 case ODM_CMNINFO_BT_HS_RSSI:
1495                         pDM_Odm->btHsRssi = (u1Byte)Value;
1496                         break;
1497
1498                 case    ODM_CMNINFO_BT_OPERATION:
1499                         pDM_Odm->bBtHsOperation = (BOOLEAN)Value;
1500                         break;
1501
1502                 case    ODM_CMNINFO_BT_LIMITED_DIG:
1503                         pDM_Odm->bBtLimitedDig = (BOOLEAN)Value;
1504                         break;
1505
1506                 case    ODM_CMNINFO_BT_DISABLE_EDCA:
1507                         pDM_Odm->bBtDisableEdcaTurbo = (BOOLEAN)Value;
1508                         break;
1509
1510 /*
1511                 case    ODM_CMNINFO_OP_MODE:
1512                         pDM_Odm->OPMode = (u1Byte)Value;
1513                         break;
1514
1515                 case    ODM_CMNINFO_WM_MODE:
1516                         pDM_Odm->WirelessMode = (u1Byte)Value;
1517                         break;
1518
1519                 case    ODM_CMNINFO_BAND:
1520                         pDM_Odm->BandType = (u1Byte)Value;
1521                         break;
1522
1523                 case    ODM_CMNINFO_SEC_CHNL_OFFSET:
1524                         pDM_Odm->SecChOffset = (u1Byte)Value;
1525                         break;
1526
1527                 case    ODM_CMNINFO_SEC_MODE:
1528                         pDM_Odm->Security = (u1Byte)Value;
1529                         break;
1530
1531                 case    ODM_CMNINFO_BW:
1532                         pDM_Odm->BandWidth = (u1Byte)Value;
1533                         break;
1534
1535                 case    ODM_CMNINFO_CHNL:
1536                         pDM_Odm->Channel = (u1Byte)Value;
1537                         break;
1538 */
1539                 default:
1540                         //do nothing
1541                         break;
1542         }
1543
1544
1545 }
1546
1547 VOID
1548 odm_CommonInfoSelfInit(
1549         IN              PDM_ODM_T               pDM_Odm
1550         )
1551 {
1552         pFAT_T                  pDM_FatTable = &pDM_Odm->DM_FatTable;
1553         pDM_Odm->bCckHighPower = (BOOLEAN) ODM_GetBBReg(pDM_Odm, ODM_REG(CCK_RPT_FORMAT,pDM_Odm), ODM_BIT(CCK_RPT_FORMAT,pDM_Odm));
1554         pDM_Odm->RFPathRxEnable = (u1Byte) ODM_GetBBReg(pDM_Odm, ODM_REG(BB_RX_PATH,pDM_Odm), ODM_BIT(BB_RX_PATH,pDM_Odm));
1555 #if (DM_ODM_SUPPORT_TYPE != ODM_CE)
1556         pDM_Odm->pbNet_closed = &pDM_Odm->BOOLEAN_temp;
1557 #endif
1558
1559         ODM_InitDebugSetting(pDM_Odm);
1560
1561         if(pDM_Odm->SupportICType==ODM_RTL8723A)
1562         {
1563                 pDM_Odm->AntDivType = SW_ANTDIV;
1564         }
1565         else if(pDM_Odm->SupportICType & (ODM_RTL8192C|ODM_RTL8192D))
1566         {
1567            #if(defined(CONFIG_HW_ANTENNA_DIVERSITY))
1568                 pDM_Odm->AntDivType = HW_ANTDIV;
1569            #elif (defined(CONFIG_SW_ANTENNA_DIVERSITY))
1570                 pDM_Odm->AntDivType = SW_ANTDIV;
1571            #endif
1572         }
1573         pDM_Odm->TxRate = 0xFF;
1574 #if(defined(CONFIG_HW_ANTENNA_DIVERSITY))
1575 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
1576
1577         if(pDM_Odm->SupportICType==ODM_RTL8723B)
1578         {
1579                 if((!pDM_Odm->DM_SWAT_Table.ANTA_ON || !pDM_Odm->DM_SWAT_Table.ANTB_ON))
1580                         pDM_Odm->SupportAbility &= ~(ODM_BB_ANT_DIV);
1581         }
1582
1583 #elif (DM_ODM_SUPPORT_TYPE == ODM_AP)
1584
1585         #if(defined(CONFIG_NOT_SUPPORT_ANTDIV))
1586                 pDM_Odm->SupportAbility &= ~(ODM_BB_ANT_DIV);
1587                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Disable AntDiv function] : Not Support 2.4G & 5G Antenna Diversity\n"));
1588         #elif(defined(CONFIG_2G5G_SUPPORT_ANTDIV))
1589                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Enable AntDiv function] : 2.4G & 5G Support Antenna Diversity Simultaneously \n"));
1590                 pDM_FatTable->AntDiv_2G_5G = (ODM_ANTDIV_2G|ODM_ANTDIV_5G);
1591                 if(pDM_Odm->SupportICType & ODM_ANTDIV_SUPPORT)
1592                         pDM_Odm->SupportAbility |= ODM_BB_ANT_DIV;
1593                 if(*pDM_Odm->pBandType == ODM_BAND_5G )
1594                 {
1595                         #if ( defined(CONFIG_5G_CGCS_RX_DIVERSITY) )
1596                                 pDM_Odm->AntDivType = CGCS_RX_HW_ANTDIV;
1597                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 5G] : AntDiv Type = CGCS_RX_HW_ANTDIV\n"));
1598                         #elif( defined(CONFIG_5G_CG_TRX_DIVERSITY) )
1599                                 pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV;
1600                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 5G] : AntDiv Type = CG_TRX_HW_ANTDIV\n"));
1601                         #elif( defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY) )
1602                                 pDM_Odm->AntDivType = CG_TRX_SMART_ANTDIV;
1603                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 5G] : AntDiv Type = CG_SMART_ANTDIV\n"));
1604                         #endif
1605                 }
1606                 else    if(*pDM_Odm->pBandType == ODM_BAND_2_4G )
1607                 {
1608                         #if ( defined(CONFIG_2G_CGCS_RX_DIVERSITY) )
1609                                 pDM_Odm->AntDivType = CGCS_RX_HW_ANTDIV;
1610                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 2.4G] : AntDiv Type = CGCS_RX_HW_ANTDIV\n"));
1611                         #elif( defined(CONFIG_2G_CG_TRX_DIVERSITY) )
1612                                 pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV;
1613                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 2.4G] : AntDiv Type = CG_TRX_HW_ANTDIV\n"));
1614                         #elif( defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY) )
1615                                 pDM_Odm->AntDivType = CG_TRX_SMART_ANTDIV;
1616                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 2.4G] : AntDiv Type = CG_SMART_ANTDIV\n"));
1617                         #endif
1618                 }
1619         #elif(defined(CONFIG_5G_SUPPORT_ANTDIV))
1620                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Enable AntDiv function] : Only 5G Support Antenna Diversity\n"));
1621                 pDM_FatTable->AntDiv_2G_5G = (ODM_ANTDIV_5G);
1622                 if(*pDM_Odm->pBandType == ODM_BAND_5G )
1623                 {
1624                         if(pDM_Odm->SupportICType & ODM_ANTDIV_5G_SUPPORT_IC)
1625                                 pDM_Odm->SupportAbility |= ODM_BB_ANT_DIV;
1626                         #if ( defined(CONFIG_5G_CGCS_RX_DIVERSITY) )
1627                                 pDM_Odm->AntDivType = CGCS_RX_HW_ANTDIV;
1628                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 5G] : AntDiv Type = CGCS_RX_HW_ANTDIV\n"));
1629                         #elif( defined(CONFIG_5G_CG_TRX_DIVERSITY) )
1630                                 pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV;
1631                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 5G] : AntDiv Type = CG_TRX_HW_ANTDIV\n"));
1632                         #elif( defined(CONFIG_5G_CG_SMART_ANT_DIVERSITY) )
1633                                 pDM_Odm->AntDivType = CG_TRX_SMART_ANTDIV;
1634                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 5G] : AntDiv Type = CG_SMART_ANTDIV\n"));
1635                         #endif
1636                 }
1637                 else if(*pDM_Odm->pBandType == ODM_BAND_2_4G )
1638                 {
1639                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("Not Support 2G AntDivType\n"));
1640                         pDM_Odm->SupportAbility &= ~(ODM_BB_ANT_DIV);
1641                 }
1642         #elif(defined(CONFIG_2G_SUPPORT_ANTDIV))
1643                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ Enable AntDiv function] : Only 2.4G Support Antenna Diversity\n"));
1644                 pDM_FatTable->AntDiv_2G_5G = (ODM_ANTDIV_2G);
1645                 if(*pDM_Odm->pBandType == ODM_BAND_2_4G )
1646                 {
1647                         if(pDM_Odm->SupportICType & ODM_ANTDIV_2G_SUPPORT_IC)
1648                                 pDM_Odm->SupportAbility |= ODM_BB_ANT_DIV;
1649                         #if ( defined(CONFIG_2G_CGCS_RX_DIVERSITY) )
1650                                 pDM_Odm->AntDivType = CGCS_RX_HW_ANTDIV;
1651                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 2.4G] : AntDiv Type = CGCS_RX_HW_ANTDIV\n"));
1652                         #elif( defined(CONFIG_2G_CG_TRX_DIVERSITY) )
1653                                 pDM_Odm->AntDivType = CG_TRX_HW_ANTDIV;
1654                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 2.4G] : AntDiv Type = CG_TRX_HW_ANTDIV\n"));
1655                         #elif( defined(CONFIG_2G_CG_SMART_ANT_DIVERSITY) )
1656                                 pDM_Odm->AntDivType = CG_TRX_SMART_ANTDIV;
1657                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("[ 2.4G] : AntDiv Type = CG_SMART_ANTDIV\n"));
1658                         #endif
1659                 }
1660                 else if(*pDM_Odm->pBandType == ODM_BAND_5G )
1661                 {
1662                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("Not Support 5G AntDivType\n"));
1663                         pDM_Odm->SupportAbility &= ~(ODM_BB_ANT_DIV);
1664                 }
1665         #endif
1666 #endif //#if (DM_ODM_SUPPORT_TYPE == ODM_AP)
1667 #endif //#if(defined(CONFIG_HW_ANTENNA_DIVERSITY))
1668
1669 }
1670
1671 VOID
1672 odm_CommonInfoSelfUpdate(
1673         IN              PDM_ODM_T               pDM_Odm
1674         )
1675 {
1676         u1Byte  EntryCnt=0;
1677         u1Byte  i;
1678         PSTA_INFO_T     pEntry;
1679
1680 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1681
1682         PADAPTER        Adapter =  pDM_Odm->Adapter;
1683         PMGNT_INFO      pMgntInfo = &Adapter->MgntInfo;
1684
1685         pEntry = pDM_Odm->pODM_StaInfo[0];
1686         if(pMgntInfo->mAssoc)
1687         {
1688                 pEntry->bUsed=TRUE;
1689                 for (i=0; i<6; i++)
1690                         pEntry->MacAddr[i] = pMgntInfo->Bssid[i];
1691         }
1692         else
1693         {
1694                 pEntry->bUsed=FALSE;
1695                 for (i=0; i<6; i++)
1696                         pEntry->MacAddr[i] = 0;
1697         }
1698 #endif
1699
1700
1701         if(*(pDM_Odm->pBandWidth) == ODM_BW40M)
1702         {
1703                 if(*(pDM_Odm->pSecChOffset) == 1)
1704                         pDM_Odm->ControlChannel = *(pDM_Odm->pChannel) -2;
1705                 else if(*(pDM_Odm->pSecChOffset) == 2)
1706                         pDM_Odm->ControlChannel = *(pDM_Odm->pChannel) +2;
1707         }
1708         else
1709                 pDM_Odm->ControlChannel = *(pDM_Odm->pChannel);
1710
1711         for (i=0; i<ODM_ASSOCIATE_ENTRY_NUM; i++)
1712         {
1713                 pEntry = pDM_Odm->pODM_StaInfo[i];
1714                 if(IS_STA_VALID(pEntry))
1715                         EntryCnt++;
1716         }
1717         if(EntryCnt == 1)
1718                 pDM_Odm->bOneEntryOnly = TRUE;
1719         else
1720                 pDM_Odm->bOneEntryOnly = FALSE;
1721 }
1722
1723 VOID
1724 odm_CmnInfoInit_Debug(
1725         IN              PDM_ODM_T               pDM_Odm
1726         )
1727 {
1728         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_CmnInfoInit_Debug==>\n"));
1729         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportPlatform=%d\n",pDM_Odm->SupportPlatform) );
1730         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportAbility=0x%x\n",pDM_Odm->SupportAbility) );
1731         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportInterface=%d\n",pDM_Odm->SupportInterface) );
1732         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("SupportICType=0x%x\n",pDM_Odm->SupportICType) );
1733         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("CutVersion=%d\n",pDM_Odm->CutVersion) );
1734         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("FabVersion=%d\n",pDM_Odm->FabVersion) );
1735         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("RFType=%d\n",pDM_Odm->RFType) );
1736         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("BoardType=%d\n",pDM_Odm->BoardType) );
1737         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("ExtLNA=%d\n",pDM_Odm->ExtLNA) );
1738         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("ExtPA=%d\n",pDM_Odm->ExtPA) );
1739         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("ExtTRSW=%d\n",pDM_Odm->ExtTRSW) );
1740         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("PatchID=%d\n",pDM_Odm->PatchID) );
1741         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("bInHctTest=%d\n",pDM_Odm->bInHctTest) );
1742         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("bWIFITest=%d\n",pDM_Odm->bWIFITest) );
1743         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("bDualMacSmartConcurrent=%d\n",pDM_Odm->bDualMacSmartConcurrent) );
1744
1745 }
1746
1747 VOID
1748 odm_CmnInfoHook_Debug(
1749         IN              PDM_ODM_T               pDM_Odm
1750         )
1751 {
1752         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_CmnInfoHook_Debug==>\n"));
1753         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pNumTxBytesUnicast=%llu\n",*(pDM_Odm->pNumTxBytesUnicast)) );
1754         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pNumRxBytesUnicast=%llu\n",*(pDM_Odm->pNumRxBytesUnicast)) );
1755         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pWirelessMode=0x%x\n",*(pDM_Odm->pWirelessMode)) );
1756         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pSecChOffset=%d\n",*(pDM_Odm->pSecChOffset)) );
1757         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pSecurity=%d\n",*(pDM_Odm->pSecurity)) );
1758         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pBandWidth=%d\n",*(pDM_Odm->pBandWidth)) );
1759         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pChannel=%d\n",*(pDM_Odm->pChannel)) );
1760
1761         if(pDM_Odm->SupportICType==ODM_RTL8192D)
1762         {
1763                 if(pDM_Odm->pBandType)
1764                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pBandType=%d\n",*(pDM_Odm->pBandType)) );
1765                 if(pDM_Odm->pMacPhyMode)
1766                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pMacPhyMode=%d\n",*(pDM_Odm->pMacPhyMode)) );
1767                 if(pDM_Odm->pBuddyAdapter)
1768                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pbGetValueFromOtherMac=%d\n",*(pDM_Odm->pbGetValueFromOtherMac)) );
1769                 if(pDM_Odm->pBuddyAdapter)
1770                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pBuddyAdapter=%p\n",*(pDM_Odm->pBuddyAdapter)) );
1771                 if(pDM_Odm->pbMasterOfDMSP)
1772                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pbMasterOfDMSP=%d\n",*(pDM_Odm->pbMasterOfDMSP)) );
1773         }
1774         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pbScanInProcess=%d\n",*(pDM_Odm->pbScanInProcess)) );
1775         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pbPowerSaving=%d\n",*(pDM_Odm->pbPowerSaving)) );
1776
1777         if(pDM_Odm->SupportPlatform & (ODM_AP|ODM_ADSL))
1778                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("pOnePathCCA=%d\n",*(pDM_Odm->pOnePathCCA)) );
1779 }
1780
1781 VOID
1782 odm_CmnInfoUpdate_Debug(
1783         IN              PDM_ODM_T               pDM_Odm
1784         )
1785 {
1786         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_CmnInfoUpdate_Debug==>\n"));
1787         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("bWIFI_Direct=%d\n",pDM_Odm->bWIFI_Direct) );
1788         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("bWIFI_Display=%d\n",pDM_Odm->bWIFI_Display) );
1789         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("bLinked=%d\n",pDM_Odm->bLinked) );
1790         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("RSSI_Min=%d\n",pDM_Odm->RSSI_Min) );
1791 }
1792
1793 VOID
1794 odm_BasicDbgMessage
1795 (
1796         IN              PDM_ODM_T               pDM_Odm
1797         )
1798 {
1799         PFALSE_ALARM_STATISTICS FalseAlmCnt = &(pDM_Odm->FalseAlmCnt);
1800         pDIG_T  pDM_DigTable = &pDM_Odm->DM_DigTable;
1801
1802         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("odm_BasicDbgMsg==>\n"));
1803         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("bLinked = %d, RSSI_Min = %d, CurrentIGI = 0x%x \n",
1804                 pDM_Odm->bLinked, pDM_Odm->RSSI_Min, pDM_DigTable->CurIGValue) );
1805         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("Cnt_Cck_fail = %d, Cnt_Ofdm_fail = %d, Total False Alarm = %d\n",
1806                 FalseAlmCnt->Cnt_Cck_fail, FalseAlmCnt->Cnt_Ofdm_fail, FalseAlmCnt->Cnt_all));
1807         ODM_RT_TRACE(pDM_Odm,ODM_COMP_COMMON, ODM_DBG_LOUD, ("RxRate = 0x%x, RSSI_A = %d, RSSI_B = %d\n",
1808                 pDM_Odm->RxRate, pDM_Odm->RSSI_A, pDM_Odm->RSSI_B));
1809
1810 }
1811
1812 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
1813 VOID
1814 ODM_InitAllWorkItems(IN PDM_ODM_T       pDM_Odm )
1815 {
1816 #if USE_WORKITEM
1817         PADAPTER                pAdapter = pDM_Odm->Adapter;
1818
1819         ODM_InitializeWorkItem( pDM_Odm,
1820                                                         &pDM_Odm->DM_SWAT_Table.SwAntennaSwitchWorkitem_8723B,
1821                                                         (RT_WORKITEM_CALL_BACK)ODM_SW_AntDiv_WorkitemCallback,
1822                                                         (PVOID)pAdapter,
1823                                                         "AntennaSwitchWorkitem");
1824
1825         ODM_InitializeWorkItem( pDM_Odm,
1826                                                         &pDM_Odm->DM_SWAT_Table.SwAntennaSwitchWorkitem,
1827                                                         (RT_WORKITEM_CALL_BACK)odm_SwAntDivChkAntSwitchWorkitemCallback,
1828                                                         (PVOID)pAdapter,
1829                                                         "AntennaSwitchWorkitem");
1830
1831
1832         ODM_InitializeWorkItem(
1833                 pDM_Odm,
1834                 &(pDM_Odm->PathDivSwitchWorkitem),
1835                 (RT_WORKITEM_CALL_BACK)odm_PathDivChkAntSwitchWorkitemCallback,
1836                 (PVOID)pAdapter,
1837                 "SWAS_WorkItem");
1838
1839         ODM_InitializeWorkItem(
1840                 pDM_Odm,
1841                 &(pDM_Odm->CCKPathDiversityWorkitem),
1842                 (RT_WORKITEM_CALL_BACK)odm_CCKTXPathDiversityWorkItemCallback,
1843                 (PVOID)pAdapter,
1844                 "CCKTXPathDiversityWorkItem");
1845
1846         ODM_InitializeWorkItem(
1847                 pDM_Odm,
1848                 &(pDM_Odm->MPT_DIGWorkitem),
1849                 (RT_WORKITEM_CALL_BACK)odm_MPT_DIGWorkItemCallback,
1850                 (PVOID)pAdapter,
1851                 "MPT_DIGWorkitem");
1852
1853         ODM_InitializeWorkItem(
1854                 pDM_Odm,
1855                 &(pDM_Odm->RaRptWorkitem),
1856                 (RT_WORKITEM_CALL_BACK)ODM_UpdateInitRateWorkItemCallback,
1857                 (PVOID)pAdapter,
1858                 "RaRptWorkitem");
1859
1860 #if(defined(CONFIG_HW_ANTENNA_DIVERSITY))
1861 #if (RTL8188E_SUPPORT == 1)
1862         ODM_InitializeWorkItem(
1863                 pDM_Odm,
1864                 &(pDM_Odm->FastAntTrainingWorkitem),
1865                 (RT_WORKITEM_CALL_BACK)odm_FastAntTrainingWorkItemCallback,
1866                 (PVOID)pAdapter,
1867                 "FastAntTrainingWorkitem");
1868 #endif
1869 #endif
1870         ODM_InitializeWorkItem(
1871                 pDM_Odm,
1872                 &(pDM_Odm->DM_RXHP_Table.PSDTimeWorkitem),
1873                 (RT_WORKITEM_CALL_BACK)odm_PSD_RXHPWorkitemCallback,
1874                 (PVOID)pAdapter,
1875                 "PSDRXHP_WorkItem");
1876 #endif
1877 }
1878
1879 VOID
1880 ODM_FreeAllWorkItems(IN PDM_ODM_T       pDM_Odm )
1881 {
1882 #if USE_WORKITEM
1883         ODM_FreeWorkItem(       &(pDM_Odm->DM_SWAT_Table.SwAntennaSwitchWorkitem_8723B));
1884
1885         ODM_FreeWorkItem(       &(pDM_Odm->DM_SWAT_Table.SwAntennaSwitchWorkitem));
1886
1887         ODM_FreeWorkItem(&(pDM_Odm->PathDivSwitchWorkitem));
1888
1889         ODM_FreeWorkItem(&(pDM_Odm->CCKPathDiversityWorkitem));
1890
1891         ODM_FreeWorkItem(&(pDM_Odm->FastAntTrainingWorkitem));
1892
1893         ODM_FreeWorkItem(&(pDM_Odm->MPT_DIGWorkitem));
1894
1895         ODM_FreeWorkItem(&(pDM_Odm->RaRptWorkitem));
1896
1897         ODM_FreeWorkItem((&pDM_Odm->DM_RXHP_Table.PSDTimeWorkitem));
1898 #endif
1899
1900 }
1901 #endif
1902
1903 /*
1904 VOID
1905 odm_FindMinimumRSSI(
1906         IN              PDM_ODM_T               pDM_Odm
1907         )
1908 {
1909         u4Byte  i;
1910         u1Byte  RSSI_Min = 0xFF;
1911
1912         for(i=0; i<ODM_ASSOCIATE_ENTRY_NUM; i++)
1913         {
1914 //              if(pDM_Odm->pODM_StaInfo[i] != NULL)
1915                 if(IS_STA_VALID(pDM_Odm->pODM_StaInfo[i]) )
1916                 {
1917                         if(pDM_Odm->pODM_StaInfo[i]->RSSI_Ave < RSSI_Min)
1918                         {
1919                                 RSSI_Min = pDM_Odm->pODM_StaInfo[i]->RSSI_Ave;
1920                         }
1921                 }
1922         }
1923
1924         pDM_Odm->RSSI_Min = RSSI_Min;
1925
1926 }
1927
1928 VOID
1929 odm_IsLinked(
1930         IN              PDM_ODM_T               pDM_Odm
1931         )
1932 {
1933         u4Byte i;
1934         BOOLEAN Linked = FALSE;
1935
1936         for(i=0; i<ODM_ASSOCIATE_ENTRY_NUM; i++)
1937         {
1938                         if(IS_STA_VALID(pDM_Odm->pODM_StaInfo[i]) )
1939                         {
1940                                 Linked = TRUE;
1941                                 break;
1942                         }
1943
1944         }
1945
1946         pDM_Odm->bLinked = Linked;
1947 }
1948 */
1949
1950
1951 //3============================================================
1952 //3 DIG
1953 //3============================================================
1954 /*-----------------------------------------------------------------------------
1955  * Function:    odm_DIGInit()
1956  *
1957  * Overview:    Set DIG scheme init value.
1958  *
1959  * Input:               NONE
1960  *
1961  * Output:              NONE
1962  *
1963  * Return:              NONE
1964  *
1965  * Revised History:
1966  *      When            Who             Remark
1967  *
1968  *---------------------------------------------------------------------------*/
1969 VOID
1970 ODM_ChangeDynamicInitGainThresh(
1971         IN      PDM_ODM_T       pDM_Odm,
1972         IN      u4Byte          DM_Type,
1973         IN      u4Byte          DM_Value
1974         )
1975 {
1976         pDIG_T  pDM_DigTable = &pDM_Odm->DM_DigTable;
1977
1978         if (DM_Type == DIG_TYPE_THRESH_HIGH)
1979         {
1980                 pDM_DigTable->RssiHighThresh = DM_Value;
1981         }
1982         else if (DM_Type == DIG_TYPE_THRESH_LOW)
1983         {
1984                 pDM_DigTable->RssiLowThresh = DM_Value;
1985         }
1986         else if (DM_Type == DIG_TYPE_ENABLE)
1987         {
1988                 pDM_DigTable->Dig_Enable_Flag   = TRUE;
1989         }
1990         else if (DM_Type == DIG_TYPE_DISABLE)
1991         {
1992                 pDM_DigTable->Dig_Enable_Flag = FALSE;
1993         }
1994         else if (DM_Type == DIG_TYPE_BACKOFF)
1995         {
1996                 if(DM_Value > 30)
1997                         DM_Value = 30;
1998                 pDM_DigTable->BackoffVal = (u1Byte)DM_Value;
1999         }
2000         else if(DM_Type == DIG_TYPE_RX_GAIN_MIN)
2001         {
2002                 if(DM_Value == 0)
2003                         DM_Value = 0x1;
2004                 pDM_DigTable->rx_gain_range_min = (u1Byte)DM_Value;
2005         }
2006         else if(DM_Type == DIG_TYPE_RX_GAIN_MAX)
2007         {
2008                 if(DM_Value > 0x50)
2009                         DM_Value = 0x50;
2010                 pDM_DigTable->rx_gain_range_max = (u1Byte)DM_Value;
2011         }
2012 }       /* DM_ChangeDynamicInitGainThresh */
2013
2014 int getIGIForDiff(int value_IGI)
2015 {
2016         #define ONERCCA_LOW_TH          0x30
2017         #define ONERCCA_LOW_DIFF        8
2018
2019         if (value_IGI < ONERCCA_LOW_TH) {
2020                 if ((ONERCCA_LOW_TH - value_IGI) < ONERCCA_LOW_DIFF)
2021                         return ONERCCA_LOW_TH;
2022                 else
2023                         return value_IGI + ONERCCA_LOW_DIFF;
2024         } else {
2025                 return value_IGI;
2026         }
2027 }
2028
2029
2030 VOID
2031 odm_AdaptivityInit(
2032 IN PDM_ODM_T pDM_Odm
2033 )
2034 {
2035         if(pDM_Odm->SupportICType == ODM_RTL8723B)
2036         {
2037                 pDM_Odm->TH_L2H_ini = 0xf8; // -8
2038         }
2039         if((pDM_Odm->SupportICType == ODM_RTL8192E)&&(pDM_Odm->SupportInterface == ODM_ITRF_PCIE))
2040         {
2041                 pDM_Odm->TH_L2H_ini = 0xf0; // -16
2042         }
2043         else
2044         {
2045                 pDM_Odm->TH_L2H_ini = 0xf9; // -7
2046         }
2047
2048         pDM_Odm->TH_EDCCA_HL_diff = 7;
2049         pDM_Odm->IGI_Base = 0x32;
2050         pDM_Odm->IGI_target = 0x1c;
2051         pDM_Odm->ForceEDCCA = 0;
2052         pDM_Odm->AdapEn_RSSI = 20;
2053
2054         //Reg524[11]=0 is easily to transmit packets during adaptivity test
2055
2056         //ODM_SetBBReg(pDM_Odm, 0x524, BIT11, 1);// stop counting if EDCCA is asserted
2057 }
2058
2059 // Add by Neil Chen to enable edcca to MP Platform
2060 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
2061
2062 VOID
2063 odm_EnableEDCCA(
2064         IN              PDM_ODM_T               pDM_Odm
2065 )
2066 {
2067
2068         // This should be moved out of OUTSRC
2069         PADAPTER                pAdapter        = pDM_Odm->Adapter;
2070         // Enable EDCCA. The value is suggested by SD3 Wilson.
2071
2072         //
2073         // Revised for ASUS 11b/g performance issues, suggested by BB Neil, 2012.04.13.
2074         //
2075         if((pDM_Odm->SupportICType == ODM_RTL8723A)&&(IS_WIRELESS_MODE_G(pAdapter)))
2076         {
2077                 //PlatformEFIOWrite1Byte(Adapter, rOFDM0_ECCAThreshold, 0x00);
2078                 ODM_Write1Byte(pDM_Odm,rOFDM0_ECCAThreshold,0x00);
2079                 ODM_Write1Byte(pDM_Odm,rOFDM0_ECCAThreshold+2,0xFD);
2080
2081         }
2082         else
2083         {
2084                 //PlatformEFIOWrite1Byte(Adapter, rOFDM0_ECCAThreshold, 0x03);
2085                 ODM_Write1Byte(pDM_Odm,rOFDM0_ECCAThreshold,0x03);
2086                 ODM_Write1Byte(pDM_Odm,rOFDM0_ECCAThreshold+2,0x00);
2087         }
2088
2089         //PlatformEFIOWrite1Byte(Adapter, rOFDM0_ECCAThreshold+2, 0x00);
2090 }
2091
2092 VOID
2093 odm_DisableEDCCA(
2094         IN              PDM_ODM_T               pDM_Odm
2095 )
2096 {
2097         // Disable EDCCA..
2098         ODM_Write1Byte(pDM_Odm, rOFDM0_ECCAThreshold, 0x7f);
2099         ODM_Write1Byte(pDM_Odm, rOFDM0_ECCAThreshold+2, 0x7f);
2100 }
2101
2102 //
2103 // Description: According to initial gain value to determine to enable or disable EDCCA.
2104 //
2105 // Suggested by SD3 Wilson. Added by tynli. 2011.11.25.
2106 //
2107 VOID
2108 odm_DynamicEDCCA(
2109         IN              PDM_ODM_T               pDM_Odm
2110 )
2111 {
2112         PADAPTER                pAdapter        = pDM_Odm->Adapter;
2113         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);
2114         u1Byte  RegC50, RegC58;
2115         BOOLEAN         bFwCurrentInPSMode=FALSE;
2116
2117         pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_FW_PSMODE_STATUS, (pu1Byte)(&bFwCurrentInPSMode));
2118
2119         // Disable EDCCA mode while under LPS mode, added by Roger, 2012.09.14.
2120         if(bFwCurrentInPSMode)
2121                 return;
2122
2123         RegC50 = (u1Byte)ODM_GetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskByte0);
2124         RegC58 = (u1Byte)ODM_GetBBReg(pDM_Odm, rOFDM0_XBAGCCore1, bMaskByte0);
2125
2126
2127         if((RegC50 > 0x28 && RegC58 > 0x28) ||
2128                 ((pDM_Odm->SupportICType == ODM_RTL8723A && IS_WIRELESS_MODE_G(pAdapter) && RegC50>0x26)) ||
2129                 (pDM_Odm->SupportICType == ODM_RTL8188E && RegC50 > 0x28))
2130         {
2131                 if(!pHalData->bPreEdccaEnable)
2132                 {
2133                         odm_EnableEDCCA(pDM_Odm);
2134                         pHalData->bPreEdccaEnable = TRUE;
2135                 }
2136
2137         }
2138         else if((RegC50 < 0x25 && RegC58 < 0x25) || (pDM_Odm->SupportICType == ODM_RTL8188E && RegC50 < 0x25))
2139         {
2140                 if(pHalData->bPreEdccaEnable)
2141                 {
2142                         odm_DisableEDCCA(pDM_Odm);
2143                         pHalData->bPreEdccaEnable = FALSE;
2144                 }
2145         }
2146 }
2147
2148
2149 #endif    // end MP platform support
2150
2151 VOID
2152 odm_Adaptivity(
2153         IN              PDM_ODM_T               pDM_Odm,
2154         IN              u1Byte                  IGI
2155 )
2156 {
2157         s1Byte TH_L2H_dmc, TH_H2L_dmc;
2158         s1Byte Diff, IGI_target;
2159         BOOLEAN EDCCA_State = 0;
2160
2161 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
2162         PADAPTER                pAdapter        = pDM_Odm->Adapter;
2163         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);
2164         BOOLEAN         bFwCurrentInPSMode=FALSE;
2165         PMGNT_INFO                              pMgntInfo = &(pAdapter->MgntInfo);
2166
2167         pAdapter->HalFunc.GetHwRegHandler(pAdapter, HW_VAR_FW_PSMODE_STATUS, (pu1Byte)(&bFwCurrentInPSMode));
2168
2169         // Disable EDCCA mode while under LPS mode, added by Roger, 2012.09.14.
2170         if(bFwCurrentInPSMode)
2171                 return;
2172 #endif
2173
2174         if(!(pDM_Odm->SupportAbility & ODM_BB_ADAPTIVITY))
2175         {
2176                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("Go to odm_DynamicEDCCA() \n"));
2177                 // Add by Neil Chen to enable edcca to MP Platform
2178 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
2179                 // Adjust EDCCA.
2180                 if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
2181                         odm_DynamicEDCCA(pDM_Odm);
2182 #endif
2183                 return;
2184         }
2185         ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_Adaptivity() =====> \n"));
2186
2187         ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("ForceEDCCA=%d, IGI_Base=0x%x, TH_L2H_ini = %d, TH_EDCCA_HL_diff = %d, AdapEn_RSSI = %d\n",
2188                 pDM_Odm->ForceEDCCA, pDM_Odm->IGI_Base, pDM_Odm->TH_L2H_ini, pDM_Odm->TH_EDCCA_HL_diff, pDM_Odm->AdapEn_RSSI));
2189
2190         if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
2191                 ODM_SetBBReg(pDM_Odm, 0x800, BIT10, 0); //ADC_mask enable
2192
2193         if((!pDM_Odm->bLinked)||(*pDM_Odm->pChannel > 149)) // Band4 doesn't need adaptivity
2194         {
2195                 if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
2196                 {
2197                         ODM_SetBBReg(pDM_Odm,rOFDM0_ECCAThreshold, bMaskByte0, 0x7f);
2198                         ODM_SetBBReg(pDM_Odm,rOFDM0_ECCAThreshold, bMaskByte2, 0x7f);
2199                 }
2200                 else
2201                         ODM_SetBBReg(pDM_Odm, rFPGA0_XB_LSSIReadBack, 0xFFFF, (0x7f<<8) | 0x7f);
2202                 return;
2203         }
2204
2205 #if (DM_ODM_SUPPORT_TYPE==ODM_WIN)
2206                 if(pMgntInfo->IOTPeer == HT_IOT_PEER_BROADCOM)
2207                         ODM_Write1Byte(pDM_Odm, REG_TRX_SIFS_OFDM, 0x0a);
2208                 else
2209                         ODM_Write1Byte(pDM_Odm, REG_TRX_SIFS_OFDM, 0x0e);
2210 #endif
2211         if(!pDM_Odm->ForceEDCCA)
2212         {
2213                 if(pDM_Odm->RSSI_Min > pDM_Odm->AdapEn_RSSI)
2214                         EDCCA_State = 1;
2215                 else if(pDM_Odm->RSSI_Min < (pDM_Odm->AdapEn_RSSI - 5))
2216                         EDCCA_State = 0;
2217         }
2218         else
2219                 EDCCA_State = 1;
2220         //if((pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) && (*pDM_Odm->pBandType == BAND_ON_5G))
2221                 //IGI_target = pDM_Odm->IGI_Base;
2222         //else
2223         {
2224
2225                 if(*pDM_Odm->pBandWidth == ODM_BW20M) //CHANNEL_WIDTH_20
2226                         IGI_target = pDM_Odm->IGI_Base;
2227                 else if(*pDM_Odm->pBandWidth == ODM_BW40M)
2228                         IGI_target = pDM_Odm->IGI_Base + 2;
2229                 else if(*pDM_Odm->pBandWidth == ODM_BW80M)
2230                         IGI_target = pDM_Odm->IGI_Base + 6;
2231                 else
2232                         IGI_target = pDM_Odm->IGI_Base;
2233         }
2234
2235         pDM_Odm->IGI_target = (u1Byte) IGI_target;
2236
2237         ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("BandWidth=%s, IGI_target=0x%x, EDCCA_State=%d\n",
2238                 (*pDM_Odm->pBandWidth==ODM_BW80M)?"80M":((*pDM_Odm->pBandWidth==ODM_BW40M)?"40M":"20M"), IGI_target, EDCCA_State));
2239
2240         if(EDCCA_State == 1)
2241         {
2242                 Diff = IGI_target -(s1Byte)IGI;
2243                 TH_L2H_dmc = pDM_Odm->TH_L2H_ini + Diff;
2244                 if(TH_L2H_dmc > 10)     TH_L2H_dmc = 10;
2245                 TH_H2L_dmc = TH_L2H_dmc - pDM_Odm->TH_EDCCA_HL_diff;
2246         }
2247         else
2248         {
2249                 TH_L2H_dmc = 0x7f;
2250                 TH_H2L_dmc = 0x7f;
2251         }
2252         ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("IGI=0x%x, TH_L2H_dmc = %d, TH_H2L_dmc = %d\n",
2253                 IGI, TH_L2H_dmc, TH_H2L_dmc));
2254
2255         if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
2256         {
2257                 ODM_SetBBReg(pDM_Odm,rOFDM0_ECCAThreshold, bMaskByte0, (u1Byte)TH_L2H_dmc);
2258                 ODM_SetBBReg(pDM_Odm,rOFDM0_ECCAThreshold, bMaskByte2, (u1Byte)TH_H2L_dmc);
2259         }
2260         else
2261                 ODM_SetBBReg(pDM_Odm, rFPGA0_XB_LSSIReadBack, 0xFFFF, ((u1Byte)TH_H2L_dmc<<8) | (u1Byte)TH_L2H_dmc);
2262 }
2263
2264 VOID
2265 ODM_DynamicATCSwitch_init(
2266         IN              PDM_ODM_T               pDM_Odm
2267 )
2268 {
2269         PADAPTER                Adapter = pDM_Odm->Adapter;
2270         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
2271
2272 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN )
2273
2274         pDM_Odm->CrystalCap = pHalData->CrystalCap;
2275         pDM_Odm->bATCStatus = (u1Byte)ODM_GetBBReg(pDM_Odm, rOFDM1_CFOTracking, BIT11);
2276         pDM_Odm->CFOThreshold = CFO_Threshold_Xtal;
2277
2278 #endif
2279 }
2280
2281 VOID
2282 ODM_DynamicATCSwitch(
2283         IN              PDM_ODM_T               pDM_Odm
2284 )
2285 {
2286         PADAPTER                Adapter = pDM_Odm->Adapter;
2287         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
2288         u1Byte                  CrystalCap,ATC_status_temp = 0;
2289         u4Byte                  packet_count;
2290         int                             CFO_kHz_A,CFO_kHz_B,CFO_ave = 0, Adjust_Xtal = 0;
2291         int                             CFO_ave_diff;
2292
2293 #if (MP_DRIVER == 1)
2294         if ( *(pDM_Odm->mp_mode) == 1)
2295                 pDM_Odm->bLinked = TRUE;
2296 #endif
2297
2298 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN )
2299
2300         if(!(pDM_Odm->SupportAbility & ODM_BB_DYNAMIC_ATC))
2301                 return;
2302
2303         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_ATC, ODM_DBG_LOUD, ("=========> ODM_DynamicATCSwitch()\n"));
2304
2305         //2 No link!
2306         //
2307         if(!pDM_Odm->bLinked)
2308         {
2309                 //3
2310                 //3 1.Enable ATC
2311                 if(pDM_Odm->bATCStatus == ATC_Status_Off)
2312                 {
2313                         if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
2314                                 ODM_SetBBReg(pDM_Odm, rOFDM1_CFOTracking, BIT11, ATC_Status_On);
2315
2316                         if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
2317                                 ODM_SetBBReg(pDM_Odm, rFc_area_Jaguar, BIT14, ATC_Status_On);
2318
2319                         pDM_Odm->bATCStatus = ATC_Status_On;
2320                 }
2321
2322                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_ATC, ODM_DBG_LOUD, ("ODM_DynamicATCSwitch(): No link!!\n"));
2323                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_ATC, ODM_DBG_LOUD, ("ODM_DynamicATCSwitch(): ATCStatus = %d\n", pDM_Odm->bATCStatus));
2324
2325                 //3 2.Disable CFO tracking for BT
2326                 if(!pDM_Odm->bBtDisabled)
2327                 {
2328                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_ATC, ODM_DBG_LOUD, ("ODM_DynamicATCSwitch(): Disable CFO tracking for BT!!\n"));
2329                         return;
2330                 }
2331
2332                 //3 3.Reset Crystal Cap.
2333                 if(pDM_Odm->CrystalCap != pHalData->CrystalCap)
2334                 {
2335                         pDM_Odm->CrystalCap = pHalData->CrystalCap;
2336                         CrystalCap = pDM_Odm->CrystalCap & 0x3f;
2337                         odm_Write_CrystalCap(pDM_Odm,CrystalCap);
2338                 }
2339                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_ATC, ODM_DBG_LOUD, ("ODM_DynamicATCSwitch(): CrystalCap = 0x%x\n", pDM_Odm->CrystalCap));
2340
2341         }
2342         else
2343         {
2344
2345         //2 Initialization
2346         //
2347                 //3 1. Calculate CFO for path-A & path-B
2348                 CFO_kHz_A =  (int)(pDM_Odm->CFO_tail[0] * 3125)  / 1280;
2349                 CFO_kHz_B =  (int)(pDM_Odm->CFO_tail[1] * 3125)  / 1280;
2350                 packet_count = pDM_Odm->packetCount;
2351
2352                 //3 2.No new packet
2353                 if(packet_count == pDM_Odm->packetCount_pre)
2354                 {
2355                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_ATC, ODM_DBG_LOUD, ("ODM_DynamicATCSwitch(): packet counter doesn't change\n"));
2356                         return;
2357                 }
2358                 pDM_Odm->packetCount_pre = packet_count;
2359                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_ATC, ODM_DBG_LOUD, ("ODM_DynamicATCSwitch(): packet counter = %d\n", pDM_Odm->packetCount));
2360
2361                 //3 3.Average CFO
2362                 if(pDM_Odm->RFType == ODM_1T1R)
2363                         CFO_ave = CFO_kHz_A;
2364                 else
2365                         CFO_ave = (int)(CFO_kHz_A + CFO_kHz_B) >> 1;
2366
2367                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_ATC, ODM_DBG_LOUD, ("ODM_DynamicATCSwitch(): CFO_kHz_A = %dkHz, CFO_kHz_B = %dkHz, CFO_ave = %dkHz\n",
2368                                                 CFO_kHz_A, CFO_kHz_B, CFO_ave));
2369
2370                 //3 4.Avoid abnormal large CFO
2371                 CFO_ave_diff = (pDM_Odm->CFO_ave_pre >= CFO_ave)?(pDM_Odm->CFO_ave_pre - CFO_ave):(CFO_ave - pDM_Odm->CFO_ave_pre);
2372                 if(CFO_ave_diff > 20 && pDM_Odm->largeCFOHit == 0)
2373                 {
2374                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_ATC, ODM_DBG_LOUD, ("ODM_DynamicATCSwitch(): first large CFO hit\n"));
2375                         pDM_Odm->largeCFOHit = 1;
2376                         return;
2377                 }
2378                 else
2379                         pDM_Odm->largeCFOHit = 0;
2380                 pDM_Odm->CFO_ave_pre = CFO_ave;
2381
2382         //2 CFO tracking by adjusting Xtal cap.
2383         //
2384                 if (pDM_Odm->bBtDisabled)
2385                 {
2386                         //3 1.Dynamic Xtal threshold
2387                         if(CFO_ave >= -pDM_Odm->CFOThreshold && CFO_ave <= pDM_Odm->CFOThreshold && pDM_Odm->bIsfreeze == 0)
2388                         {
2389                                 if (pDM_Odm->CFOThreshold == CFO_Threshold_Xtal)
2390                                 {
2391                                         pDM_Odm->CFOThreshold = CFO_Threshold_Xtal + 10;
2392                                         pDM_Odm->bIsfreeze = 1;
2393                                 }
2394                                 else
2395                                         pDM_Odm->CFOThreshold = CFO_Threshold_Xtal;
2396                         }
2397                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_ATC, ODM_DBG_LOUD, ("ODM_DynamicATCSwitch(): Dynamic threshold = %d\n", pDM_Odm->CFOThreshold));
2398
2399                 //3      2.Calculate Xtal offset
2400                         if(CFO_ave > pDM_Odm->CFOThreshold && pDM_Odm->CrystalCap < 0x3f)
2401                                 Adjust_Xtal =  ((CFO_ave - CFO_Threshold_Xtal) >> 2) + 1;
2402                         else if(CFO_ave < (-pDM_Odm->CFOThreshold) && pDM_Odm->CrystalCap > 0)
2403                                 Adjust_Xtal =  ((CFO_ave + CFO_Threshold_Xtal) >> 2) - 1;
2404                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_ATC, ODM_DBG_LOUD, ("ODM_DynamicATCSwitch(): Crystal cap = 0x%x, Crystal cap offset = %d\n", pDM_Odm->CrystalCap, Adjust_Xtal));
2405
2406                         //3 3.Adjudt Crystal Cap.
2407                         if(Adjust_Xtal != 0)
2408                         {
2409                                 pDM_Odm->bIsfreeze = 0;
2410                                 pDM_Odm->CrystalCap = pDM_Odm->CrystalCap + Adjust_Xtal;
2411
2412                                 if(pDM_Odm->CrystalCap > 0x3f)
2413                                         pDM_Odm->CrystalCap = 0x3f;
2414                                 else if (pDM_Odm->CrystalCap < 0)
2415                                         pDM_Odm->CrystalCap = 0;
2416
2417                                 CrystalCap = pDM_Odm->CrystalCap & 0x3f;
2418                                 odm_Write_CrystalCap(pDM_Odm,CrystalCap);
2419
2420                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_ATC, ODM_DBG_LOUD, ("ODM_DynamicATCSwitch(): New crystal cap = 0x%x \n", pDM_Odm->CrystalCap));
2421                         }
2422                 }
2423                 else if(pDM_Odm->CrystalCap != pHalData->CrystalCap)
2424                 {
2425                         //3 Reset Xtal Cap when BT is enable
2426                         pDM_Odm->CrystalCap = pHalData->CrystalCap;
2427                         CrystalCap = pDM_Odm->CrystalCap & 0x3f;
2428                         odm_Write_CrystalCap(pDM_Odm,CrystalCap);
2429                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_ATC, ODM_DBG_LOUD, ("ODM_DynamicATCSwitch(): Disable CFO tracking for BT!! (CrystalCap is reset)\n"));
2430                 }
2431                 else
2432                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_ATC, ODM_DBG_LOUD, ("ODM_DynamicATCSwitch(): Disable CFO tracking for BT!! (CrystalCap is unchanged)\n"));
2433                 if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES){
2434                         //2 Dynamic ATC switch
2435                         //
2436                                 //3 1.Enable ATC when CFO is larger then 80kHz
2437                                 if(CFO_ave < CFO_Threshold_ATC && CFO_ave > -CFO_Threshold_ATC)
2438                                 {
2439                                         if(pDM_Odm->bATCStatus == ATC_Status_On)
2440                                         {
2441                                         ODM_SetBBReg(pDM_Odm, rOFDM1_CFOTracking, BIT11, ATC_Status_Off);
2442                                         pDM_Odm->bATCStatus = ATC_Status_Off;
2443                                         }
2444                                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_ATC, ODM_DBG_LOUD, ("ODM_DynamicATCSwitch(): Disable ATC!!\n"));
2445                                 }
2446                                 else
2447                                 {
2448                                         if(pDM_Odm->bATCStatus == ATC_Status_Off)
2449                                         {
2450                                                 ODM_SetBBReg(pDM_Odm, rOFDM1_CFOTracking, BIT11, ATC_Status_On);
2451                                                 pDM_Odm->bATCStatus = ATC_Status_On;
2452                                         }
2453                                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DYNAMIC_ATC, ODM_DBG_LOUD, ("ODM_DynamicATCSwitch(): Enable ATC!!\n"));
2454                                 }
2455                 }
2456         }
2457 #endif
2458 }
2459
2460 VOID
2461 odm_Write_CrystalCap(
2462         IN              PDM_ODM_T               pDM_Odm,
2463         IN              u1Byte                  CrystalCap
2464 )
2465 {
2466         PADAPTER                Adapter = pDM_Odm->Adapter;
2467         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
2468
2469         if(IS_HARDWARE_TYPE_8192D(Adapter))
2470         {
2471                 PHY_SetBBReg(Adapter, 0x24, 0xF0, CrystalCap & 0x0F);
2472                 PHY_SetBBReg(Adapter, 0x28, 0xF0000000, ((CrystalCap & 0xF0) >> 4));
2473         }
2474
2475         if(IS_HARDWARE_TYPE_8188E(Adapter))
2476         {
2477                 // write 0x24[16:11] = 0x24[22:17] = CrystalCap
2478                 PHY_SetBBReg(Adapter, REG_AFE_XTAL_CTRL, 0x7ff800, (CrystalCap | (CrystalCap << 6)));
2479         }
2480
2481         if(IS_HARDWARE_TYPE_8812(Adapter))
2482         {
2483                 // write 0x2C[30:25] = 0x2C[24:19] = CrystalCap
2484                 CrystalCap = CrystalCap & 0x3F;
2485                 PHY_SetBBReg(Adapter, REG_MAC_PHY_CTRL, 0x7FF80000, (CrystalCap | (CrystalCap << 6)));
2486         }
2487
2488         //only for B-cut
2489         if ((IS_HARDWARE_TYPE_8723A(Adapter) && pHalData->EEPROMVersion >= 0x01) ||
2490                 IS_HARDWARE_TYPE_8723B(Adapter) ||IS_HARDWARE_TYPE_8192E(Adapter) || IS_HARDWARE_TYPE_8821(Adapter))
2491         {
2492                 // 0x2C[23:18] = 0x2C[17:12] = CrystalCap
2493                 CrystalCap = CrystalCap & 0x3F;
2494                 PHY_SetBBReg(Adapter, REG_MAC_PHY_CTRL, 0xFFF000, (CrystalCap | (CrystalCap << 6)));
2495         }
2496
2497         if(IS_HARDWARE_TYPE_8723AE(Adapter))
2498                 PHY_SetBBReg(Adapter, REG_LDOA15_CTRL, bMaskDWord, 0x01572505);
2499
2500 }
2501
2502
2503 VOID
2504 ODM_Write_DIG(
2505         IN      PDM_ODM_T               pDM_Odm,
2506         IN      u1Byte                  CurrentIGI
2507         )
2508 {
2509         pDIG_T  pDM_DigTable = &pDM_Odm->DM_DigTable;
2510
2511         if(pDM_Odm->StopDIG)
2512         {
2513                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("Stop Writing IGI\n"));
2514                 return;
2515         }
2516
2517         ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("ODM_REG(IGI_A,pDM_Odm)=0x%x, ODM_BIT(IGI,pDM_Odm)=0x%x \n",
2518                 ODM_REG(IGI_A,pDM_Odm),ODM_BIT(IGI,pDM_Odm)));
2519
2520         if(pDM_DigTable->CurIGValue != CurrentIGI)//if(pDM_DigTable->PreIGValue != CurrentIGI)
2521         {
2522                 if(pDM_Odm->SupportPlatform & (ODM_CE|ODM_WIN))
2523                 {
2524                                 ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI);
2525                         if(pDM_Odm->RFType != ODM_1T1R)
2526                                 ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_B,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI);
2527                         }
2528                 else if(pDM_Odm->SupportPlatform & (ODM_AP|ODM_ADSL))
2529                 {
2530                         switch(*(pDM_Odm->pOnePathCCA))
2531                         {
2532                         case ODM_CCA_2R:
2533                         ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI);
2534                                         if(pDM_Odm->RFType != ODM_1T1R)
2535                                         ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_B,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI);
2536                                 break;
2537                         case ODM_CCA_1R_A:
2538                                 ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI);
2539                                         if(pDM_Odm->RFType != ODM_1T1R)
2540                                         ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_B,pDM_Odm), ODM_BIT(IGI,pDM_Odm), getIGIForDiff(CurrentIGI));
2541                                 break;
2542                         case ODM_CCA_1R_B:
2543                                 ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_A,pDM_Odm), ODM_BIT(IGI,pDM_Odm), getIGIForDiff(CurrentIGI));
2544                                         if(pDM_Odm->RFType != ODM_1T1R)
2545                                         ODM_SetBBReg(pDM_Odm, ODM_REG(IGI_B,pDM_Odm), ODM_BIT(IGI,pDM_Odm), CurrentIGI);
2546                                         break;
2547                                 }
2548                 }
2549
2550                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("CurrentIGI(0x%02x). \n",CurrentIGI));
2551                 //pDM_DigTable->PreIGValue = pDM_DigTable->CurIGValue;
2552                 pDM_DigTable->CurIGValue = CurrentIGI;
2553         }
2554         ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("ODM_Write_DIG():CurrentIGI=0x%x \n",CurrentIGI));
2555
2556 }
2557
2558 VOID
2559 odm_DIGbyRSSI_LPS(
2560         IN              PDM_ODM_T               pDM_Odm
2561         )
2562 {
2563         //PADAPTER                                      pAdapter =pDM_Odm->Adapter;
2564         //pDIG_T                                                pDM_DigTable = &pDM_Odm->DM_DigTable;
2565         PFALSE_ALARM_STATISTICS         pFalseAlmCnt = &pDM_Odm->FalseAlmCnt;
2566
2567 #if 0           //and 2.3.5 coding rule
2568         struct mlme_priv        *pmlmepriv = &(pAdapter->mlmepriv);
2569         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);
2570         struct dm_priv  *pdmpriv = &pHalData->dmpriv;
2571 #endif
2572
2573         u1Byte  RSSI_Lower=DM_DIG_MIN_NIC;   //0x1E or 0x1C
2574         u1Byte  CurrentIGI=pDM_Odm->RSSI_Min;
2575
2576         CurrentIGI=CurrentIGI+RSSI_OFFSET_DIG;
2577
2578
2579         //ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG_LPS, ODM_DBG_LOUD, ("odm_DIG()==>\n"));
2580
2581         // Using FW PS mode to make IGI
2582
2583         ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("---Neil---odm_DIG is in LPS mode\n"));
2584         //Adjust by  FA in LPS MODE
2585         if(pFalseAlmCnt->Cnt_all> DM_DIG_FA_TH2_LPS)
2586                 CurrentIGI = CurrentIGI+2;
2587         else if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH1_LPS)
2588                 CurrentIGI = CurrentIGI+1;
2589         else if(pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0_LPS)
2590                 CurrentIGI = CurrentIGI-1;
2591
2592
2593         //Lower bound checking
2594
2595         //RSSI Lower bound check
2596         if((pDM_Odm->RSSI_Min-10) > DM_DIG_MIN_NIC)
2597                 RSSI_Lower =(pDM_Odm->RSSI_Min-10);
2598         else
2599                 RSSI_Lower =DM_DIG_MIN_NIC;
2600
2601         //Upper and Lower Bound checking
2602          if(CurrentIGI > DM_DIG_MAX_NIC)
2603                 CurrentIGI=DM_DIG_MAX_NIC;
2604          else if(CurrentIGI < RSSI_Lower)
2605                 CurrentIGI =RSSI_Lower;
2606
2607         ODM_Write_DIG(pDM_Odm, CurrentIGI);//ODM_Write_DIG(pDM_Odm, pDM_DigTable->CurIGValue);
2608
2609 }
2610
2611 VOID
2612 odm_DIGInit(
2613         IN              PDM_ODM_T               pDM_Odm
2614         )
2615 {
2616         pDIG_T  pDM_DigTable = &pDM_Odm->DM_DigTable;
2617
2618         //pDM_DigTable->Dig_Enable_Flag = TRUE;
2619         //pDM_DigTable->Dig_Ext_Port_Stage = DIG_EXT_PORT_STAGE_MAX;
2620         pDM_DigTable->CurIGValue = (u1Byte) ODM_GetBBReg(pDM_Odm, ODM_REG(IGI_A,pDM_Odm), ODM_BIT(IGI,pDM_Odm));
2621         //pDM_DigTable->PreIGValue = 0x0;
2622         //pDM_DigTable->CurSTAConnectState = pDM_DigTable->PreSTAConnectState = DIG_STA_DISCONNECT;
2623         //pDM_DigTable->CurMultiSTAConnectState = DIG_MultiSTA_DISCONNECT;
2624         pDM_DigTable->RssiLowThresh     = DM_DIG_THRESH_LOW;
2625         pDM_DigTable->RssiHighThresh    = DM_DIG_THRESH_HIGH;
2626         pDM_DigTable->FALowThresh       = DM_FALSEALARM_THRESH_LOW;
2627         pDM_DigTable->FAHighThresh      = DM_FALSEALARM_THRESH_HIGH;
2628         if(pDM_Odm->BoardType & (ODM_BOARD_EXT_PA|ODM_BOARD_EXT_LNA))
2629         {
2630                 pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC;
2631                 pDM_DigTable->rx_gain_range_min = DM_DIG_MIN_NIC;
2632         }
2633         else
2634         {
2635                 pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC;
2636                 pDM_DigTable->rx_gain_range_min = DM_DIG_MIN_NIC;
2637         }
2638         pDM_DigTable->BackoffVal = DM_DIG_BACKOFF_DEFAULT;
2639         pDM_DigTable->BackoffVal_range_max = DM_DIG_BACKOFF_MAX;
2640         pDM_DigTable->BackoffVal_range_min = DM_DIG_BACKOFF_MIN;
2641         pDM_DigTable->PreCCK_CCAThres = 0xFF;
2642         pDM_DigTable->CurCCK_CCAThres = 0x83;
2643         pDM_DigTable->ForbiddenIGI = DM_DIG_MIN_NIC;
2644         pDM_DigTable->LargeFAHit = 0;
2645         pDM_DigTable->Recover_cnt = 0;
2646         pDM_DigTable->DIG_Dynamic_MIN_0 = DM_DIG_MIN_NIC;
2647         pDM_DigTable->DIG_Dynamic_MIN_1 = DM_DIG_MIN_NIC;
2648         pDM_DigTable->bMediaConnect_0 = FALSE;
2649         pDM_DigTable->bMediaConnect_1 = FALSE;
2650
2651         //To Initialize pDM_Odm->bDMInitialGainEnable == FALSE to avoid DIG error
2652         pDM_Odm->bDMInitialGainEnable = TRUE;
2653
2654         //To Initi BT30 IGI
2655         pDM_DigTable->BT30_CurIGI=0x32;
2656
2657 }
2658
2659 VOID
2660 odm_DigForBtHsMode(
2661         IN              PDM_ODM_T               pDM_Odm
2662         )
2663 {
2664 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
2665         pDIG_T                                  pDM_DigTable=&pDM_Odm->DM_DigTable;
2666         u1Byte                                  digForBtHs=0;
2667         u1Byte                                  digUpBound=0x5a;
2668
2669         if(pDM_Odm->bBtConnectProcess)
2670         {
2671                 if(pDM_Odm->SupportICType&(ODM_RTL8723A))
2672                         digForBtHs = 0x28;
2673                 else
2674                         digForBtHs = 0x22;
2675         }
2676         else
2677         {
2678                 //
2679                 // Decide DIG value by BT HS RSSI.
2680                 //
2681                 digForBtHs = pDM_Odm->btHsRssi+4;
2682
2683                 //DIG Bound
2684                 if(pDM_Odm->SupportICType&(ODM_RTL8723A))
2685                         digUpBound = 0x3e;
2686
2687                 if(digForBtHs > digUpBound)
2688                         digForBtHs = digUpBound;
2689                 if(digForBtHs < 0x1c)
2690                         digForBtHs = 0x1c;
2691
2692                 // update Current IGI
2693                 pDM_DigTable->BT30_CurIGI = digForBtHs;
2694         }
2695         ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DigForBtHsMode() : set DigValue=0x%x\n", digForBtHs));
2696 #endif
2697 }
2698
2699 VOID
2700 odm_DIG(
2701         IN              PDM_ODM_T               pDM_Odm
2702         )
2703 {
2704         pDIG_T                                          pDM_DigTable = &pDM_Odm->DM_DigTable;
2705         PFALSE_ALARM_STATISTICS         pFalseAlmCnt = &pDM_Odm->FalseAlmCnt;
2706         pRXHP_T                                         pRX_HP_Table  = &pDM_Odm->DM_RXHP_Table;
2707         u1Byte                                          DIG_Dynamic_MIN;
2708         u1Byte                                          DIG_MaxOfMin;
2709         BOOLEAN                                         FirstConnect, FirstDisConnect;
2710         u1Byte                                          dm_dig_max, dm_dig_min, offset;
2711         u1Byte                                          CurrentIGI = pDM_DigTable->CurIGValue;
2712         u1Byte                                          Adap_IGI_Upper = pDM_Odm->IGI_target + 30 + (u1Byte) pDM_Odm->TH_L2H_ini -(u1Byte) pDM_Odm->TH_EDCCA_HL_diff;
2713
2714 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
2715 // This should be moved out of OUTSRC
2716         PADAPTER                pAdapter        = pDM_Odm->Adapter;
2717 #if OS_WIN_FROM_WIN7(OS_VERSION)
2718         if(IsAPModeExist( pAdapter) && pAdapter->bInHctTest)
2719         {
2720                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() Return: Is AP mode or In HCT Test \n"));
2721                 return;
2722         }
2723 #endif
2724 /*
2725         if (pDM_Odm->SupportICType==ODM_RTL8723B)
2726                 return;
2727 */
2728
2729         if(pDM_Odm->bBtHsOperation)
2730         {
2731                 odm_DigForBtHsMode(pDM_Odm);
2732         }
2733
2734         if(!(pDM_Odm->SupportICType &(ODM_RTL8723A|ODM_RTL8188E)))
2735         {
2736                 if(pRX_HP_Table->RXHP_flag == 1)
2737                 {
2738                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() Return: In RXHP Operation \n"));
2739                         return;
2740                 }
2741         }
2742 #endif
2743 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
2744 #ifdef CONFIG_SPECIAL_SETTING_FOR_FUNAI_TV
2745         if((pDM_Odm->bLinked) && (pDM_Odm->Adapter->registrypriv.force_igi !=0))
2746         {
2747                 printk("pDM_Odm->RSSI_Min=%d \n",pDM_Odm->RSSI_Min);
2748                 ODM_Write_DIG(pDM_Odm,pDM_Odm->Adapter->registrypriv.force_igi);
2749                 return;
2750         }
2751 #endif
2752 #endif
2753 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
2754         prtl8192cd_priv priv                    = pDM_Odm->priv;
2755         if (!((priv->up_time > 5) && (priv->up_time % 2)) )
2756         {
2757                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() Return: Not In DIG Operation Period \n"));
2758                 return;
2759         }
2760 #endif
2761
2762         ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG()==>\n"));
2763         //if(!(pDM_Odm->SupportAbility & (ODM_BB_DIG|ODM_BB_FA_CNT)))
2764         if((!(pDM_Odm->SupportAbility&ODM_BB_DIG)) ||(!(pDM_Odm->SupportAbility&ODM_BB_FA_CNT)))
2765         {
2766 #if 0
2767                 if(pDM_Odm->SupportPlatform & (ODM_AP|ODM_ADSL))
2768                 {
2769                         if ((pDM_Odm->SupportICType == ODM_RTL8192C) && (pDM_Odm->ExtLNA == 1))
2770                                 CurrentIGI = 0x30; //pDM_DigTable->CurIGValue  = 0x30;
2771                         else
2772                                 CurrentIGI = 0x20; //pDM_DigTable->CurIGValue  = 0x20;
2773                         ODM_Write_DIG(pDM_Odm, CurrentIGI);//ODM_Write_DIG(pDM_Odm, pDM_DigTable->CurIGValue);
2774                 }
2775 #endif
2776                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() Return: SupportAbility ODM_BB_DIG or ODM_BB_FA_CNT is disabled\n"));
2777                 return;
2778         }
2779
2780         if(*(pDM_Odm->pbScanInProcess))
2781         {
2782                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() Return: In Scan Progress \n"));
2783                 return;
2784         }
2785
2786         //add by Neil Chen to avoid PSD is processing
2787         if(pDM_Odm->SupportICType==ODM_RTL8723A)
2788         {
2789                 if(pDM_Odm->bDMInitialGainEnable == FALSE)
2790                 {
2791                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() Return: PSD is Processing \n"));
2792                         return;
2793                 }
2794         }
2795
2796         if(pDM_Odm->SupportICType == ODM_RTL8192D)
2797         {
2798                 if(*(pDM_Odm->pMacPhyMode) == ODM_DMSP)
2799                 {
2800                         if(*(pDM_Odm->pbMasterOfDMSP))
2801                         {
2802                                 DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_0;
2803                                 FirstConnect = (pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0 == FALSE);
2804                                 FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0 == TRUE);
2805                         }
2806                         else
2807                         {
2808                                 DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_1;
2809                                 FirstConnect = (pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_1 == FALSE);
2810                                 FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_1 == TRUE);
2811                         }
2812                 }
2813                 else
2814                 {
2815                         if(*(pDM_Odm->pBandType) == ODM_BAND_5G)
2816                         {
2817                                 DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_0;
2818                                 FirstConnect = (pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0 == FALSE);
2819                                 FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0 == TRUE);
2820                         }
2821                         else
2822                         {
2823                                 DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_1;
2824                                 FirstConnect = (pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_1 == FALSE);
2825                                 FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_1 == TRUE);
2826                         }
2827                 }
2828         }
2829         else
2830         {
2831                 DIG_Dynamic_MIN = pDM_DigTable->DIG_Dynamic_MIN_0;
2832                 FirstConnect = (pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0 == FALSE);
2833                 FirstDisConnect = (!pDM_Odm->bLinked) && (pDM_DigTable->bMediaConnect_0 == TRUE);
2834         }
2835
2836         //1 Boundary Decision
2837         if(pDM_Odm->SupportICType & (ODM_RTL8192C) &&(pDM_Odm->BoardType & (ODM_BOARD_EXT_LNA | ODM_BOARD_EXT_PA)))
2838         {
2839                 if(pDM_Odm->SupportPlatform & (ODM_AP|ODM_ADSL))
2840                 {
2841
2842                         dm_dig_max = DM_DIG_MAX_AP_HP;
2843                         dm_dig_min = DM_DIG_MIN_AP_HP;
2844                 }
2845                 else
2846                 {
2847                         dm_dig_max = DM_DIG_MAX_NIC_HP;
2848                         dm_dig_min = DM_DIG_MIN_NIC_HP;
2849                 }
2850                 DIG_MaxOfMin = DM_DIG_MAX_AP_HP;
2851         }
2852         else
2853         {
2854                 if(pDM_Odm->SupportPlatform & (ODM_AP|ODM_ADSL))
2855                 {
2856 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
2857 #ifdef DFS
2858                         if (!priv->pmib->dot11DFSEntry.disable_DFS &&
2859                                 (OPMODE & WIFI_AP_STATE) &&
2860                                 (((pDM_Odm->ControlChannel >= 52) &&
2861                                 (pDM_Odm->ControlChannel <= 64)) ||
2862                                 ((pDM_Odm->ControlChannel >= 100) &&
2863                                 (pDM_Odm->ControlChannel <= 140))))
2864                                 dm_dig_max = 0x24;
2865                         else
2866 #endif
2867                         if (priv->pmib->dot11RFEntry.tx2path) {
2868                                 if (*(pDM_Odm->pWirelessMode) == ODM_WM_B)//(priv->pmib->dot11BssType.net_work_type == WIRELESS_11B)
2869                                         dm_dig_max = 0x2A;
2870                                 else
2871                                         dm_dig_max = 0x32;
2872                         }
2873                         else
2874 #endif
2875                         dm_dig_max = DM_DIG_MAX_AP;
2876                         dm_dig_min = DM_DIG_MIN_AP;
2877                         DIG_MaxOfMin = dm_dig_max;
2878                 }
2879                 else
2880                 {
2881                         if((pDM_Odm->SupportICType >= ODM_RTL8188E) && (pDM_Odm->SupportPlatform & (ODM_WIN|ODM_CE)))
2882                                 dm_dig_max = 0x5A;
2883                         else
2884                                 dm_dig_max = DM_DIG_MAX_NIC;
2885
2886                         if(pDM_Odm->SupportICType != ODM_RTL8821)
2887                                 dm_dig_min = DM_DIG_MIN_NIC;
2888                         else
2889                                 dm_dig_min = 0x1C;
2890
2891                         DIG_MaxOfMin = DM_DIG_MAX_AP;
2892                 }
2893         }
2894
2895         if(0 < *pDM_Odm->pu1ForcedIgiLb)
2896         {
2897                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): force IGI lb to: %u\n", *pDM_Odm->pu1ForcedIgiLb));
2898                 dm_dig_min = *pDM_Odm->pu1ForcedIgiLb;
2899                 dm_dig_max = (dm_dig_min <= dm_dig_max) ? (dm_dig_max) : (dm_dig_min + 1);
2900         }
2901
2902         if(pDM_Odm->bLinked)
2903         {
2904                 if(pDM_Odm->SupportICType&(ODM_RTL8723A/*|ODM_RTL8821*/))
2905                 {
2906                         //2 Upper Bound
2907                         if(( pDM_Odm->RSSI_Min + 10) > DM_DIG_MAX_NIC )
2908                                 pDM_DigTable->rx_gain_range_max = DM_DIG_MAX_NIC;
2909                         else if(( pDM_Odm->RSSI_Min + 10) < DM_DIG_MIN_NIC )
2910                                 pDM_DigTable->rx_gain_range_max = DM_DIG_MIN_NIC;
2911                         else
2912                                 pDM_DigTable->rx_gain_range_max = pDM_Odm->RSSI_Min + 10;
2913
2914                         //BT is Concurrent
2915
2916                         if(pDM_Odm->bBtLimitedDig)
2917                         {
2918                                 if(pDM_Odm->RSSI_Min>10)
2919                                 {
2920                                         if((pDM_Odm->RSSI_Min - 10) > DM_DIG_MAX_NIC)
2921                                                 DIG_Dynamic_MIN = DM_DIG_MAX_NIC;
2922                                         else if((pDM_Odm->RSSI_Min - 10) < DM_DIG_MIN_NIC)
2923                                                 DIG_Dynamic_MIN = DM_DIG_MIN_NIC;
2924                                         else
2925                                                 DIG_Dynamic_MIN = pDM_Odm->RSSI_Min - 10;
2926                                 }
2927                                 else
2928                                         DIG_Dynamic_MIN=DM_DIG_MIN_NIC;
2929                         }
2930                         else
2931                         {
2932                                 if((pDM_Odm->RSSI_Min + 20) > dm_dig_max )
2933                                         pDM_DigTable->rx_gain_range_max = dm_dig_max;
2934                                 else if((pDM_Odm->RSSI_Min + 20) < dm_dig_min )
2935                                         pDM_DigTable->rx_gain_range_max = dm_dig_min;
2936                                 else
2937                                         pDM_DigTable->rx_gain_range_max = pDM_Odm->RSSI_Min + 20;
2938
2939                         }
2940                 }
2941                 else
2942                 {
2943                         if((pDM_Odm->SupportICType & (ODM_RTL8192E|ODM_RTL8723B|ODM_RTL8812|ODM_RTL8821)) && (pDM_Odm->bBtLimitedDig==1)){
2944                                 //2 Modify DIG upper bound for 92E, 8723B, 8821 & 8812 BT
2945                                 if((pDM_Odm->RSSI_Min + 10) > dm_dig_max )
2946                                         pDM_DigTable->rx_gain_range_max = dm_dig_max;
2947                                 else if((pDM_Odm->RSSI_Min + 10) < dm_dig_min )
2948                                         pDM_DigTable->rx_gain_range_max = dm_dig_min;
2949                                 else
2950                                         pDM_DigTable->rx_gain_range_max = pDM_Odm->RSSI_Min + 10;
2951                         }
2952                         else{
2953
2954                         //2 Modify DIG upper bound
2955                         //2013.03.19 Luke: Modified upper bound for Netgear rental house test
2956                         if(pDM_Odm->SupportICType != ODM_RTL8821 && pDM_Odm->SupportICType != ODM_RTL8192E)
2957                                 offset = 20;
2958                         else
2959                                 offset = 10;
2960
2961                         if((pDM_Odm->RSSI_Min + offset) > dm_dig_max )
2962                                 pDM_DigTable->rx_gain_range_max = dm_dig_max;
2963                                 else if((pDM_Odm->RSSI_Min + offset) < dm_dig_min )
2964                                         pDM_DigTable->rx_gain_range_max = dm_dig_min;
2965                         else
2966                                 pDM_DigTable->rx_gain_range_max = pDM_Odm->RSSI_Min + offset;
2967
2968                         }
2969
2970                         //2 Modify DIG lower bound
2971                 /*
2972                         if((pFalseAlmCnt->Cnt_all > 500)&&(DIG_Dynamic_MIN < 0x25))
2973                                 DIG_Dynamic_MIN++;
2974                         else if(((pFalseAlmCnt->Cnt_all < 500)||(pDM_Odm->RSSI_Min < 8))&&(DIG_Dynamic_MIN > dm_dig_min))
2975                                 DIG_Dynamic_MIN--;
2976                 */
2977                         if(pDM_Odm->bOneEntryOnly)
2978                         {
2979                                 if(pDM_Odm->SupportICType != ODM_RTL8723B)
2980                                         offset = 0;
2981                                 else
2982                                         offset = 12;
2983
2984                                 if(pDM_Odm->RSSI_Min - offset < dm_dig_min)
2985                                         DIG_Dynamic_MIN = dm_dig_min;
2986                                 else if (pDM_Odm->RSSI_Min - offset > DIG_MaxOfMin)
2987                                         DIG_Dynamic_MIN = DIG_MaxOfMin;
2988                                 else
2989                                         DIG_Dynamic_MIN = pDM_Odm->RSSI_Min - offset;
2990
2991                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() : bOneEntryOnly=TRUE,  DIG_Dynamic_MIN=0x%x\n",DIG_Dynamic_MIN));
2992                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() : pDM_Odm->RSSI_Min=%d",pDM_Odm->RSSI_Min));
2993                         }
2994                         //1 Lower Bound for 88E AntDiv
2995 #if (defined(CONFIG_HW_ANTENNA_DIVERSITY))
2996                         else if( (pDM_Odm->SupportICType & ODM_ANTDIV_SUPPORT) &&(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV) )
2997                         //else if((pDM_Odm->SupportICType == ODM_RTL8188E)&&(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV))
2998                         {
2999                                 if((pDM_Odm->AntDivType == CG_TRX_HW_ANTDIV)||(pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV) ||pDM_Odm->AntDivType == S0S1_SW_ANTDIV)
3000                                 {
3001                                         DIG_Dynamic_MIN = (u1Byte) pDM_DigTable->AntDiv_RSSI_max;
3002                                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_DIG(): pDM_DigTable->AntDiv_RSSI_max=%d \n",pDM_DigTable->AntDiv_RSSI_max));
3003                                 }
3004                         }
3005 #endif
3006                         else
3007                         {
3008                                 DIG_Dynamic_MIN=dm_dig_min;
3009                         }
3010                 }
3011         }
3012         else
3013         {
3014                 pDM_DigTable->rx_gain_range_max = dm_dig_max;
3015                 DIG_Dynamic_MIN = dm_dig_min;
3016                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() : No Link\n"));
3017         }
3018
3019         //1 Modify DIG lower bound, deal with abnorally large false alarm
3020         if(pFalseAlmCnt->Cnt_all > 10000)
3021         {
3022                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("dm_DIG(): Abnornally false alarm case. \n"));
3023
3024                 if(pDM_DigTable->LargeFAHit != 3)
3025                         pDM_DigTable->LargeFAHit++;
3026                 if(pDM_DigTable->ForbiddenIGI < CurrentIGI)//if(pDM_DigTable->ForbiddenIGI < pDM_DigTable->CurIGValue)
3027                 {
3028                         pDM_DigTable->ForbiddenIGI = (u1Byte)CurrentIGI;//pDM_DigTable->ForbiddenIGI = pDM_DigTable->CurIGValue;
3029                         pDM_DigTable->LargeFAHit = 1;
3030                 }
3031
3032                 if(pDM_DigTable->LargeFAHit >= 3)
3033                 {
3034                         if((pDM_DigTable->ForbiddenIGI+1) >pDM_DigTable->rx_gain_range_max)
3035                                 pDM_DigTable->rx_gain_range_min = pDM_DigTable->rx_gain_range_max;
3036                         else
3037                                 pDM_DigTable->rx_gain_range_min = (pDM_DigTable->ForbiddenIGI + 1);
3038                         pDM_DigTable->Recover_cnt = 3600; //3600=2hr
3039                 }
3040
3041         }
3042         else
3043         {
3044                 //Recovery mechanism for IGI lower bound
3045                 if(pDM_DigTable->Recover_cnt != 0)
3046                         pDM_DigTable->Recover_cnt --;
3047                 else
3048                 {
3049                         if(pDM_DigTable->LargeFAHit < 3)
3050                         {
3051                                 if((pDM_DigTable->ForbiddenIGI -1) < DIG_Dynamic_MIN) //DM_DIG_MIN)
3052                                 {
3053                                         pDM_DigTable->ForbiddenIGI = DIG_Dynamic_MIN; //DM_DIG_MIN;
3054                                         pDM_DigTable->rx_gain_range_min = DIG_Dynamic_MIN; //DM_DIG_MIN;
3055                                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Normal Case: At Lower Bound\n"));
3056                                 }
3057                                 else
3058                                 {
3059                                         pDM_DigTable->ForbiddenIGI --;
3060                                         pDM_DigTable->rx_gain_range_min = (pDM_DigTable->ForbiddenIGI + 1);
3061                                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Normal Case: Approach Lower Bound\n"));
3062                                 }
3063                         }
3064                         else
3065                         {
3066                                 pDM_DigTable->LargeFAHit = 0;
3067                         }
3068                 }
3069         }
3070         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): pDM_DigTable->LargeFAHit=%d\n",pDM_DigTable->LargeFAHit));
3071
3072         #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
3073         if(IS_STA_VALID(pDM_Odm->pODM_StaInfo[0])) //STA mode is linked to AP
3074                 pDM_Odm->bsta_state = _TRUE;
3075         #endif
3076
3077         if((pDM_Odm->SupportPlatform&(ODM_WIN|ODM_CE))&&(pDM_Odm->PhyDbgInfo.NumQryBeaconPkt < 2) && (pDM_Odm->bsta_state) )
3078         {
3079                         pDM_DigTable->rx_gain_range_min = dm_dig_min;
3080         }
3081
3082         if(pDM_DigTable->rx_gain_range_min > pDM_DigTable->rx_gain_range_max)
3083                 pDM_DigTable->rx_gain_range_min = pDM_DigTable->rx_gain_range_max;
3084
3085         //1 Adjust initial gain by false alarm
3086         if(pDM_Odm->bLinked)
3087         {
3088                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): DIG AfterLink\n"));
3089                 if(FirstConnect)
3090                 {
3091                         if(pDM_Odm->RSSI_Min <= DIG_MaxOfMin)
3092                                 CurrentIGI = pDM_Odm->RSSI_Min;
3093                         else
3094                                 CurrentIGI = DIG_MaxOfMin;
3095                         ODM_RT_TRACE(pDM_Odm,   ODM_COMP_DIG, ODM_DBG_LOUD, ("DIG: First Connect\n"));
3096
3097                         ODM_ConfigBBWithHeaderFile(pDM_Odm, CONFIG_BB_AGC_TAB_DIFF);
3098                 }
3099                 else
3100                 {
3101                         if(pDM_Odm->SupportICType == ODM_RTL8192D)
3102                         {
3103                                 if(pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH2_92D)
3104                                         CurrentIGI = CurrentIGI + 4;//pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2;
3105                                 else if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH1_92D)
3106                                         CurrentIGI = CurrentIGI + 2; //pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1;
3107                                 else if(pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0_92D)
3108                                         CurrentIGI = CurrentIGI - 2;//pDM_DigTable->CurIGValue =pDM_DigTable->PreIGValue-1;
3109                         }
3110                         else
3111                         {
3112                                 //FA for Combo IC--NeilChen--2012--09--28
3113                                 if(pDM_Odm->SupportICType == ODM_RTL8723A)
3114                                 {
3115                                         //WLAN and BT ConCurrent
3116                                         if(pDM_Odm->bBtLimitedDig)
3117                                         {
3118                                                 if(pFalseAlmCnt->Cnt_all > 0x300)
3119                                                         CurrentIGI = CurrentIGI + 4;
3120                                                 else if (pFalseAlmCnt->Cnt_all > 0x250)
3121                                                         CurrentIGI = CurrentIGI + 2;
3122                                                 else if(pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0)
3123                                                         CurrentIGI = CurrentIGI -2;
3124                                         }
3125                                         else //Not Concurrent
3126                                         {
3127                                                 if(pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH2)
3128                                                         CurrentIGI = CurrentIGI + 4;//pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2;
3129                                                 else if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH1)
3130                                                         CurrentIGI = CurrentIGI + 2;//pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1;
3131                                                 else if(pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0)
3132                                                         CurrentIGI = CurrentIGI - 2;//pDM_DigTable->CurIGValue =pDM_DigTable->PreIGValue-1;
3133                                         }
3134                                 }
3135                                 else
3136                                 {
3137                                         if(pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH2)
3138                                                 CurrentIGI = CurrentIGI + 4;//pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+2;
3139                                         else if (pFalseAlmCnt->Cnt_all > DM_DIG_FA_TH1)
3140                                                 CurrentIGI = CurrentIGI + 2;//pDM_DigTable->CurIGValue = pDM_DigTable->PreIGValue+1;
3141                                         else if(pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH0)
3142                                                 CurrentIGI = CurrentIGI - 2;//pDM_DigTable->CurIGValue =pDM_DigTable->PreIGValue-1;
3143
3144                                         #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
3145                                         if(IS_STA_VALID(pDM_Odm->pODM_StaInfo[0])) //STA mode is linked to AP
3146                                                 pDM_Odm->bsta_state = _TRUE;
3147                                         #endif
3148
3149                                         if((pDM_Odm->SupportPlatform&(ODM_WIN|ODM_CE))&&(pDM_Odm->PhyDbgInfo.NumQryBeaconPkt < 2)
3150                                                 &&(pFalseAlmCnt->Cnt_all < DM_DIG_FA_TH1) && (pDM_Odm->bsta_state))
3151                                         {
3152                                                 CurrentIGI = pDM_DigTable->rx_gain_range_min;
3153                                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): Beacon is less than 10 and FA is less than 768, IGI GOES TO 0x1E!!!!!!!!!!!!\n"));
3154                                         }
3155                                         /*{
3156                                                 u2Byte value16;
3157                                                 value16 = (u2Byte) ODM_GetBBReg(pDM_Odm, 0x664, bMaskLWord);
3158                                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): NumQryBeaconPkt = %d, OFDM_OK_Cnt = %d\n",
3159                                                         pDM_Odm->PhyDbgInfo.NumQryBeaconPkt, value16));
3160                                         }*/
3161                                 }
3162                         }
3163                 }
3164         }
3165         else
3166         {
3167                 //CurrentIGI = pDM_DigTable->rx_gain_range_min;//pDM_DigTable->CurIGValue = pDM_DigTable->rx_gain_range_min
3168                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): DIG BeforeLink\n"));
3169                 if(FirstDisConnect)
3170                 {
3171                                 CurrentIGI = pDM_DigTable->rx_gain_range_min;
3172                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): First DisConnect \n"));
3173                 }
3174                 else
3175                 {
3176                         //2012.03.30 LukeLee: enable DIG before link but with very high thresholds
3177                      if(pFalseAlmCnt->Cnt_all > 10000)
3178                                 CurrentIGI = CurrentIGI + 4;
3179                         else if (pFalseAlmCnt->Cnt_all > 8000)
3180                                 CurrentIGI = CurrentIGI + 2;
3181                         else if(pFalseAlmCnt->Cnt_all < 500)
3182                                 CurrentIGI = CurrentIGI - 2;
3183                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): England DIG \n"));
3184                 }
3185         }
3186         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): DIG End Adjust IGI\n"));
3187         //1 Check initial gain by upper/lower bound
3188
3189         if(CurrentIGI > pDM_DigTable->rx_gain_range_max)
3190                 CurrentIGI = pDM_DigTable->rx_gain_range_max;
3191         if(CurrentIGI < pDM_DigTable->rx_gain_range_min)
3192                 CurrentIGI = pDM_DigTable->rx_gain_range_min;
3193
3194         if(pDM_Odm->SupportAbility & ODM_BB_ADAPTIVITY)
3195         {
3196                 if(CurrentIGI > Adap_IGI_Upper)
3197                         CurrentIGI = Adap_IGI_Upper;
3198
3199                 if(pDM_Odm->IGI_LowerBound != 0)
3200                 {
3201                         if(CurrentIGI < pDM_Odm->IGI_LowerBound)
3202                                 CurrentIGI = pDM_Odm->IGI_LowerBound;
3203                 }
3204                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): pDM_Odm->IGI_LowerBound = %d\n", pDM_Odm->IGI_LowerBound));
3205         }
3206
3207         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): rx_gain_range_max=0x%x, rx_gain_range_min=0x%x\n",
3208                 pDM_DigTable->rx_gain_range_max, pDM_DigTable->rx_gain_range_min));
3209         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): TotalFA=%d\n", pFalseAlmCnt->Cnt_all));
3210         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): CurIGValue=0x%x\n", CurrentIGI));
3211
3212         //2 High power RSSI threshold
3213 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
3214 {
3215         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pDM_Odm->Adapter);
3216         //PMGNT_INFO                    pMgntInfo       = &(pAdapter->MgntInfo);
3217         // for LC issue to dymanic modify DIG lower bound----------LC Mocca Issue
3218         u8Byte                  curTxOkCnt=0, curRxOkCnt=0;
3219         static u8Byte           lastTxOkCnt=0, lastRxOkCnt=0;
3220
3221         //u8Byte                        OKCntAll=0;
3222         //static u8Byte         TXByteCnt_A=0, TXByteCnt_B=0, RXByteCnt_A=0, RXByteCnt_B=0;
3223         //u8Byte                        CurByteCnt=0, PreByteCnt=0;
3224
3225         curTxOkCnt = pAdapter->TxStats.NumTxBytesUnicast - lastTxOkCnt;
3226         curRxOkCnt =pAdapter->RxStats.NumRxBytesUnicast - lastRxOkCnt;
3227         lastTxOkCnt = pAdapter->TxStats.NumTxBytesUnicast;
3228         lastRxOkCnt = pAdapter->RxStats.NumRxBytesUnicast;
3229         //----------------------------------------------------------end for LC Mocca issue
3230         if((pDM_Odm->SupportICType == ODM_RTL8723A)&& (pHalData->UndecoratedSmoothedPWDB > DM_DIG_HIGH_PWR_THRESHOLD))
3231         {
3232                 // High power IGI lower bound
3233                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): UndecoratedSmoothedPWDB(%#x)\n", pHalData->UndecoratedSmoothedPWDB));
3234                 if(CurrentIGI < DM_DIG_HIGH_PWR_IGI_LOWER_BOUND)
3235                 {
3236                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): CurIGValue(%#x)\n", pDM_DigTable->CurIGValue));
3237                         //pDM_DigTable->CurIGValue = DM_DIG_HIGH_PWR_IGI_LOWER_BOUND;
3238                         CurrentIGI=DM_DIG_HIGH_PWR_IGI_LOWER_BOUND;
3239                 }
3240         }
3241         if((pDM_Odm->SupportICType & ODM_RTL8723A) &&
3242                         IS_WIRELESS_MODE_G(pAdapter))
3243                 {
3244                         if(pHalData->UndecoratedSmoothedPWDB > 0x28)
3245                         {
3246                                 if(CurrentIGI < DM_DIG_Gmode_HIGH_PWR_IGI_LOWER_BOUND)
3247                                 {
3248                                         //pDM_DigTable->CurIGValue = DM_DIG_Gmode_HIGH_PWR_IGI_LOWER_BOUND;
3249                                         CurrentIGI = DM_DIG_Gmode_HIGH_PWR_IGI_LOWER_BOUND;
3250                                 }
3251                         }
3252                 }
3253 #if 0
3254         if((pDM_Odm->SupportICType & ODM_RTL8723A)&&(pMgntInfo->CustomerID = RT_CID_LENOVO_CHINA))
3255         {
3256                 OKCntAll = (curTxOkCnt+curRxOkCnt);
3257                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): CurIGValue(%#x)\n", CurrentIGI));
3258                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): UndecoratedSmoothedPWDB(%#x)\n", pHalData->UndecoratedSmoothedPWDB));
3259                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG(): OKCntAll(%#x)\n", OKCntAll));
3260                 //8723AS_VAU
3261                 if(pDM_Odm->SupportInterface==ODM_ITRF_USB)
3262                 {
3263                         if(pHalData->UndecoratedSmoothedPWDB < 12)
3264                         {
3265                                 if(CurrentIGI > DM_DIG_MIN_NIC)
3266                                 {
3267                                         if(OKCntAll >= 1500000)                  // >=6Mbps
3268                                                 CurrentIGI=0x1B;
3269                                         else if(OKCntAll >= 1000000)     //4Mbps
3270                                                 CurrentIGI=0x1A;
3271                                         else if(OKCntAll >= 500000)              //2Mbps
3272                                                 CurrentIGI=0x19;
3273                                         else if(OKCntAll >= 250000)             //1Mbps
3274                                                 CurrentIGI=0x18;
3275                                         else
3276                                         {
3277                                                 CurrentIGI=0x17;                //SCAN mode
3278                                         }
3279                                 }
3280                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, ODM_DBG_LOUD, ("Modify---->CurIGValue(%#x)\n", CurrentIGI));
3281                         }
3282                 }
3283         }
3284 #endif
3285 }
3286 #endif
3287
3288 #if (RTL8192D_SUPPORT==1)
3289         if(pDM_Odm->SupportICType == ODM_RTL8192D)
3290         {
3291                 //sherry  delete DualMacSmartConncurrent 20110517
3292                 if(*(pDM_Odm->pMacPhyMode) == ODM_DMSP)
3293                 {
3294                         ODM_Write_DIG_DMSP(pDM_Odm, (u1Byte)CurrentIGI);//ODM_Write_DIG_DMSP(pDM_Odm, pDM_DigTable->CurIGValue);
3295                         if(*(pDM_Odm->pbMasterOfDMSP))
3296                         {
3297                                 pDM_DigTable->bMediaConnect_0 = pDM_Odm->bLinked;
3298                                 pDM_DigTable->DIG_Dynamic_MIN_0 = DIG_Dynamic_MIN;
3299                         }
3300                         else
3301                         {
3302                                 pDM_DigTable->bMediaConnect_1 = pDM_Odm->bLinked;
3303                                 pDM_DigTable->DIG_Dynamic_MIN_1 = DIG_Dynamic_MIN;
3304                         }
3305                 }
3306                 else
3307                 {
3308                         ODM_Write_DIG(pDM_Odm, CurrentIGI);//ODM_Write_DIG(pDM_Odm, pDM_DigTable->CurIGValue);
3309                         if(*(pDM_Odm->pBandType) == ODM_BAND_5G)
3310                         {
3311                                 pDM_DigTable->bMediaConnect_0 = pDM_Odm->bLinked;
3312                                 pDM_DigTable->DIG_Dynamic_MIN_0 = DIG_Dynamic_MIN;
3313                         }
3314                         else
3315                         {
3316                                 pDM_DigTable->bMediaConnect_1 = pDM_Odm->bLinked;
3317                                 pDM_DigTable->DIG_Dynamic_MIN_1 = DIG_Dynamic_MIN;
3318                         }
3319                 }
3320         }
3321         else
3322 #endif
3323         {
3324                 if(pDM_Odm->bBtHsOperation)
3325                 {
3326                         if(pDM_Odm->bLinked)
3327                         {
3328                                 if(pDM_DigTable->BT30_CurIGI > (CurrentIGI))
3329                                 {
3330                                         ODM_Write_DIG(pDM_Odm, CurrentIGI);
3331
3332                                 }
3333                                 else
3334                                 {
3335                                         ODM_Write_DIG(pDM_Odm, pDM_DigTable->BT30_CurIGI);
3336                                 }
3337                                 pDM_DigTable->bMediaConnect_0 = pDM_Odm->bLinked;
3338                                 pDM_DigTable->DIG_Dynamic_MIN_0 = DIG_Dynamic_MIN;
3339                         }
3340                         else
3341                         {
3342                                 if(pDM_Odm->bLinkInProcess)
3343                                 {
3344                                         ODM_Write_DIG(pDM_Odm, 0x1c);
3345                                 }
3346                                 else if(pDM_Odm->bBtConnectProcess)
3347                                 {
3348                                         ODM_Write_DIG(pDM_Odm, 0x28);
3349                                 }
3350                                 else
3351                                 {
3352                                         ODM_Write_DIG(pDM_Odm, pDM_DigTable->BT30_CurIGI);//ODM_Write_DIG(pDM_Odm, pDM_DigTable->CurIGValue);
3353                                 }
3354                         }
3355                 }
3356                 else            // BT is not using
3357                 {
3358                         ODM_Write_DIG(pDM_Odm, CurrentIGI);//ODM_Write_DIG(pDM_Odm, pDM_DigTable->CurIGValue);
3359                         pDM_DigTable->bMediaConnect_0 = pDM_Odm->bLinked;
3360                         pDM_DigTable->DIG_Dynamic_MIN_0 = DIG_Dynamic_MIN;
3361                 }
3362         }
3363 }
3364
3365
3366 BOOLEAN
3367 odm_DigAbort(
3368         IN              PDM_ODM_T               pDM_Odm
3369         )
3370 {
3371 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
3372 // This should be moved out of OUTSRC
3373         PADAPTER                pAdapter        = pDM_Odm->Adapter;
3374         pRXHP_T                 pRX_HP_Table  = &pDM_Odm->DM_RXHP_Table;
3375
3376 #if OS_WIN_FROM_WIN7(OS_VERSION)
3377         if(IsAPModeExist( pAdapter) && pAdapter->bInHctTest)
3378         {
3379                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() Return: Is AP mode or In HCT Test \n"));
3380                 return  TRUE;
3381         }
3382 #endif
3383
3384         if(pRX_HP_Table->RXHP_flag == 1)
3385         {
3386                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_DIG() Return: In RXHP Operation \n"));
3387                 return  TRUE;
3388         }
3389
3390         return  FALSE;
3391 #else   // For Other team any special case for DIG?
3392         return  FALSE;
3393 #endif
3394
3395
3396 }
3397
3398 //3============================================================
3399 //3 FASLE ALARM CHECK
3400 //3============================================================
3401
3402 VOID
3403 odm_FalseAlarmCounterStatistics(
3404         IN              PDM_ODM_T               pDM_Odm
3405         )
3406 {
3407         u4Byte ret_value;
3408         PFALSE_ALARM_STATISTICS FalseAlmCnt = &(pDM_Odm->FalseAlmCnt);
3409
3410 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
3411         prtl8192cd_priv priv            = pDM_Odm->priv;
3412         if( (priv->auto_channel != 0) && (priv->auto_channel != 2) )
3413                 return;
3414 #endif
3415
3416 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
3417         if((pDM_Odm->SupportICType == ODM_RTL8192D) &&
3418                 (*(pDM_Odm->pMacPhyMode)==ODM_DMSP)&&    ////modify by Guo.Mingzhi 2011-12-29
3419                 (!(*(pDM_Odm->pbMasterOfDMSP))))
3420         {
3421                 odm_FalseAlarmCounterStatistics_ForSlaveOfDMSP(pDM_Odm);
3422                 return;
3423         }
3424 #endif
3425
3426         if(!(pDM_Odm->SupportAbility & ODM_BB_FA_CNT))
3427                 return;
3428
3429         if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES)
3430         {
3431
3432         //hold ofdm counter
3433                 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_HOLDC_11N, BIT31, 1); //hold page C counter
3434                 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT31, 1); //hold page D counter
3435
3436                 ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE1_11N, bMaskDWord);
3437                 FalseAlmCnt->Cnt_Fast_Fsync = (ret_value&0xffff);
3438                 FalseAlmCnt->Cnt_SB_Search_fail = ((ret_value&0xffff0000)>>16);
3439                 ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE2_11N, bMaskDWord);
3440                 FalseAlmCnt->Cnt_OFDM_CCA = (ret_value&0xffff);
3441                 FalseAlmCnt->Cnt_Parity_Fail = ((ret_value&0xffff0000)>>16);
3442                 ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE3_11N, bMaskDWord);
3443                 FalseAlmCnt->Cnt_Rate_Illegal = (ret_value&0xffff);
3444                 FalseAlmCnt->Cnt_Crc8_fail = ((ret_value&0xffff0000)>>16);
3445                 ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_TYPE4_11N, bMaskDWord);
3446                 FalseAlmCnt->Cnt_Mcs_fail = (ret_value&0xffff);
3447
3448                 FalseAlmCnt->Cnt_Ofdm_fail =    FalseAlmCnt->Cnt_Parity_Fail + FalseAlmCnt->Cnt_Rate_Illegal +
3449                                                                         FalseAlmCnt->Cnt_Crc8_fail + FalseAlmCnt->Cnt_Mcs_fail +
3450                                                                         FalseAlmCnt->Cnt_Fast_Fsync + FalseAlmCnt->Cnt_SB_Search_fail;
3451
3452 #if (RTL8188E_SUPPORT==1)
3453                 if((pDM_Odm->SupportICType == ODM_RTL8188E)||(pDM_Odm->SupportICType == ODM_RTL8192E))
3454                 {
3455                                 ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_SC_CNT_11N, bMaskDWord);
3456                         FalseAlmCnt->Cnt_BW_LSC = (ret_value&0xffff);
3457                         FalseAlmCnt->Cnt_BW_USC = ((ret_value&0xffff0000)>>16);
3458                 }
3459 #endif
3460
3461 #if (RTL8192D_SUPPORT==1)
3462                 if(pDM_Odm->SupportICType == ODM_RTL8192D)
3463                 {
3464                         odm_GetCCKFalseAlarm_92D(pDM_Odm);
3465                 }
3466                 else
3467 #endif
3468                 {
3469                         //hold cck counter
3470                                 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT12, 1);
3471                                 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT14, 1);
3472
3473                                 ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_FA_LSB_11N, bMaskByte0);
3474                         FalseAlmCnt->Cnt_Cck_fail = ret_value;
3475                                 ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_FA_MSB_11N, bMaskByte3);
3476                         FalseAlmCnt->Cnt_Cck_fail +=  (ret_value& 0xff)<<8;
3477
3478                                 ret_value = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_CCA_CNT_11N, bMaskDWord);
3479                         FalseAlmCnt->Cnt_CCK_CCA = ((ret_value&0xFF)<<8) |((ret_value&0xFF00)>>8);
3480                 }
3481
3482                 FalseAlmCnt->Cnt_all = (        FalseAlmCnt->Cnt_Fast_Fsync +
3483                                                         FalseAlmCnt->Cnt_SB_Search_fail +
3484                                                         FalseAlmCnt->Cnt_Parity_Fail +
3485                                                         FalseAlmCnt->Cnt_Rate_Illegal +
3486                                                         FalseAlmCnt->Cnt_Crc8_fail +
3487                                                         FalseAlmCnt->Cnt_Mcs_fail +
3488                                                         FalseAlmCnt->Cnt_Cck_fail);
3489
3490                 FalseAlmCnt->Cnt_CCA_all = FalseAlmCnt->Cnt_OFDM_CCA + FalseAlmCnt->Cnt_CCK_CCA;
3491
3492 #if (RTL8192C_SUPPORT==1)
3493                 if(pDM_Odm->SupportICType == ODM_RTL8192C)
3494                         odm_ResetFACounter_92C(pDM_Odm);
3495 #endif
3496
3497 #if (RTL8192D_SUPPORT==1)
3498                 if(pDM_Odm->SupportICType == ODM_RTL8192D)
3499                         odm_ResetFACounter_92D(pDM_Odm);
3500 #endif
3501
3502                 if(pDM_Odm->SupportICType >=ODM_RTL8723A)
3503                 {
3504                         //reset false alarm counter registers
3505                                 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTC_11N, BIT31, 1);
3506                                 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTC_11N, BIT31, 0);
3507                                 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT27, 1);
3508                                 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT27, 0);
3509                         //update ofdm counter
3510                                 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_HOLDC_11N, BIT31, 0); //update page C counter
3511                                 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RSTD_11N, BIT31, 0); //update page D counter
3512
3513                         //reset CCK CCA counter
3514                                 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT13|BIT12, 0);
3515                                 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT13|BIT12, 2);
3516                         //reset CCK FA counter
3517                                 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT15|BIT14, 0);
3518                                 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11N, BIT15|BIT14, 2);
3519                 }
3520
3521                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Enter odm_FalseAlarmCounterStatistics\n"));
3522                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Fast_Fsync=%d, Cnt_SB_Search_fail=%d\n",
3523                         FalseAlmCnt->Cnt_Fast_Fsync, FalseAlmCnt->Cnt_SB_Search_fail));
3524                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Parity_Fail=%d, Cnt_Rate_Illegal=%d\n",
3525                         FalseAlmCnt->Cnt_Parity_Fail, FalseAlmCnt->Cnt_Rate_Illegal));
3526                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Crc8_fail=%d, Cnt_Mcs_fail=%d\n",
3527                         FalseAlmCnt->Cnt_Crc8_fail, FalseAlmCnt->Cnt_Mcs_fail));
3528         }
3529         else if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)
3530         {
3531                 u4Byte CCKenable;
3532                 //read OFDM FA counter
3533                 FalseAlmCnt->Cnt_Ofdm_fail = ODM_GetBBReg(pDM_Odm, ODM_REG_OFDM_FA_11AC, bMaskLWord);
3534                 FalseAlmCnt->Cnt_Cck_fail = ODM_GetBBReg(pDM_Odm, ODM_REG_CCK_FA_11AC, bMaskLWord);
3535
3536                 CCKenable =  ODM_GetBBReg(pDM_Odm, ODM_REG_BB_RX_PATH_11AC, BIT28);
3537                 if(CCKenable)//if(*pDM_Odm->pBandType == ODM_BAND_2_4G)
3538                         FalseAlmCnt->Cnt_all = FalseAlmCnt->Cnt_Ofdm_fail + FalseAlmCnt->Cnt_Cck_fail;
3539                 else
3540                         FalseAlmCnt->Cnt_all = FalseAlmCnt->Cnt_Ofdm_fail;
3541
3542                 // reset OFDM FA coutner
3543                 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RST_11AC, BIT17, 1);
3544                 ODM_SetBBReg(pDM_Odm, ODM_REG_OFDM_FA_RST_11AC, BIT17, 0);
3545                 // reset CCK FA counter
3546                 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11AC, BIT15, 0);
3547                 ODM_SetBBReg(pDM_Odm, ODM_REG_CCK_FA_RST_11AC, BIT15, 1);
3548         }
3549         ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Cck_fail=%d\n",       FalseAlmCnt->Cnt_Cck_fail));
3550         ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Cnt_Ofdm_fail=%d\n",      FalseAlmCnt->Cnt_Ofdm_fail));
3551         ODM_RT_TRACE(pDM_Odm,ODM_COMP_FA_CNT, ODM_DBG_LOUD, ("Total False Alarm=%d\n",  FalseAlmCnt->Cnt_all));
3552 }
3553
3554 //3============================================================
3555 //3 CCK Packet Detect Threshold
3556 //3============================================================
3557
3558 VOID
3559 odm_CCKPacketDetectionThresh(
3560         IN              PDM_ODM_T               pDM_Odm
3561         )
3562 {
3563
3564         u1Byte  CurCCK_CCAThres;
3565         PFALSE_ALARM_STATISTICS FalseAlmCnt = &(pDM_Odm->FalseAlmCnt);
3566
3567 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
3568 //modify by Guo.Mingzhi 2011-12-29
3569         if (pDM_Odm->bDualMacSmartConcurrent == TRUE)
3570 //      if (pDM_Odm->bDualMacSmartConcurrent == FALSE)
3571                 return;
3572
3573         if(pDM_Odm->bBtHsOperation)
3574         {
3575                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, ODM_DBG_LOUD, ("odm_CCKPacketDetectionThresh() write 0xcd for BT HS mode!!\n"));
3576                 ODM_Write_CCK_CCA_Thres(pDM_Odm, 0xcd);
3577                 return;
3578         }
3579
3580 #endif
3581
3582         if(!(pDM_Odm->SupportAbility & (ODM_BB_CCK_PD|ODM_BB_FA_CNT)))
3583                 return;
3584
3585         if(pDM_Odm->ExtLNA)
3586                 return;
3587
3588         if(pDM_Odm->bLinked)
3589         {
3590                 if(pDM_Odm->RSSI_Min > 25)
3591                         CurCCK_CCAThres = 0xcd;
3592                 else if((pDM_Odm->RSSI_Min <= 25) && (pDM_Odm->RSSI_Min > 10))
3593                         CurCCK_CCAThres = 0x83;
3594                 else
3595                 {
3596                         if(FalseAlmCnt->Cnt_Cck_fail > 1000)
3597                                 CurCCK_CCAThres = 0x83;
3598                         else
3599                                 CurCCK_CCAThres = 0x40;
3600                 }
3601         }
3602         else
3603         {
3604                 if(FalseAlmCnt->Cnt_Cck_fail > 1000)
3605                         CurCCK_CCAThres = 0x83;
3606                 else
3607                         CurCCK_CCAThres = 0x40;
3608         }
3609
3610 #if (RTL8192D_SUPPORT==1)
3611         if((pDM_Odm->SupportICType == ODM_RTL8192D)&&(*pDM_Odm->pBandType == ODM_BAND_2_4G))
3612                 ODM_Write_CCK_CCA_Thres_92D(pDM_Odm, CurCCK_CCAThres);
3613         else
3614 #endif
3615                 ODM_Write_CCK_CCA_Thres(pDM_Odm, CurCCK_CCAThres);
3616 }
3617
3618 VOID
3619 ODM_Write_CCK_CCA_Thres(
3620         IN      PDM_ODM_T               pDM_Odm,
3621         IN      u1Byte                  CurCCK_CCAThres
3622         )
3623 {
3624         pDIG_T  pDM_DigTable = &pDM_Odm->DM_DigTable;
3625
3626         if(pDM_DigTable->CurCCK_CCAThres!=CurCCK_CCAThres)              //modify by Guo.Mingzhi 2012-01-03
3627         {
3628                 ODM_Write1Byte(pDM_Odm, ODM_REG(CCK_CCA,pDM_Odm), CurCCK_CCAThres);
3629         }
3630         pDM_DigTable->PreCCK_CCAThres = pDM_DigTable->CurCCK_CCAThres;
3631         pDM_DigTable->CurCCK_CCAThres = CurCCK_CCAThres;
3632
3633 }
3634
3635 //3============================================================
3636 //3 BB Power Save
3637 //3============================================================
3638 VOID
3639 odm_DynamicBBPowerSavingInit(
3640         IN              PDM_ODM_T               pDM_Odm
3641         )
3642 {
3643         pPS_T   pDM_PSTable = &pDM_Odm->DM_PSTable;
3644
3645         pDM_PSTable->PreCCAState = CCA_MAX;
3646         pDM_PSTable->CurCCAState = CCA_MAX;
3647         pDM_PSTable->PreRFState = RF_MAX;
3648         pDM_PSTable->CurRFState = RF_MAX;
3649         pDM_PSTable->Rssi_val_min = 0;
3650         pDM_PSTable->initialize = 0;
3651 }
3652
3653
3654 VOID
3655 odm_DynamicBBPowerSaving(
3656         IN              PDM_ODM_T               pDM_Odm
3657         )
3658 {
3659 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
3660
3661         if (pDM_Odm->SupportICType != ODM_RTL8723A)
3662                 return;
3663         if(!(pDM_Odm->SupportAbility & ODM_BB_PWR_SAVE))
3664                 return;
3665         if(!(pDM_Odm->SupportPlatform & (ODM_WIN|ODM_CE)))
3666                 return;
3667
3668         //1 2.Power Saving for 92C
3669         if((pDM_Odm->SupportICType == ODM_RTL8192C) &&(pDM_Odm->RFType == ODM_2T2R))
3670         {
3671                 odm_1R_CCA(pDM_Odm);
3672         }
3673
3674         // 20100628 Joseph: Turn off BB power save for 88CE because it makesthroughput unstable.
3675         // 20100831 Joseph: Turn ON BB power save again after modifying AGC delay from 900ns ot 600ns.
3676         //1 3.Power Saving for 88C
3677         else
3678         {
3679                 ODM_RF_Saving(pDM_Odm, FALSE);
3680         }
3681 #endif  // #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
3682
3683 }
3684
3685 VOID
3686 odm_1R_CCA(
3687         IN      PDM_ODM_T       pDM_Odm
3688         )
3689 {
3690         pPS_T   pDM_PSTable = &pDM_Odm->DM_PSTable;
3691
3692         if(pDM_Odm->RSSI_Min!= 0xFF)
3693         {
3694
3695                 if(pDM_PSTable->PreCCAState == CCA_2R)
3696                 {
3697                         if(pDM_Odm->RSSI_Min >= 35)
3698                                 pDM_PSTable->CurCCAState = CCA_1R;
3699                         else
3700                                 pDM_PSTable->CurCCAState = CCA_2R;
3701
3702                 }
3703                 else{
3704                         if(pDM_Odm->RSSI_Min <= 30)
3705                                 pDM_PSTable->CurCCAState = CCA_2R;
3706                         else
3707                                 pDM_PSTable->CurCCAState = CCA_1R;
3708                 }
3709         }
3710         else{
3711                 pDM_PSTable->CurCCAState=CCA_MAX;
3712         }
3713
3714         if(pDM_PSTable->PreCCAState != pDM_PSTable->CurCCAState)
3715         {
3716                 if(pDM_PSTable->CurCCAState == CCA_1R)
3717                 {
3718                         if(  pDM_Odm->RFType ==ODM_2T2R )
3719                         {
3720                                 ODM_SetBBReg(pDM_Odm, 0xc04  , bMaskByte0, 0x13);
3721                                 //PHY_SetBBReg(pAdapter, 0xe70, bMaskByte3, 0x20);
3722                         }
3723                         else
3724                         {
3725                                 ODM_SetBBReg(pDM_Odm, 0xc04  , bMaskByte0, 0x23);
3726                                 //PHY_SetBBReg(pAdapter, 0xe70, 0x7fc00000, 0x10c); // Set RegE70[30:22] = 9b'100001100
3727                         }
3728                 }
3729                 else
3730                 {
3731                         ODM_SetBBReg(pDM_Odm, 0xc04  , bMaskByte0, 0x33);
3732                         //PHY_SetBBReg(pAdapter,0xe70, bMaskByte3, 0x63);
3733                 }
3734                 pDM_PSTable->PreCCAState = pDM_PSTable->CurCCAState;
3735         }
3736         //ODM_RT_TRACE(pDM_Odm, COMP_BB_POWERSAVING, DBG_LOUD, ("CCAStage = %s\n",(pDM_PSTable->CurCCAState==0)?"1RCCA":"2RCCA"));
3737 }
3738
3739 void
3740 ODM_RF_Saving(
3741         IN      PDM_ODM_T       pDM_Odm,
3742         IN      u1Byte          bForceInNormal
3743         )
3744 {
3745 #if (DM_ODM_SUPPORT_TYPE != ODM_AP)
3746         pPS_T   pDM_PSTable = &pDM_Odm->DM_PSTable;
3747         u1Byte  Rssi_Up_bound = 30 ;
3748         u1Byte  Rssi_Low_bound = 25;
3749         #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
3750         if(pDM_Odm->PatchID == 40 ) //RT_CID_819x_FUNAI_TV
3751         {
3752                 Rssi_Up_bound = 50 ;
3753                 Rssi_Low_bound = 45;
3754         }
3755         #endif
3756         if(pDM_PSTable->initialize == 0){
3757
3758                 pDM_PSTable->Reg874 = (ODM_GetBBReg(pDM_Odm, 0x874, bMaskDWord)&0x1CC000)>>14;
3759                 pDM_PSTable->RegC70 = (ODM_GetBBReg(pDM_Odm, 0xc70, bMaskDWord)&BIT3)>>3;
3760                 pDM_PSTable->Reg85C = (ODM_GetBBReg(pDM_Odm, 0x85c, bMaskDWord)&0xFF000000)>>24;
3761                 pDM_PSTable->RegA74 = (ODM_GetBBReg(pDM_Odm, 0xa74, bMaskDWord)&0xF000)>>12;
3762                 //Reg818 = PHY_QueryBBReg(pAdapter, 0x818, bMaskDWord);
3763                 pDM_PSTable->initialize = 1;
3764         }
3765
3766         if(!bForceInNormal)
3767         {
3768                 if(pDM_Odm->RSSI_Min != 0xFF)
3769                 {
3770                         if(pDM_PSTable->PreRFState == RF_Normal)
3771                         {
3772                                 if(pDM_Odm->RSSI_Min >= Rssi_Up_bound)
3773                                         pDM_PSTable->CurRFState = RF_Save;
3774                                 else
3775                                         pDM_PSTable->CurRFState = RF_Normal;
3776                         }
3777                         else{
3778                                 if(pDM_Odm->RSSI_Min <= Rssi_Low_bound)
3779                                         pDM_PSTable->CurRFState = RF_Normal;
3780                                 else
3781                                         pDM_PSTable->CurRFState = RF_Save;
3782                         }
3783                 }
3784                 else
3785                         pDM_PSTable->CurRFState=RF_MAX;
3786         }
3787         else
3788         {
3789                 pDM_PSTable->CurRFState = RF_Normal;
3790         }
3791
3792         if(pDM_PSTable->PreRFState != pDM_PSTable->CurRFState)
3793         {
3794                 if(pDM_PSTable->CurRFState == RF_Save)
3795                 {
3796                         // <tynli_note> 8723 RSSI report will be wrong. Set 0x874[5]=1 when enter BB power saving mode.
3797                         // Suggested by SD3 Yu-Nan. 2011.01.20.
3798                         if(pDM_Odm->SupportICType == ODM_RTL8723A)
3799                         {
3800                                 ODM_SetBBReg(pDM_Odm, 0x874  , BIT5, 0x1); //Reg874[5]=1b'1
3801                         }
3802                         ODM_SetBBReg(pDM_Odm, 0x874  , 0x1C0000, 0x2); //Reg874[20:18]=3'b010
3803                         ODM_SetBBReg(pDM_Odm, 0xc70, BIT3, 0); //RegC70[3]=1'b0
3804                         ODM_SetBBReg(pDM_Odm, 0x85c, 0xFF000000, 0x63); //Reg85C[31:24]=0x63
3805                         ODM_SetBBReg(pDM_Odm, 0x874, 0xC000, 0x2); //Reg874[15:14]=2'b10
3806                         ODM_SetBBReg(pDM_Odm, 0xa74, 0xF000, 0x3); //RegA75[7:4]=0x3
3807                         ODM_SetBBReg(pDM_Odm, 0x818, BIT28, 0x0); //Reg818[28]=1'b0
3808                         ODM_SetBBReg(pDM_Odm, 0x818, BIT28, 0x1); //Reg818[28]=1'b1
3809                         //ODM_RT_TRACE(pDM_Odm, COMP_BB_POWERSAVING, DBG_LOUD, (" RF_Save"));
3810                 }
3811                 else
3812                 {
3813                         ODM_SetBBReg(pDM_Odm, 0x874  , 0x1CC000, pDM_PSTable->Reg874);
3814                         ODM_SetBBReg(pDM_Odm, 0xc70, BIT3, pDM_PSTable->RegC70);
3815                         ODM_SetBBReg(pDM_Odm, 0x85c, 0xFF000000, pDM_PSTable->Reg85C);
3816                         ODM_SetBBReg(pDM_Odm, 0xa74, 0xF000, pDM_PSTable->RegA74);
3817                         ODM_SetBBReg(pDM_Odm,0x818, BIT28, 0x0);
3818
3819                         if(pDM_Odm->SupportICType == ODM_RTL8723A)
3820                         {
3821                                 ODM_SetBBReg(pDM_Odm,0x874  , BIT5, 0x0); //Reg874[5]=1b'0
3822                         }
3823                         //ODM_RT_TRACE(pDM_Odm, COMP_BB_POWERSAVING, DBG_LOUD, (" RF_Normal"));
3824                 }
3825                 pDM_PSTable->PreRFState =pDM_PSTable->CurRFState;
3826         }
3827 #endif
3828 }
3829
3830
3831 //3============================================================
3832 //3 RATR MASK
3833 //3============================================================
3834 //3============================================================
3835 //3 Rate Adaptive
3836 //3============================================================
3837
3838 VOID
3839 odm_RateAdaptiveMaskInit(
3840         IN      PDM_ODM_T       pDM_Odm
3841         )
3842 {
3843         PODM_RATE_ADAPTIVE      pOdmRA = &pDM_Odm->RateAdaptive;
3844
3845 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
3846         PMGNT_INFO              pMgntInfo = &pDM_Odm->Adapter->MgntInfo;
3847         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pDM_Odm->Adapter);
3848
3849         pMgntInfo->Ratr_State = DM_RATR_STA_INIT;
3850
3851         if (pMgntInfo->DM_Type == DM_Type_ByDriver)
3852                 pHalData->bUseRAMask = TRUE;
3853         else
3854                 pHalData->bUseRAMask = FALSE;
3855
3856 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
3857         pOdmRA->Type = DM_Type_ByDriver;
3858         if (pOdmRA->Type == DM_Type_ByDriver)
3859                 pDM_Odm->bUseRAMask = _TRUE;
3860         else
3861                 pDM_Odm->bUseRAMask = _FALSE;
3862 #endif
3863
3864         pOdmRA->RATRState = DM_RATR_STA_INIT;
3865         pOdmRA->LdpcThres = 35;
3866         pOdmRA->bUseLdpc = FALSE;
3867         pOdmRA->HighRSSIThresh = 50;
3868         pOdmRA->LowRSSIThresh = 20;
3869 }
3870
3871 #if (DM_ODM_SUPPORT_TYPE & ODM_WIN)
3872 VOID
3873 ODM_RateAdaptiveStateApInit(
3874         IN      PADAPTER                Adapter ,
3875         IN      PRT_WLAN_STA    pEntry
3876         )
3877 {
3878         pEntry->Ratr_State = DM_RATR_STA_INIT;
3879 }
3880 #endif
3881
3882 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
3883 u4Byte ODM_Get_Rate_Bitmap(
3884         IN      PDM_ODM_T       pDM_Odm,
3885         IN      u4Byte          macid,
3886         IN      u4Byte          ra_mask,
3887         IN      u1Byte          rssi_level)
3888 {
3889         PSTA_INFO_T     pEntry;
3890         u4Byte  rate_bitmap = 0;
3891         u1Byte  WirelessMode;
3892         //u1Byte        WirelessMode =*(pDM_Odm->pWirelessMode);
3893
3894
3895         pEntry = pDM_Odm->pODM_StaInfo[macid];
3896         if(!IS_STA_VALID(pEntry))
3897                 return ra_mask;
3898
3899         WirelessMode = pEntry->wireless_mode;
3900
3901         switch(WirelessMode)
3902         {
3903                 case ODM_WM_B:
3904                         if(ra_mask & 0x0000000c)                //11M or 5.5M enable
3905                                 rate_bitmap = 0x0000000d;
3906                         else
3907                                 rate_bitmap = 0x0000000f;
3908                         break;
3909
3910                 case (ODM_WM_G):
3911                 case (ODM_WM_A):
3912                         if(rssi_level == DM_RATR_STA_HIGH)
3913                                 rate_bitmap = 0x00000f00;
3914                         else
3915                                 rate_bitmap = 0x00000ff0;
3916                         break;
3917
3918                 case (ODM_WM_B|ODM_WM_G):
3919                         if(rssi_level == DM_RATR_STA_HIGH)
3920                                 rate_bitmap = 0x00000f00;
3921                         else if(rssi_level == DM_RATR_STA_MIDDLE)
3922                                 rate_bitmap = 0x00000ff0;
3923                         else
3924                                 rate_bitmap = 0x00000ff5;
3925                         break;
3926
3927                 case (ODM_WM_B|ODM_WM_G|ODM_WM_N24G)    :
3928                 case (ODM_WM_B|ODM_WM_N24G)     :
3929                 case (ODM_WM_G|ODM_WM_N24G)     :
3930                 case (ODM_WM_A|ODM_WM_N5G)      :
3931                         {
3932                                 if (    pDM_Odm->RFType == ODM_1T2R ||pDM_Odm->RFType == ODM_1T1R)
3933                                 {
3934                                         if(rssi_level == DM_RATR_STA_HIGH)
3935                                         {
3936                                                 rate_bitmap = 0x000f0000;
3937                                         }
3938                                         else if(rssi_level == DM_RATR_STA_MIDDLE)
3939                                         {
3940                                                 rate_bitmap = 0x000ff000;
3941                                         }
3942                                         else{
3943                                                 if (*(pDM_Odm->pBandWidth) == ODM_BW40M)
3944                                                         rate_bitmap = 0x000ff015;
3945                                                 else
3946                                                         rate_bitmap = 0x000ff005;
3947                                         }
3948                                 }
3949                                 else
3950                                 {
3951                                         if(rssi_level == DM_RATR_STA_HIGH)
3952                                         {
3953                                                 rate_bitmap = 0x0f8f0000;
3954                                         }
3955                                         else if(rssi_level == DM_RATR_STA_MIDDLE)
3956                                         {
3957                                                 rate_bitmap = 0x0f8ff000;
3958                                         }
3959                                         else
3960                                         {
3961                                                 if (*(pDM_Odm->pBandWidth) == ODM_BW40M)
3962                                                         rate_bitmap = 0x0f8ff015;
3963                                                 else
3964                                                         rate_bitmap = 0x0f8ff005;
3965                                         }
3966                                 }
3967                         }
3968                         break;
3969
3970                 case (ODM_WM_AC|ODM_WM_G):
3971                         if(rssi_level == 1)
3972                                 rate_bitmap = 0xfc3f0000;
3973                         else if(rssi_level == 2)
3974                                 rate_bitmap = 0xfffff000;
3975                         else
3976                                 rate_bitmap = 0xffffffff;
3977                         break;
3978
3979                 case (ODM_WM_AC|ODM_WM_A):
3980
3981                         if (pDM_Odm->RFType == RF_1T1R)
3982                         {
3983                                 if(rssi_level == 1)                             // add by Gary for ac-series
3984                                         rate_bitmap = 0x003f8000;
3985                                 else if (rssi_level == 2)
3986                                         rate_bitmap = 0x003ff000;
3987                                 else
3988                                         rate_bitmap = 0x003ff010;
3989                         }
3990                         else
3991                         {
3992                                 if(rssi_level == 1)                             // add by Gary for ac-series
3993                                         rate_bitmap = 0xfe3f8000;       // VHT 2SS MCS3~9
3994                                 else if (rssi_level == 2)
3995                                         rate_bitmap = 0xfffff000;       // VHT 2SS MCS0~9
3996                                 else
3997                                         rate_bitmap = 0xfffff010;       // All
3998                         }
3999                         break;
4000
4001                 default:
4002                         if(pDM_Odm->RFType == RF_1T2R)
4003                                 rate_bitmap = 0x000fffff;
4004                         else
4005                                 rate_bitmap = 0x0fffffff;
4006                         break;
4007
4008         }
4009
4010         //printk("%s ==> rssi_level:0x%02x, WirelessMode:0x%02x, rate_bitmap:0x%08x \n",__FUNCTION__,rssi_level,WirelessMode,rate_bitmap);
4011         ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, (" ==> rssi_level:0x%02x, WirelessMode:0x%02x, rate_bitmap:0x%08x \n",rssi_level,WirelessMode,rate_bitmap));
4012
4013         return (ra_mask&rate_bitmap);
4014
4015 }
4016 #endif
4017
4018
4019 VOID
4020 odm_RefreshBasicRateMask(
4021         IN              PDM_ODM_T               pDM_Odm
4022         )
4023 {
4024 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
4025         PADAPTER                Adapter  =  pDM_Odm->Adapter;
4026         static u1Byte           Stage = 0;
4027         u1Byte                  CurStage = 0;
4028         OCTET_STRING    osRateSet;
4029         PMGNT_INFO              pMgntInfo = GetDefaultMgntInfo(Adapter);
4030         u1Byte                  RateSet[5] = {MGN_1M, MGN_2M, MGN_5_5M, MGN_11M, MGN_6M};
4031
4032         if(pDM_Odm->SupportICType != ODM_RTL8812 && pDM_Odm->SupportICType != ODM_RTL8821 )
4033                 return;
4034
4035         if(pDM_Odm->bLinked == FALSE)   // unlink Default port information
4036                 CurStage = 0;
4037         else if(pDM_Odm->RSSI_Min < 40) // link RSSI  < 40%
4038                 CurStage = 1;
4039         else if(pDM_Odm->RSSI_Min > 45) // link RSSI > 45%
4040                 CurStage = 3;
4041         else
4042                 CurStage = 2;                                   // link  25% <= RSSI <= 30%
4043
4044         if(CurStage != Stage)
4045         {
4046                 if(CurStage == 1)
4047                 {
4048                         FillOctetString(osRateSet, RateSet, 5);
4049                         FilterSupportRate(pMgntInfo->mBrates, &osRateSet, FALSE);
4050                         Adapter->HalFunc.SetHwRegHandler(Adapter, HW_VAR_BASIC_RATE, (pu1Byte)&osRateSet);
4051                 }
4052                 else if(CurStage == 3 && (Stage == 1 || Stage == 2))
4053                 {
4054                         Adapter->HalFunc.SetHwRegHandler( Adapter, HW_VAR_BASIC_RATE, (pu1Byte)(&pMgntInfo->mBrates) );
4055                 }
4056         }
4057
4058         Stage = CurStage;
4059 #endif
4060 }
4061
4062 /*-----------------------------------------------------------------------------
4063  * Function:    odm_RefreshRateAdaptiveMask()
4064  *
4065  * Overview:    Update rate table mask according to rssi
4066  *
4067  * Input:               NONE
4068  *
4069  * Output:              NONE
4070  *
4071  * Return:              NONE
4072  *
4073  * Revised History:
4074  *      When            Who             Remark
4075  *      05/27/2009      hpfan   Create Version 0.
4076  *
4077  *---------------------------------------------------------------------------*/
4078 VOID
4079 odm_RefreshRateAdaptiveMask(
4080         IN              PDM_ODM_T               pDM_Odm
4081         )
4082 {
4083
4084         ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_TRACE, ("odm_RefreshRateAdaptiveMask()---------->\n"));
4085         if (!(pDM_Odm->SupportAbility & ODM_BB_RA_MASK))
4086         {
4087                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_TRACE, ("odm_RefreshRateAdaptiveMask(): Return cos not supported\n"));
4088                 return;
4089         }
4090         //
4091         // 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate
4092         // at the same time. In the stage2/3, we need to prive universal interface and merge all
4093         // HW dynamic mechanism.
4094         //
4095         switch  (pDM_Odm->SupportPlatform)
4096         {
4097                 case    ODM_WIN:
4098                         odm_RefreshRateAdaptiveMaskMP(pDM_Odm);
4099                         break;
4100
4101                 case    ODM_CE:
4102                         odm_RefreshRateAdaptiveMaskCE(pDM_Odm);
4103                         break;
4104
4105                 case    ODM_AP:
4106                 case    ODM_ADSL:
4107                         odm_RefreshRateAdaptiveMaskAPADSL(pDM_Odm);
4108                         break;
4109         }
4110
4111 }
4112
4113 VOID
4114 odm_RefreshRateAdaptiveMaskMP(
4115         IN              PDM_ODM_T               pDM_Odm
4116         )
4117 {
4118 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
4119         PADAPTER                                pAdapter         =  pDM_Odm->Adapter;
4120         PADAPTER                                pTargetAdapter = NULL;
4121         HAL_DATA_TYPE                   *pHalData = GET_HAL_DATA(pAdapter);
4122         PMGNT_INFO                              pMgntInfo = GetDefaultMgntInfo(pAdapter);
4123         PODM_RATE_ADAPTIVE              pRA = &pDM_Odm->RateAdaptive;
4124
4125         if(pAdapter->bDriverStopped)
4126         {
4127                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_TRACE, ("<---- odm_RefreshRateAdaptiveMask(): driver is going to unload\n"));
4128                 return;
4129         }
4130
4131         if(!pHalData->bUseRAMask)
4132         {
4133                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("<---- odm_RefreshRateAdaptiveMask(): driver does not control rate adaptive mask\n"));
4134                 return;
4135         }
4136
4137         // if default port is connected, update RA table for default port (infrastructure mode only)
4138         if(pMgntInfo->mAssoc && (!ACTING_AS_AP(pAdapter)))
4139         {
4140
4141                 if(pHalData->UndecoratedSmoothedPWDB < pRA->LdpcThres)
4142                 {
4143                         pRA->bUseLdpc = TRUE;
4144                         pRA->bLowerRtsRate = TRUE;
4145                         if((pDM_Odm->SupportICType == ODM_RTL8821) && (pDM_Odm->CutVersion == ODM_CUT_A))
4146                                 MgntSet_TX_LDPC(pAdapter,0,TRUE);
4147                         //DbgPrint("RSSI=%d, bUseLdpc = TRUE\n", pHalData->UndecoratedSmoothedPWDB);
4148                 }
4149                 else if(pHalData->UndecoratedSmoothedPWDB > (pRA->LdpcThres-5))
4150                 {
4151                         pRA->bUseLdpc = FALSE;
4152                         pRA->bLowerRtsRate = FALSE;
4153                         if((pDM_Odm->SupportICType == ODM_RTL8821) && (pDM_Odm->CutVersion == ODM_CUT_A))
4154                                 MgntSet_TX_LDPC(pAdapter,0,FALSE);
4155                         //DbgPrint("RSSI=%d, bUseLdpc = FALSE\n", pHalData->UndecoratedSmoothedPWDB);
4156                 }
4157
4158                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("odm_RefreshRateAdaptiveMask(): Infrasture Mode\n"));
4159                 if( ODM_RAStateCheck(pDM_Odm, pHalData->UndecoratedSmoothedPWDB, pMgntInfo->bSetTXPowerTrainingByOid, &pMgntInfo->Ratr_State) )
4160                 {
4161                         ODM_PRINT_ADDR(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Target AP addr : "), pMgntInfo->Bssid);
4162                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI:%d, RSSI_LEVEL:%d\n", pHalData->UndecoratedSmoothedPWDB, pMgntInfo->Ratr_State));
4163                         pAdapter->HalFunc.UpdateHalRAMaskHandler(pAdapter, pMgntInfo->mMacId, NULL, pMgntInfo->Ratr_State);
4164                 }
4165         }
4166
4167         //
4168         // The following part configure AP/VWifi/IBSS rate adaptive mask.
4169         //
4170
4171         if(pMgntInfo->mIbss)    // Target: AP/IBSS peer.
4172                 pTargetAdapter = GetDefaultAdapter(pAdapter);
4173         else
4174                 pTargetAdapter = GetFirstAPAdapter(pAdapter);
4175
4176         // if extension port (softap) is started, updaet RA table for more than one clients associate
4177         if(pTargetAdapter != NULL)
4178         {
4179                 int     i;
4180                 PRT_WLAN_STA    pEntry;
4181
4182                 for(i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++)
4183                 {
4184                         pEntry = AsocEntry_EnumStation(pTargetAdapter, i);
4185                         if(NULL != pEntry)
4186                         {
4187                                 if(pEntry->bAssociated)
4188                                 {
4189                                         if(ODM_RAStateCheck(pDM_Odm, pEntry->rssi_stat.UndecoratedSmoothedPWDB, pMgntInfo->bSetTXPowerTrainingByOid, &pEntry->Ratr_State) )
4190                                         {
4191                                                 ODM_PRINT_ADDR(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Target STA addr : "), pEntry->MacAddr);
4192                                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI:%d, RSSI_LEVEL:%d\n", pEntry->rssi_stat.UndecoratedSmoothedPWDB, pEntry->Ratr_State));
4193                                                 pAdapter->HalFunc.UpdateHalRAMaskHandler(pTargetAdapter, pEntry->AssociatedMacId, pEntry, pEntry->Ratr_State);
4194                                         }
4195                                 }
4196                         }
4197                 }
4198         }
4199
4200         if(pMgntInfo->bSetTXPowerTrainingByOid)
4201                 pMgntInfo->bSetTXPowerTrainingByOid = FALSE;
4202 #endif  // #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
4203 }
4204
4205
4206 VOID
4207 odm_RefreshRateAdaptiveMaskCE(
4208         IN              PDM_ODM_T               pDM_Odm
4209         )
4210 {
4211 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
4212         u1Byte  i;
4213         PADAPTER        pAdapter         =  pDM_Odm->Adapter;
4214         PODM_RATE_ADAPTIVE              pRA = &pDM_Odm->RateAdaptive;
4215
4216         if(pAdapter->bDriverStopped)
4217         {
4218                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_TRACE, ("<---- odm_RefreshRateAdaptiveMask(): driver is going to unload\n"));
4219                 return;
4220         }
4221
4222         if(!pDM_Odm->bUseRAMask)
4223         {
4224                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("<---- odm_RefreshRateAdaptiveMask(): driver does not control rate adaptive mask\n"));
4225                 return;
4226         }
4227
4228         //printk("==> %s \n",__FUNCTION__);
4229
4230         for(i=0; i<ODM_ASSOCIATE_ENTRY_NUM; i++){
4231                 PSTA_INFO_T pstat = pDM_Odm->pODM_StaInfo[i];
4232                 if(IS_STA_VALID(pstat) ) {
4233                         if(IS_MCAST( pstat->hwaddr))  //if(psta->mac_id ==1)
4234                                  continue;
4235                         if(IS_MCAST( pstat->hwaddr))
4236                                 continue;
4237
4238                         #if((RTL8812A_SUPPORT==1)||(RTL8821A_SUPPORT==1))
4239                         if((pDM_Odm->SupportICType == ODM_RTL8812)||(pDM_Odm->SupportICType == ODM_RTL8821))
4240                         {
4241                                 if(pstat->rssi_stat.UndecoratedSmoothedPWDB < pRA->LdpcThres)
4242                                 {
4243                                         pRA->bUseLdpc = TRUE;
4244                                         pRA->bLowerRtsRate = TRUE;
4245                                         if((pDM_Odm->SupportICType == ODM_RTL8821) && (pDM_Odm->CutVersion == ODM_CUT_A))
4246                                                 Set_RA_LDPC_8812(pstat, TRUE);
4247                                         //DbgPrint("RSSI=%d, bUseLdpc = TRUE\n", pHalData->UndecoratedSmoothedPWDB);
4248                                 }
4249                                 else if(pstat->rssi_stat.UndecoratedSmoothedPWDB > (pRA->LdpcThres-5))
4250                                 {
4251                                         pRA->bUseLdpc = FALSE;
4252                                         pRA->bLowerRtsRate = FALSE;
4253                                         if((pDM_Odm->SupportICType == ODM_RTL8821) && (pDM_Odm->CutVersion == ODM_CUT_A))
4254                                                 Set_RA_LDPC_8812(pstat, FALSE);
4255                                         //DbgPrint("RSSI=%d, bUseLdpc = FALSE\n", pHalData->UndecoratedSmoothedPWDB);
4256                                 }
4257                         }
4258                         #endif
4259
4260                         if( TRUE == ODM_RAStateCheck(pDM_Odm, pstat->rssi_stat.UndecoratedSmoothedPWDB, FALSE , &pstat->rssi_level) )
4261                         {
4262                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI:%d, RSSI_LEVEL:%d\n", pstat->rssi_stat.UndecoratedSmoothedPWDB, pstat->rssi_level));
4263                                 //printk("RSSI:%d, RSSI_LEVEL:%d\n", pstat->rssi_stat.UndecoratedSmoothedPWDB, pstat->rssi_level);
4264                                 rtw_hal_update_ra_mask(pstat, pstat->rssi_level);
4265                         }
4266
4267                 }
4268         }
4269
4270 #endif
4271 }
4272
4273 VOID
4274 odm_RefreshRateAdaptiveMaskAPADSL(
4275         IN              PDM_ODM_T               pDM_Odm
4276         )
4277 {
4278 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
4279         struct rtl8192cd_priv *priv = pDM_Odm->priv;
4280         struct stat_info        *pstat;
4281
4282         if (!priv->pmib->dot11StationConfigEntry.autoRate)
4283                 return;
4284
4285         if (list_empty(&priv->asoc_list))
4286                 return;
4287
4288         list_for_each_entry(pstat, &priv->asoc_list, asoc_list) {
4289                 if(ODM_RAStateCheck(pDM_Odm, (s4Byte)pstat->rssi, FALSE, &pstat->rssi_level) ) {
4290                         ODM_PRINT_ADDR(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("Target STA addr : "), pstat->hwaddr);
4291                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI:%d, RSSI_LEVEL:%d\n", pstat->rssi, pstat->rssi_level));
4292
4293 #ifdef CONFIG_RTL_88E_SUPPORT
4294                         if (GET_CHIP_VER(priv)==VERSION_8188E) {
4295 #ifdef TXREPORT
4296                                 add_RATid(priv, pstat);
4297 #endif
4298                         } else
4299 #endif
4300                         {
4301 #if defined(CONFIG_RTL_92D_SUPPORT) || defined(CONFIG_RTL_92C_SUPPORT)
4302                         add_update_RATid(priv, pstat);
4303 #endif
4304                         }
4305                 }
4306         }
4307 #endif
4308 }
4309
4310 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
4311 VOID
4312 ODM_DynamicARFBSelect(
4313         IN              PDM_ODM_T               pDM_Odm,
4314         IN              u1Byte                  rate,
4315         IN              BOOLEAN                 Collision_State
4316 )
4317 {
4318
4319         if(pDM_Odm->SupportICType != ODM_RTL8192E)
4320                 return;
4321
4322         if (rate >= DESC_RATEMCS8  && rate <= DESC_RATEMCS12){
4323                 if (Collision_State == 1){
4324                         if(rate == DESC_RATEMCS12){
4325
4326                                 ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x0);
4327                                 ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x07060501);
4328                         }
4329                         else if(rate == DESC_RATEMCS11){
4330
4331                                 ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x0);
4332                                 ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x07070605);
4333                         }
4334                         else if(rate == DESC_RATEMCS10){
4335
4336                                 ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x0);
4337                                 ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x08080706);
4338                         }
4339                         else if(rate == DESC_RATEMCS9){
4340
4341                                 ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x0);
4342                                 ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x08080707);
4343                         }
4344                         else{
4345
4346                                 ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x0);
4347                                 ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x09090808);
4348                         }
4349                 }
4350                 else{   // Collision_State == 0
4351                         if(rate == DESC_RATEMCS12){
4352
4353                                 ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x05010000);
4354                                 ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x09080706);
4355                         }
4356                         else if(rate == DESC_RATEMCS11){
4357
4358                                 ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x06050000);
4359                                 ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x09080807);
4360                         }
4361                         else if(rate == DESC_RATEMCS10){
4362
4363                                 ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x07060000);
4364                                 ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x0a090908);
4365                         }
4366                         else if(rate == DESC_RATEMCS9){
4367
4368                                 ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x07070000);
4369                                 ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x0a090808);
4370                         }
4371                         else{
4372
4373                                 ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x08080000);
4374                                 ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x0b0a0909);
4375                         }
4376                 }
4377         }
4378         else{  // MCS13~MCS15,  1SS, G-mode
4379                 if (Collision_State == 1){
4380                         if(rate == DESC_RATEMCS15){
4381
4382                                 ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x00000000);
4383                                 ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x05040302);
4384                         }
4385                         else if(rate == DESC_RATEMCS14){
4386
4387                                 ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x00000000);
4388                                 ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x06050302);
4389                         }
4390                         else if(rate == DESC_RATEMCS13){
4391
4392                                 ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x00000000);
4393                                 ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x07060502);
4394                         }
4395                         else{
4396
4397                                 ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x00000000);
4398                                 ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x06050402);
4399                         }
4400                 }
4401                 else{   // Collision_State == 0
4402                         if(rate == DESC_RATEMCS15){
4403
4404                                 ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x03020000);
4405                                 ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x07060504);
4406                         }
4407                         else if(rate == DESC_RATEMCS14){
4408
4409                                 ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x03020000);
4410                                 ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x08070605);
4411                         }
4412                         else if(rate == DESC_RATEMCS13){
4413
4414                                 ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x05020000);
4415                                 ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x09080706);
4416                         }
4417                         else{
4418
4419                                 ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E, 0x04020000);
4420                                 ODM_Write4Byte(pDM_Odm, REG_DARFRC_8192E+4, 0x08070605);
4421                         }
4422
4423
4424                 }
4425
4426         }
4427
4428 }
4429
4430 #endif
4431
4432 // Return Value: BOOLEAN
4433 // - TRUE: RATRState is changed.
4434 BOOLEAN
4435 ODM_RAStateCheck(
4436         IN              PDM_ODM_T               pDM_Odm,
4437         IN              s4Byte                  RSSI,
4438         IN              BOOLEAN                 bForceUpdate,
4439         OUT             pu1Byte                 pRATRState
4440         )
4441 {
4442         PODM_RATE_ADAPTIVE pRA = &pDM_Odm->RateAdaptive;
4443         const u1Byte GoUpGap = 5;
4444         u1Byte HighRSSIThreshForRA = pRA->HighRSSIThresh;
4445         u1Byte LowRSSIThreshForRA = pRA->LowRSSIThresh;
4446         u1Byte RATRState;
4447
4448         // Threshold Adjustment:
4449         // when RSSI state trends to go up one or two levels, make sure RSSI is high enough.
4450         // Here GoUpGap is added to solve the boundary's level alternation issue.
4451         switch (*pRATRState)
4452         {
4453                 case DM_RATR_STA_INIT:
4454                 case DM_RATR_STA_HIGH:
4455                         break;
4456
4457                 case DM_RATR_STA_MIDDLE:
4458                         HighRSSIThreshForRA += GoUpGap;
4459                         break;
4460
4461                 case DM_RATR_STA_LOW:
4462                         HighRSSIThreshForRA += GoUpGap;
4463                         LowRSSIThreshForRA += GoUpGap;
4464                         break;
4465
4466                 default:
4467                         ODM_RT_ASSERT(pDM_Odm, FALSE, ("wrong rssi level setting %d !", *pRATRState) );
4468                         break;
4469         }
4470
4471         // Decide RATRState by RSSI.
4472         if(RSSI > HighRSSIThreshForRA)
4473                 RATRState = DM_RATR_STA_HIGH;
4474         else if(RSSI > LowRSSIThreshForRA)
4475                 RATRState = DM_RATR_STA_MIDDLE;
4476         else
4477                 RATRState = DM_RATR_STA_LOW;
4478         //printk("==>%s,RATRState:0x%02x ,RSSI:%d \n",__FUNCTION__,RATRState,RSSI);
4479
4480         if( *pRATRState!=RATRState || bForceUpdate)
4481         {
4482                 ODM_RT_TRACE( pDM_Odm, ODM_COMP_RA_MASK, ODM_DBG_LOUD, ("RSSI Level %d -> %d\n", *pRATRState, RATRState) );
4483                 *pRATRState = RATRState;
4484                 return TRUE;
4485         }
4486
4487         return FALSE;
4488 }
4489
4490
4491 //============================================================
4492
4493 //3============================================================
4494 //3 Dynamic Tx Power
4495 //3============================================================
4496
4497 VOID
4498 odm_DynamicTxPowerInit(
4499         IN              PDM_ODM_T               pDM_Odm
4500         )
4501 {
4502 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
4503         PADAPTER        Adapter = pDM_Odm->Adapter;
4504         PMGNT_INFO                      pMgntInfo = &Adapter->MgntInfo;
4505         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(Adapter);
4506
4507         #if DEV_BUS_TYPE==RT_USB_INTERFACE
4508         if(RT_GetInterfaceSelection(Adapter) == INTF_SEL1_USB_High_Power)
4509         {
4510                 odm_DynamicTxPowerSavePowerIndex(pDM_Odm);
4511                 pMgntInfo->bDynamicTxPowerEnable = TRUE;
4512         }
4513         else
4514         #else
4515         //so 92c pci do not need dynamic tx power? vivi check it later
4516         if(IS_HARDWARE_TYPE_8192D(Adapter))
4517                 pMgntInfo->bDynamicTxPowerEnable = TRUE;
4518         else
4519                 pMgntInfo->bDynamicTxPowerEnable = FALSE;
4520         #endif
4521
4522
4523         pHalData->LastDTPLvl = TxHighPwrLevel_Normal;
4524         pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
4525 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
4526         PADAPTER        Adapter = pDM_Odm->Adapter;
4527         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
4528         struct dm_priv  *pdmpriv = &pHalData->dmpriv;
4529         pdmpriv->bDynamicTxPowerEnable = _FALSE;
4530
4531         #if (RTL8192C_SUPPORT==1)
4532         #ifdef CONFIG_USB_HCI
4533
4534         #ifdef CONFIG_INTEL_PROXIM
4535         if((pHalData->BoardType == BOARD_USB_High_PA)||(Adapter->proximity.proxim_support==_TRUE))
4536         #else
4537         if(pHalData->BoardType == BOARD_USB_High_PA)
4538         #endif
4539
4540         {
4541                 //odm_SavePowerIndex(Adapter);
4542                 odm_DynamicTxPowerSavePowerIndex(pDM_Odm);
4543                 pdmpriv->bDynamicTxPowerEnable = _TRUE;
4544         }
4545         else
4546         #else
4547                 pdmpriv->bDynamicTxPowerEnable = _FALSE;
4548         #endif
4549         #endif
4550
4551         pdmpriv->LastDTPLvl = TxHighPwrLevel_Normal;
4552         pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
4553
4554 #endif
4555
4556 }
4557
4558 VOID
4559 odm_DynamicTxPowerSavePowerIndex(
4560         IN              PDM_ODM_T               pDM_Odm
4561         )
4562 {
4563         u1Byte          index;
4564         u4Byte          Power_Index_REG[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a};
4565
4566 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
4567         PADAPTER        Adapter = pDM_Odm->Adapter;
4568         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
4569         for(index = 0; index< 6; index++)
4570                 pHalData->PowerIndex_backup[index] = PlatformEFIORead1Byte(Adapter, Power_Index_REG[index]);
4571 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
4572         PADAPTER        Adapter = pDM_Odm->Adapter;
4573         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
4574         struct dm_priv  *pdmpriv = &pHalData->dmpriv;
4575         for(index = 0; index< 6; index++)
4576                 pdmpriv->PowerIndex_backup[index] = rtw_read8(Adapter, Power_Index_REG[index]);
4577 #endif
4578 }
4579
4580 VOID
4581 odm_DynamicTxPowerRestorePowerIndex(
4582         IN              PDM_ODM_T               pDM_Odm
4583         )
4584 {
4585         u1Byte                  index;
4586         PADAPTER                Adapter = pDM_Odm->Adapter;
4587
4588 #if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_WIN))
4589         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
4590         u4Byte                  Power_Index_REG[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a};
4591 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
4592         for(index = 0; index< 6; index++)
4593                 PlatformEFIOWrite1Byte(Adapter, Power_Index_REG[index], pHalData->PowerIndex_backup[index]);
4594 #elif(DM_ODM_SUPPORT_TYPE == ODM_CE)
4595         struct dm_priv  *pdmpriv = &pHalData->dmpriv;
4596         for(index = 0; index< 6; index++)
4597                 rtw_write8(Adapter, Power_Index_REG[index], pdmpriv->PowerIndex_backup[index]);
4598 #endif
4599 #endif
4600 }
4601
4602 VOID
4603 odm_DynamicTxPowerWritePowerIndex(
4604         IN      PDM_ODM_T       pDM_Odm,
4605         IN      u1Byte          Value)
4606 {
4607
4608         u1Byte                  index;
4609         u4Byte                  Power_Index_REG[6] = {0xc90, 0xc91, 0xc92, 0xc98, 0xc99, 0xc9a};
4610
4611         for(index = 0; index< 6; index++)
4612                 //PlatformEFIOWrite1Byte(Adapter, Power_Index_REG[index], Value);
4613                 ODM_Write1Byte(pDM_Odm, Power_Index_REG[index], Value);
4614
4615 }
4616
4617
4618 VOID
4619 odm_DynamicTxPower(
4620         IN              PDM_ODM_T               pDM_Odm
4621         )
4622 {
4623         //
4624         // For AP/ADSL use prtl8192cd_priv
4625         // For CE/NIC use PADAPTER
4626         //
4627         //PADAPTER              pAdapter = pDM_Odm->Adapter;
4628 //      prtl8192cd_priv priv            = pDM_Odm->priv;
4629
4630         if (!(pDM_Odm->SupportAbility & ODM_BB_DYNAMIC_TXPWR))
4631                 return;
4632
4633         //
4634         // 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate
4635         // at the same time. In the stage2/3, we need to prive universal interface and merge all
4636         // HW dynamic mechanism.
4637         //
4638         switch  (pDM_Odm->SupportPlatform)
4639         {
4640                 case    ODM_WIN:
4641                 case    ODM_CE:
4642                         odm_DynamicTxPowerNIC(pDM_Odm);
4643                         break;
4644                 case    ODM_AP:
4645                         odm_DynamicTxPowerAP(pDM_Odm);
4646                         break;
4647
4648                 case    ODM_ADSL:
4649                         //odm_DIGAP(pDM_Odm);
4650                         break;
4651         }
4652
4653
4654 }
4655
4656
4657 VOID
4658 odm_DynamicTxPowerNIC(
4659         IN              PDM_ODM_T               pDM_Odm
4660         )
4661 {
4662         if (!(pDM_Odm->SupportAbility & ODM_BB_DYNAMIC_TXPWR))
4663                 return;
4664
4665 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
4666
4667         if(pDM_Odm->SupportICType == ODM_RTL8192C)
4668         {
4669                 odm_DynamicTxPower_92C(pDM_Odm);
4670         }
4671         else if(pDM_Odm->SupportICType == ODM_RTL8192D)
4672         {
4673                 odm_DynamicTxPower_92D(pDM_Odm);
4674         }
4675         else if (pDM_Odm->SupportICType == ODM_RTL8821)
4676         {
4677 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
4678                 PADAPTER                Adapter  =  pDM_Odm->Adapter;
4679                 PMGNT_INFO              pMgntInfo = GetDefaultMgntInfo(Adapter);
4680
4681                 if (pMgntInfo->RegRspPwr == 1)
4682                 {
4683                         if(pDM_Odm->RSSI_Min > 60)
4684                         {
4685                                 ODM_SetMACReg(pDM_Odm, ODM_REG_RESP_TX_11AC, BIT20|BIT19|BIT18, 1); // Resp TXAGC offset = -3dB
4686
4687                         }
4688                         else if(pDM_Odm->RSSI_Min < 55)
4689                         {
4690                                 ODM_SetMACReg(pDM_Odm, ODM_REG_RESP_TX_11AC, BIT20|BIT19|BIT18, 0); // Resp TXAGC offset = 0dB
4691                         }
4692                 }
4693 #endif
4694         }
4695 #endif
4696 }
4697
4698 VOID
4699 odm_DynamicTxPowerAP(
4700         IN              PDM_ODM_T               pDM_Odm
4701
4702         )
4703 {
4704 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
4705         prtl8192cd_priv priv            = pDM_Odm->priv;
4706         s4Byte i;
4707
4708         if(!priv->pshare->rf_ft_var.tx_pwr_ctrl)
4709                 return;
4710
4711 #ifdef HIGH_POWER_EXT_PA
4712         if(pDM_Odm->ExtPA)
4713                 tx_power_control(priv);
4714 #endif
4715
4716         /*
4717          *      Check if station is near by to use lower tx power
4718          */
4719
4720         if ((priv->up_time % 3) == 0 )  {
4721                 for(i=0; i<ODM_ASSOCIATE_ENTRY_NUM; i++){
4722                         PSTA_INFO_T pstat = pDM_Odm->pODM_StaInfo[i];
4723                         if(IS_STA_VALID(pstat) ) {
4724                                 if ((pstat->hp_level == 0) && (pstat->rssi > TX_POWER_NEAR_FIELD_THRESH_AP+4))
4725                                         pstat->hp_level = 1;
4726                                 else if ((pstat->hp_level == 1) && (pstat->rssi < TX_POWER_NEAR_FIELD_THRESH_AP))
4727                                         pstat->hp_level = 0;
4728                         }
4729                 }
4730         }
4731
4732 #endif
4733 }
4734
4735
4736 VOID
4737 odm_DynamicTxPower_92C(
4738         IN      PDM_ODM_T       pDM_Odm
4739         )
4740 {
4741 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
4742         PADAPTER Adapter = pDM_Odm->Adapter;
4743         PMGNT_INFO                      pMgntInfo = &Adapter->MgntInfo;
4744         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(Adapter);
4745         s4Byte                          UndecoratedSmoothedPWDB;
4746
4747         // 2012/01/12 MH According to Luke's suggestion, only high power will support the feature.
4748         if (pDM_Odm->ExtPA == FALSE)
4749                 return;
4750
4751         // STA not connected and AP not connected
4752         if((!pMgntInfo->bMediaConnect) &&
4753                 (pHalData->EntryMinUndecoratedSmoothedPWDB == 0))
4754         {
4755                 ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("Not connected to any \n"));
4756                 pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
4757
4758                 //the LastDTPlvl should reset when disconnect,
4759                 //otherwise the tx power level wouldn't change when disconnect and connect again.
4760                 // Maddest 20091220.
4761                  pHalData->LastDTPLvl=TxHighPwrLevel_Normal;
4762                 return;
4763         }
4764
4765 #if (INTEL_PROXIMITY_SUPPORT == 1)
4766         // Intel set fixed tx power
4767         if(pMgntInfo->IntelProximityModeInfo.PowerOutput > 0)
4768         {
4769                 switch(pMgntInfo->IntelProximityModeInfo.PowerOutput){
4770                         case 1:
4771                                 pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_100;
4772                                 ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_100\n"));
4773                                 break;
4774                         case 2:
4775                                 pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_70;
4776                                 ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_70\n"));
4777                                 break;
4778                         case 3:
4779                                 pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_50;
4780                                 ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_50\n"));
4781                                 break;
4782                         case 4:
4783                                 pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_35;
4784                                 ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_35\n"));
4785                                 break;
4786                         case 5:
4787                                 pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_15;
4788                                 ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_15\n"));
4789                                 break;
4790                         default:
4791                                 pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_100;
4792                                 ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_100\n"));
4793                                 break;
4794                 }
4795         }
4796         else
4797 #endif
4798         {
4799                 if(     (pMgntInfo->bDynamicTxPowerEnable != TRUE) ||
4800                         (pHalData->DMFlag & HAL_DM_HIPWR_DISABLE) ||
4801                         pMgntInfo->IOTAction & HT_IOT_ACT_DISABLE_HIGH_POWER)
4802                 {
4803                         pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
4804                 }
4805                 else
4806                 {
4807                         if(pMgntInfo->bMediaConnect)    // Default port
4808                         {
4809                                 if(ACTING_AS_AP(Adapter) || ACTING_AS_IBSS(Adapter))
4810                                 {
4811                                         UndecoratedSmoothedPWDB = pHalData->EntryMinUndecoratedSmoothedPWDB;
4812                                         ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("AP Client PWDB = 0x%x \n", UndecoratedSmoothedPWDB));
4813                                 }
4814                                 else
4815                                 {
4816                                         UndecoratedSmoothedPWDB = pHalData->UndecoratedSmoothedPWDB;
4817                                         ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("STA Default Port PWDB = 0x%x \n", UndecoratedSmoothedPWDB));
4818                                 }
4819                         }
4820                         else // associated entry pwdb
4821                         {
4822                                 UndecoratedSmoothedPWDB = pHalData->EntryMinUndecoratedSmoothedPWDB;
4823                                 ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("AP Ext Port PWDB = 0x%x \n", UndecoratedSmoothedPWDB));
4824                         }
4825
4826                         if(UndecoratedSmoothedPWDB >= TX_POWER_NEAR_FIELD_THRESH_LVL2)
4827                         {
4828                                 pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Level2;
4829                                 ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_Level1 (TxPwr=0x0)\n"));
4830                         }
4831                         else if((UndecoratedSmoothedPWDB < (TX_POWER_NEAR_FIELD_THRESH_LVL2-3)) &&
4832                                 (UndecoratedSmoothedPWDB >= TX_POWER_NEAR_FIELD_THRESH_LVL1) )
4833                         {
4834                                 pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Level1;
4835                                 ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_Level1 (TxPwr=0x10)\n"));
4836                         }
4837                         else if(UndecoratedSmoothedPWDB < (TX_POWER_NEAR_FIELD_THRESH_LVL1-5))
4838                         {
4839                                 pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
4840                                 ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_Normal\n"));
4841                         }
4842                 }
4843         }
4844         if( pHalData->DynamicTxHighPowerLvl != pHalData->LastDTPLvl )
4845         {
4846                 ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("PHY_SetTxPowerLevel8192C() Channel = %d \n" , pHalData->CurrentChannel));
4847                 PHY_SetTxPowerLevel8192C(Adapter, pHalData->CurrentChannel);
4848                 if(     (pHalData->DynamicTxHighPowerLvl == TxHighPwrLevel_Normal) &&
4849                         (pHalData->LastDTPLvl == TxHighPwrLevel_Level1 || pHalData->LastDTPLvl == TxHighPwrLevel_Level2)) //TxHighPwrLevel_Normal
4850                         odm_DynamicTxPowerRestorePowerIndex(pDM_Odm);
4851                 else if(pHalData->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1)
4852                         odm_DynamicTxPowerWritePowerIndex(pDM_Odm, 0x14);
4853                 else if(pHalData->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2)
4854                         odm_DynamicTxPowerWritePowerIndex(pDM_Odm, 0x10);
4855         }
4856         pHalData->LastDTPLvl = pHalData->DynamicTxHighPowerLvl;
4857
4858
4859 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
4860
4861         #if (RTL8192C_SUPPORT==1)
4862         PADAPTER Adapter = pDM_Odm->Adapter;
4863         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
4864         struct dm_priv  *pdmpriv = &pHalData->dmpriv;
4865         struct mlme_priv        *pmlmepriv = &(Adapter->mlmepriv);
4866         struct mlme_ext_priv    *pmlmeext = &Adapter->mlmeextpriv;
4867         int     UndecoratedSmoothedPWDB;
4868
4869         if(!pdmpriv->bDynamicTxPowerEnable)
4870                 return;
4871
4872 #ifdef CONFIG_INTEL_PROXIM
4873         if(Adapter->proximity.proxim_on== _TRUE){
4874                 struct proximity_priv *prox_priv=Adapter->proximity.proximity_priv;
4875                 // Intel set fixed tx power
4876                 printk("\n %s  Adapter->proximity.proxim_on=%d prox_priv->proxim_modeinfo->power_output=%d \n",__FUNCTION__,Adapter->proximity.proxim_on,prox_priv->proxim_modeinfo->power_output);
4877                 if(prox_priv!=NULL){
4878                         if(prox_priv->proxim_modeinfo->power_output> 0)
4879                         {
4880                                 switch(prox_priv->proxim_modeinfo->power_output)
4881                                 {
4882                                         case 1:
4883                                                 pdmpriv->DynamicTxHighPowerLvl  = TxHighPwrLevel_100;
4884                                                 printk("TxHighPwrLevel_100\n");
4885                                                 break;
4886                                         case 2:
4887                                                 pdmpriv->DynamicTxHighPowerLvl  = TxHighPwrLevel_70;
4888                                                 printk("TxHighPwrLevel_70\n");
4889                                                 break;
4890                                         case 3:
4891                                                 pdmpriv->DynamicTxHighPowerLvl  = TxHighPwrLevel_50;
4892                                                 printk("TxHighPwrLevel_50\n");
4893                                                 break;
4894                                         case 4:
4895                                                 pdmpriv->DynamicTxHighPowerLvl  = TxHighPwrLevel_35;
4896                                                 printk("TxHighPwrLevel_35\n");
4897                                                 break;
4898                                         case 5:
4899                                                 pdmpriv->DynamicTxHighPowerLvl  = TxHighPwrLevel_15;
4900                                                 printk("TxHighPwrLevel_15\n");
4901                                                 break;
4902                                         default:
4903                                                 pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_100;
4904                                                 printk("TxHighPwrLevel_100\n");
4905                                                 break;
4906                                 }
4907                         }
4908                 }
4909         }
4910         else
4911 #endif
4912         {
4913                 // STA not connected and AP not connected
4914                 if((check_fwstate(pmlmepriv, _FW_LINKED) != _TRUE) &&
4915                         (pdmpriv->EntryMinUndecoratedSmoothedPWDB == 0))
4916                 {
4917                         //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("Not connected to any \n"));
4918                         pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
4919
4920                         //the LastDTPlvl should reset when disconnect,
4921                         //otherwise the tx power level wouldn't change when disconnect and connect again.
4922                         // Maddest 20091220.
4923                         pdmpriv->LastDTPLvl=TxHighPwrLevel_Normal;
4924                         return;
4925                 }
4926
4927                 if(check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)       // Default port
4928                 {
4929                 #if 0
4930                         //todo: AP Mode
4931                         if ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) ||
4932                                (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE))
4933                         {
4934                                 UndecoratedSmoothedPWDB = pdmpriv->EntryMinUndecoratedSmoothedPWDB;
4935                                 //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("AP Client PWDB = 0x%x \n", UndecoratedSmoothedPWDB));
4936                         }
4937                         else
4938                         {
4939                                 UndecoratedSmoothedPWDB = pdmpriv->UndecoratedSmoothedPWDB;
4940                                 //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("STA Default Port PWDB = 0x%x \n", UndecoratedSmoothedPWDB));
4941                         }
4942                 #else
4943                 UndecoratedSmoothedPWDB = pdmpriv->EntryMinUndecoratedSmoothedPWDB;
4944                 #endif
4945                 }
4946                 else // associated entry pwdb
4947                 {
4948                         UndecoratedSmoothedPWDB = pdmpriv->EntryMinUndecoratedSmoothedPWDB;
4949                         //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("AP Ext Port PWDB = 0x%x \n", UndecoratedSmoothedPWDB));
4950                 }
4951
4952                 if(UndecoratedSmoothedPWDB >= TX_POWER_NEAR_FIELD_THRESH_LVL2)
4953                 {
4954                         pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Level2;
4955                         //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_Level1 (TxPwr=0x0)\n"));
4956                 }
4957                 else if((UndecoratedSmoothedPWDB < (TX_POWER_NEAR_FIELD_THRESH_LVL2-3)) &&
4958                         (UndecoratedSmoothedPWDB >= TX_POWER_NEAR_FIELD_THRESH_LVL1) )
4959                 {
4960                         pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Level1;
4961                         //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_Level1 (TxPwr=0x10)\n"));
4962                 }
4963                 else if(UndecoratedSmoothedPWDB < (TX_POWER_NEAR_FIELD_THRESH_LVL1-5))
4964                 {
4965                         pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
4966                         //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_Normal\n"));
4967                 }
4968         }
4969         if( (pdmpriv->DynamicTxHighPowerLvl != pdmpriv->LastDTPLvl) )
4970         {
4971                 PHY_SetTxPowerLevel8192C(Adapter, pHalData->CurrentChannel);
4972                 if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Normal) // HP1 -> Normal  or HP2 -> Normal
4973                         odm_DynamicTxPowerRestorePowerIndex(pDM_Odm);
4974                 else if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level1)
4975                         odm_DynamicTxPowerWritePowerIndex(pDM_Odm, 0x14);
4976                 else if(pdmpriv->DynamicTxHighPowerLvl == TxHighPwrLevel_Level2)
4977                         odm_DynamicTxPowerWritePowerIndex(pDM_Odm, 0x10);
4978         }
4979         pdmpriv->LastDTPLvl = pdmpriv->DynamicTxHighPowerLvl;
4980         #endif
4981 #endif  // #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
4982
4983 }
4984
4985
4986 VOID
4987 odm_DynamicTxPower_92D(
4988         IN      PDM_ODM_T       pDM_Odm
4989         )
4990 {
4991 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
4992         PADAPTER Adapter = pDM_Odm->Adapter;
4993         PMGNT_INFO                      pMgntInfo = &Adapter->MgntInfo;
4994         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(Adapter);
4995         s4Byte                          UndecoratedSmoothedPWDB;
4996
4997         PADAPTER        BuddyAdapter = Adapter->BuddyAdapter;
4998         BOOLEAN         bGetValueFromBuddyAdapter = dm_DualMacGetParameterFromBuddyAdapter(Adapter);
4999         u1Byte          HighPowerLvlBackForMac0 = TxHighPwrLevel_Level1;
5000
5001         // 2012/01/12 MH According to Luke's suggestion, only high power will support the feature.
5002         if (pDM_Odm->ExtPA == FALSE)
5003                 return;
5004
5005         // If dynamic high power is disabled.
5006         if( (pMgntInfo->bDynamicTxPowerEnable != TRUE) ||
5007                 (pHalData->DMFlag & HAL_DM_HIPWR_DISABLE) ||
5008                 pMgntInfo->IOTAction & HT_IOT_ACT_DISABLE_HIGH_POWER)
5009         {
5010                 pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
5011                 return;
5012         }
5013
5014         // STA not connected and AP not connected
5015         if((!pMgntInfo->bMediaConnect) &&
5016                 (pHalData->EntryMinUndecoratedSmoothedPWDB == 0))
5017         {
5018                 ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("Not connected to any \n"));
5019                 pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
5020
5021                 //the LastDTPlvl should reset when disconnect,
5022                 //otherwise the tx power level wouldn't change when disconnect and connect again.
5023                 // Maddest 20091220.
5024                  pHalData->LastDTPLvl=TxHighPwrLevel_Normal;
5025                 return;
5026         }
5027
5028         if(pMgntInfo->bMediaConnect)    // Default port
5029         {
5030                 if(ACTING_AS_AP(Adapter) || pMgntInfo->mIbss)
5031                 {
5032                         UndecoratedSmoothedPWDB = pHalData->EntryMinUndecoratedSmoothedPWDB;
5033                         ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("AP Client PWDB = 0x%x \n", UndecoratedSmoothedPWDB));
5034                 }
5035                 else
5036                 {
5037                         UndecoratedSmoothedPWDB = pHalData->UndecoratedSmoothedPWDB;
5038                         ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("STA Default Port PWDB = 0x%x \n", UndecoratedSmoothedPWDB));
5039                 }
5040         }
5041         else // associated entry pwdb
5042         {
5043                 UndecoratedSmoothedPWDB = pHalData->EntryMinUndecoratedSmoothedPWDB;
5044                 ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("AP Ext Port PWDB = 0x%x \n", UndecoratedSmoothedPWDB));
5045         }
5046
5047         if(IS_HARDWARE_TYPE_8192D(Adapter) && GET_HAL_DATA(Adapter)->CurrentBandType == 1){
5048                 if(UndecoratedSmoothedPWDB >= 0x33)
5049                 {
5050                         pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Level2;
5051                         ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("5G:TxHighPwrLevel_Level2 (TxPwr=0x0)\n"));
5052                 }
5053                 else if((UndecoratedSmoothedPWDB <0x33) &&
5054                         (UndecoratedSmoothedPWDB >= 0x2b) )
5055                 {
5056                         pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Level1;
5057                         ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("5G:TxHighPwrLevel_Level1 (TxPwr=0x10)\n"));
5058                 }
5059                 else if(UndecoratedSmoothedPWDB < 0x2b)
5060                 {
5061                         pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
5062                         ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("5G:TxHighPwrLevel_Normal\n"));
5063                 }
5064
5065         }
5066         else
5067
5068         {
5069                 if(UndecoratedSmoothedPWDB >= TX_POWER_NEAR_FIELD_THRESH_LVL2)
5070                 {
5071                         pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Level1;
5072                         ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_Level1 (TxPwr=0x0)\n"));
5073                 }
5074                 else if((UndecoratedSmoothedPWDB < (TX_POWER_NEAR_FIELD_THRESH_LVL2-3)) &&
5075                         (UndecoratedSmoothedPWDB >= TX_POWER_NEAR_FIELD_THRESH_LVL1) )
5076                 {
5077                         pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Level1;
5078                         ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_Level1 (TxPwr=0x10)\n"));
5079                 }
5080                 else if(UndecoratedSmoothedPWDB < (TX_POWER_NEAR_FIELD_THRESH_LVL1-5))
5081                 {
5082                         pHalData->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
5083                         ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_Normal\n"));
5084                 }
5085
5086         }
5087
5088 //sherry  delete flag 20110517
5089         if(bGetValueFromBuddyAdapter)
5090         {
5091                 ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() mac 0 for mac 1 \n"));
5092                 if(Adapter->DualMacDMSPControl.bChangeTxHighPowerLvlForAnotherMacOfDMSP)
5093                 {
5094                         ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() change value \n"));
5095                         HighPowerLvlBackForMac0 = pHalData->DynamicTxHighPowerLvl;
5096                         pHalData->DynamicTxHighPowerLvl = Adapter->DualMacDMSPControl.CurTxHighLvlForAnotherMacOfDMSP;
5097                         PHY_SetTxPowerLevel8192C(Adapter, pHalData->CurrentChannel);
5098                         pHalData->DynamicTxHighPowerLvl = HighPowerLvlBackForMac0;
5099                         Adapter->DualMacDMSPControl.bChangeTxHighPowerLvlForAnotherMacOfDMSP = FALSE;
5100                 }
5101         }
5102
5103         if( (pHalData->DynamicTxHighPowerLvl != pHalData->LastDTPLvl) )
5104         {
5105                         ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("PHY_SetTxPowerLevel8192S() Channel = %d \n" , pHalData->CurrentChannel));
5106                         if(Adapter->DualMacSmartConcurrent == TRUE)
5107                         {
5108                                 if(BuddyAdapter == NULL)
5109                                 {
5110                                         ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() BuddyAdapter == NULL case \n"));
5111                                         if(!Adapter->bSlaveOfDMSP)
5112                                         {
5113                                                 PHY_SetTxPowerLevel8192C(Adapter, pHalData->CurrentChannel);
5114                                         }
5115                                 }
5116                                 else
5117                                 {
5118                                         if(pHalData->MacPhyMode92D == DUALMAC_SINGLEPHY)
5119                                         {
5120                                                 ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() BuddyAdapter DMSP \n"));
5121                                                 if(Adapter->bSlaveOfDMSP)
5122                                                 {
5123                                                         ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() bslave case  \n"));
5124                                                         BuddyAdapter->DualMacDMSPControl.bChangeTxHighPowerLvlForAnotherMacOfDMSP = TRUE;
5125                                                         BuddyAdapter->DualMacDMSPControl.CurTxHighLvlForAnotherMacOfDMSP = pHalData->DynamicTxHighPowerLvl;
5126                                                 }
5127                                                 else
5128                                                 {
5129                                                         ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() master case  \n"));
5130                                                         if(!bGetValueFromBuddyAdapter)
5131                                                         {
5132                                                                 ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() mac 0 for mac 0 \n"));
5133                                                                 PHY_SetTxPowerLevel8192C(Adapter, pHalData->CurrentChannel);
5134                                                         }
5135                                                 }
5136                                         }
5137                                         else
5138                                         {
5139                                                 ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() BuddyAdapter DMDP\n"));
5140                                                 PHY_SetTxPowerLevel8192C(Adapter, pHalData->CurrentChannel);
5141                                         }
5142                                 }
5143                         }
5144                         else
5145                         {
5146                                 PHY_SetTxPowerLevel8192C(Adapter, pHalData->CurrentChannel);
5147                         }
5148
5149                 }
5150         pHalData->LastDTPLvl = pHalData->DynamicTxHighPowerLvl;
5151 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
5152 #if (RTL8192D_SUPPORT==1)
5153         PADAPTER Adapter = pDM_Odm->Adapter;
5154         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
5155         struct mlme_priv        *pmlmepriv = &(Adapter->mlmepriv);
5156
5157         struct dm_priv  *pdmpriv = &pHalData->dmpriv;
5158         DM_ODM_T                *podmpriv = &pHalData->odmpriv;
5159         int     UndecoratedSmoothedPWDB;
5160         #if (RTL8192D_EASY_SMART_CONCURRENT == 1)
5161         PADAPTER        BuddyAdapter = Adapter->BuddyAdapter;
5162         BOOLEAN         bGetValueFromBuddyAdapter = DualMacGetParameterFromBuddyAdapter(Adapter);
5163         u8              HighPowerLvlBackForMac0 = TxHighPwrLevel_Level1;
5164         #endif
5165
5166         // If dynamic high power is disabled.
5167         if( (pdmpriv->bDynamicTxPowerEnable != _TRUE) ||
5168                 (!(podmpriv->SupportAbility& ODM_BB_DYNAMIC_TXPWR)) )
5169         {
5170                 pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
5171                 return;
5172         }
5173
5174         // STA not connected and AP not connected
5175         if((check_fwstate(pmlmepriv, _FW_LINKED) != _TRUE) &&
5176                 (pdmpriv->EntryMinUndecoratedSmoothedPWDB == 0))
5177         {
5178                 //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("Not connected to any \n"));
5179                 pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
5180                 //the LastDTPlvl should reset when disconnect,
5181                 //otherwise the tx power level wouldn't change when disconnect and connect again.
5182                 // Maddest 20091220.
5183                 pdmpriv->LastDTPLvl=TxHighPwrLevel_Normal;
5184                 return;
5185         }
5186
5187         if(check_fwstate(pmlmepriv, _FW_LINKED) == _TRUE)       // Default port
5188         {
5189         #if 0
5190                 //todo: AP Mode
5191                 if ((check_fwstate(pmlmepriv, WIFI_ADHOC_MASTER_STATE) == _TRUE) ||
5192                (check_fwstate(pmlmepriv, WIFI_ADHOC_STATE) == _TRUE))
5193                 {
5194                         UndecoratedSmoothedPWDB = pdmpriv->EntryMinUndecoratedSmoothedPWDB;
5195                         //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("AP Client PWDB = 0x%x \n", UndecoratedSmoothedPWDB));
5196                 }
5197                 else
5198                 {
5199                         UndecoratedSmoothedPWDB = pdmpriv->UndecoratedSmoothedPWDB;
5200                         //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("STA Default Port PWDB = 0x%x \n", UndecoratedSmoothedPWDB));
5201                 }
5202         #else
5203         UndecoratedSmoothedPWDB = pdmpriv->EntryMinUndecoratedSmoothedPWDB;
5204         #endif
5205         }
5206         else // associated entry pwdb
5207         {
5208                 UndecoratedSmoothedPWDB = pdmpriv->EntryMinUndecoratedSmoothedPWDB;
5209                 //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("AP Ext Port PWDB = 0x%x \n", UndecoratedSmoothedPWDB));
5210         }
5211 #if TX_POWER_FOR_5G_BAND == 1
5212         if(pHalData->CurrentBandType92D == BAND_ON_5G){
5213                 if(UndecoratedSmoothedPWDB >= 0x33)
5214                 {
5215                         pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Level2;
5216                         //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("5G:TxHighPwrLevel_Level2 (TxPwr=0x0)\n"));
5217                 }
5218                 else if((UndecoratedSmoothedPWDB <0x33) &&
5219                         (UndecoratedSmoothedPWDB >= 0x2b) )
5220                 {
5221                         pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Level1;
5222                         //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("5G:TxHighPwrLevel_Level1 (TxPwr=0x10)\n"));
5223                 }
5224                 else if(UndecoratedSmoothedPWDB < 0x2b)
5225                 {
5226                         pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
5227                         //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("5G:TxHighPwrLevel_Normal\n"));
5228                 }
5229         }
5230         else
5231 #endif
5232         {
5233                 if(UndecoratedSmoothedPWDB >= TX_POWER_NEAR_FIELD_THRESH_LVL2)
5234                 {
5235                         pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Level2;
5236                         //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_Level1 (TxPwr=0x0)\n"));
5237                 }
5238                 else if((UndecoratedSmoothedPWDB < (TX_POWER_NEAR_FIELD_THRESH_LVL2-3)) &&
5239                         (UndecoratedSmoothedPWDB >= TX_POWER_NEAR_FIELD_THRESH_LVL1) )
5240                 {
5241                         pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Level1;
5242                         //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_Level1 (TxPwr=0x10)\n"));
5243                 }
5244                 else if(UndecoratedSmoothedPWDB < (TX_POWER_NEAR_FIELD_THRESH_LVL1-5))
5245                 {
5246                         pdmpriv->DynamicTxHighPowerLvl = TxHighPwrLevel_Normal;
5247                         //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("TxHighPwrLevel_Normal\n"));
5248                 }
5249         }
5250 #if (RTL8192D_EASY_SMART_CONCURRENT == 1)
5251         if(bGetValueFromBuddyAdapter)
5252         {
5253                 //ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() mac 0 for mac 1 \n"));
5254                 if(Adapter->DualMacDMSPControl.bChangeTxHighPowerLvlForAnotherMacOfDMSP)
5255                 {
5256                         //ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() change value \n"));
5257                         HighPowerLvlBackForMac0 = pHalData->DynamicTxHighPowerLvl;
5258                         pHalData->DynamicTxHighPowerLvl = Adapter->DualMacDMSPControl.CurTxHighLvlForAnotherMacOfDMSP;
5259                         PHY_SetTxPowerLevel8192D(Adapter, pHalData->CurrentChannel);
5260                         pHalData->DynamicTxHighPowerLvl = HighPowerLvlBackForMac0;
5261                         Adapter->DualMacDMSPControl.bChangeTxHighPowerLvlForAnotherMacOfDMSP = _FALSE;
5262                 }
5263         }
5264 #endif
5265
5266         if( (pdmpriv->DynamicTxHighPowerLvl != pdmpriv->LastDTPLvl) )
5267         {
5268                 //ODM_RT_TRACE(pDM_Odm,COMP_HIPWR, DBG_LOUD, ("PHY_SetTxPowerLevel8192S() Channel = %d \n" , pHalData->CurrentChannel));
5269 #if (RTL8192D_EASY_SMART_CONCURRENT == 1)
5270                 if(BuddyAdapter == NULL)
5271                 {
5272                         //ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() BuddyAdapter == NULL case \n"));
5273                         if(!Adapter->bSlaveOfDMSP)
5274                         {
5275                                 PHY_SetTxPowerLevel8192D(Adapter, pHalData->CurrentChannel);
5276                         }
5277                 }
5278                 else
5279                 {
5280                         if(pHalData->MacPhyMode92D == DUALMAC_SINGLEPHY)
5281                         {
5282                                 //ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() BuddyAdapter DMSP \n"));
5283                                 if(Adapter->bSlaveOfDMSP)
5284                                 {
5285                                         //ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() bslave case  \n"));
5286                                         BuddyAdapter->DualMacDMSPControl.bChangeTxHighPowerLvlForAnotherMacOfDMSP = _TRUE;
5287                                         BuddyAdapter->DualMacDMSPControl.CurTxHighLvlForAnotherMacOfDMSP = pHalData->DynamicTxHighPowerLvl;
5288                                 }
5289                                 else
5290                                 {
5291                                         //ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() master case  \n"));
5292                                         if(!bGetValueFromBuddyAdapter)
5293                                         {
5294                                                 //ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() mac 0 for mac 0 \n"));
5295                                                 PHY_SetTxPowerLevel8192D(Adapter, pHalData->CurrentChannel);
5296                                         }
5297                                 }
5298                         }
5299                         else
5300                         {
5301                                 //ODM_RT_TRACE(pDM_Odm,COMP_MLME,DBG_LOUD,("dm_DynamicTxPower() BuddyAdapter DMDP\n"));
5302                                 PHY_SetTxPowerLevel8192D(Adapter, pHalData->CurrentChannel);
5303                         }
5304                 }
5305 #else
5306                 PHY_SetTxPowerLevel8192D(Adapter, pHalData->CurrentChannel);
5307 #endif
5308         }
5309         pdmpriv->LastDTPLvl = pdmpriv->DynamicTxHighPowerLvl;
5310 #endif
5311 #endif  // #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
5312
5313 }
5314
5315
5316 //3============================================================
5317 //3 RSSI Monitor
5318 //3============================================================
5319
5320 VOID
5321 odm_RSSIDumpToRegister(
5322         IN      PDM_ODM_T       pDM_Odm
5323         )
5324 {
5325 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
5326         PADAPTER                Adapter = pDM_Odm->Adapter;
5327
5328         if(pDM_Odm->SupportICType == ODM_RTL8812)
5329         {
5330                 PlatformEFIOWrite1Byte(Adapter, rA_RSSIDump_Jaguar, Adapter->RxStats.RxRSSIPercentage[0]);
5331                 PlatformEFIOWrite1Byte(Adapter, rB_RSSIDump_Jaguar, Adapter->RxStats.RxRSSIPercentage[1]);
5332
5333                 // Rx EVM
5334                 PlatformEFIOWrite1Byte(Adapter, rS1_RXevmDump_Jaguar, Adapter->RxStats.RxEVMdbm[0]);
5335                 PlatformEFIOWrite1Byte(Adapter, rS2_RXevmDump_Jaguar, Adapter->RxStats.RxEVMdbm[1]);
5336
5337                 // Rx SNR
5338                 PlatformEFIOWrite1Byte(Adapter, rA_RXsnrDump_Jaguar, (u1Byte)(Adapter->RxStats.RxSNRdB[0]));
5339                 PlatformEFIOWrite1Byte(Adapter, rB_RXsnrDump_Jaguar, (u1Byte)(Adapter->RxStats.RxSNRdB[1]));
5340
5341                 // Rx Cfo_Short
5342                 PlatformEFIOWrite2Byte(Adapter, rA_CfoShortDump_Jaguar, Adapter->RxStats.RxCfoShort[0]);
5343                 PlatformEFIOWrite2Byte(Adapter, rB_CfoShortDump_Jaguar, Adapter->RxStats.RxCfoShort[1]);
5344
5345                 // Rx Cfo_Tail
5346                 PlatformEFIOWrite2Byte(Adapter, rA_CfoLongDump_Jaguar, Adapter->RxStats.RxCfoTail[0]);
5347                 PlatformEFIOWrite2Byte(Adapter, rB_CfoLongDump_Jaguar, Adapter->RxStats.RxCfoTail[1]);
5348         }
5349         else if(pDM_Odm->SupportICType == ODM_RTL8192E)
5350         {
5351                 PlatformEFIOWrite1Byte(Adapter, rA_RSSIDump_92E, Adapter->RxStats.RxRSSIPercentage[0]);
5352                 PlatformEFIOWrite1Byte(Adapter, rB_RSSIDump_92E, Adapter->RxStats.RxRSSIPercentage[1]);
5353                 // Rx EVM
5354                 PlatformEFIOWrite1Byte(Adapter, rS1_RXevmDump_92E, Adapter->RxStats.RxEVMdbm[0]);
5355                 PlatformEFIOWrite1Byte(Adapter, rS2_RXevmDump_92E, Adapter->RxStats.RxEVMdbm[1]);
5356                 // Rx SNR
5357                 PlatformEFIOWrite1Byte(Adapter, rA_RXsnrDump_92E, (u1Byte)(Adapter->RxStats.RxSNRdB[0]));
5358                 PlatformEFIOWrite1Byte(Adapter, rB_RXsnrDump_92E, (u1Byte)(Adapter->RxStats.RxSNRdB[1]));
5359                 // Rx Cfo_Short
5360                 PlatformEFIOWrite2Byte(Adapter, rA_CfoShortDump_92E, Adapter->RxStats.RxCfoShort[0]);
5361                 PlatformEFIOWrite2Byte(Adapter, rB_CfoShortDump_92E, Adapter->RxStats.RxCfoShort[1]);
5362                 // Rx Cfo_Tail
5363                 PlatformEFIOWrite2Byte(Adapter, rA_CfoLongDump_92E, Adapter->RxStats.RxCfoTail[0]);
5364                 PlatformEFIOWrite2Byte(Adapter, rB_CfoLongDump_92E, Adapter->RxStats.RxCfoTail[1]);
5365          }
5366 #endif
5367 }
5368
5369
5370 VOID
5371 odm_RSSIMonitorInit(
5372         IN      PDM_ODM_T       pDM_Odm
5373         )
5374 {
5375         pRA_T           pRA_Table = &pDM_Odm->DM_RA_Table;
5376
5377         pRA_Table->firstconnect = FALSE;
5378
5379 }
5380
5381 VOID
5382 odm_RSSIMonitorCheck(
5383         IN              PDM_ODM_T               pDM_Odm
5384         )
5385 {
5386         //
5387         // For AP/ADSL use prtl8192cd_priv
5388         // For CE/NIC use PADAPTER
5389         //
5390
5391         if (!(pDM_Odm->SupportAbility & ODM_BB_RSSI_MONITOR))
5392                 return;
5393
5394         //
5395         // 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate
5396         // at the same time. In the stage2/3, we need to prive universal interface and merge all
5397         // HW dynamic mechanism.
5398         //
5399         switch  (pDM_Odm->SupportPlatform)
5400         {
5401                 case    ODM_WIN:
5402                         odm_RSSIMonitorCheckMP(pDM_Odm);
5403                         break;
5404
5405                 case    ODM_CE:
5406                         odm_RSSIMonitorCheckCE(pDM_Odm);
5407                         break;
5408
5409                 case    ODM_AP:
5410                         odm_RSSIMonitorCheckAP(pDM_Odm);
5411                         break;
5412
5413                 case    ODM_ADSL:
5414                         //odm_DIGAP(pDM_Odm);
5415                         break;
5416         }
5417
5418 }       // odm_RSSIMonitorCheck
5419
5420
5421 VOID
5422 odm_RSSIMonitorCheckMP(
5423         IN      PDM_ODM_T       pDM_Odm
5424         )
5425 {
5426 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
5427         PADAPTER                Adapter = pDM_Odm->Adapter;
5428         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
5429         PRT_WLAN_STA    pEntry;
5430         u1Byte                  i;
5431         s4Byte                  tmpEntryMaxPWDB=0, tmpEntryMinPWDB=0xff;
5432         u1Byte                  H2C_Parameter[4] ={0};
5433         PMGNT_INFO              pMgntInfo = &Adapter->MgntInfo;
5434         u8Byte                  curTxOkCnt = 0, curRxOkCnt = 0;
5435         u1Byte                  STBC_TX = 0;
5436         BOOLEAN                 FirstConnect;
5437         pRA_T                   pRA_Table = &pDM_Odm->DM_RA_Table;
5438 #if (BEAMFORMING_SUPPORT == 1)
5439         BEAMFORMING_CAP Beamform_cap = BEAMFORMING_CAP_NONE;
5440         u1Byte                  TxBF_EN = 0;
5441 #endif
5442
5443         RT_DISP(FDM, DM_PWDB, ("pHalData->UndecoratedSmoothedPWDB = 0x%x( %d)\n",
5444                 pHalData->UndecoratedSmoothedPWDB,
5445                 pHalData->UndecoratedSmoothedPWDB));
5446
5447         curTxOkCnt = Adapter->TxStats.NumTxBytesUnicast - pMgntInfo->lastTxOkCnt;
5448         curRxOkCnt = Adapter->RxStats.NumRxBytesUnicast - pMgntInfo->lastRxOkCnt;
5449         pMgntInfo->lastTxOkCnt = curTxOkCnt;
5450         pMgntInfo->lastRxOkCnt = curRxOkCnt;
5451
5452         RT_DISP(FDM, DM_PWDB, ("Tx = %d Rx = %d\n", curTxOkCnt, curRxOkCnt));
5453
5454        FirstConnect = (pHalData->bLinked) && (pRA_Table->firstconnect == FALSE);
5455         pRA_Table->firstconnect = pHalData->bLinked;
5456        H2C_Parameter[3] |= FirstConnect << 5;
5457
5458         if(pDM_Odm->SupportICType == ODM_RTL8188E && (pMgntInfo->CustomerID==RT_CID_819x_HP))
5459         {
5460                 if(curRxOkCnt >(curTxOkCnt*6))
5461                         PlatformEFIOWrite4Byte(Adapter, REG_ARFR0, 0x8f015);
5462                 else
5463                         PlatformEFIOWrite4Byte(Adapter, REG_ARFR0, 0xff015);
5464         }
5465
5466         if(pDM_Odm->SupportICType == ODM_RTL8812 || pDM_Odm->SupportICType == ODM_RTL8821)
5467         {
5468                 if(curRxOkCnt >(curTxOkCnt*6))
5469                         H2C_Parameter[3]=0x01;
5470                 else
5471                         H2C_Parameter[3]=0x00;
5472         }
5473
5474         for(i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++)
5475         {
5476                 if(IsAPModeExist(Adapter)  && GetFirstExtAdapter(Adapter) != NULL)
5477                 {
5478                         pEntry = AsocEntry_EnumStation(GetFirstExtAdapter(Adapter), i);
5479                 }
5480                 else
5481                 {
5482                         pEntry = AsocEntry_EnumStation(GetDefaultAdapter(Adapter), i);
5483                 }
5484
5485                 if(pEntry != NULL)
5486                 {
5487                         if(pEntry->bAssociated)
5488                         {
5489
5490                                 RT_DISP_ADDR(FDM, DM_PWDB, ("pEntry->MacAddr ="), pEntry->MacAddr);
5491                                 RT_DISP(FDM, DM_PWDB, ("pEntry->rssi = 0x%x(%d)\n",
5492                                         pEntry->rssi_stat.UndecoratedSmoothedPWDB, pEntry->rssi_stat.UndecoratedSmoothedPWDB));
5493
5494                                 if(pDM_Odm->SupportICType == ODM_RTL8192E || pDM_Odm->SupportICType == ODM_RTL8812)
5495                                 {
5496
5497 #if (BEAMFORMING_SUPPORT == 1)
5498                                         Beamform_cap = Beamforming_GetEntryBeamCapByMacId(pMgntInfo, pEntry->AssociatedMacId);
5499                                         if(Beamform_cap & (BEAMFORMER_CAP_HT_EXPLICIT |BEAMFORMER_CAP_VHT_SU))
5500                                                 TxBF_EN = 1;
5501                                         else
5502                                                 TxBF_EN = 0;
5503
5504                                         H2C_Parameter[3] |= TxBF_EN << 6;
5505
5506                                         if(TxBF_EN)
5507                                                 STBC_TX = 0;
5508                                         else
5509 #endif
5510                                         {
5511                                                 if(IS_WIRELESS_MODE_AC(Adapter))
5512                                                         STBC_TX = TEST_FLAG(pEntry->VHTInfo.STBC, STBC_VHT_ENABLE_TX);
5513                                                 else
5514                                                         STBC_TX = TEST_FLAG(pEntry->HTInfo.STBC, STBC_HT_ENABLE_TX);
5515                                         }
5516
5517                                         H2C_Parameter[3] |= STBC_TX << 1;
5518                                 }
5519
5520                                 if(pEntry->rssi_stat.UndecoratedSmoothedPWDB < tmpEntryMinPWDB)
5521                                         tmpEntryMinPWDB = pEntry->rssi_stat.UndecoratedSmoothedPWDB;
5522                                 if(pEntry->rssi_stat.UndecoratedSmoothedPWDB > tmpEntryMaxPWDB)
5523                                         tmpEntryMaxPWDB = pEntry->rssi_stat.UndecoratedSmoothedPWDB;
5524
5525                                 H2C_Parameter[2] = (u1Byte)(pEntry->rssi_stat.UndecoratedSmoothedPWDB & 0xFF);
5526                                 H2C_Parameter[1] = 0x20;   // fw v12 cmdid 5:use max macid ,for nic ,default macid is 0 ,max macid is 1
5527                                 H2C_Parameter[0] = (pEntry->AssociatedMacId);
5528                                 if(pDM_Odm->SupportICType == ODM_RTL8812)
5529                                         ODM_FillH2CCmd(Adapter, ODM_H2C_RSSI_REPORT, 4, H2C_Parameter);
5530                                 else if(pDM_Odm->SupportICType == ODM_RTL8192E)
5531                                         ODM_FillH2CCmd(Adapter, ODM_H2C_RSSI_REPORT, 4, H2C_Parameter);
5532                                 else
5533                                         ODM_FillH2CCmd(Adapter, ODM_H2C_RSSI_REPORT, 3, H2C_Parameter);
5534                         }
5535                 }
5536                 else
5537                 {
5538                         break;
5539                 }
5540         }
5541
5542         if(tmpEntryMaxPWDB != 0)        // If associated entry is found
5543         {
5544                 pHalData->EntryMaxUndecoratedSmoothedPWDB = tmpEntryMaxPWDB;
5545                 RT_DISP(FDM, DM_PWDB, ("EntryMaxPWDB = 0x%x(%d)\n",     tmpEntryMaxPWDB, tmpEntryMaxPWDB));
5546         }
5547         else
5548         {
5549                 pHalData->EntryMaxUndecoratedSmoothedPWDB = 0;
5550         }
5551
5552         if(tmpEntryMinPWDB != 0xff) // If associated entry is found
5553         {
5554                 pHalData->EntryMinUndecoratedSmoothedPWDB = tmpEntryMinPWDB;
5555                 RT_DISP(FDM, DM_PWDB, ("EntryMinPWDB = 0x%x(%d)\n", tmpEntryMinPWDB, tmpEntryMinPWDB));
5556
5557         }
5558         else
5559         {
5560                 pHalData->EntryMinUndecoratedSmoothedPWDB = 0;
5561         }
5562
5563         // Indicate Rx signal strength to FW.
5564         if(pHalData->bUseRAMask)
5565         {
5566                 if(pDM_Odm->SupportICType == ODM_RTL8192E || pDM_Odm->SupportICType == ODM_RTL8812)
5567                 {
5568                         PRT_HIGH_THROUGHPUT             pHTInfo = GET_HT_INFO(pMgntInfo);
5569                         PRT_VERY_HIGH_THROUGHPUT        pVHTInfo = GET_VHT_INFO(pMgntInfo);
5570
5571 #if (BEAMFORMING_SUPPORT == 1)
5572
5573                         Beamform_cap = Beamforming_GetEntryBeamCapByMacId(pMgntInfo, pMgntInfo->mMacId);
5574
5575                         if(Beamform_cap & (BEAMFORMER_CAP_HT_EXPLICIT |BEAMFORMER_CAP_VHT_SU))
5576                                 TxBF_EN = 1;
5577                         else
5578                                 TxBF_EN = 0;
5579
5580                         H2C_Parameter[3] |= TxBF_EN << 6;
5581
5582                         if(TxBF_EN)
5583                                 STBC_TX = 0;
5584                         else
5585 #endif
5586                         {
5587                                 if(IS_WIRELESS_MODE_AC(Adapter))
5588                                         STBC_TX = TEST_FLAG(pVHTInfo->VhtCurStbc, STBC_VHT_ENABLE_TX);
5589                                 else
5590                                         STBC_TX = TEST_FLAG(pHTInfo->HtCurStbc, STBC_HT_ENABLE_TX);
5591                         }
5592
5593                         H2C_Parameter[3] |= STBC_TX << 1;
5594                 }
5595
5596                 H2C_Parameter[2] = (u1Byte)(pHalData->UndecoratedSmoothedPWDB & 0xFF);
5597                 H2C_Parameter[1] = 0x20;        // fw v12 cmdid 5:use max macid ,for nic ,default macid is 0 ,max macid is 1
5598                 H2C_Parameter[0] = 0;           // fw v12 cmdid 5:use max macid ,for nic ,default macid is 0 ,max macid is 1
5599                 if(pDM_Odm->SupportICType == ODM_RTL8812)
5600                         ODM_FillH2CCmd(Adapter, ODM_H2C_RSSI_REPORT, 4, H2C_Parameter);
5601                 else  if(pDM_Odm->SupportICType == ODM_RTL8192E)
5602                         ODM_FillH2CCmd(Adapter, ODM_H2C_RSSI_REPORT, 4, H2C_Parameter);
5603                 else
5604                         ODM_FillH2CCmd(Adapter, ODM_H2C_RSSI_REPORT, 3, H2C_Parameter);
5605         }
5606         else
5607         {
5608                 PlatformEFIOWrite1Byte(Adapter, 0x4fe, (u1Byte)pHalData->UndecoratedSmoothedPWDB);
5609         }
5610
5611         if((pDM_Odm->SupportICType == ODM_RTL8812)||(pDM_Odm->SupportICType == ODM_RTL8192E))
5612                 odm_RSSIDumpToRegister(pDM_Odm);
5613
5614         odm_FindMinimumRSSI(Adapter);
5615         ODM_CmnInfoUpdate(&pHalData->DM_OutSrc ,ODM_CMNINFO_LINK, (u8Byte)pHalData->bLinked);
5616         ODM_CmnInfoUpdate(&pHalData->DM_OutSrc ,ODM_CMNINFO_RSSI_MIN, (u8Byte)pHalData->MinUndecoratedPWDBForDM);
5617 #endif  // #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
5618 }
5619
5620 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
5621 //
5622 //sherry move from DUSC to here 20110517
5623 //
5624 static VOID
5625 FindMinimumRSSI_Dmsp(
5626         IN      PADAPTER        pAdapter
5627 )
5628 {
5629 #if 0
5630         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);
5631         struct dm_priv  *pdmpriv = &pHalData->dmpriv;
5632         s32     Rssi_val_min_back_for_mac0;
5633         BOOLEAN         bGetValueFromBuddyAdapter = dm_DualMacGetParameterFromBuddyAdapter(pAdapter);
5634         BOOLEAN         bRestoreRssi = _FALSE;
5635         PADAPTER        BuddyAdapter = pAdapter->BuddyAdapter;
5636
5637         if(pHalData->MacPhyMode92D == DUALMAC_SINGLEPHY)
5638         {
5639                 if(BuddyAdapter!= NULL)
5640                 {
5641                         if(pHalData->bSlaveOfDMSP)
5642                         {
5643                                 //ODM_RT_TRACE(pDM_Odm,COMP_EASY_CONCURRENT,DBG_LOUD,("bSlavecase of dmsp\n"));
5644                                 BuddyAdapter->DualMacDMSPControl.RssiValMinForAnotherMacOfDMSP = pdmpriv->MinUndecoratedPWDBForDM;
5645                         }
5646                         else
5647                         {
5648                                 if(bGetValueFromBuddyAdapter)
5649                                 {
5650                                         //ODM_RT_TRACE(pDM_Odm,COMP_EASY_CONCURRENT,DBG_LOUD,("get new RSSI\n"));
5651                                         bRestoreRssi = _TRUE;
5652                                         Rssi_val_min_back_for_mac0 = pdmpriv->MinUndecoratedPWDBForDM;
5653                                         pdmpriv->MinUndecoratedPWDBForDM = pAdapter->DualMacDMSPControl.RssiValMinForAnotherMacOfDMSP;
5654                                 }
5655                         }
5656                 }
5657
5658         }
5659
5660         if(bRestoreRssi)
5661         {
5662                 bRestoreRssi = _FALSE;
5663                 pdmpriv->MinUndecoratedPWDBForDM = Rssi_val_min_back_for_mac0;
5664         }
5665 #endif
5666 }
5667
5668 static void
5669 FindMinimumRSSI(
5670 IN      PADAPTER        pAdapter
5671         )
5672 {
5673         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);
5674         struct dm_priv  *pdmpriv = &pHalData->dmpriv;
5675         PDM_ODM_T               pDM_Odm = &(pHalData->odmpriv);
5676
5677         //1 1.Determine the minimum RSSI
5678
5679         if((pDM_Odm->bLinked != _TRUE) &&
5680                 (pdmpriv->EntryMinUndecoratedSmoothedPWDB == 0))
5681         {
5682                 pdmpriv->MinUndecoratedPWDBForDM = 0;
5683                 //ODM_RT_TRACE(pDM_Odm,COMP_BB_POWERSAVING, DBG_LOUD, ("Not connected to any \n"));
5684         }
5685         else
5686         {
5687                 pdmpriv->MinUndecoratedPWDBForDM = pdmpriv->EntryMinUndecoratedSmoothedPWDB;
5688         }
5689
5690         //DBG_8192C("%s=>MinUndecoratedPWDBForDM(%d)\n",__FUNCTION__,pdmpriv->MinUndecoratedPWDBForDM);
5691         //ODM_RT_TRACE(pDM_Odm,COMP_DIG, DBG_LOUD, ("MinUndecoratedPWDBForDM =%d\n",pHalData->MinUndecoratedPWDBForDM));
5692 }
5693 #endif
5694
5695 VOID
5696 odm_RSSIMonitorCheckCE(
5697         IN              PDM_ODM_T               pDM_Odm
5698         )
5699 {
5700 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
5701         PADAPTER        Adapter = pDM_Odm->Adapter;
5702         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
5703         struct dm_priv  *pdmpriv = &pHalData->dmpriv;
5704         struct dvobj_priv       *pdvobjpriv = adapter_to_dvobj(Adapter);
5705         int     i;
5706         int     tmpEntryMaxPWDB=0, tmpEntryMinPWDB=0xff;
5707         u8      sta_cnt=0;
5708         u8      UL_DL_STATE = 0, STBC_TX = 0;
5709         u32     PWDB_rssi[NUM_STA]={0};//[0~15]:MACID, [16~31]:PWDB_rssi
5710         BOOLEAN                 FirstConnect = FALSE;
5711         pRA_T                   pRA_Table = &pDM_Odm->DM_RA_Table;
5712
5713         if(pDM_Odm->bLinked != _TRUE)
5714                 return;
5715
5716         #if((RTL8812A_SUPPORT==1)||(RTL8821A_SUPPORT==1))
5717         if((pDM_Odm->SupportICType == ODM_RTL8812)||(pDM_Odm->SupportICType == ODM_RTL8821))
5718         {
5719                 u64     curTxOkCnt = pdvobjpriv->traffic_stat.cur_tx_bytes;
5720                 u64     curRxOkCnt = pdvobjpriv->traffic_stat.cur_rx_bytes;
5721
5722                 if(curRxOkCnt >(curTxOkCnt*6))
5723                         UL_DL_STATE = 1;
5724                 else
5725                         UL_DL_STATE = 0;
5726         }
5727         #endif
5728
5729        FirstConnect = (pDM_Odm->bLinked) && (pRA_Table->firstconnect == FALSE);
5730         pRA_Table->firstconnect = pDM_Odm->bLinked;
5731
5732         //if(check_fwstate(&Adapter->mlmepriv, WIFI_AP_STATE|WIFI_ADHOC_STATE|WIFI_ADHOC_MASTER_STATE) == _TRUE)
5733         {
5734                 #if 1
5735                 struct sta_info *psta;
5736
5737                 for(i=0; i<ODM_ASSOCIATE_ENTRY_NUM; i++) {
5738                         if (IS_STA_VALID(psta = pDM_Odm->pODM_StaInfo[i]))
5739                         {
5740                                         if(IS_MCAST( psta->hwaddr))  //if(psta->mac_id ==1)
5741                                                  continue;
5742
5743                                         if(psta->rssi_stat.UndecoratedSmoothedPWDB == (-1))
5744                                                  continue;
5745
5746                                         if(psta->rssi_stat.UndecoratedSmoothedPWDB < tmpEntryMinPWDB)
5747                                                 tmpEntryMinPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB;
5748
5749                                         if(psta->rssi_stat.UndecoratedSmoothedPWDB > tmpEntryMaxPWDB)
5750                                                 tmpEntryMaxPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB;
5751
5752                                         #if 0
5753                                         DBG_871X("%s mac_id:%u, mac:"MAC_FMT", rssi:%d\n", __func__,
5754                                                 psta->mac_id, MAC_ARG(psta->hwaddr), psta->rssi_stat.UndecoratedSmoothedPWDB);
5755                                         #endif
5756
5757                                         if(psta->rssi_stat.UndecoratedSmoothedPWDB != (-1)) {
5758
5759                                                 #ifdef CONFIG_80211N_HT
5760                                                 if(pDM_Odm->SupportICType == ODM_RTL8192E || pDM_Odm->SupportICType == ODM_RTL8812)
5761                                                 {
5762                                                         #ifdef CONFIG_80211AC_VHT
5763                                                         if(IsSupportedVHT(psta->wireless_mode))
5764                                                                 STBC_TX = TEST_FLAG(psta->vhtpriv.stbc_cap, STBC_VHT_ENABLE_TX);
5765                                                         else
5766                                                         #endif
5767                                                                 STBC_TX = TEST_FLAG(psta->htpriv.stbc_cap, STBC_HT_ENABLE_TX);
5768                                                 }
5769                                                 #endif
5770
5771                                                 if(pDM_Odm->SupportICType == ODM_RTL8192D)
5772                                                         PWDB_rssi[sta_cnt++] = (psta->mac_id | (psta->rssi_stat.UndecoratedSmoothedPWDB<<16) | ((Adapter->stapriv.asoc_sta_count+1) << 8));
5773                                                 else if ((pDM_Odm->SupportICType == ODM_RTL8192E)||(pDM_Odm->SupportICType == ODM_RTL8812)||(pDM_Odm->SupportICType == ODM_RTL8821))
5774                                                         PWDB_rssi[sta_cnt++] = (((u8)(psta->mac_id&0xFF)) | ((psta->rssi_stat.UndecoratedSmoothedPWDB&0x7F)<<16) | (STBC_TX << 25) | (FirstConnect << 29));
5775                                                 else
5776                                                         PWDB_rssi[sta_cnt++] = (psta->mac_id | (psta->rssi_stat.UndecoratedSmoothedPWDB<<16) );
5777                                         }
5778                         }
5779                 }
5780                 #else
5781                 _irqL irqL;
5782                 _list   *plist, *phead;
5783                 struct sta_info *psta;
5784                 struct sta_priv *pstapriv = &Adapter->stapriv;
5785                 u8 bcast_addr[ETH_ALEN]= {0xff,0xff,0xff,0xff,0xff,0xff};
5786
5787                 _enter_critical_bh(&pstapriv->sta_hash_lock, &irqL);
5788
5789                 for(i=0; i< NUM_STA; i++)
5790                 {
5791                         phead = &(pstapriv->sta_hash[i]);
5792                         plist = get_next(phead);
5793
5794                         while ((rtw_end_of_queue_search(phead, plist)) == _FALSE)
5795                         {
5796                                 psta = LIST_CONTAINOR(plist, struct sta_info, hash_list);
5797
5798                                 plist = get_next(plist);
5799
5800                                 if(_rtw_memcmp(psta->hwaddr, bcast_addr, ETH_ALEN) ||
5801                                         _rtw_memcmp(psta->hwaddr, myid(&Adapter->eeprompriv), ETH_ALEN))
5802                                         continue;
5803
5804                                 if(psta->state & WIFI_ASOC_STATE)
5805                                 {
5806
5807                                         if(psta->rssi_stat.UndecoratedSmoothedPWDB < tmpEntryMinPWDB)
5808                                                 tmpEntryMinPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB;
5809
5810                                         if(psta->rssi_stat.UndecoratedSmoothedPWDB > tmpEntryMaxPWDB)
5811                                                 tmpEntryMaxPWDB = psta->rssi_stat.UndecoratedSmoothedPWDB;
5812
5813                                         if(psta->rssi_stat.UndecoratedSmoothedPWDB != (-1)){
5814                                                 //printk("%s==> mac_id(%d),rssi(%d)\n",__FUNCTION__,psta->mac_id,psta->rssi_stat.UndecoratedSmoothedPWDB);
5815                                                 #if(RTL8192D_SUPPORT==1)
5816                                                 PWDB_rssi[sta_cnt++] = (psta->mac_id | (psta->rssi_stat.UndecoratedSmoothedPWDB<<16) | ((Adapter->stapriv.asoc_sta_count+1) << 8));
5817                                                 #else
5818                                                 PWDB_rssi[sta_cnt++] = (psta->mac_id | (psta->rssi_stat.UndecoratedSmoothedPWDB<<16) );
5819                                                 #endif
5820                                         }
5821                                 }
5822
5823                         }
5824
5825                 }
5826
5827                 _exit_critical_bh(&pstapriv->sta_hash_lock, &irqL);
5828                 #endif
5829
5830                 //printk("%s==> sta_cnt(%d)\n",__FUNCTION__,sta_cnt);
5831
5832                 for(i=0; i< sta_cnt; i++)
5833                 {
5834                         if(PWDB_rssi[i] != (0)){
5835                                 if(pHalData->fw_ractrl == _TRUE)// Report every sta's RSSI to FW
5836                                 {
5837                                         #if(RTL8192D_SUPPORT==1)
5838                                         if(pDM_Odm->SupportICType == ODM_RTL8192D){
5839                                                 FillH2CCmd92D(Adapter, H2C_RSSI_REPORT, 3, (u8 *)(&PWDB_rssi[i]));
5840                                         }
5841                                         #endif
5842
5843                                         #if((RTL8192C_SUPPORT==1)||(RTL8723A_SUPPORT==1))
5844                                         if((pDM_Odm->SupportICType == ODM_RTL8192C)||(pDM_Odm->SupportICType == ODM_RTL8723A)){
5845                                                 rtl8192c_set_rssi_cmd(Adapter, (u8*)&PWDB_rssi[i]);
5846                                         }
5847                                         #endif
5848
5849                                         #if((RTL8812A_SUPPORT==1)||(RTL8821A_SUPPORT==1))
5850                                         if((pDM_Odm->SupportICType == ODM_RTL8812)||(pDM_Odm->SupportICType == ODM_RTL8821)){
5851                                                 PWDB_rssi[i] |= (UL_DL_STATE << 24);
5852                                                 rtl8812_set_rssi_cmd(Adapter, (u8 *)(&PWDB_rssi[i]));
5853                                         }
5854                                         #endif
5855                                         #if(RTL8192E_SUPPORT==1)
5856                                         if(pDM_Odm->SupportICType == ODM_RTL8192E){
5857                                                 rtl8192e_set_rssi_cmd(Adapter, (u8 *)(&PWDB_rssi[i]));
5858                                         }
5859                                         #endif
5860                                         #if(RTL8723B_SUPPORT==1)
5861                                         if(pDM_Odm->SupportICType == ODM_RTL8723B){
5862                                                 rtl8723b_set_rssi_cmd(Adapter, (u8 *)(&PWDB_rssi[i]));
5863                                         }
5864                                         #endif
5865                                 }
5866                                 else{
5867                                         #if((RTL8188E_SUPPORT==1)&&(RATE_ADAPTIVE_SUPPORT == 1))
5868                                         if(pDM_Odm->SupportICType == ODM_RTL8188E){
5869                                                 ODM_RA_SetRSSI_8188E(
5870                                                 &(pHalData->odmpriv), (PWDB_rssi[i]&0xFF), (u8)((PWDB_rssi[i]>>16) & 0xFF));
5871                                         }
5872                                         #endif
5873                                 }
5874                         }
5875                 }
5876         }
5877
5878
5879
5880         if(tmpEntryMaxPWDB != 0)        // If associated entry is found
5881         {
5882                 pdmpriv->EntryMaxUndecoratedSmoothedPWDB = tmpEntryMaxPWDB;
5883         }
5884         else
5885         {
5886                 pdmpriv->EntryMaxUndecoratedSmoothedPWDB = 0;
5887         }
5888
5889         if(tmpEntryMinPWDB != 0xff) // If associated entry is found
5890         {
5891                 pdmpriv->EntryMinUndecoratedSmoothedPWDB = tmpEntryMinPWDB;
5892         }
5893         else
5894         {
5895                 pdmpriv->EntryMinUndecoratedSmoothedPWDB = 0;
5896         }
5897
5898         FindMinimumRSSI(Adapter);//get pdmpriv->MinUndecoratedPWDBForDM
5899
5900         #if(RTL8192D_SUPPORT==1)
5901         FindMinimumRSSI_Dmsp(Adapter);
5902         #endif
5903         pDM_Odm->RSSI_Min = pdmpriv->MinUndecoratedPWDBForDM;
5904         //ODM_CmnInfoUpdate(&pHalData->odmpriv ,ODM_CMNINFO_RSSI_MIN, pdmpriv->MinUndecoratedPWDBForDM);
5905 #endif//if (DM_ODM_SUPPORT_TYPE == ODM_CE)
5906 }
5907 VOID
5908 odm_RSSIMonitorCheckAP(
5909         IN              PDM_ODM_T               pDM_Odm
5910         )
5911 {
5912 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
5913 #ifdef CONFIG_RTL_92C_SUPPORT || defined(CONFIG_RTL_92D_SUPPORT)
5914
5915         u4Byte i;
5916         PSTA_INFO_T pstat;
5917
5918         for(i=0; i<ODM_ASSOCIATE_ENTRY_NUM; i++)
5919         {
5920                 pstat = pDM_Odm->pODM_StaInfo[i];
5921                 if(IS_STA_VALID(pstat) )
5922                 {
5923 #ifdef STA_EXT
5924                         if (REMAP_AID(pstat) < (FW_NUM_STAT - 1))
5925 #endif
5926                                 add_update_rssi(pDM_Odm->priv, pstat);
5927
5928                 }
5929         }
5930 #endif
5931 #endif
5932
5933 }
5934
5935
5936
5937 VOID
5938 ODM_InitAllTimers(
5939         IN PDM_ODM_T    pDM_Odm
5940         )
5941 {
5942 #if(defined(CONFIG_HW_ANTENNA_DIVERSITY))
5943 #if (RTL8723B_SUPPORT == 1)||(RTL8821A_SUPPORT == 1)
5944         ODM_InitializeTimer(pDM_Odm,&pDM_Odm->DM_SWAT_Table.SwAntennaSwitchTimer_8723B,
5945         (RT_TIMER_CALL_BACK)ODM_SW_AntDiv_Callback, NULL, "SwAntennaSwitchTimer_8723B");
5946 #endif
5947 #endif
5948
5949 #if(defined(CONFIG_SW_ANTENNA_DIVERSITY))
5950         ODM_InitializeTimer(pDM_Odm,&pDM_Odm->DM_SWAT_Table.SwAntennaSwitchTimer,
5951                 (RT_TIMER_CALL_BACK)odm_SwAntDivChkAntSwitchCallback, NULL, "SwAntennaSwitchTimer");
5952 #endif
5953
5954 #if (!(DM_ODM_SUPPORT_TYPE == ODM_CE))
5955 #if(defined(CONFIG_HW_ANTENNA_DIVERSITY))
5956 #if (RTL8188E_SUPPORT == 1)
5957         ODM_InitializeTimer(pDM_Odm,&pDM_Odm->FastAntTrainingTimer,
5958                 (RT_TIMER_CALL_BACK)odm_FastAntTrainingCallback, NULL, "FastAntTrainingTimer");
5959 #endif
5960 #endif
5961 #endif
5962
5963 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
5964         ODM_InitializeTimer(pDM_Odm, &pDM_Odm->PSDTimer,
5965                 (RT_TIMER_CALL_BACK)dm_PSDMonitorCallback, NULL, "PSDTimer");
5966         //
5967         //Path Diversity
5968         //Neil Chen--2011--06--16--  / 2012/02/23 MH Revise Arch.
5969         //
5970         ODM_InitializeTimer(pDM_Odm, &pDM_Odm->PathDivSwitchTimer,
5971                 (RT_TIMER_CALL_BACK)odm_PathDivChkAntSwitchCallback, NULL, "PathDivTimer");
5972
5973         ODM_InitializeTimer(pDM_Odm, &pDM_Odm->CCKPathDiversityTimer,
5974                 (RT_TIMER_CALL_BACK)odm_CCKTXPathDiversityCallback, NULL, "CCKPathDiversityTimer");
5975
5976         ODM_InitializeTimer(pDM_Odm, &pDM_Odm->MPT_DIGTimer,
5977                 (RT_TIMER_CALL_BACK)odm_MPT_DIGCallback, NULL, "MPT_DIGTimer");
5978
5979         ODM_InitializeTimer(pDM_Odm, &pDM_Odm->DM_RXHP_Table.PSDTimer,
5980                 (RT_TIMER_CALL_BACK)odm_PSD_RXHPCallback, NULL, "PSDRXHPTimer");
5981 #endif
5982 }
5983
5984 VOID
5985 ODM_CancelAllTimers(
5986         IN PDM_ODM_T    pDM_Odm
5987         )
5988 {
5989 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
5990         //
5991         // 2012/01/12 MH Temp BSOD fix. We need to find NIC allocate mem fail reason in
5992         // win7 platform.
5993         //
5994         HAL_ADAPTER_STS_CHK(pDM_Odm)
5995 #endif
5996 #if(defined(CONFIG_HW_ANTENNA_DIVERSITY))
5997 #if (RTL8723B_SUPPORT == 1)||(RTL8821A_SUPPORT == 1)
5998         ODM_CancelTimer(pDM_Odm,&pDM_Odm->DM_SWAT_Table.SwAntennaSwitchTimer_8723B);
5999 #endif
6000 #endif
6001
6002 #if(defined(CONFIG_SW_ANTENNA_DIVERSITY))
6003         ODM_CancelTimer(pDM_Odm,&pDM_Odm->DM_SWAT_Table.SwAntennaSwitchTimer);
6004 #endif
6005
6006 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
6007
6008 #if (RTL8188E_SUPPORT == 1)
6009         ODM_CancelTimer(pDM_Odm,&pDM_Odm->FastAntTrainingTimer);
6010 #endif
6011         ODM_CancelTimer(pDM_Odm, &pDM_Odm->PSDTimer);
6012         //
6013         //Path Diversity
6014         //Neil Chen--2011--06--16--  / 2012/02/23 MH Revise Arch.
6015         //
6016         ODM_CancelTimer(pDM_Odm, &pDM_Odm->PathDivSwitchTimer);
6017
6018         ODM_CancelTimer(pDM_Odm, &pDM_Odm->CCKPathDiversityTimer);
6019
6020         ODM_CancelTimer(pDM_Odm, &pDM_Odm->MPT_DIGTimer);
6021
6022         ODM_CancelTimer(pDM_Odm, &pDM_Odm->DM_RXHP_Table.PSDTimer);
6023 #endif
6024 }
6025
6026
6027 VOID
6028 ODM_ReleaseAllTimers(
6029         IN PDM_ODM_T    pDM_Odm
6030         )
6031 {
6032 #if(defined(CONFIG_HW_ANTENNA_DIVERSITY))
6033 #if (RTL8723B_SUPPORT == 1)||(RTL8821A_SUPPORT == 1)
6034         ODM_ReleaseTimer(pDM_Odm,&pDM_Odm->DM_SWAT_Table.SwAntennaSwitchTimer_8723B);
6035 #endif
6036 #endif
6037
6038 #if(defined(CONFIG_SW_ANTENNA_DIVERSITY))
6039         ODM_ReleaseTimer(pDM_Odm,&pDM_Odm->DM_SWAT_Table.SwAntennaSwitchTimer);
6040 #endif
6041
6042 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
6043
6044 #if (RTL8188E_SUPPORT == 1)
6045         ODM_ReleaseTimer(pDM_Odm,&pDM_Odm->FastAntTrainingTimer);
6046 #endif
6047
6048         ODM_ReleaseTimer(pDM_Odm, &pDM_Odm->PSDTimer);
6049         //
6050         //Path Diversity
6051         //Neil Chen--2011--06--16--  / 2012/02/23 MH Revise Arch.
6052         //
6053         ODM_ReleaseTimer(pDM_Odm, &pDM_Odm->PathDivSwitchTimer);
6054
6055         ODM_ReleaseTimer(pDM_Odm, &pDM_Odm->CCKPathDiversityTimer);
6056
6057         ODM_ReleaseTimer(pDM_Odm, &pDM_Odm->MPT_DIGTimer);
6058
6059         ODM_ReleaseTimer(pDM_Odm, &pDM_Odm->DM_RXHP_Table.PSDTimer);
6060 #endif
6061 }
6062
6063
6064 //3============================================================
6065 //3 Tx Power Tracking
6066 //3============================================================
6067
6068 VOID
6069 odm_IQCalibrate(
6070                 IN      PDM_ODM_T       pDM_Odm
6071                 )
6072 {
6073         PADAPTER        Adapter = pDM_Odm->Adapter;
6074
6075         if(!IS_HARDWARE_TYPE_JAGUAR(Adapter))
6076                 return;
6077         else if(IS_HARDWARE_TYPE_8812AU(Adapter))
6078                 return;
6079 #if (RTL8821A_SUPPORT == 1)
6080         if(pDM_Odm->bLinked)
6081         {
6082                 if((*pDM_Odm->pChannel != pDM_Odm->preChannel) && (!*pDM_Odm->pbScanInProcess))
6083                 {
6084                         pDM_Odm->preChannel = *pDM_Odm->pChannel;
6085                         pDM_Odm->LinkedInterval = 0;
6086                 }
6087
6088                 if(pDM_Odm->LinkedInterval < 3)
6089                         pDM_Odm->LinkedInterval++;
6090
6091                 if(pDM_Odm->LinkedInterval == 2)
6092                 {
6093                         // Mark out IQK flow to prevent tx stuck. by Maddest 20130306
6094                         // Open it verified by James 20130715
6095                         PHY_IQCalibrate_8821A(Adapter, FALSE);
6096                 }
6097         }
6098         else
6099                 pDM_Odm->LinkedInterval = 0;
6100 #endif
6101 }
6102
6103
6104 VOID
6105 odm_TXPowerTrackingInit(
6106         IN      PDM_ODM_T       pDM_Odm
6107         )
6108 {
6109         odm_TXPowerTrackingThermalMeterInit(pDM_Odm);
6110 }
6111
6112 u1Byte
6113 getSwingIndex(
6114         IN      PDM_ODM_T       pDM_Odm
6115         )
6116 {
6117         PADAPTER                Adapter = pDM_Odm->Adapter;
6118         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
6119         u1Byte                  i = 0;
6120         u4Byte                  bbSwing;
6121         u4Byte                  swingTableSize;
6122         pu4Byte                         pSwingTable;
6123
6124         if (pDM_Odm->SupportICType == ODM_RTL8188E || pDM_Odm->SupportICType == ODM_RTL8723B ||
6125                 pDM_Odm->SupportICType == ODM_RTL8192E)
6126         {
6127                 bbSwing = PHY_QueryBBReg(Adapter, rOFDM0_XATxIQImbalance, 0xFFC00000);
6128
6129                 pSwingTable = OFDMSwingTable_New;
6130                 swingTableSize = OFDM_TABLE_SIZE;
6131         } else {
6132 #if ((RTL8812A_SUPPORT==1)||(RTL8821A_SUPPORT==1))
6133                 if (pDM_Odm->SupportICType == ODM_RTL8812 || pDM_Odm->SupportICType == ODM_RTL8821)
6134                 {
6135                         bbSwing = PHY_GetTxBBSwing_8812A(Adapter, pHalData->CurrentBandType, ODM_RF_PATH_A);
6136                         pSwingTable = TxScalingTable_Jaguar;
6137                         swingTableSize = TXSCALE_TABLE_SIZE;
6138                 }
6139                 else
6140 #endif
6141                 {
6142                         bbSwing = 0;
6143                         pSwingTable = OFDMSwingTable;
6144                         swingTableSize = OFDM_TABLE_SIZE;
6145                 }
6146         }
6147
6148         for (i = 0; i < swingTableSize; ++i) {
6149                 u4Byte tableValue = pSwingTable[i];
6150
6151                 if (tableValue >= 0x100000 )
6152                         tableValue >>= 22;
6153                 if (bbSwing == tableValue)
6154                         break;
6155         }
6156         return i;
6157 }
6158
6159 VOID
6160 odm_TXPowerTrackingThermalMeterInit(
6161         IN      PDM_ODM_T       pDM_Odm
6162         )
6163 {
6164         u1Byte defaultSwingIndex = getSwingIndex(pDM_Odm);
6165         u1Byte                  p = 0;
6166 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
6167         PADAPTER                Adapter = pDM_Odm->Adapter;
6168         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
6169
6170         #if     MP_DRIVER != 1                                  //for mp driver, turn off txpwrtracking as default
6171         pHalData->TxPowerTrackControl = TRUE;
6172         #endif
6173 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
6174         PADAPTER                        Adapter = pDM_Odm->Adapter;
6175         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(Adapter);
6176
6177
6178         if (pDM_Odm->SupportICType >= ODM_RTL8188E)
6179         {
6180                 pDM_Odm->RFCalibrateInfo.bTXPowerTracking = _TRUE;
6181                 pDM_Odm->RFCalibrateInfo.TXPowercount = 0;
6182                 pDM_Odm->RFCalibrateInfo.bTXPowerTrackingInit = _FALSE;
6183                 //#if   (MP_DRIVER != 1)                //for mp driver, turn off txpwrtracking as default
6184                 if ( *(pDM_Odm->mp_mode) != 1)
6185                         pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = _TRUE;
6186                 //#endif//#if   (MP_DRIVER != 1)
6187                 MSG_8192C("pDM_Odm TxPowerTrackControl = %d\n", pDM_Odm->RFCalibrateInfo.TxPowerTrackControl);
6188         }
6189         else
6190         {
6191                 struct dm_priv  *pdmpriv = &pHalData->dmpriv;
6192
6193                 pdmpriv->bTXPowerTracking = _TRUE;
6194                 pdmpriv->TXPowercount = 0;
6195                 pdmpriv->bTXPowerTrackingInit = _FALSE;
6196                 //#if   (MP_DRIVER != 1)                //for mp driver, turn off txpwrtracking as default
6197
6198                 if (*(pDM_Odm->mp_mode) != 1)
6199                         pdmpriv->TxPowerTrackControl = _TRUE;
6200                 //#endif//#if   (MP_DRIVER != 1)
6201
6202                 //MSG_8192C("pdmpriv->TxPowerTrackControl = %d\n", pdmpriv->TxPowerTrackControl);
6203         }
6204
6205 #elif (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
6206         #ifdef RTL8188E_SUPPORT
6207         {
6208                 pDM_Odm->RFCalibrateInfo.bTXPowerTracking = _TRUE;
6209                 pDM_Odm->RFCalibrateInfo.TXPowercount = 0;
6210                 pDM_Odm->RFCalibrateInfo.bTXPowerTrackingInit = _FALSE;
6211                 pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = _TRUE;
6212         }
6213         #endif
6214 #endif
6215
6216         pDM_Odm->RFCalibrateInfo.TxPowerTrackControl = TRUE;
6217         pDM_Odm->RFCalibrateInfo.ThermalValue = pHalData->EEPROMThermalMeter;
6218         pDM_Odm->RFCalibrateInfo.ThermalValue_IQK = pHalData->EEPROMThermalMeter;
6219         pDM_Odm->RFCalibrateInfo.ThermalValue_LCK = pHalData->EEPROMThermalMeter;
6220
6221         // The index of "0 dB" in SwingTable.
6222         if (pDM_Odm->SupportICType == ODM_RTL8188E || pDM_Odm->SupportICType == ODM_RTL8723B ||
6223                 pDM_Odm->SupportICType == ODM_RTL8192E)
6224         {
6225                 pDM_Odm->DefaultOfdmIndex = (defaultSwingIndex >= OFDM_TABLE_SIZE) ? 30 : defaultSwingIndex;
6226                 pDM_Odm->DefaultCckIndex = 20;
6227         }
6228         else
6229         {
6230                 pDM_Odm->DefaultOfdmIndex = (defaultSwingIndex >= TXSCALE_TABLE_SIZE) ? 24 : defaultSwingIndex;
6231                 pDM_Odm->DefaultCckIndex = 24;
6232         }
6233
6234         pDM_Odm->BbSwingIdxCckBase = pDM_Odm->DefaultCckIndex;
6235         pDM_Odm->RFCalibrateInfo.CCK_index = pDM_Odm->DefaultCckIndex;
6236
6237         for (p = ODM_RF_PATH_A; p < MAX_RF_PATH; ++p)
6238         {
6239                 pDM_Odm->BbSwingIdxOfdmBase[p] = pDM_Odm->DefaultOfdmIndex;
6240                 pDM_Odm->RFCalibrateInfo.OFDM_index[p] = pDM_Odm->DefaultOfdmIndex;
6241                 pDM_Odm->RFCalibrateInfo.DeltaPowerIndex[p] = 0;
6242                 pDM_Odm->RFCalibrateInfo.DeltaPowerIndexLast[p] = 0;
6243                 pDM_Odm->RFCalibrateInfo.PowerIndexOffset[p] = 0;
6244         }
6245
6246 }
6247
6248
6249 VOID
6250 ODM_TXPowerTrackingCheck(
6251         IN              PDM_ODM_T               pDM_Odm
6252         )
6253 {
6254         //
6255         // 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate
6256         // at the same time. In the stage2/3, we need to prive universal interface and merge all
6257         // HW dynamic mechanism.
6258         //
6259         switch  (pDM_Odm->SupportPlatform)
6260         {
6261                 case    ODM_WIN:
6262                         odm_TXPowerTrackingCheckMP(pDM_Odm);
6263                         break;
6264
6265                 case    ODM_CE:
6266                         odm_TXPowerTrackingCheckCE(pDM_Odm);
6267                         break;
6268
6269                 case    ODM_AP:
6270                         odm_TXPowerTrackingCheckAP(pDM_Odm);
6271                         break;
6272
6273                 case    ODM_ADSL:
6274                         //odm_DIGAP(pDM_Odm);
6275                         break;
6276         }
6277
6278 }
6279
6280 VOID
6281 odm_TXPowerTrackingCheckCE(
6282         IN              PDM_ODM_T               pDM_Odm
6283         )
6284 {
6285 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
6286         PADAPTER        Adapter = pDM_Odm->Adapter;
6287         #if( (RTL8192C_SUPPORT==1) ||  (RTL8723A_SUPPORT==1) )
6288         if(IS_HARDWARE_TYPE_8192C(Adapter)){
6289                 rtl8192c_odm_CheckTXPowerTracking(Adapter);
6290                 return;
6291         }
6292         #endif
6293
6294         #if (RTL8192D_SUPPORT==1)
6295         if(IS_HARDWARE_TYPE_8192D(Adapter)){
6296                 #if (RTL8192D_EASY_SMART_CONCURRENT == 1)
6297                 if(!Adapter->bSlaveOfDMSP)
6298                 #endif
6299                         rtl8192d_odm_CheckTXPowerTracking(Adapter);
6300                 return;
6301         }
6302         #endif
6303
6304         #if(((RTL8188E_SUPPORT==1) ||  (RTL8812A_SUPPORT==1) ||  (RTL8821A_SUPPORT==1) ||  (RTL8192E_SUPPORT==1)  ||  (RTL8723B_SUPPORT==1)  ))
6305         if(!(pDM_Odm->SupportAbility & ODM_RF_TX_PWR_TRACK))
6306         {
6307                 return;
6308         }
6309
6310         if(!pDM_Odm->RFCalibrateInfo.TM_Trigger)                //at least delay 1 sec
6311         {
6312                 //pHalData->TxPowerCheckCnt++;  //cosa add for debug
6313                 if(IS_HARDWARE_TYPE_8188E(Adapter) || IS_HARDWARE_TYPE_JAGUAR(Adapter) || IS_HARDWARE_TYPE_8192E(Adapter)||IS_HARDWARE_TYPE_8723B(Adapter))
6314                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_T_METER_NEW, (BIT17 | BIT16), 0x03);
6315                 else
6316                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_T_METER_OLD, bRFRegOffsetMask, 0x60);
6317
6318                 //DBG_871X("Trigger Thermal Meter!!\n");
6319
6320                 pDM_Odm->RFCalibrateInfo.TM_Trigger = 1;
6321                 return;
6322         }
6323         else
6324         {
6325                 //DBG_871X("Schedule TxPowerTracking direct call!!\n");
6326                 ODM_TXPowerTrackingCallback_ThermalMeter(Adapter);
6327                 pDM_Odm->RFCalibrateInfo.TM_Trigger = 0;
6328         }
6329         #endif
6330 #endif
6331 }
6332
6333 VOID
6334 odm_TXPowerTrackingCheckMP(
6335         IN              PDM_ODM_T               pDM_Odm
6336         )
6337 {
6338 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
6339         PADAPTER        Adapter = pDM_Odm->Adapter;
6340
6341         if (ODM_CheckPowerStatus(Adapter) == FALSE)
6342         {
6343                 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("===>ODM_CheckPowerStatus() return FALSE\n"));
6344                 return;
6345         }
6346
6347         if(IS_HARDWARE_TYPE_8723A(Adapter))
6348                 return;
6349
6350         if(!Adapter->bSlaveOfDMSP || Adapter->DualMacSmartConcurrent == FALSE)
6351                 odm_TXPowerTrackingThermalMeterCheck(Adapter);
6352         else {
6353                 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD, ("!Adapter->bSlaveOfDMSP || Adapter->DualMacSmartConcurrent == FALSE\n"));
6354         }
6355 #endif
6356
6357 }
6358
6359
6360 VOID
6361 odm_TXPowerTrackingCheckAP(
6362         IN              PDM_ODM_T               pDM_Odm
6363         )
6364 {
6365 #if (DM_ODM_SUPPORT_TYPE == ODM_AP)
6366         prtl8192cd_priv priv            = pDM_Odm->priv;
6367
6368         if ( (priv->pmib->dot11RFEntry.ther) && ((priv->up_time % priv->pshare->rf_ft_var.tpt_period) == 0)){
6369 #ifdef CONFIG_RTL_92D_SUPPORT
6370                 if (GET_CHIP_VER(priv)==VERSION_8192D){
6371                         tx_power_tracking_92D(priv);
6372                 } else
6373 #endif
6374                 {
6375 #ifdef CONFIG_RTL_92C_SUPPORT
6376                         tx_power_tracking(priv);
6377 #endif
6378                 }
6379         }
6380 #endif
6381
6382 }
6383
6384
6385
6386 //antenna mapping info
6387 // 1: right-side antenna
6388 // 2/0: left-side antenna
6389 //PDM_SWAT_Table->CCK_Ant1_Cnt /OFDM_Ant1_Cnt:  for right-side antenna:   Ant:1    RxDefaultAnt1
6390 //PDM_SWAT_Table->CCK_Ant2_Cnt /OFDM_Ant2_Cnt:  for left-side antenna:     Ant:0    RxDefaultAnt2
6391 // We select left antenna as default antenna in initial process, modify it as needed
6392 //
6393
6394 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
6395
6396 VOID
6397 odm_TXPowerTrackingThermalMeterCheck(
6398         IN      PADAPTER                Adapter
6399         )
6400 {
6401 #ifndef AP_BUILD_WORKAROUND
6402         static u1Byte                   TM_Trigger = 0;
6403
6404         if(!(GET_HAL_DATA(Adapter)->DM_OutSrc.SupportAbility & ODM_RF_TX_PWR_TRACK))
6405         {
6406                 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,
6407                         ("===>odm_TXPowerTrackingThermalMeterCheck(),pMgntInfo->bTXPowerTracking is FALSE, return!!\n"));
6408                 return;
6409         }
6410
6411         if(!TM_Trigger)         //at least delay 1 sec
6412         {
6413                 if(IS_HARDWARE_TYPE_8192D(Adapter))
6414                         PHY_SetRFReg(Adapter, ODM_RF_PATH_A, RF_T_METER_92D, BIT17 | BIT16, 0x03);
6415                 else if(IS_HARDWARE_TYPE_8188E(Adapter) || IS_HARDWARE_TYPE_JAGUAR(Adapter) || IS_HARDWARE_TYPE_8192E(Adapter) ||
6416                             IS_HARDWARE_TYPE_8723B(Adapter))
6417                         PHY_SetRFReg(Adapter, ODM_RF_PATH_A, RF_T_METER_88E, BIT17 | BIT16, 0x03);
6418                 else
6419                         PHY_SetRFReg(Adapter, ODM_RF_PATH_A, RF_T_METER, bRFRegOffsetMask, 0x60);
6420
6421                 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,("Trigger Thermal Meter!!\n"));
6422
6423                 TM_Trigger = 1;
6424                 return;
6425         }
6426         else
6427         {
6428                 RT_TRACE(COMP_POWER_TRACKING, DBG_LOUD,("Schedule TxPowerTracking direct call!!\n"));
6429                 odm_TXPowerTrackingDirectCall(Adapter); //Using direct call is instead, added by Roger, 2009.06.18.
6430                 TM_Trigger = 0;
6431         }
6432 #endif
6433 }
6434
6435 // Only for 8723A SW ANT DIV INIT--2012--07--17
6436 VOID
6437 odm_SwAntDivInit_NIC_8723A(
6438         IN      PDM_ODM_T               pDM_Odm)
6439 {
6440         pSWAT_T         pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
6441         PADAPTER                Adapter = pDM_Odm->Adapter;
6442
6443         u1Byte                  btAntNum=BT_GetPgAntNum(Adapter);
6444
6445         if(IS_HARDWARE_TYPE_8723A(Adapter))
6446         {
6447                 pDM_SWAT_Table->ANTA_ON =TRUE;
6448
6449                 // Set default antenna B status by PG
6450                 if(btAntNum == 2)
6451                         pDM_SWAT_Table->ANTB_ON = TRUE;
6452                 else if(btAntNum == 1)
6453                         pDM_SWAT_Table->ANTB_ON = FALSE;
6454                 else
6455                         pDM_SWAT_Table->ANTB_ON = TRUE;
6456         }
6457
6458 }
6459
6460 #endif //end #ifMP
6461
6462
6463
6464 //3============================================================
6465 //3 SW Antenna Diversity
6466 //3============================================================
6467 #if(defined(CONFIG_SW_ANTENNA_DIVERSITY))
6468 VOID
6469 odm_SwAntDivInit(
6470         IN              PDM_ODM_T               pDM_Odm
6471         )
6472 {
6473 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE))
6474         odm_SwAntDivInit_NIC(pDM_Odm);
6475 #elif(DM_ODM_SUPPORT_TYPE == ODM_AP)
6476         dm_SW_AntennaSwitchInit(pDM_Odm->priv);
6477 #endif
6478 }
6479
6480 VOID
6481 odm_SwAntDivInit_NIC(
6482         IN              PDM_ODM_T               pDM_Odm
6483         )
6484 {
6485         pSWAT_T         pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
6486
6487
6488 // Init SW ANT DIV mechanism for 8723AE/AU/AS
6489 // Neil Chen--2012--07--17---
6490 // CE/AP/ADSL no using SW ANT DIV for 8723A Series IC
6491 //#if (DM_ODM_SUPPORT_TYPE==ODM_WIN)
6492 #if (RTL8723A_SUPPORT==1)
6493         if(pDM_Odm->SupportICType == ODM_RTL8723A)
6494         {
6495                 odm_SwAntDivInit_NIC_8723A(pDM_Odm);
6496         }
6497 #endif
6498         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("SWAS:Init SW Antenna Switch\n"));
6499         pDM_SWAT_Table->RSSI_sum_A = 0;
6500         pDM_SWAT_Table->RSSI_cnt_A = 0;
6501         pDM_SWAT_Table->RSSI_sum_B = 0;
6502         pDM_SWAT_Table->RSSI_cnt_B = 0;
6503         pDM_SWAT_Table->CurAntenna = MAIN_ANT;
6504         pDM_SWAT_Table->PreAntenna = MAIN_ANT;
6505         pDM_SWAT_Table->try_flag = 0xff;
6506         pDM_SWAT_Table->PreRSSI = 0;
6507         pDM_SWAT_Table->SWAS_NoLink_State = 0;
6508         pDM_SWAT_Table->bTriggerAntennaSwitch = 0;
6509         pDM_SWAT_Table->SelectAntennaMap=0xAA;
6510         pDM_SWAT_Table->lastTxOkCnt = 0;
6511         pDM_SWAT_Table->lastRxOkCnt = 0;
6512         pDM_SWAT_Table->TXByteCnt_A = 0;
6513         pDM_SWAT_Table->TXByteCnt_B = 0;
6514         pDM_SWAT_Table->RXByteCnt_A = 0;
6515         pDM_SWAT_Table->RXByteCnt_B = 0;
6516         pDM_SWAT_Table->TrafficLoad = TRAFFIC_LOW;
6517         pDM_SWAT_Table->SWAS_NoLink_BK_Reg860 = ODM_Read4Byte(pDM_Odm, 0x860);
6518
6519 }
6520
6521 //
6522 // 20100514 Joseph:
6523 // Add new function to reset the state of antenna diversity before link.
6524 //
6525 VOID
6526 ODM_SwAntDivResetBeforeLink(
6527         IN              PDM_ODM_T               pDM_Odm
6528         )
6529 {
6530
6531         pSWAT_T         pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
6532
6533         pDM_SWAT_Table->SWAS_NoLink_State = 0;
6534
6535 }
6536
6537 //
6538 // 20100514 Luke/Joseph:
6539 // Add new function to reset antenna diversity state after link.
6540 //
6541 VOID
6542 ODM_SwAntDivRestAfterLink(
6543         IN              PDM_ODM_T               pDM_Odm
6544         )
6545 {
6546         pSWAT_T         pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
6547         pFAT_T          pDM_FatTable = &pDM_Odm->DM_FatTable;
6548         u4Byte             i;
6549
6550         if(pDM_Odm->SupportICType == ODM_RTL8723A)
6551         {
6552             pDM_SWAT_Table->RSSI_cnt_A = 0;
6553             pDM_SWAT_Table->RSSI_cnt_B = 0;
6554             pDM_Odm->RSSI_test = FALSE;
6555             pDM_SWAT_Table->try_flag = 0xff;
6556             pDM_SWAT_Table->RSSI_Trying = 0;
6557             pDM_SWAT_Table->SelectAntennaMap=0xAA;
6558
6559         }
6560         else if(pDM_Odm->SupportICType & (ODM_RTL8723B|ODM_RTL8821))
6561         {
6562                 pDM_Odm->RSSI_test = FALSE;
6563                 pDM_SWAT_Table->try_flag = 0xff;
6564                 pDM_SWAT_Table->RSSI_Trying = 0;
6565                 pDM_SWAT_Table->Double_chk_flag= 0;
6566
6567                 pDM_FatTable->RxIdleAnt=MAIN_ANT;
6568
6569                 for (i=0; i<ODM_ASSOCIATE_ENTRY_NUM; i++)
6570                 {
6571                         pDM_FatTable->MainAnt_Sum[i] = 0;
6572                         pDM_FatTable->AuxAnt_Sum[i] = 0;
6573                         pDM_FatTable->MainAnt_Cnt[i] = 0;
6574                         pDM_FatTable->AuxAnt_Cnt[i] = 0;
6575                 }
6576
6577         }
6578 }
6579
6580 void
6581 odm_SwAntDetectInit(
6582         IN              PDM_ODM_T               pDM_Odm
6583         )
6584 {
6585         pSWAT_T         pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
6586 #if (RTL8723B_SUPPORT == 1)
6587         pDM_SWAT_Table->SWAS_NoLink_BK_Reg92c = ODM_Read4Byte(pDM_Odm, rDPDT_control);
6588 #endif
6589         pDM_SWAT_Table->PreAntenna = MAIN_ANT;
6590         pDM_SWAT_Table->CurAntenna = MAIN_ANT;
6591         pDM_SWAT_Table->SWAS_NoLink_State = 0;
6592 }
6593
6594 VOID
6595 ODM_SwAntDivChkPerPktRssi(
6596         IN PDM_ODM_T    pDM_Odm,
6597         IN u1Byte               StationID,
6598         IN PODM_PHY_INFO_T pPhyInfo
6599         )
6600 {
6601         SWAT_T          *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
6602
6603         if(!(pDM_Odm->SupportAbility & (ODM_BB_ANT_DIV)))
6604                 return;
6605
6606 // temporary Fix 8723A MP SW ANT DIV Bug --NeilChen--2012--07--11
6607 #if (DM_ODM_SUPPORT_TYPE==ODM_WIN)
6608         if(pDM_Odm->SupportICType == ODM_RTL8723A)
6609         {
6610                 //if(StationID == pDM_SWAT_Table->RSSI_target)
6611                 //{
6612                 //1 RSSI for SW Antenna Switch
6613                 if(pDM_SWAT_Table->CurAntenna == MAIN_ANT)
6614                 {
6615                         pDM_SWAT_Table->RSSI_sum_A += pPhyInfo->RxPWDBAll;
6616                         pDM_SWAT_Table->RSSI_cnt_A++;
6617                 }
6618                 else
6619                 {
6620                         pDM_SWAT_Table->RSSI_sum_B += pPhyInfo->RxPWDBAll;
6621                         pDM_SWAT_Table->RSSI_cnt_B++;
6622
6623                 }
6624                 //}
6625         }
6626         else
6627         {
6628                 if(StationID == pDM_SWAT_Table->RSSI_target)
6629                 {
6630                         //1 RSSI for SW Antenna Switch
6631                         if(pDM_SWAT_Table->CurAntenna == MAIN_ANT)
6632                         {
6633                                 pDM_SWAT_Table->RSSI_sum_A += pPhyInfo->RxPWDBAll;
6634                                 pDM_SWAT_Table->RSSI_cnt_A++;
6635                         }
6636                         else
6637                         {
6638                                 pDM_SWAT_Table->RSSI_sum_B += pPhyInfo->RxPWDBAll;
6639                                 pDM_SWAT_Table->RSSI_cnt_B++;
6640
6641                         }
6642                 }
6643         }
6644 #else
6645         if(StationID == pDM_SWAT_Table->RSSI_target)
6646         {
6647                 //1 RSSI for SW Antenna Switch
6648                 if(pDM_SWAT_Table->CurAntenna == MAIN_ANT)
6649                 {
6650                         pDM_SWAT_Table->RSSI_sum_A += pPhyInfo->RxPWDBAll;
6651                         pDM_SWAT_Table->RSSI_cnt_A++;
6652                 }
6653                 else
6654                 {
6655                         pDM_SWAT_Table->RSSI_sum_B += pPhyInfo->RxPWDBAll;
6656                         pDM_SWAT_Table->RSSI_cnt_B++;
6657
6658                 }
6659         }
6660 #endif
6661 }
6662
6663 //
6664 VOID
6665 odm_SwAntDivChkAntSwitch(
6666         IN              PDM_ODM_T               pDM_Odm,
6667         IN              u1Byte                  Step
6668         )
6669 {
6670         //
6671         // For AP/ADSL use prtl8192cd_priv
6672         // For CE/NIC use PADAPTER
6673         //
6674         prtl8192cd_priv priv            = pDM_Odm->priv;
6675
6676         //
6677         // 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate
6678         // at the same time. In the stage2/3, we need to prive universal interface and merge all
6679         // HW dynamic mechanism.
6680         //
6681         switch  (pDM_Odm->SupportPlatform)
6682         {
6683                 case    ODM_WIN:
6684                         odm_SwAntDivChkAntSwitchNIC(pDM_Odm, Step);
6685                         break;
6686                 case    ODM_CE:
6687                         odm_SwAntDivChkAntSwitchNIC(pDM_Odm, Step);
6688                         break;
6689
6690                 case    ODM_AP:
6691                 case    ODM_ADSL:
6692 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP |ODM_ADSL))
6693                         if (priv->pshare->rf_ft_var.antSw_enable && (priv->up_time % 4==1))
6694                                 dm_SW_AntennaSwitch(priv, SWAW_STEP_PEAK);
6695 #endif
6696                         break;
6697         }
6698
6699 }
6700
6701 //
6702 // 20100514 Luke/Joseph:
6703 // Add new function for antenna diversity after link.
6704 // This is the main function of antenna diversity after link.
6705 // This function is called in HalDmWatchDog() and ODM_SwAntDivChkAntSwitchCallback().
6706 // HalDmWatchDog() calls this function with SWAW_STEP_PEAK to initialize the antenna test.
6707 // In SWAW_STEP_PEAK, another antenna and a 500ms timer will be set for testing.
6708 // After 500ms, ODM_SwAntDivChkAntSwitchCallback() calls this function to compare the signal just
6709 // listened on the air with the RSSI of original antenna.
6710 // It chooses the antenna with better RSSI.
6711 // There is also a aged policy for error trying. Each error trying will cost more 5 seconds waiting
6712 // penalty to get next try.
6713
6714
6715 VOID
6716 ODM_SetAntenna(
6717         IN      PDM_ODM_T       pDM_Odm,
6718         IN      u1Byte          Antenna)
6719 {
6720         ODM_SetBBReg(pDM_Odm, 0x860, BIT8|BIT9, Antenna);
6721 }
6722
6723 VOID
6724 odm_SwAntDivChkAntSwitchNIC(
6725         IN              PDM_ODM_T               pDM_Odm,
6726         IN              u1Byte          Step
6727         )
6728 {
6729 #if ((RTL8192C_SUPPORT==1)||(RTL8723A_SUPPORT==1))
6730         //PMGNT_INFO            pMgntInfo = &(Adapter->MgntInfo);
6731         //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
6732
6733 #if (DM_ODM_SUPPORT_TYPE==ODM_WIN)
6734         PADAPTER                Adapter=pDM_Odm->Adapter;
6735 #endif
6736
6737         pSWAT_T         pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
6738         s4Byte                  curRSSI=100, RSSI_A, RSSI_B;
6739         u1Byte                  nextAntenna=AUX_ANT;
6740         //static u8Byte         lastTxOkCnt=0, lastRxOkCnt=0;
6741         u8Byte                  curTxOkCnt=0, curRxOkCnt=0;
6742         //static u8Byte         TXByteCnt_A=0, TXByteCnt_B=0, RXByteCnt_A=0, RXByteCnt_B=0;
6743         u8Byte                  CurByteCnt=0, PreByteCnt=0;
6744         //static u1Byte         TrafficLoad = TRAFFIC_LOW;
6745         u1Byte                  Score_A=0, Score_B=0;       //A: Main; B: AUX
6746         u1Byte                  i;
6747
6748         if(!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV))
6749                 return;
6750
6751         if (pDM_Odm->SupportICType & (ODM_RTL8192D|ODM_RTL8188E))
6752                 return;
6753
6754         if((pDM_Odm->SupportICType == ODM_RTL8192C) &&(pDM_Odm->RFType == ODM_2T2R))
6755                 return;
6756
6757         if(pDM_Odm->SupportPlatform & ODM_WIN)
6758         {
6759                 if(*(pDM_Odm->pAntennaTest))
6760                         return;
6761         }
6762
6763         if((pDM_SWAT_Table->ANTA_ON == FALSE) ||(pDM_SWAT_Table->ANTB_ON == FALSE))
6764         {
6765                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
6766                                 ("odm_SwAntDivChkAntSwitch(): No AntDiv Mechanism, Antenna A or B is off\n"));
6767                 return;
6768         }
6769
6770         // Radio off: Status reset to default and return.
6771         if(*(pDM_Odm->pbPowerSaving)==TRUE) //pHalData->eRFPowerState==eRfOff
6772         {
6773                 ODM_SwAntDivRestAfterLink(pDM_Odm);
6774                 return;
6775         }
6776
6777
6778         // Handling step mismatch condition.
6779         // Peak step is not finished at last time. Recover the variable and check again.
6780         if(     Step != pDM_SWAT_Table->try_flag        )
6781         {
6782                 ODM_SwAntDivRestAfterLink(pDM_Odm);
6783         }
6784
6785 #if  (DM_ODM_SUPPORT_TYPE &( ODM_WIN| ODM_CE ))
6786
6787         if(pDM_SWAT_Table->try_flag == 0xff)
6788         {
6789                 pDM_SWAT_Table->RSSI_target = 0xff;
6790
6791                 #if(DM_ODM_SUPPORT_TYPE & ODM_CE)
6792                 {
6793                         u1Byte                  index = 0;
6794                         PSTA_INFO_T             pEntry = NULL;
6795
6796
6797                         for(index=0; index<ODM_ASSOCIATE_ENTRY_NUM; index++)
6798                         {
6799                                 pEntry =  pDM_Odm->pODM_StaInfo[index];
6800                                 if(IS_STA_VALID(pEntry) ) {
6801                                         break;
6802                                 }
6803                         }
6804                         if(pEntry == NULL)
6805                         {
6806                                 ODM_SwAntDivRestAfterLink(pDM_Odm);
6807                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_SwAntDivChkAntSwitch(): No Link.\n"));
6808                                 return;
6809                         }
6810                         else
6811                         {
6812                                 pDM_SWAT_Table->RSSI_target = index;
6813                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_SwAntDivChkAntSwitch(): RSSI_target is PEER STA\n"));
6814                         }
6815                 }
6816                 #elif (DM_ODM_SUPPORT_TYPE & ODM_WIN)
6817                 {
6818                         PADAPTER        pAdapter         =  pDM_Odm->Adapter;
6819                         PMGNT_INFO      pMgntInfo=&pAdapter->MgntInfo;
6820
6821                         // Select RSSI checking target
6822                         if(pMgntInfo->mAssoc && !ACTING_AS_AP(pAdapter))
6823                         {
6824                                 // Target: Infrastructure mode AP.
6825                                 //pDM_SWAT_Table->RSSI_target = NULL;
6826                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("odm_SwAntDivChkAntSwitch(): RSSI_target is DEF AP!\n"));
6827                         }
6828                         else
6829                         {
6830                                 u1Byte                  index = 0;
6831                                 PSTA_INFO_T             pEntry = NULL;
6832                                 PADAPTER                pTargetAdapter = NULL;
6833
6834                                 if(pMgntInfo->mIbss )
6835                                 {
6836                                         // Target: AP/IBSS peer.
6837                                         pTargetAdapter = pAdapter;
6838                                 }
6839                                 else
6840                                 {
6841                                         pTargetAdapter = GetFirstAPAdapter(pAdapter);
6842                                 }
6843
6844                                 if(pTargetAdapter != NULL)
6845                                 {
6846                                         for(index=0; index<ODM_ASSOCIATE_ENTRY_NUM; index++)
6847                                         {
6848
6849                                                 pEntry = AsocEntry_EnumStation(pTargetAdapter, index);
6850                                                 if(pEntry != NULL)
6851                                                 {
6852                                                         if(pEntry->bAssociated)
6853                                                                 break;
6854                                                 }
6855
6856                                         }
6857
6858                                 }
6859
6860                                 if(pEntry == NULL)
6861                                 {
6862                                         ODM_SwAntDivRestAfterLink(pDM_Odm);
6863                                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_SwAntDivChkAntSwitch(): No Link.\n"));
6864                                         return;
6865                                 }
6866                                 else
6867                                 {
6868                                         //pDM_SWAT_Table->RSSI_target = pEntry;
6869                                         pDM_SWAT_Table->RSSI_target = index;
6870                                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("odm_SwAntDivChkAntSwitch(): RSSI_target is PEER STA\n"));
6871                                 }
6872                         }//end if(pMgntInfo->mAssoc && !ACTING_AS_AP(Adapter))
6873
6874                 }
6875                 #endif
6876
6877                 pDM_SWAT_Table->RSSI_cnt_A = 0;
6878                 pDM_SWAT_Table->RSSI_cnt_B = 0;
6879                 pDM_SWAT_Table->try_flag = 0;
6880                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("odm_SwAntDivChkAntSwitch(): Set try_flag to 0 prepare for peak!\n"));
6881                 return;
6882         }
6883         else
6884         {
6885
6886 // To Fix 8723A SW ANT DIV Bug issue
6887 #if (DM_ODM_SUPPORT_TYPE==ODM_WIN)
6888                 if (pDM_Odm->SupportICType & ODM_RTL8723A)
6889                 {
6890                         curTxOkCnt = Adapter->TxStats.NumTxBytesUnicast - pDM_SWAT_Table->lastTxOkCnt;
6891                         curRxOkCnt =Adapter->RxStats.NumRxBytesUnicast - pDM_SWAT_Table->lastRxOkCnt;
6892                         pDM_SWAT_Table->lastTxOkCnt = Adapter->TxStats.NumTxBytesUnicast;
6893                         pDM_SWAT_Table->lastRxOkCnt = Adapter->RxStats.NumRxBytesUnicast;
6894                 }
6895 #else
6896                 curTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast) - pDM_SWAT_Table->lastTxOkCnt;
6897                 curRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast) - pDM_SWAT_Table->lastRxOkCnt;
6898                 pDM_SWAT_Table->lastTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast);
6899                 pDM_SWAT_Table->lastRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast);
6900 #endif
6901                 if(pDM_SWAT_Table->try_flag == 1)
6902                 {
6903                         if(pDM_SWAT_Table->CurAntenna == MAIN_ANT)
6904                         {
6905                                 pDM_SWAT_Table->TXByteCnt_A += curTxOkCnt;
6906                                 pDM_SWAT_Table->RXByteCnt_A += curRxOkCnt;
6907                         }
6908                         else
6909                         {
6910                                 pDM_SWAT_Table->TXByteCnt_B += curTxOkCnt;
6911                                 pDM_SWAT_Table->RXByteCnt_B += curRxOkCnt;
6912                         }
6913
6914                         nextAntenna = (pDM_SWAT_Table->CurAntenna == MAIN_ANT)? AUX_ANT : MAIN_ANT;
6915                         pDM_SWAT_Table->RSSI_Trying--;
6916                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("RSSI_Trying = %d\n",pDM_SWAT_Table->RSSI_Trying));
6917                         if(pDM_SWAT_Table->RSSI_Trying == 0)
6918                         {
6919                                 CurByteCnt = (pDM_SWAT_Table->CurAntenna == MAIN_ANT)? (pDM_SWAT_Table->TXByteCnt_A+pDM_SWAT_Table->RXByteCnt_A) : (pDM_SWAT_Table->TXByteCnt_B+pDM_SWAT_Table->RXByteCnt_B);
6920                                 PreByteCnt = (pDM_SWAT_Table->CurAntenna == MAIN_ANT)? (pDM_SWAT_Table->TXByteCnt_B+pDM_SWAT_Table->RXByteCnt_B) : (pDM_SWAT_Table->TXByteCnt_A+pDM_SWAT_Table->RXByteCnt_A);
6921
6922                                 if(pDM_SWAT_Table->TrafficLoad == TRAFFIC_HIGH)
6923                                         //CurByteCnt = PlatformDivision64(CurByteCnt, 9);
6924                                         PreByteCnt = PreByteCnt*9;
6925                                 else if(pDM_SWAT_Table->TrafficLoad == TRAFFIC_LOW)
6926                                         //CurByteCnt = PlatformDivision64(CurByteCnt, 2);
6927                                         PreByteCnt = PreByteCnt*2;
6928
6929                                 if(pDM_SWAT_Table->RSSI_cnt_A > 0)
6930                                         RSSI_A = pDM_SWAT_Table->RSSI_sum_A/pDM_SWAT_Table->RSSI_cnt_A;
6931                                 else
6932                                         RSSI_A = 0;
6933                                 if(pDM_SWAT_Table->RSSI_cnt_B > 0)
6934                                         RSSI_B = pDM_SWAT_Table->RSSI_sum_B/pDM_SWAT_Table->RSSI_cnt_B;
6935                                 else
6936                                         RSSI_B = 0;
6937                                 curRSSI = (pDM_SWAT_Table->CurAntenna == MAIN_ANT)? RSSI_A : RSSI_B;
6938                                 pDM_SWAT_Table->PreRSSI =  (pDM_SWAT_Table->CurAntenna == MAIN_ANT)? RSSI_B : RSSI_A;
6939                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Luke:PreRSSI = %d, CurRSSI = %d\n",pDM_SWAT_Table->PreRSSI, curRSSI));
6940                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("SWAS: preAntenna= %s, curAntenna= %s \n",
6941                                 (pDM_SWAT_Table->PreAntenna == MAIN_ANT?"MAIN":"AUX"), (pDM_SWAT_Table->CurAntenna == MAIN_ANT?"MAIN":"AUX")));
6942                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Luke:RSSI_A= %d, RSSI_cnt_A = %d, RSSI_B= %d, RSSI_cnt_B = %d\n",
6943                                         RSSI_A, pDM_SWAT_Table->RSSI_cnt_A, RSSI_B, pDM_SWAT_Table->RSSI_cnt_B));
6944                         }
6945
6946                 }
6947                 else
6948                 {
6949
6950                         if(pDM_SWAT_Table->RSSI_cnt_A > 0)
6951                                 RSSI_A = pDM_SWAT_Table->RSSI_sum_A/pDM_SWAT_Table->RSSI_cnt_A;
6952                         else
6953                                 RSSI_A = 0;
6954                         if(pDM_SWAT_Table->RSSI_cnt_B > 0)
6955                                 RSSI_B = pDM_SWAT_Table->RSSI_sum_B/pDM_SWAT_Table->RSSI_cnt_B;
6956                         else
6957                                 RSSI_B = 0;
6958                         curRSSI = (pDM_SWAT_Table->CurAntenna == MAIN_ANT)? RSSI_A : RSSI_B;
6959                         pDM_SWAT_Table->PreRSSI =  (pDM_SWAT_Table->PreAntenna == MAIN_ANT)? RSSI_A : RSSI_B;
6960                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Ekul:PreRSSI = %d, CurRSSI = %d\n", pDM_SWAT_Table->PreRSSI, curRSSI));
6961                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("SWAS: preAntenna= %s, curAntenna= %s \n",
6962                         (pDM_SWAT_Table->PreAntenna == MAIN_ANT?"MAIN":"AUX"), (pDM_SWAT_Table->CurAntenna == MAIN_ANT?"MAIN":"AUX")));
6963
6964                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Ekul:RSSI_A= %d, RSSI_cnt_A = %d, RSSI_B= %d, RSSI_cnt_B = %d\n",
6965                                 RSSI_A, pDM_SWAT_Table->RSSI_cnt_A, RSSI_B, pDM_SWAT_Table->RSSI_cnt_B));
6966                         //RT_TRACE(COMP_SWAS, DBG_LOUD, ("Ekul:curTxOkCnt = %d\n", curTxOkCnt));
6967                         //RT_TRACE(COMP_SWAS, DBG_LOUD, ("Ekul:curRxOkCnt = %d\n", curRxOkCnt));
6968                 }
6969
6970                 //1 Trying State
6971                 if((pDM_SWAT_Table->try_flag == 1)&&(pDM_SWAT_Table->RSSI_Trying == 0))
6972                 {
6973
6974                         if(pDM_SWAT_Table->TestMode == TP_MODE)
6975                         {
6976                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("SWAS: TestMode = TP_MODE"));
6977                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("TRY:CurByteCnt = %lld,", CurByteCnt));
6978                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("TRY:PreByteCnt = %lld\n",PreByteCnt));
6979                                 if(CurByteCnt < PreByteCnt)
6980                                 {
6981                                         if(pDM_SWAT_Table->CurAntenna == MAIN_ANT)
6982                                                 pDM_SWAT_Table->SelectAntennaMap=pDM_SWAT_Table->SelectAntennaMap<<1;
6983                                         else
6984                                                 pDM_SWAT_Table->SelectAntennaMap=(pDM_SWAT_Table->SelectAntennaMap<<1)+1;
6985                                 }
6986                                 else
6987                                 {
6988                                         if(pDM_SWAT_Table->CurAntenna == MAIN_ANT)
6989                                                 pDM_SWAT_Table->SelectAntennaMap=(pDM_SWAT_Table->SelectAntennaMap<<1)+1;
6990                                         else
6991                                                 pDM_SWAT_Table->SelectAntennaMap=pDM_SWAT_Table->SelectAntennaMap<<1;
6992                                 }
6993                                 for (i= 0; i<8; i++)
6994                                 {
6995                                         if(((pDM_SWAT_Table->SelectAntennaMap>>i)&BIT0) == 1)
6996                                                 Score_A++;
6997                                         else
6998                                                 Score_B++;
6999                                 }
7000                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("SelectAntennaMap=%x\n ",pDM_SWAT_Table->SelectAntennaMap));
7001                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Score_A=%d, Score_B=%d\n", Score_A, Score_B));
7002
7003                                 if(pDM_SWAT_Table->CurAntenna == MAIN_ANT)
7004                                 {
7005                                         nextAntenna = (Score_A > Score_B)?MAIN_ANT:AUX_ANT;
7006                                 }
7007                                 else
7008                                 {
7009                                         nextAntenna = (Score_B > Score_A)?AUX_ANT:MAIN_ANT;
7010                                 }
7011                                 //RT_TRACE(COMP_SWAS, DBG_LOUD, ("nextAntenna=%s\n",(nextAntenna==Antenna_A)?"A":"B"));
7012                                 //RT_TRACE(COMP_SWAS, DBG_LOUD, ("preAntenna= %s, curAntenna= %s \n",
7013                                 //(DM_SWAT_Table.PreAntenna == Antenna_A?"A":"B"), (DM_SWAT_Table.CurAntenna == Antenna_A?"A":"B")));
7014
7015                                 if(nextAntenna != pDM_SWAT_Table->CurAntenna)
7016                                 {
7017                                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("SWAS: Switch back to another antenna"));
7018                                 }
7019                                 else
7020                                 {
7021                                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("SWAS: current anntena is good\n"));
7022                                 }
7023                         }
7024
7025                         if(pDM_SWAT_Table->TestMode == RSSI_MODE)
7026                         {
7027                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("SWAS: TestMode = RSSI_MODE"));
7028                                 pDM_SWAT_Table->SelectAntennaMap=0xAA;
7029                                 if(curRSSI < pDM_SWAT_Table->PreRSSI) //Current antenna is worse than previous antenna
7030                                 {
7031                                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("SWAS: Switch back to another antenna"));
7032                                         nextAntenna = (pDM_SWAT_Table->CurAntenna == MAIN_ANT)? AUX_ANT : MAIN_ANT;
7033                                 }
7034                                 else // current anntena is good
7035                                 {
7036                                         nextAntenna =pDM_SWAT_Table->CurAntenna;
7037                                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("SWAS: current anntena is good\n"));
7038                                 }
7039                         }
7040                         pDM_SWAT_Table->try_flag = 0;
7041                         pDM_Odm->RSSI_test = FALSE;
7042                         pDM_SWAT_Table->RSSI_sum_A = 0;
7043                         pDM_SWAT_Table->RSSI_cnt_A = 0;
7044                         pDM_SWAT_Table->RSSI_sum_B = 0;
7045                         pDM_SWAT_Table->RSSI_cnt_B = 0;
7046                         pDM_SWAT_Table->TXByteCnt_A = 0;
7047                         pDM_SWAT_Table->TXByteCnt_B = 0;
7048                         pDM_SWAT_Table->RXByteCnt_A = 0;
7049                         pDM_SWAT_Table->RXByteCnt_B = 0;
7050
7051                 }
7052
7053                 //1 Normal State
7054                 else if(pDM_SWAT_Table->try_flag == 0)
7055                 {
7056                         if(pDM_SWAT_Table->TrafficLoad == TRAFFIC_HIGH)
7057                         {
7058                                 if ((curTxOkCnt+curRxOkCnt) > 3750000)//if(PlatformDivision64(curTxOkCnt+curRxOkCnt, 2) > 1875000)
7059                                         pDM_SWAT_Table->TrafficLoad = TRAFFIC_HIGH;
7060                                 else
7061                                         pDM_SWAT_Table->TrafficLoad = TRAFFIC_LOW;
7062                         }
7063                         else if(pDM_SWAT_Table->TrafficLoad == TRAFFIC_LOW)
7064                                 {
7065                                 if ((curTxOkCnt+curRxOkCnt) > 3750000) //if(PlatformDivision64(curTxOkCnt+curRxOkCnt, 2) > 1875000)
7066                                         pDM_SWAT_Table->TrafficLoad = TRAFFIC_HIGH;
7067                                 else
7068                                         pDM_SWAT_Table->TrafficLoad = TRAFFIC_LOW;
7069                         }
7070                         if(pDM_SWAT_Table->TrafficLoad == TRAFFIC_HIGH)
7071                                 pDM_SWAT_Table->bTriggerAntennaSwitch = 0;
7072                         //RT_TRACE(COMP_SWAS, DBG_LOUD, ("Normal:TrafficLoad = %llu\n", curTxOkCnt+curRxOkCnt));
7073
7074                         //Prepare To Try Antenna
7075                                         nextAntenna = (pDM_SWAT_Table->CurAntenna == MAIN_ANT)? AUX_ANT : MAIN_ANT;
7076                                         pDM_SWAT_Table->try_flag = 1;
7077                                         pDM_Odm->RSSI_test = TRUE;
7078                         if((curRxOkCnt+curTxOkCnt) > 1000)
7079                         {
7080                                 pDM_SWAT_Table->RSSI_Trying = 4;
7081                                 pDM_SWAT_Table->TestMode = TP_MODE;
7082                                 }
7083                                 else
7084                                 {
7085                                 pDM_SWAT_Table->RSSI_Trying = 2;
7086                                 pDM_SWAT_Table->TestMode = RSSI_MODE;
7087
7088                         }
7089                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("SWAS: Normal State -> Begin Trying!\n"));
7090
7091
7092                         pDM_SWAT_Table->RSSI_sum_A = 0;
7093                         pDM_SWAT_Table->RSSI_cnt_A = 0;
7094                         pDM_SWAT_Table->RSSI_sum_B = 0;
7095                         pDM_SWAT_Table->RSSI_cnt_B = 0;
7096                 }
7097         }
7098
7099         //1 4.Change TRX antenna
7100         if(nextAntenna != pDM_SWAT_Table->CurAntenna)
7101         {
7102                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("SWAS: Change TX Antenna!\n "));
7103                 //PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, 0x300, nextAntenna);
7104                 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
7105                 ODM_SetAntenna(pDM_Odm,nextAntenna);
7106                 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
7107                 {
7108                         BOOLEAN bEnqueue;
7109                         bEnqueue = (pDM_Odm->SupportInterface ==  ODM_ITRF_PCIE)?FALSE :TRUE;
7110                         rtw_antenna_select_cmd(pDM_Odm->Adapter, nextAntenna, bEnqueue);
7111                 }
7112                 #endif
7113
7114         }
7115
7116         //1 5.Reset Statistics
7117         pDM_SWAT_Table->PreAntenna = pDM_SWAT_Table->CurAntenna;
7118         pDM_SWAT_Table->CurAntenna = nextAntenna;
7119         pDM_SWAT_Table->PreRSSI = curRSSI;
7120
7121         //1 6.Set next timer
7122         {
7123                 //PADAPTER              pAdapter = pDM_Odm->Adapter;
7124                 //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
7125
7126
7127         if(pDM_SWAT_Table->RSSI_Trying == 0)
7128                 return;
7129
7130         if(pDM_SWAT_Table->RSSI_Trying%2 == 0)
7131         {
7132                 if(pDM_SWAT_Table->TestMode == TP_MODE)
7133                 {
7134                         if(pDM_SWAT_Table->TrafficLoad == TRAFFIC_HIGH)
7135                         {
7136                                 ODM_SetTimer(pDM_Odm,&pDM_SWAT_Table->SwAntennaSwitchTimer, 10 ); //ms
7137
7138                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("dm_SW_AntennaSwitch(): Test another antenna for 10 ms\n"));
7139                         }
7140                         else if(pDM_SWAT_Table->TrafficLoad == TRAFFIC_LOW)
7141                         {
7142                                 ODM_SetTimer(pDM_Odm,&pDM_SWAT_Table->SwAntennaSwitchTimer, 50 ); //ms
7143                                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("dm_SW_AntennaSwitch(): Test another antenna for 50 ms\n"));
7144                         }
7145                 }
7146                 else
7147                 {
7148                         ODM_SetTimer(pDM_Odm,&pDM_SWAT_Table->SwAntennaSwitchTimer, 500 ); //ms
7149                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("dm_SW_AntennaSwitch(): Test another antenna for 500 ms\n"));
7150                 }
7151         }
7152         else
7153         {
7154                 if(pDM_SWAT_Table->TestMode == TP_MODE)
7155                 {
7156                         if(pDM_SWAT_Table->TrafficLoad == TRAFFIC_HIGH)
7157                                 ODM_SetTimer(pDM_Odm,&pDM_SWAT_Table->SwAntennaSwitchTimer, 90 ); //ms
7158                         else if(pDM_SWAT_Table->TrafficLoad == TRAFFIC_LOW)
7159                                 ODM_SetTimer(pDM_Odm,&pDM_SWAT_Table->SwAntennaSwitchTimer, 100 ); //ms
7160                 }
7161                 else
7162                         ODM_SetTimer(pDM_Odm,&pDM_SWAT_Table->SwAntennaSwitchTimer, 500 ); //ms
7163         }
7164         }
7165 #endif  // #if (DM_ODM_SUPPORT_TYPE  & (ODM_WIN|ODM_CE))
7166 #endif  // #if (RTL8192C_SUPPORT==1)
7167 }
7168
7169
7170 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
7171
7172 u1Byte
7173 odm_SwAntDivSelectScanChnl(
7174         IN      PADAPTER        Adapter
7175         )
7176 {
7177 #if (RT_MEM_SIZE_LEVEL != RT_MEM_SIZE_MINIMUM)
7178         PHAL_DATA_TYPE          pHalData = GET_HAL_DATA(Adapter);
7179         PMGNT_INFO                      pMgntInfo = &(Adapter->MgntInfo);
7180         PDM_ODM_T                       pDM_Odm = &pHalData->DM_OutSrc;
7181         u1Byte                          i, j, ScanChannel = 0, ChannelNum = 0;
7182         PRT_CHANNEL_LIST        pChannelList = GET_RT_CHANNEL_LIST(pMgntInfo);
7183         u1Byte                          EachChannelSTAs[MAX_SCAN_CHANNEL_NUM] = {0};
7184
7185         if(pMgntInfo->tmpNumBssDesc == 0)
7186                 return 0;
7187
7188         for(i = 0; i < pMgntInfo->tmpNumBssDesc; i++)
7189         {
7190                 ChannelNum = pMgntInfo->tmpbssDesc[i].ChannelNumber;
7191                 for(j = 0; j < pChannelList->ChannelLen; j++)
7192                 {
7193                         if(pChannelList->ChnlListEntry[j].ChannelNum == ChannelNum)
7194                         {
7195                                 EachChannelSTAs[j]++;
7196                                 break;
7197                         }
7198                 }
7199         }
7200
7201         for(i = 0; i < MAX_SCAN_CHANNEL_NUM; i++)
7202                 {
7203                 if(EachChannelSTAs[i] > EachChannelSTAs[ScanChannel])
7204                         ScanChannel = i;
7205                 }
7206
7207         if(EachChannelSTAs[ScanChannel] == 0)
7208         {
7209                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, DBG_LOUD, ("odm_SwAntDivSelectScanChnl(): Scan List is empty.\n"));
7210                 return 0;
7211         }
7212
7213         ScanChannel = pChannelList->ChnlListEntry[ScanChannel].ChannelNum;
7214
7215
7216
7217         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, DBG_LOUD,
7218                 ("odm_SwAntDivSelectScanChnl(): Channel %d is select as scan channel.\n", ScanChannel));
7219
7220         return ScanChannel;
7221 #else
7222         return  0;
7223 #endif
7224 }
7225
7226
7227 VOID
7228 odm_SwAntDivConstructScanChnl(
7229         IN      PADAPTER        Adapter,
7230         IN      u1Byte          ScanChnl
7231         )
7232 {
7233
7234         PMGNT_INFO                      pMgntInfo = &Adapter->MgntInfo;
7235
7236         if(ScanChnl == 0)
7237         {
7238                 u1Byte                          i;
7239                 PRT_CHANNEL_LIST        pChannelList = GET_RT_CHANNEL_LIST(pMgntInfo);
7240
7241                 // 20100519 Joseph: Original antenna scanned nothing.
7242                 // Test antenna shall scan all channel with half period in this condition.
7243                 RtActChannelList(Adapter, RT_CHNL_LIST_ACTION_CONSTRUCT_SCAN_LIST, NULL, NULL);
7244                 for(i = 0; i < pChannelList->ChannelLen; i++)
7245                         pChannelList->ChnlListEntry[i].ScanPeriod /= 2;
7246         }
7247         else
7248         {
7249                 // The using of this CustomizedScanRequest is a trick to rescan the two channels
7250                 //      under the NORMAL scanning process. It will not affect MGNT_INFO.CustomizedScanRequest.
7251                 CUSTOMIZED_SCAN_REQUEST CustomScanReq;
7252
7253                 CustomScanReq.bEnabled = TRUE;
7254                 CustomScanReq.Channels[0] = ScanChnl;
7255                 CustomScanReq.Channels[1] = pMgntInfo->dot11CurrentChannelNumber;
7256                 CustomScanReq.nChannels = 2;
7257                 CustomScanReq.ScanType = SCAN_ACTIVE;
7258                 CustomScanReq.Duration = DEFAULT_PASSIVE_SCAN_PERIOD;
7259
7260                 RtActChannelList(Adapter, RT_CHNL_LIST_ACTION_CONSTRUCT_SCAN_LIST, &CustomScanReq, NULL);
7261         }
7262
7263 }
7264 #endif //#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
7265
7266 //
7267 // 20100514 Luke/Joseph:
7268 // Callback function for 500ms antenna test trying.
7269 //
7270 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
7271 VOID
7272 odm_SwAntDivChkAntSwitchCallback(
7273         PRT_TIMER               pTimer
7274 )
7275 {
7276         PADAPTER                Adapter = (PADAPTER)pTimer->Adapter;
7277         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
7278         pSWAT_T         pDM_SWAT_Table = &pHalData->DM_OutSrc.DM_SWAT_Table;
7279
7280         #if DEV_BUS_TYPE==RT_PCI_INTERFACE
7281         #if USE_WORKITEM
7282         ODM_ScheduleWorkItem(&pDM_SWAT_Table->SwAntennaSwitchWorkitem);
7283         #else
7284         odm_SwAntDivChkAntSwitch(&pHalData->DM_OutSrc, SWAW_STEP_DETERMINE);
7285         #endif
7286         #else
7287         ODM_ScheduleWorkItem(&pDM_SWAT_Table->SwAntennaSwitchWorkitem);
7288         #endif
7289
7290 }
7291 VOID
7292 odm_SwAntDivChkAntSwitchWorkitemCallback(
7293     IN PVOID            pContext
7294     )
7295 {
7296
7297         PADAPTER                pAdapter = (PADAPTER)pContext;
7298         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);
7299
7300         odm_SwAntDivChkAntSwitch(&pHalData->DM_OutSrc, SWAW_STEP_DETERMINE);
7301
7302 }
7303 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
7304 VOID odm_SwAntDivChkAntSwitchCallback(void *FunctionContext)
7305 {
7306         PDM_ODM_T       pDM_Odm= (PDM_ODM_T)FunctionContext;
7307         PADAPTER        padapter = pDM_Odm->Adapter;
7308         if(padapter->net_closed == _TRUE)
7309             return;
7310         odm_SwAntDivChkAntSwitch(pDM_Odm, SWAW_STEP_DETERMINE);
7311 }
7312 #elif (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
7313 VOID odm_SwAntDivChkAntSwitchCallback(void *FunctionContext)
7314 {
7315         PDM_ODM_T       pDM_Odm= (PDM_ODM_T)FunctionContext;
7316         odm_SwAntDivChkAntSwitch(pDM_Odm, SWAW_STEP_DETERMINE);
7317 }
7318 #endif
7319
7320 #else //#if(defined(CONFIG_SW_ANTENNA_DIVERSITY))
7321
7322 VOID odm_SwAntDivInit(  IN              PDM_ODM_T               pDM_Odm ) {}
7323 VOID ODM_SwAntDivChkPerPktRssi(
7324         IN PDM_ODM_T    pDM_Odm,
7325         IN u1Byte               StationID,
7326         IN PODM_PHY_INFO_T pPhyInfo
7327         ) {}
7328 VOID odm_SwAntDivChkAntSwitch(
7329         IN              PDM_ODM_T               pDM_Odm,
7330         IN              u1Byte                  Step
7331         ) {}
7332 VOID ODM_SwAntDivResetBeforeLink(       IN              PDM_ODM_T               pDM_Odm ){}
7333 VOID ODM_SwAntDivRestAfterLink( IN              PDM_ODM_T               pDM_Odm ){}
7334 VOID odm_SwAntDetectInit(       IN              PDM_ODM_T               pDM_Odm){}
7335 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
7336 VOID odm_SwAntDivChkAntSwitchCallback(  PRT_TIMER               pTimer){}
7337 VOID odm_SwAntDivChkAntSwitchWorkitemCallback(    IN PVOID            pContext    ){}
7338 #elif (DM_ODM_SUPPORT_TYPE == ODM_CE)
7339 VOID odm_SwAntDivChkAntSwitchCallback(void *FunctionContext){}
7340 #elif (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))
7341 VOID odm_SwAntDivChkAntSwitchCallback(void *FunctionContext){}
7342 #endif
7343
7344 #endif //#if(defined(CONFIG_SW_ANTENNA_DIVERSITY))
7345
7346
7347
7348 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
7349 BOOLEAN
7350 ODM_SwAntDivCheckBeforeLink(
7351         IN              PDM_ODM_T               pDM_Odm
7352         )
7353 {
7354
7355 #if (RT_MEM_SIZE_LEVEL != RT_MEM_SIZE_MINIMUM)
7356
7357         PADAPTER                Adapter = pDM_Odm->Adapter;
7358         HAL_DATA_TYPE*  pHalData = GET_HAL_DATA(Adapter);
7359         PMGNT_INFO              pMgntInfo = &Adapter->MgntInfo;
7360         pSWAT_T                 pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
7361         pFAT_T  pDM_FatTable = &pDM_Odm->DM_FatTable;
7362         s1Byte                  Score = 0;
7363         PRT_WLAN_BSS    pTmpBssDesc, pTestBssDesc;
7364         s4Byte                  power_diff = 0, power_target = 10;
7365         u1Byte                  index, counter = 0;
7366         static u1Byte           ScanChannel;
7367         u8Byte                  tStamp_diff = 0;
7368
7369
7370         if (pDM_Odm->Adapter == NULL)  //For BSOD when plug/unplug fast.  //By YJ,120413
7371         {       // The ODM structure is not initialized.
7372                 return FALSE;
7373         }
7374
7375         // Retrieve antenna detection registry info, added by Roger, 2012.11.27.
7376         if(!IS_ANT_DETECT_SUPPORT_RSSI(Adapter))
7377                         return FALSE;
7378
7379         // Since driver is going to set BB register, it shall check if there is another thread controlling BB/RF.
7380         PlatformAcquireSpinLock(Adapter, RT_RF_STATE_SPINLOCK);
7381         if(pHalData->eRFPowerState!=eRfOn || pMgntInfo->RFChangeInProgress || pMgntInfo->bMediaConnect)
7382         {
7383                 PlatformReleaseSpinLock(Adapter, RT_RF_STATE_SPINLOCK);
7384
7385                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
7386                                 ("ODM_SwAntDivCheckBeforeLink(): RFChangeInProgress(%x), eRFPowerState(%x)\n",
7387                                 pMgntInfo->RFChangeInProgress, pHalData->eRFPowerState));
7388
7389                 pDM_SWAT_Table->SWAS_NoLink_State = 0;
7390
7391                 return FALSE;
7392         }
7393         else
7394         {
7395                 PlatformReleaseSpinLock(Adapter, RT_RF_STATE_SPINLOCK);
7396         }
7397         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("pDM_SWAT_Table->SWAS_NoLink_State = %d\n", pDM_SWAT_Table->SWAS_NoLink_State));
7398         //1 Run AntDiv mechanism "Before Link" part.
7399         if(pDM_SWAT_Table->SWAS_NoLink_State == 0)
7400         {
7401                 //1 Prepare to do Scan again to check current antenna state.
7402
7403                 // Set check state to next step.
7404                 pDM_SWAT_Table->SWAS_NoLink_State = 1;
7405
7406                 // Copy Current Scan list.
7407                 pMgntInfo->tmpNumBssDesc = pMgntInfo->NumBssDesc;
7408                 PlatformMoveMemory((PVOID)Adapter->MgntInfo.tmpbssDesc, (PVOID)pMgntInfo->bssDesc, sizeof(RT_WLAN_BSS)*MAX_BSS_DESC);
7409
7410                 // Go back to scan function again.
7411                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink: Scan one more time\n"));
7412                 pMgntInfo->ScanStep=0;
7413                 pMgntInfo->bScanAntDetect = TRUE;
7414                 ScanChannel = odm_SwAntDivSelectScanChnl(Adapter);
7415
7416
7417                 if(pDM_Odm->SupportICType & (ODM_RTL8188E|ODM_RTL8821))
7418                 {
7419                         if(pDM_FatTable->RxIdleAnt == MAIN_ANT)
7420                                 ODM_UpdateRxIdleAnt(pDM_Odm, AUX_ANT);
7421                         else
7422                                 ODM_UpdateRxIdleAnt(pDM_Odm, MAIN_ANT);
7423                         if(ScanChannel == 0)
7424                         {
7425                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
7426                                         ("ODM_SwAntDivCheckBeforeLink(): No AP List Avaiable, Using Ant(%s)\n", (pDM_FatTable->RxIdleAnt==MAIN_ANT)?"AUX_ANT":"MAIN_ANT"));
7427
7428                                 if(IS_5G_WIRELESS_MODE(pMgntInfo->dot11CurrentWirelessMode))
7429                                 {
7430                                         pDM_SWAT_Table->Ant5G = pDM_FatTable->RxIdleAnt;
7431                                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_SWAT_Table->Ant5G=%s\n", (pDM_FatTable->RxIdleAnt==MAIN_ANT)?"MAIN_ANT":"AUX_ANT"));
7432                                 }
7433                                 else
7434                                 {
7435                                         pDM_SWAT_Table->Ant2G = pDM_FatTable->RxIdleAnt;
7436                                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_SWAT_Table->Ant2G=%s\n", (pDM_FatTable->RxIdleAnt==MAIN_ANT)?"MAIN_ANT":"AUX_ANT"));
7437                                 }
7438                                 return FALSE;
7439                         }
7440
7441                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
7442                                 ("ODM_SwAntDivCheckBeforeLink: Change to %s for testing.\n", ((pDM_FatTable->RxIdleAnt == MAIN_ANT)?"MAIN_ANT":"AUX_ANT")));
7443                 }
7444                 else if(pDM_Odm->SupportICType & (ODM_RTL8192C|ODM_RTL8723B))
7445                 {
7446                         // Switch Antenna to another one.
7447                         pDM_SWAT_Table->PreAntenna = pDM_SWAT_Table->CurAntenna;
7448                         pDM_SWAT_Table->CurAntenna = (pDM_SWAT_Table->CurAntenna==MAIN_ANT)?AUX_ANT:MAIN_ANT;
7449
7450                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
7451                                 ("ODM_SwAntDivCheckBeforeLink: Change to Ant(%s) for testing.\n", (pDM_SWAT_Table->CurAntenna==MAIN_ANT)?"MAIN":"AUX"));
7452                         //PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, 0x300, DM_SWAT_Table.CurAntenna);
7453                         if(pDM_Odm->SupportICType == ODM_RTL8192C)
7454                         {
7455                                 pDM_SWAT_Table->SWAS_NoLink_BK_Reg860 = ((pDM_SWAT_Table->SWAS_NoLink_BK_Reg860 & 0xfffffcff) | (pDM_SWAT_Table->CurAntenna<<8));
7456                                 ODM_SetBBReg(pDM_Odm,  rFPGA0_XA_RFInterfaceOE, bMaskDWord, pDM_SWAT_Table->SWAS_NoLink_BK_Reg860);
7457                         }
7458                         else if(pDM_Odm->SupportICType == ODM_RTL8723B)
7459                         {
7460                                 pDM_SWAT_Table->SWAS_NoLink_BK_Reg92c = ((pDM_SWAT_Table->SWAS_NoLink_BK_Reg92c & 0xfffffffc) | (pDM_SWAT_Table->CurAntenna));
7461                                 ODM_SetBBReg(pDM_Odm,  rfe_ctrl_anta_src, 0xff, 0x77);
7462                                 ODM_SetBBReg(pDM_Odm,  rDPDT_control, bMaskDWord, pDM_SWAT_Table->SWAS_NoLink_BK_Reg92c);
7463                         }
7464                 }
7465
7466                 odm_SwAntDivConstructScanChnl(Adapter, ScanChannel);
7467                 PlatformSetTimer(Adapter, &pMgntInfo->ScanTimer, 5);
7468
7469                 return TRUE;
7470         }
7471         else
7472         {
7473                 //1 ScanComple() is called after antenna swiched.
7474                 //1 Check scan result and determine which antenna is going
7475                 //1 to be used.
7476
7477                 for(index = 0; index < pMgntInfo->tmpNumBssDesc; index++)
7478                 {
7479                         pTmpBssDesc = &(pMgntInfo->tmpbssDesc[index]); // Antenna 1
7480                         pTestBssDesc = &(pMgntInfo->bssDesc[index]); // Antenna 2
7481
7482                         if(PlatformCompareMemory(pTestBssDesc->bdBssIdBuf, pTmpBssDesc->bdBssIdBuf, 6)!=0)
7483                         {
7484                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink(): ERROR!! This shall not happen.\n"));
7485                                 continue;
7486                         }
7487
7488                         if(pDM_Odm->SupportICType != ODM_RTL8723B)
7489                         {
7490                                 if(pTmpBssDesc->ChannelNumber == ScanChannel)
7491                                 {
7492                         if(pTmpBssDesc->RecvSignalPower > pTestBssDesc->RecvSignalPower)
7493                         {
7494                                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink: Compare scan entry: Score++\n"));
7495                                                 RT_PRINT_STR(COMP_SCAN, DBG_WARNING, "GetScanInfo(): new Bss SSID:", pTmpBssDesc->bdSsIdBuf, pTmpBssDesc->bdSsIdLen);
7496                                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("at ch %d, Original: %d, Test: %d\n\n", pTmpBssDesc->ChannelNumber, pTmpBssDesc->RecvSignalPower, pTestBssDesc->RecvSignalPower));
7497
7498                                 Score++;
7499                                 PlatformMoveMemory(pTestBssDesc, pTmpBssDesc, sizeof(RT_WLAN_BSS));
7500                         }
7501                         else if(pTmpBssDesc->RecvSignalPower < pTestBssDesc->RecvSignalPower)
7502                         {
7503                                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink: Compare scan entry: Score--\n"));
7504                                                 RT_PRINT_STR(COMP_SCAN, DBG_WARNING, "GetScanInfo(): new Bss SSID:", pTmpBssDesc->bdSsIdBuf, pTmpBssDesc->bdSsIdLen);
7505                                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("at ch %d, Original: %d, Test: %d\n\n", pTmpBssDesc->ChannelNumber, pTmpBssDesc->RecvSignalPower, pTestBssDesc->RecvSignalPower));
7506                                 Score--;
7507                         }
7508                                         else
7509                                         {
7510                                                 if(pTestBssDesc->bdTstamp - pTmpBssDesc->bdTstamp < 5000)
7511                                                 {
7512                                                         RT_PRINT_STR(COMP_SCAN, DBG_WARNING, "GetScanInfo(): new Bss SSID:", pTmpBssDesc->bdSsIdBuf, pTmpBssDesc->bdSsIdLen);
7513                                                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("at ch %d, Original: %d, Test: %d\n", pTmpBssDesc->ChannelNumber, pTmpBssDesc->RecvSignalPower, pTestBssDesc->RecvSignalPower));
7514                                                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("The 2nd Antenna didn't get this AP\n\n"));
7515                                                 }
7516                                         }
7517                                 }
7518                         }
7519                         else
7520                         {
7521                                 if(pTmpBssDesc->ChannelNumber == ScanChannel)
7522                                 {
7523                                         if(pTmpBssDesc->RecvSignalPower > pTestBssDesc->RecvSignalPower)
7524                                         {
7525                                                 counter++;
7526                                                 power_diff = power_diff + (pTmpBssDesc->RecvSignalPower - pTestBssDesc->RecvSignalPower);
7527                                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Original: %d, Test: %d\n", pTmpBssDesc->RecvSignalPower, pTestBssDesc->RecvSignalPower));
7528                                                 ODM_PRINT_ADDR(pDM_Odm,ODM_COMP_ANT_DIV, DBG_LOUD, ("SSID:"), pTmpBssDesc->bdSsIdBuf);
7529                                                 ODM_PRINT_ADDR(pDM_Odm,ODM_COMP_ANT_DIV, DBG_LOUD, ("BSSID:"), pTmpBssDesc->bdBssIdBuf);
7530                                                 PlatformMoveMemory(pTestBssDesc, pTmpBssDesc, sizeof(RT_WLAN_BSS));
7531                                         }
7532                                         else if(pTestBssDesc->RecvSignalPower > pTmpBssDesc->RecvSignalPower)
7533                                         {
7534                                                 counter++;
7535                                                 power_diff = power_diff + (pTestBssDesc->RecvSignalPower - pTmpBssDesc->RecvSignalPower);
7536                                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Original: %d, Test: %d\n", pTmpBssDesc->RecvSignalPower, pTestBssDesc->RecvSignalPower));
7537                                                 ODM_PRINT_ADDR(pDM_Odm,ODM_COMP_ANT_DIV, DBG_LOUD, ("SSID:"), pTmpBssDesc->bdSsIdBuf);
7538                                                 ODM_PRINT_ADDR(pDM_Odm,ODM_COMP_ANT_DIV, DBG_LOUD, ("BSSID:"), pTmpBssDesc->bdBssIdBuf)
7539                                         }
7540                                         else if(pTestBssDesc->bdTstamp > pTmpBssDesc->bdTstamp)
7541                                         {
7542                                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("time_diff: %lld\n", (pTestBssDesc->bdTstamp-pTmpBssDesc->bdTstamp)/1000));
7543                                                 if(pTestBssDesc->bdTstamp - pTmpBssDesc->bdTstamp > 5000)
7544                                                 {
7545                                                         counter++;
7546                                                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("Original: %d, Test: %d\n", pTmpBssDesc->RecvSignalPower, pTestBssDesc->RecvSignalPower));
7547                                                         ODM_PRINT_ADDR(pDM_Odm,ODM_COMP_ANT_DIV, DBG_LOUD, ("SSID:"), pTmpBssDesc->bdSsIdBuf);
7548                                                         ODM_PRINT_ADDR(pDM_Odm,ODM_COMP_ANT_DIV, DBG_LOUD, ("BSSID:"), pTmpBssDesc->bdBssIdBuf)
7549                                                 }
7550                                         }
7551                                 }
7552                         }
7553                 }
7554
7555                 if(pDM_Odm->SupportICType == ODM_RTL8723B)
7556                 {
7557                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("counter: %d power_diff: %d\n", counter, power_diff));
7558
7559                         if(counter != 0)
7560                                 power_diff = power_diff / counter;
7561
7562                         if(power_diff <= power_target && counter != 0)
7563                                 Score++;
7564                 }
7565
7566                 if(pDM_Odm->SupportICType & (ODM_RTL8188E|ODM_RTL8821))
7567                 {
7568                         if(pMgntInfo->NumBssDesc!=0 && Score<0)
7569                         {
7570                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
7571                                                         ("ODM_SwAntDivCheckBeforeLink(): Using Ant(%s)\n", (pDM_FatTable->RxIdleAnt==MAIN_ANT)?"MAIN_ANT":"AUX_ANT"));
7572                         }
7573                         else
7574                         {
7575                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
7576                                                 ("ODM_SwAntDivCheckBeforeLink(): Remain Ant(%s)\n", (pDM_FatTable->RxIdleAnt==MAIN_ANT)?"AUX_ANT":"MAIN_ANT"));
7577
7578                                 if(pDM_FatTable->RxIdleAnt == MAIN_ANT)
7579                                         ODM_UpdateRxIdleAnt(pDM_Odm, AUX_ANT);
7580                                 else
7581                                         ODM_UpdateRxIdleAnt(pDM_Odm, MAIN_ANT);
7582                         }
7583
7584                         if(IS_5G_WIRELESS_MODE(pMgntInfo->dot11CurrentWirelessMode))
7585                         {
7586                                 pDM_SWAT_Table->Ant5G = pDM_FatTable->RxIdleAnt;
7587                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_SWAT_Table->Ant5G=%s\n", (pDM_FatTable->RxIdleAnt==MAIN_ANT)?"MAIN_ANT":"AUX_ANT"));
7588                         }
7589                         else
7590                         {
7591                                 pDM_SWAT_Table->Ant2G = pDM_FatTable->RxIdleAnt;
7592                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("pDM_SWAT_Table->Ant2G=%s\n", (pDM_FatTable->RxIdleAnt==MAIN_ANT)?"MAIN_ANT":"AUX_ANT"));
7593                         }
7594                 }
7595                 else if(pDM_Odm->SupportICType == ODM_RTL8723B)
7596                 {
7597                         pDM_SWAT_Table->CurAntenna = pDM_SWAT_Table->PreAntenna;
7598                         pDM_SWAT_Table->SWAS_NoLink_BK_Reg92c = ((pDM_SWAT_Table->SWAS_NoLink_BK_Reg92c & 0xfffffffc) | (pDM_SWAT_Table->CurAntenna));
7599                         ODM_SetBBReg(pDM_Odm,  rfe_ctrl_anta_src, 0xff, 0x77);
7600                         ODM_SetBBReg(pDM_Odm,  rDPDT_control,bMaskDWord, pDM_SWAT_Table->SWAS_NoLink_BK_Reg92c);
7601
7602                         if(counter != 0)
7603                         {
7604                                 if(pMgntInfo->NumBssDesc != 0 && Score > 0)
7605                                 {
7606                                         if(pDM_Odm->DM_SWAT_Table.ANTB_ON == FALSE)
7607                                         {
7608                                                 pDM_Odm->DM_SWAT_Table.ANTA_ON = TRUE;
7609                                                 pDM_Odm->DM_SWAT_Table.ANTB_ON = TRUE;
7610                                         }
7611                                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("ODM_SwAntDivCheckBeforeLink(): Dual antenna\n"));
7612                                 }
7613                                 else
7614                                 {
7615                                         if(pDM_Odm->DM_SWAT_Table.ANTB_ON == TRUE)
7616                                         {
7617                                                 pDM_Odm->DM_SWAT_Table.ANTA_ON = TRUE;
7618                                                 pDM_Odm->DM_SWAT_Table.ANTB_ON = FALSE;
7619                                                 BT_SetBtCoexAntNum(Adapter, BT_COEX_ANT_TYPE_DETECTED, 1);
7620                                         }
7621                                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SwAntDivCheckBeforeLink(): Single antenna\n"));
7622                                 }
7623                         }
7624                         else
7625                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("ODM_SwAntDivCheckBeforeLink(): Igone result\n"));
7626                 }
7627                 else if(pDM_Odm->SupportICType == ODM_RTL8192C)
7628                 {
7629                         if(pMgntInfo->NumBssDesc!=0 && Score<=0)
7630                         {
7631                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
7632                                         ("ODM_SwAntDivCheckBeforeLink(): Using Ant(%s)\n", (pDM_SWAT_Table->CurAntenna==MAIN_ANT)?"MAIN":"AUX"));
7633
7634                                 pDM_SWAT_Table->PreAntenna = pDM_SWAT_Table->CurAntenna;
7635                         }
7636                         else
7637                         {
7638                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,
7639                                         ("ODM_SwAntDivCheckBeforeLink(): Remain Ant(%s)\n", (pDM_SWAT_Table->CurAntenna==MAIN_ANT)?"AUX":"MAIN"));
7640
7641                                 pDM_SWAT_Table->CurAntenna = pDM_SWAT_Table->PreAntenna;
7642
7643                                 //PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, 0x300, DM_SWAT_Table.CurAntenna);
7644                                 pDM_SWAT_Table->SWAS_NoLink_BK_Reg860 = ((pDM_SWAT_Table->SWAS_NoLink_BK_Reg860 & 0xfffffcff) | (pDM_SWAT_Table->CurAntenna<<8));
7645                                 PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, bMaskDWord, pDM_SWAT_Table->SWAS_NoLink_BK_Reg860);
7646                         }
7647                 }
7648
7649                 // Check state reset to default and wait for next time.
7650                 pDM_SWAT_Table->SWAS_NoLink_State = 0;
7651                 pMgntInfo->bScanAntDetect = FALSE;
7652
7653                 return FALSE;
7654         }
7655
7656 #else
7657                 return  FALSE;
7658 #endif
7659
7660 return FALSE;
7661 }
7662
7663 #endif //#if(DM_ODM_SUPPORT_TYPE==ODM_WIN)
7664
7665
7666 //3============================================================
7667 //3 SW Antenna Diversity
7668 //3============================================================
7669
7670 #if(defined(CONFIG_HW_ANTENNA_DIVERSITY))
7671 VOID
7672 odm_InitHybridAntDiv_88C_92D(
7673         IN PDM_ODM_T    pDM_Odm
7674         )
7675 {
7676
7677 #if((DM_ODM_SUPPORT_TYPE==ODM_AP)||(DM_ODM_SUPPORT_TYPE==ODM_ADSL))
7678         struct rtl8192cd_priv *priv=pDM_Odm->priv;
7679 #endif
7680         SWAT_T                  *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
7681         u1Byte                  bTxPathSel=0;           //0:Path-A   1:Path-B
7682         u1Byte                  i;
7683
7684         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("odm_InitHybridAntDiv==============>\n"));
7685
7686         //whether to do antenna diversity or not
7687 #if(DM_ODM_SUPPORT_TYPE==ODM_AP)
7688         if(priv==NULL)  return;
7689         if(!priv->pshare->rf_ft_var.antHw_enable)
7690                 return;
7691
7692         #ifdef SW_ANT_SWITCH
7693         priv->pshare->rf_ft_var.antSw_enable =0;
7694         #endif
7695 #endif
7696
7697         if((pDM_Odm->SupportICType != ODM_RTL8192C) && (pDM_Odm->SupportICType != ODM_RTL8192D))
7698                 return;
7699
7700
7701         bTxPathSel=(pDM_Odm->RFType==ODM_1T1R)?FALSE:TRUE;
7702
7703         ODM_SetBBReg(pDM_Odm,ODM_REG_BB_PWR_SAV1_11N, BIT23, 0); //No update ANTSEL during GNT_BT=1
7704         ODM_SetBBReg(pDM_Odm,ODM_REG_TX_ANT_CTRL_11N, BIT21, 1); //TX atenna selection from tx_info
7705         ODM_SetBBReg(pDM_Odm,ODM_REG_ANTSEL_PIN_11N, BIT23, 1); //enable LED[1:0] pin as ANTSEL
7706         ODM_SetBBReg(pDM_Odm,ODM_REG_ANTSEL_CTRL_11N, BIT8|BIT9, 0x01); // 0x01: left antenna, 0x02: right antenna
7707         // check HW setting: ANTSEL pin connection
7708         #if(DM_ODM_SUPPORT_TYPE==ODM_AP)
7709         ODM_Write2Byte(pDM_Odm,ODM_REG_RF_PIN_11N, (ODM_Read2Byte(pDM_Odm,0x804)&0xf0ff )| BIT(8) );    // b11-b8=0001,update RFPin setting
7710         #endif
7711
7712         // only AP support different path selection temperarly
7713         if(!bTxPathSel){                 //PATH-A
7714                 ODM_SetBBReg(pDM_Odm,ODM_REG_PIN_CTRL_11N, BIT8|BIT9, 0 ); // ANTSEL as HW control
7715                 ODM_SetBBReg(pDM_Odm,ODM_REG_ANTSEL_PATH_11N, BIT13, 1);         //select TX ANTESEL from path A
7716         }
7717         else    {
7718                 ODM_SetBBReg(pDM_Odm,ODM_REG_PIN_CTRL_11N, BIT24|BIT25, 0 ); // ANTSEL as HW control
7719                 ODM_SetBBReg(pDM_Odm,ODM_REG_ANTSEL_PATH_11N, BIT13, 0);                 //select ANTESEL from path B
7720         }
7721
7722         //Set OFDM HW RX Antenna Diversity
7723         ODM_SetBBReg(pDM_Odm,ODM_REG_ANTDIV_PARA1_11N, 0x7FF, 0x0c0); //Pwdb threshold=8dB
7724         ODM_SetBBReg(pDM_Odm,ODM_REG_ANTDIV_PARA1_11N, BIT11, 0); //Switch to another antenna by checking pwdb threshold
7725         ODM_SetBBReg(pDM_Odm,ODM_REG_ANTDIV_PARA3_11N, BIT23, 1);       // Decide final antenna by comparing 2 antennas' pwdb
7726
7727         //Set CCK HW RX Antenna Diversity
7728         ODM_SetBBReg(pDM_Odm,ODM_REG_CCK_ANTDIV_PARA2_11N, BIT4, 0); //Antenna diversity decision period = 32 sample
7729         ODM_SetBBReg(pDM_Odm,ODM_REG_CCK_ANTDIV_PARA2_11N, 0xf, 0xf); //Threshold for antenna diversity. Check another antenna power if input power < ANT_lim*4
7730         ODM_SetBBReg(pDM_Odm,ODM_REG_CCK_ANTDIV_PARA3_11N, BIT13, 1); //polarity ana_A=1 and ana_B=0
7731         ODM_SetBBReg(pDM_Odm,ODM_REG_CCK_ANTDIV_PARA4_11N, 0x1f, 0x8); //default antenna power = inpwr*(0.5 + r_ant_step/16)
7732
7733
7734         //Enable HW Antenna Diversity
7735         if(!bTxPathSel)                 //PATH-A
7736                 ODM_SetBBReg(pDM_Odm,ODM_REG_IGI_A_11N, BIT7,1);        // Enable Hardware antenna switch
7737         else
7738                 ODM_SetBBReg(pDM_Odm,ODM_REG_IGI_B_11N, BIT7,1);        // Enable Hardware antenna switch
7739         ODM_SetBBReg(pDM_Odm,ODM_REG_CCK_ANTDIV_PARA1_11N, BIT15, 1);//Enable antenna diversity
7740
7741         pDM_SWAT_Table->CurAntenna=0;                   //choose left antenna as default antenna
7742         pDM_SWAT_Table->PreAntenna=0;
7743         for(i=0; i<ASSOCIATE_ENTRY_NUM ; i++)
7744         {
7745                 pDM_SWAT_Table->CCK_Ant1_Cnt[i] = 0;
7746                 pDM_SWAT_Table->CCK_Ant2_Cnt[i] = 0;
7747                 pDM_SWAT_Table->OFDM_Ant1_Cnt[i] = 0;
7748                 pDM_SWAT_Table->OFDM_Ant2_Cnt[i] = 0;
7749                 pDM_SWAT_Table->RSSI_Ant1_Sum[i] = 0;
7750                 pDM_SWAT_Table->RSSI_Ant2_Sum[i] = 0;
7751         }
7752         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("<==============odm_InitHybridAntDiv\n"));
7753 }
7754
7755
7756 VOID
7757 odm_InitHybridAntDiv(
7758         IN PDM_ODM_T    pDM_Odm
7759         )
7760 {
7761         if(!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV))
7762         {
7763                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("Return: Not Support HW AntDiv\n"));
7764                 return;
7765         }
7766
7767         if(pDM_Odm->SupportICType & (ODM_RTL8192C | ODM_RTL8192D))
7768         {
7769 #if ((RTL8192C_SUPPORT == 1)||(RTL8192D_SUPPORT == 1))
7770                 odm_InitHybridAntDiv_88C_92D(pDM_Odm);
7771 #endif
7772         }
7773 }
7774
7775
7776 BOOLEAN
7777 odm_StaDefAntSel(
7778         IN PDM_ODM_T    pDM_Odm,
7779         IN u4Byte               OFDM_Ant1_Cnt,
7780         IN u4Byte               OFDM_Ant2_Cnt,
7781         IN u4Byte               CCK_Ant1_Cnt,
7782         IN u4Byte               CCK_Ant2_Cnt,
7783         OUT u1Byte              *pDefAnt
7784
7785         )
7786 {
7787 #if 1
7788         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("odm_StaDefAntSelect==============>\n"));
7789
7790         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("OFDM_Ant1_Cnt:%d, OFDM_Ant2_Cnt:%d\n",OFDM_Ant1_Cnt,OFDM_Ant2_Cnt));
7791         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("CCK_Ant1_Cnt:%d, CCK_Ant2_Cnt:%d\n",CCK_Ant1_Cnt,CCK_Ant2_Cnt));
7792
7793
7794         if(((OFDM_Ant1_Cnt+OFDM_Ant2_Cnt)==0)&&((CCK_Ant1_Cnt + CCK_Ant2_Cnt) <10)){
7795                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("odm_StaDefAntSelect Fail: No enough packet info!\n"));
7796                 return  FALSE;
7797         }
7798
7799         if(OFDM_Ant1_Cnt || OFDM_Ant2_Cnt )     {
7800                 //if RX OFDM packet number larger than 0
7801                 if(OFDM_Ant1_Cnt > OFDM_Ant2_Cnt)
7802                         (*pDefAnt)=1;
7803                 else
7804                         (*pDefAnt)=0;
7805         }
7806         // else if RX CCK packet number larger than 10
7807         else if((CCK_Ant1_Cnt + CCK_Ant2_Cnt) >=10 )
7808         {
7809                 if(CCK_Ant1_Cnt > (5*CCK_Ant2_Cnt))
7810                         (*pDefAnt)=1;
7811                 else if(CCK_Ant2_Cnt > (5*CCK_Ant1_Cnt))
7812                         (*pDefAnt)=0;
7813                 else if(CCK_Ant1_Cnt > CCK_Ant2_Cnt)
7814                         (*pDefAnt)=0;
7815                 else
7816                         (*pDefAnt)=1;
7817
7818         }
7819
7820         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("TxAnt = %s\n",((*pDefAnt)==1)?"Ant1":"Ant2"));
7821
7822 #endif
7823         //u4Byte antsel = ODM_GetBBReg(pDM_Odm, 0xc88, bMaskByte0);
7824         //(*pDefAnt)= (u1Byte) antsel;
7825
7826
7827
7828
7829         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("<==============odm_StaDefAntSelect\n"));
7830
7831         return TRUE;
7832
7833
7834 }
7835
7836
7837 VOID
7838 odm_SetRxIdleAnt(
7839         IN      PDM_ODM_T       pDM_Odm,
7840         IN      u1Byte  Ant,
7841         IN   BOOLEAN   bDualPath
7842 )
7843 {
7844         SWAT_T                  *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
7845
7846         //ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("odm_SetRxIdleAnt==============>\n"));
7847
7848         if(Ant != pDM_SWAT_Table->RxIdleAnt)
7849         {
7850         //for path-A
7851         if(Ant==1)
7852                         ODM_SetBBReg(pDM_Odm,ODM_REG_RX_DEFUALT_A_11N, 0xFFFF, 0x65a9);   //right-side antenna
7853         else
7854                         ODM_SetBBReg(pDM_Odm,ODM_REG_RX_DEFUALT_A_11N, 0xFFFF, 0x569a);   //left-side antenna
7855
7856         //for path-B
7857         if(bDualPath){
7858                 if(Ant==0)
7859                                 ODM_SetBBReg(pDM_Odm,ODM_REG_RX_DEFUALT_A_11N, 0xFFFF0000, 0x65a9);   //right-side antenna
7860                 else
7861                                 ODM_SetBBReg(pDM_Odm,ODM_REG_RX_DEFUALT_A_11N, 0xFFFF0000, 0x569a);  //left-side antenna
7862                 }
7863         }
7864                 pDM_SWAT_Table->RxIdleAnt = Ant;
7865         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("RxIdleAnt: %s  Reg858=0x%x\n",(Ant==1)?"Ant1":"Ant2",(Ant==1)?0x65a9:0x569a));
7866
7867         //ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("<==============odm_SetRxIdleAnt\n"));
7868
7869         }
7870
7871 VOID
7872 ODM_AntselStatistics_88C(
7873         IN              PDM_ODM_T               pDM_Odm,
7874         IN              u1Byte                  MacId,
7875         IN              u4Byte                  PWDBAll,
7876         IN              BOOLEAN                 isCCKrate
7877 )
7878 {
7879         SWAT_T                  *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
7880
7881         if(pDM_SWAT_Table->antsel == 1)
7882         {
7883                 if(isCCKrate)
7884                         pDM_SWAT_Table->CCK_Ant1_Cnt[MacId]++;
7885                 else
7886                 {
7887                         pDM_SWAT_Table->OFDM_Ant1_Cnt[MacId]++;
7888                         pDM_SWAT_Table->RSSI_Ant1_Sum[MacId] += PWDBAll;
7889                 }
7890         }
7891         else
7892         {
7893                 if(isCCKrate)
7894                         pDM_SWAT_Table->CCK_Ant2_Cnt[MacId]++;
7895                 else
7896                 {
7897                         pDM_SWAT_Table->OFDM_Ant2_Cnt[MacId]++;
7898                         pDM_SWAT_Table->RSSI_Ant2_Sum[MacId] += PWDBAll;
7899                 }
7900         }
7901
7902 }
7903
7904
7905
7906
7907 #if(DM_ODM_SUPPORT_TYPE==ODM_WIN)
7908 VOID
7909 ODM_SetTxAntByTxInfo_88C_92D(
7910         IN              PDM_ODM_T               pDM_Odm,
7911         IN              pu1Byte                 pDesc,
7912         IN              u1Byte                  macId
7913 )
7914 {
7915         SWAT_T                  *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
7916         u1Byte                  antsel;
7917
7918         if(!(pDM_Odm->SupportAbility&ODM_BB_ANT_DIV))
7919                 return;
7920
7921         if(pDM_SWAT_Table->RxIdleAnt == 1)
7922                 antsel=(pDM_SWAT_Table->TxAnt[macId] == 1)?0:1;
7923         else
7924                 antsel=(pDM_SWAT_Table->TxAnt[macId] == 1)?1:0;
7925
7926         SET_TX_DESC_ANTSEL_A_92C(pDesc, antsel);
7927         //SET_TX_DESC_ANTSEL_B_92C(pDesc, antsel);
7928         //ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("SET_TX_DESC_ANTSEL_A_92C=%d\n", pDM_SWAT_Table->TxAnt[macId]));
7929 }
7930 #elif(DM_ODM_SUPPORT_TYPE==ODM_CE)
7931 VOID
7932 ODM_SetTxAntByTxInfo_88C_92D(
7933         IN              PDM_ODM_T               pDM_Odm
7934 )
7935 {
7936
7937 }
7938 #elif(DM_ODM_SUPPORT_TYPE==ODM_AP)
7939 VOID
7940 ODM_SetTxAntByTxInfo_88C_92D(
7941         IN              PDM_ODM_T               pDM_Odm
7942 )
7943 {
7944
7945 }
7946 #endif
7947
7948 VOID
7949 odm_HwAntDiv_92C_92D(
7950         IN      PDM_ODM_T       pDM_Odm
7951 )
7952 {
7953         SWAT_T                  *pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
7954         u4Byte                  RSSI_Min=0xFF, RSSI, RSSI_Ant1, RSSI_Ant2;
7955         u1Byte                  RxIdleAnt, i;
7956         BOOLEAN         bRet=FALSE;
7957         PSTA_INFO_T     pEntry;
7958
7959 #if (DM_ODM_SUPPORT_TYPE==ODM_AP)
7960         struct rtl8192cd_priv *priv=pDM_Odm->priv;
7961         //if test, return
7962         if(priv->pshare->rf_ft_var.CurAntenna & 0x80)
7963                 return;
7964 #endif
7965
7966         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("odm_HwAntDiv==============>\n"));
7967
7968         if(!(pDM_Odm->SupportAbility&ODM_BB_ANT_DIV))                                    //if don't support antenna diveristy
7969         {
7970                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("odm_HwAntDiv: Not supported!\n"));
7971                 return;
7972         }
7973
7974         if((pDM_Odm->SupportICType != ODM_RTL8192C) && (pDM_Odm->SupportICType != ODM_RTL8192D))
7975         {
7976                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("Return: IC Type is not 92C or 92D\n"));
7977                 return;
7978         }
7979
7980 #if (DM_ODM_SUPPORT_TYPE&(ODM_WIN|ODM_CE))
7981         if(!pDM_Odm->bLinked)
7982         {
7983                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("Return: bLinked is FALSE\n"));
7984                 return;
7985         }
7986 #endif
7987
7988         for (i=0; i<ODM_ASSOCIATE_ENTRY_NUM; i++)
7989         {
7990                 pEntry = pDM_Odm->pODM_StaInfo[i];
7991                 if(IS_STA_VALID(pEntry))
7992                 {
7993
7994                         RSSI_Ant1 = (pDM_SWAT_Table->OFDM_Ant1_Cnt[i] == 0)?0:(pDM_SWAT_Table->RSSI_Ant1_Sum[i]/pDM_SWAT_Table->OFDM_Ant1_Cnt[i]);
7995                         RSSI_Ant2 = (pDM_SWAT_Table->OFDM_Ant2_Cnt[i] == 0)?0:(pDM_SWAT_Table->RSSI_Ant2_Sum[i]/pDM_SWAT_Table->OFDM_Ant2_Cnt[i]);
7996
7997                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("RSSI_Ant1=%d,  RSSI_Ant2=%d\n", RSSI_Ant1, RSSI_Ant2));
7998
7999                         if(RSSI_Ant1 ||RSSI_Ant2)
8000                         {
8001 #if (DM_ODM_SUPPORT_TYPE==ODM_AP)
8002                                 if(pDM_Odm->pODM_StaInfo[i]->expire_to)
8003 #endif
8004                                 {
8005                                         RSSI = (RSSI_Ant1 < RSSI_Ant2) ? RSSI_Ant1 : RSSI_Ant2;
8006                                         if((!RSSI) || ( RSSI < RSSI_Min) ) {
8007                                                 pDM_SWAT_Table->TargetSTA = i;
8008                                                 RSSI_Min = RSSI;
8009                                         }
8010                                 }
8011         }
8012                         ///STA: found out default antenna
8013                         bRet=odm_StaDefAntSel(pDM_Odm,
8014                                                  pDM_SWAT_Table->OFDM_Ant1_Cnt[i],
8015                                                  pDM_SWAT_Table->OFDM_Ant2_Cnt[i],
8016                                                  pDM_SWAT_Table->CCK_Ant1_Cnt[i],
8017                                                  pDM_SWAT_Table->CCK_Ant2_Cnt[i],
8018                                                  &pDM_SWAT_Table->TxAnt[i]);
8019
8020                         //if Tx antenna selection: successful
8021                         if(bRet){
8022                                 pDM_SWAT_Table->RSSI_Ant1_Sum[i] = 0;
8023                                 pDM_SWAT_Table->RSSI_Ant2_Sum[i] = 0;
8024                                 pDM_SWAT_Table->OFDM_Ant1_Cnt[i] = 0;
8025                                 pDM_SWAT_Table->OFDM_Ant2_Cnt[i] = 0;
8026                                 pDM_SWAT_Table->CCK_Ant1_Cnt[i] = 0;
8027                                 pDM_SWAT_Table->CCK_Ant2_Cnt[i] = 0;
8028                         }
8029                 }
8030         }
8031
8032         //set RX Idle Ant
8033         RxIdleAnt = pDM_SWAT_Table->TxAnt[pDM_SWAT_Table->TargetSTA];
8034         odm_SetRxIdleAnt(pDM_Odm, RxIdleAnt, FALSE);
8035
8036 #if (DM_ODM_SUPPORT_TYPE==ODM_AP)
8037 #ifdef TX_SHORTCUT
8038         if (!priv->pmib->dot11OperationEntry.disable_txsc) {
8039                 plist = phead->next;
8040                 while(plist != phead)   {
8041                         pstat = list_entry(plist, struct stat_info, asoc_list);
8042                         if(pstat->expire_to) {
8043                                 for (i=0; i<TX_SC_ENTRY_NUM; i++) {
8044                                         struct tx_desc *pdesc= &(pstat->tx_sc_ent[i].hwdesc1);
8045                                         pdesc->Dword2 &= set_desc(~ (BIT(24)|BIT(25)));
8046                                         if((pstat->CurAntenna^priv->pshare->rf_ft_var.CurAntenna)&1)
8047                                                 pdesc->Dword2 |= set_desc(BIT(24)|BIT(25));
8048                                         pdesc= &(pstat->tx_sc_ent[i].hwdesc2);
8049                                         pdesc->Dword2 &= set_desc(~ (BIT(24)|BIT(25)));
8050                                         if((pstat->CurAntenna^priv->pshare->rf_ft_var.CurAntenna)&1)
8051                                                 pdesc->Dword2 |= set_desc(BIT(24)|BIT(25));
8052                                 }
8053                         }
8054
8055                         if (plist == plist->next)
8056                                 break;
8057                         plist = plist->next;
8058                 };
8059         }
8060 #endif
8061 #endif
8062
8063         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("<==============odm_HwAntDiv\n"));
8064
8065 }
8066
8067 VOID
8068 odm_HwAntDiv(
8069         IN      PDM_ODM_T       pDM_Odm
8070 )
8071 {
8072
8073         PADAPTER                pAdapter        = pDM_Odm->Adapter;
8074
8075 #if(DM_ODM_SUPPORT_TYPE==ODM_WIN)
8076         if(pAdapter->MgntInfo.AntennaTest)
8077                 return;
8078 #endif
8079         if(!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV))
8080         {
8081                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("Return: Not Support HW AntDiv\n"));
8082                 return;
8083         }
8084
8085         if(pDM_Odm->SupportICType & (ODM_RTL8192C | ODM_RTL8192D))
8086         {
8087 #if ((RTL8192C_SUPPORT == 1)||(RTL8192D_SUPPORT == 1))
8088                 odm_HwAntDiv_92C_92D(pDM_Odm);
8089 #endif
8090         }
8091 }
8092
8093
8094 #if(DM_ODM_SUPPORT_TYPE==ODM_AP)
8095 #if 0
8096 VOID
8097 odm_HwAntDiv(
8098         IN      PDM_ODM_T       pDM_Odm
8099 )
8100 {
8101         struct rtl8192cd_priv *priv=pDM_Odm->priv;
8102         struct stat_info        *pstat, *pstat_min=NULL;
8103         struct list_head        *phead, *plist;
8104         int rssi_min= 0xff, i;
8105         u1Byte  idleAnt=priv->pshare->rf_ft_var.CurAntenna;
8106         u1Byte  nextAnt;
8107         BOOLEAN         bRet=FALSE;
8108
8109         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("odm_HwAntDiv==============>\n"));
8110
8111         if((!priv->pshare->rf_ft_var.antHw_enable) ||(!(pDM_Odm->SupportAbility & ODM_BB_ANT_DIV)))
8112                 return;
8113
8114         //if test, return
8115         if(priv->pshare->rf_ft_var.CurAntenna & 0x80)
8116                 return;
8117
8118         phead = &priv->asoc_list;
8119         plist = phead->next;
8120         ////=========================
8121         //find mimum rssi sta
8122         ////=========================
8123         while(plist != phead)   {
8124                 pstat = list_entry(plist, struct stat_info, asoc_list);
8125                 if((pstat->expire_to) && (pstat->AntRSSI[0] || pstat->AntRSSI[1])) {
8126                         int rssi = (pstat->AntRSSI[0] < pstat->AntRSSI[1]) ? pstat->AntRSSI[0] : pstat->AntRSSI[1];
8127                         if((!pstat_min) || ( rssi < rssi_min) ) {
8128                                 pstat_min = pstat;
8129                                 rssi_min = rssi;
8130                         }
8131                 }
8132                 ///STA: found out default antenna
8133                 bRet=odm_StaDefAntSel(pDM_Odm,
8134                                                 pstat->hwRxAntSel[1],
8135                                                 pstat->hwRxAntSel[0],
8136                                                 pstat->cckPktCount[1],
8137                                                 pstat->cckPktCount[0],
8138                                                 &nextAnt
8139                                                 );
8140
8141                 //if default antenna selection: successful
8142                 if(bRet){
8143                         pstat->CurAntenna = nextAnt;
8144                         //update rssi
8145                         for(i=0; i<2; i++) {
8146                                 if(pstat->cckPktCount[i]==0 && pstat->hwRxAntSel[i]==0)
8147                                         pstat->AntRSSI[i] = 0;
8148                         }
8149                         if(pstat->AntRSSI[idleAnt]==0)
8150                                 pstat->AntRSSI[idleAnt] = pstat->AntRSSI[idleAnt^1];
8151                         // reset variables
8152                         pstat->hwRxAntSel[1] = pstat->hwRxAntSel[0] =0;
8153                         pstat->cckPktCount[1]= pstat->cckPktCount[0] =0;
8154                 }
8155
8156                 if (plist == plist->next)
8157                         break;
8158                 plist = plist->next;
8159
8160         };
8161         ////=========================
8162         //Choose  RX Idle antenna according to minmum rssi
8163         ////=========================
8164         if(pstat_min)   {
8165                 if(priv->pshare->rf_ft_var.CurAntenna!=pstat_min->CurAntenna)
8166                         odm_SetRxIdleAnt(pDM_Odm,pstat_min->CurAntenna,TRUE);
8167                 priv->pshare->rf_ft_var.CurAntenna = pstat_min->CurAntenna;
8168         }
8169
8170
8171 #ifdef TX_SHORTCUT
8172         if (!priv->pmib->dot11OperationEntry.disable_txsc) {
8173                 plist = phead->next;
8174                 while(plist != phead)   {
8175                         pstat = list_entry(plist, struct stat_info, asoc_list);
8176                         if(pstat->expire_to) {
8177                                 for (i=0; i<TX_SC_ENTRY_NUM; i++) {
8178                                         struct tx_desc *pdesc= &(pstat->tx_sc_ent[i].hwdesc1);
8179                                         pdesc->Dword2 &= set_desc(~ (BIT(24)|BIT(25)));
8180                                         if((pstat->CurAntenna^priv->pshare->rf_ft_var.CurAntenna)&1)
8181                                                 pdesc->Dword2 |= set_desc(BIT(24)|BIT(25));
8182                                         pdesc= &(pstat->tx_sc_ent[i].hwdesc2);
8183                                         pdesc->Dword2 &= set_desc(~ (BIT(24)|BIT(25)));
8184                                         if((pstat->CurAntenna^priv->pshare->rf_ft_var.CurAntenna)&1)
8185                                                 pdesc->Dword2 |= set_desc(BIT(24)|BIT(25));
8186                                 }
8187                         }
8188
8189                         if (plist == plist->next)
8190                                 break;
8191                         plist = plist->next;
8192                 };
8193         }
8194 #endif
8195         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV, ODM_DBG_LOUD,"<==============odm_HwAntDiv\n");
8196 }
8197 #endif
8198
8199 u1Byte
8200 ODM_Diversity_AntennaSelect(
8201         IN      PDM_ODM_T       pDM_Odm,
8202         IN      u1Byte  *data
8203 )
8204 {
8205         struct rtl8192cd_priv *priv=pDM_Odm->priv;
8206
8207         int ant = _atoi(data, 16);
8208
8209         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("ODM_Diversity_AntennaSelect==============>\n"));
8210
8211         #ifdef PCIE_POWER_SAVING
8212         PCIeWakeUp(priv, POWER_DOWN_T0);
8213         #endif
8214
8215         if (ant==AUX_ANT || ant==MAIN_ANT)
8216         {
8217                 if ( !priv->pshare->rf_ft_var.antSw_select) {
8218                         ODM_Write4Byte(pDM_Odm,0x870, ODM_Read4Byte(pDM_Odm,0x870) | BIT(8)| BIT(9) );  //  ANTSEL A as SW control
8219                         ODM_Write1Byte(pDM_Odm,0xc50, ODM_Read1Byte(pDM_Odm,0xc50) & (~ BIT(7)));       // rx OFDM SW control
8220                         PHY_SetBBReg(priv, 0x860, 0x300, ant);
8221                 } else {
8222                         ODM_Write4Byte(pDM_Odm,0x870, ODM_Read4Byte(pDM_Odm,0x870) | BIT(24)| BIT(25) ); // ANTSEL B as HW control
8223                         PHY_SetBBReg(priv, 0x864, 0x300, ant);
8224                         ODM_Write1Byte(pDM_Odm,0xc58, ODM_Read1Byte(pDM_Odm,0xc58) & (~ BIT(7)));               // rx OFDM SW control
8225                 }
8226
8227                 ODM_Write1Byte(pDM_Odm,0xa01, ODM_Read1Byte(pDM_Odm,0xa01) & (~ BIT(7)));       // rx CCK SW control
8228                 ODM_Write4Byte(pDM_Odm,0x80c, ODM_Read4Byte(pDM_Odm,0x80c) & (~ BIT(21))); // select ant by tx desc
8229                 ODM_Write4Byte(pDM_Odm,0x858, 0x569a569a);
8230
8231                 priv->pshare->rf_ft_var.antHw_enable = 0;
8232                 priv->pshare->rf_ft_var.CurAntenna  = (ant%2);
8233
8234                 #ifdef SW_ANT_SWITCH
8235                 priv->pshare->rf_ft_var.antSw_enable = 0;
8236                 priv->pshare->DM_SWAT_Table.CurAntenna = ant;
8237                 priv->pshare->RSSI_test =0;
8238                 #endif
8239         }
8240         else if(ant==0){
8241
8242                 if ( !priv->pshare->rf_ft_var.antSw_select)  {
8243                         ODM_Write4Byte(pDM_Odm,0x870, ODM_Read4Byte(pDM_Odm,0x870) & ~(BIT(8)| BIT(9)) );
8244                         ODM_Write1Byte(pDM_Odm,0xc50, ODM_Read1Byte(pDM_Odm,0xc50) | BIT(7));   // OFDM HW control
8245                 } else {
8246                         ODM_Write4Byte(pDM_Odm,0x870, ODM_Read4Byte(pDM_Odm,0x870) & ~(BIT(24)| BIT(25)) );
8247                         ODM_Write1Byte(pDM_Odm,0xc58, ODM_Read1Byte(pDM_Odm,0xc58) | BIT(7));   // OFDM HW control
8248                 }
8249
8250                 ODM_Write1Byte(pDM_Odm,0xa01, ODM_Read1Byte(pDM_Odm,0xa01) | BIT(7));   // CCK HW control
8251                 ODM_Write4Byte(pDM_Odm,0x80c, ODM_Read4Byte(pDM_Odm,0x80c) | BIT(21) ); // by tx desc
8252                 priv->pshare->rf_ft_var.CurAntenna = 0;
8253                 ODM_Write4Byte(pDM_Odm,0x858, 0x569a569a);
8254                 priv->pshare->rf_ft_var.antHw_enable = 1;
8255 #ifdef SW_ANT_SWITCH
8256                 priv->pshare->rf_ft_var.antSw_enable = 0;
8257                 priv->pshare->RSSI_test =0;
8258 #endif
8259         }
8260 #ifdef SW_ANT_SWITCH
8261         else if(ant==3) {
8262                 if(!priv->pshare->rf_ft_var.antSw_enable) {
8263
8264                         dm_SW_AntennaSwitchInit(priv);
8265                         ODM_Write4Byte(pDM_Odm,0x858, 0x569a569a);
8266                         priv->pshare->lastTxOkCnt = priv->net_stats.tx_bytes;
8267                         priv->pshare->lastRxOkCnt = priv->net_stats.rx_bytes;
8268                 }
8269                 if ( !priv->pshare->rf_ft_var.antSw_select)
8270                         ODM_Write1Byte(pDM_Odm,0xc50, ODM_Read1Byte(pDM_Odm,0xc50) & (~ BIT(7)));       // rx OFDM SW control
8271                 else
8272                         ODM_Write1Byte(pDM_Odm,0xc58, ODM_Read1Byte(pDM_Odm,0xc58) & (~ BIT(7)));       // rx OFDM SW control
8273
8274                 ODM_Write1Byte(pDM_Odm,0xa01, ODM_Read1Byte(pDM_Odm,0xa01) & (~ BIT(7)));               // rx CCK SW control
8275                 ODM_Write4Byte(pDM_Odm,0x80c, ODM_Read4Byte(pDM_Odm,0x80c) & (~ BIT(21)));      // select ant by tx desc
8276                 priv->pshare->rf_ft_var.antHw_enable = 0;
8277                 priv->pshare->rf_ft_var.antSw_enable = 1;
8278
8279         }
8280 #endif
8281         ODM_RT_TRACE(pDM_Odm, ODM_COMP_ANT_DIV,ODM_DBG_LOUD,("<==============ODM_Diversity_AntennaSelect\n"));
8282
8283         return 1;
8284 }
8285 #endif
8286
8287 #else //#if(defined(CONFIG_HW_ANTENNA_DIVERSITY))
8288
8289 VOID odm_InitHybridAntDiv(      IN PDM_ODM_T    pDM_Odm         ){}
8290 VOID odm_HwAntDiv(      IN      PDM_ODM_T       pDM_Odm){}
8291 #if(DM_ODM_SUPPORT_TYPE==ODM_WIN)
8292 VOID ODM_SetTxAntByTxInfo_88C_92D(
8293         IN              PDM_ODM_T               pDM_Odm,
8294         IN              pu1Byte                 pDesc,
8295         IN              u1Byte                  macId
8296 ){}
8297 #elif(DM_ODM_SUPPORT_TYPE==ODM_CE)
8298 VOID ODM_SetTxAntByTxInfo_88C_92D(      IN              PDM_ODM_T               pDM_Odm){ }
8299 #elif(DM_ODM_SUPPORT_TYPE==ODM_AP)
8300 VOID ODM_SetTxAntByTxInfo_88C_92D(      IN              PDM_ODM_T               pDM_Odm){ }
8301 #endif
8302
8303 #endif //#if(defined(CONFIG_HW_ANTENNA_DIVERSITY))
8304
8305
8306
8307 //============================================================
8308 //EDCA Turbo
8309 //============================================================
8310 VOID
8311 ODM_EdcaTurboInit(
8312         IN    PDM_ODM_T         pDM_Odm)
8313 {
8314
8315 #if ((DM_ODM_SUPPORT_TYPE == ODM_AP)||(DM_ODM_SUPPORT_TYPE==ODM_ADSL))
8316         odm_EdcaParaInit(pDM_Odm);
8317 #elif (DM_ODM_SUPPORT_TYPE==ODM_WIN)
8318         PADAPTER        Adapter = NULL;
8319         HAL_DATA_TYPE   *pHalData = NULL;
8320
8321         if(pDM_Odm->Adapter==NULL)      {
8322                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("EdcaTurboInit fail!!!\n"));
8323                 return;
8324         }
8325
8326         Adapter=pDM_Odm->Adapter;
8327         pHalData=GET_HAL_DATA(Adapter);
8328
8329         pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = FALSE;
8330         pDM_Odm->DM_EDCA_Table.bIsCurRDLState = FALSE;
8331         pHalData->bIsAnyNonBEPkts = FALSE;
8332
8333 #elif(DM_ODM_SUPPORT_TYPE==ODM_CE)
8334         PADAPTER        Adapter = pDM_Odm->Adapter;
8335         pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = FALSE;
8336         pDM_Odm->DM_EDCA_Table.bIsCurRDLState = FALSE;
8337         Adapter->recvpriv.bIsAnyNonBEPkts =FALSE;
8338
8339 #endif
8340         ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Orginial VO PARAM: 0x%x\n",ODM_Read4Byte(pDM_Odm,ODM_EDCA_VO_PARAM)));
8341         ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Orginial VI PARAM: 0x%x\n",ODM_Read4Byte(pDM_Odm,ODM_EDCA_VI_PARAM)));
8342         ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Orginial BE PARAM: 0x%x\n",ODM_Read4Byte(pDM_Odm,ODM_EDCA_BE_PARAM)));
8343         ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Orginial BK PARAM: 0x%x\n",ODM_Read4Byte(pDM_Odm,ODM_EDCA_BK_PARAM)));
8344
8345
8346 }       // ODM_InitEdcaTurbo
8347
8348 VOID
8349 odm_EdcaTurboCheck(
8350         IN              PDM_ODM_T               pDM_Odm
8351         )
8352 {
8353         //
8354         // For AP/ADSL use prtl8192cd_priv
8355         // For CE/NIC use PADAPTER
8356         //
8357
8358         //
8359         // 2011/09/29 MH In HW integration first stage, we provide 4 different handle to operate
8360         // at the same time. In the stage2/3, we need to prive universal interface and merge all
8361         // HW dynamic mechanism.
8362         //
8363         ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("odm_EdcaTurboCheck========================>\n"));
8364
8365         if(!(pDM_Odm->SupportAbility& ODM_MAC_EDCA_TURBO ))
8366                 return;
8367
8368         switch  (pDM_Odm->SupportPlatform)
8369         {
8370                 case    ODM_WIN:
8371
8372 #if(DM_ODM_SUPPORT_TYPE==ODM_WIN)
8373                         odm_EdcaTurboCheckMP(pDM_Odm);
8374 #endif
8375                         break;
8376
8377                 case    ODM_CE:
8378 #if(DM_ODM_SUPPORT_TYPE==ODM_CE)
8379                         odm_EdcaTurboCheckCE(pDM_Odm);
8380 #endif
8381                         break;
8382
8383                 case    ODM_AP:
8384                 case    ODM_ADSL:
8385
8386 #if ((DM_ODM_SUPPORT_TYPE == ODM_AP)||(DM_ODM_SUPPORT_TYPE==ODM_ADSL))
8387                 odm_IotEngine(pDM_Odm);
8388 #endif
8389                         break;
8390         }
8391         ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("<========================odm_EdcaTurboCheck\n"));
8392
8393 }       // odm_CheckEdcaTurbo
8394
8395 #if(DM_ODM_SUPPORT_TYPE==ODM_CE)
8396
8397
8398 VOID
8399 odm_EdcaTurboCheckCE(
8400         IN              PDM_ODM_T               pDM_Odm
8401         )
8402 {
8403
8404 #if(DM_ODM_SUPPORT_TYPE==ODM_CE)
8405
8406         PADAPTER                       Adapter = pDM_Odm->Adapter;
8407         u32     EDCA_BE_UL = 0x5ea42b;//Parameter suggested by Scott  //edca_setting_UL[pMgntInfo->IOTPeer];
8408         u32     EDCA_BE_DL = 0x5ea42b;//Parameter suggested by Scott  //edca_setting_DL[pMgntInfo->IOTPeer];
8409         u32     ICType=pDM_Odm->SupportICType;
8410         u32     IOTPeer=0;
8411         u8      WirelessMode=0xFF;                   //invalid value
8412         u32     trafficIndex;
8413         u32     edca_param;
8414         u64     cur_tx_bytes = 0;
8415         u64     cur_rx_bytes = 0;
8416         u8      bbtchange = _FALSE;
8417         u8      bBiasOnRx = _FALSE;
8418         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(Adapter);
8419         struct dvobj_priv               *pdvobjpriv = adapter_to_dvobj(Adapter);
8420         struct xmit_priv                *pxmitpriv = &(Adapter->xmitpriv);
8421         struct recv_priv                *precvpriv = &(Adapter->recvpriv);
8422         struct registry_priv    *pregpriv = &Adapter->registrypriv;
8423         struct mlme_ext_priv    *pmlmeext = &(Adapter->mlmeextpriv);
8424         struct mlme_ext_info    *pmlmeinfo = &(pmlmeext->mlmext_info);
8425
8426         if(pDM_Odm->bLinked != _TRUE)
8427                 goto dm_CheckEdcaTurbo_EXIT;
8428
8429         if ((pregpriv->wifi_spec == 1) )//|| (pmlmeinfo->HT_enable == 0))
8430         {
8431                 goto dm_CheckEdcaTurbo_EXIT;
8432         }
8433
8434         if(pDM_Odm->pWirelessMode!=NULL)
8435                 WirelessMode=*(pDM_Odm->pWirelessMode);
8436
8437         IOTPeer = pmlmeinfo->assoc_AP_vendor;
8438
8439         if (IOTPeer >=  HT_IOT_PEER_MAX)
8440         {
8441                 goto dm_CheckEdcaTurbo_EXIT;
8442         }
8443
8444         if(     (pDM_Odm->SupportICType == ODM_RTL8192C) ||
8445                 (pDM_Odm->SupportICType == ODM_RTL8723A) ||
8446                 (pDM_Odm->SupportICType == ODM_RTL8188E))
8447         {
8448                 if((IOTPeer == HT_IOT_PEER_RALINK)||(IOTPeer == HT_IOT_PEER_ATHEROS))
8449                         bBiasOnRx = _TRUE;
8450         }
8451
8452         // Check if the status needs to be changed.
8453         if((bbtchange) || (!precvpriv->bIsAnyNonBEPkts) )
8454         {
8455                 cur_tx_bytes = pdvobjpriv->traffic_stat.cur_tx_bytes;
8456                 cur_rx_bytes = pdvobjpriv->traffic_stat.cur_rx_bytes;
8457
8458                 //traffic, TX or RX
8459                 if(bBiasOnRx)
8460                 {
8461                         if (cur_tx_bytes > (cur_rx_bytes << 2))
8462                         { // Uplink TP is present.
8463                                 trafficIndex = UP_LINK;
8464                         }
8465                         else
8466                         { // Balance TP is present.
8467                                 trafficIndex = DOWN_LINK;
8468                         }
8469                 }
8470                 else
8471                 {
8472                         if (cur_rx_bytes > (cur_tx_bytes << 2))
8473                         { // Downlink TP is present.
8474                                 trafficIndex = DOWN_LINK;
8475                         }
8476                         else
8477                         { // Balance TP is present.
8478                                 trafficIndex = UP_LINK;
8479                         }
8480                 }
8481
8482                 //if ((pDM_Odm->DM_EDCA_Table.prv_traffic_idx != trafficIndex) || (!pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA))
8483                 {
8484                         if(ICType==ODM_RTL8192D)
8485                         {
8486                                 // Single PHY
8487                                 if(pDM_Odm->RFType==ODM_2T2R)
8488                                 {
8489                                         EDCA_BE_UL = 0x60a42b;    //0x5ea42b;
8490                                         EDCA_BE_DL = 0x60a42b;    //0x5ea42b;
8491                                 }
8492                                 else
8493                                 {
8494                                         EDCA_BE_UL = 0x6ea42b;
8495                                         EDCA_BE_DL = 0x6ea42b;
8496                                 }
8497                         }
8498                         else
8499                         {
8500                                 if(pDM_Odm->SupportInterface==ODM_ITRF_PCIE) {
8501                                         if((ICType==ODM_RTL8192C)&&(pDM_Odm->RFType==ODM_2T2R)) {
8502                                                 EDCA_BE_UL = 0x60a42b;
8503                                                 EDCA_BE_DL = 0x60a42b;
8504                                         }
8505                                         else
8506                                         {
8507                                                 EDCA_BE_UL = 0x6ea42b;
8508                                                 EDCA_BE_DL = 0x6ea42b;
8509                                         }
8510                                 }
8511                         }
8512
8513                         //92D txop can't be set to 0x3e for cisco1250
8514                         if((ICType!=ODM_RTL8192D) && (IOTPeer== HT_IOT_PEER_CISCO) &&(WirelessMode==ODM_WM_N24G))
8515                         {
8516                                 EDCA_BE_DL = edca_setting_DL[IOTPeer];
8517                                 EDCA_BE_UL = edca_setting_UL[IOTPeer];
8518                         }
8519                         //merge from 92s_92c_merge temp brunch v2445    20120215
8520                         else if((IOTPeer == HT_IOT_PEER_CISCO) &&((WirelessMode==ODM_WM_G)||(WirelessMode==(ODM_WM_B|ODM_WM_G))||(WirelessMode==ODM_WM_A)||(WirelessMode==ODM_WM_B)))
8521                         {
8522                                 EDCA_BE_DL = edca_setting_DL_GMode[IOTPeer];
8523                         }
8524                         else if((IOTPeer== HT_IOT_PEER_AIRGO )&& ((WirelessMode==ODM_WM_G)||(WirelessMode==ODM_WM_A)))
8525                         {
8526                                 EDCA_BE_DL = 0xa630;
8527                         }
8528                         else if(IOTPeer == HT_IOT_PEER_MARVELL)
8529                         {
8530                                 EDCA_BE_DL = edca_setting_DL[IOTPeer];
8531                                 EDCA_BE_UL = edca_setting_UL[IOTPeer];
8532                         }
8533                         else if(IOTPeer == HT_IOT_PEER_ATHEROS)
8534                         {
8535                                 // Set DL EDCA for Atheros peer to 0x3ea42b. Suggested by SD3 Wilson for ASUS TP issue.
8536                                 EDCA_BE_DL = edca_setting_DL[IOTPeer];
8537                         }
8538
8539                         if((ICType==ODM_RTL8812)||(ICType==ODM_RTL8821)||(ICType==ODM_RTL8192E))           //add 8812AU/8812AE
8540                         {
8541                                 EDCA_BE_UL = 0x5ea42b;
8542                                 EDCA_BE_DL = 0x5ea42b;
8543
8544                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("8812A: EDCA_BE_UL=0x%x EDCA_BE_DL =0x%x",EDCA_BE_UL,EDCA_BE_DL));
8545                         }
8546
8547                         if (trafficIndex == DOWN_LINK)
8548                                 edca_param = EDCA_BE_DL;
8549                         else
8550                                 edca_param = EDCA_BE_UL;
8551
8552                         rtw_write32(Adapter, REG_EDCA_BE_PARAM, edca_param);
8553
8554                         pDM_Odm->DM_EDCA_Table.prv_traffic_idx = trafficIndex;
8555                 }
8556
8557                 pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = _TRUE;
8558         }
8559         else
8560         {
8561                 //
8562                 // Turn Off EDCA turbo here.
8563                 // Restore original EDCA according to the declaration of AP.
8564                 //
8565                  if(pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA)
8566                 {
8567                         rtw_write32(Adapter, REG_EDCA_BE_PARAM, pHalData->AcParam_BE);
8568                         pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = _FALSE;
8569                 }
8570         }
8571
8572 dm_CheckEdcaTurbo_EXIT:
8573         // Set variables for next time.
8574         precvpriv->bIsAnyNonBEPkts = _FALSE;
8575 #endif
8576 }
8577
8578
8579 #elif(DM_ODM_SUPPORT_TYPE==ODM_WIN)
8580 VOID
8581 odm_EdcaTurboCheckMP(
8582         IN              PDM_ODM_T               pDM_Odm
8583         )
8584 {
8585
8586
8587         PADAPTER                       Adapter = pDM_Odm->Adapter;
8588         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(Adapter);
8589
8590         PADAPTER                        pDefaultAdapter = GetDefaultAdapter(Adapter);
8591         PADAPTER                        pExtAdapter = GetFirstExtAdapter(Adapter);//NULL;
8592         PMGNT_INFO                      pMgntInfo = &Adapter->MgntInfo;
8593         PSTA_QOS                        pStaQos = Adapter->MgntInfo.pStaQos;
8594         //[Win7 Count Tx/Rx statistic for Extension Port] odm_CheckEdcaTurbo's Adapter is always Default. 2009.08.20, by Bohn
8595         u8Byte                          Ext_curTxOkCnt = 0;
8596         u8Byte                          Ext_curRxOkCnt = 0;
8597         //For future Win7  Enable Default Port to modify AMPDU size dynamically, 2009.08.20, Bohn.
8598         u1Byte TwoPortStatus = (u1Byte)TWO_PORT_STATUS__WITHOUT_ANY_ASSOCIATE;
8599
8600         // Keep past Tx/Rx packet count for RT-to-RT EDCA turbo.
8601         u8Byte                          curTxOkCnt = 0;
8602         u8Byte                          curRxOkCnt = 0;
8603         u4Byte                          EDCA_BE_UL = 0x5ea42b;//Parameter suggested by Scott  //edca_setting_UL[pMgntInfo->IOTPeer];
8604         u4Byte                          EDCA_BE_DL = 0x5ea42b;//Parameter suggested by Scott  //edca_setting_DL[pMgntInfo->IOTPeer];
8605         u4Byte                         EDCA_BE = 0x5ea42b;
8606         u1Byte                         IOTPeer=0;
8607         BOOLEAN                      *pbIsCurRDLState=NULL;
8608         BOOLEAN                      bLastIsCurRDLState=FALSE;
8609         BOOLEAN                          bBiasOnRx=FALSE;
8610         BOOLEAN                         bEdcaTurboOn=FALSE;
8611         u1Byte                          TxRate = 0xFF;
8612         u8Byte                          value64;
8613
8614         ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("odm_EdcaTurboCheckMP========================>"));
8615         ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Orginial BE PARAM: 0x%x\n",ODM_Read4Byte(pDM_Odm,ODM_EDCA_BE_PARAM)));
8616
8617 ////===============================
8618 ////list paramter for different platform
8619 ////===============================
8620         bLastIsCurRDLState=pDM_Odm->DM_EDCA_Table.bIsCurRDLState;
8621         pbIsCurRDLState=&(pDM_Odm->DM_EDCA_Table.bIsCurRDLState);
8622
8623         //2012/09/14 MH Add
8624         if (pMgntInfo->NumNonBePkt > pMgntInfo->RegEdcaThresh && !Adapter->MgntInfo.bWiFiConfg)
8625                 pHalData->bIsAnyNonBEPkts = TRUE;
8626
8627         pMgntInfo->NumNonBePkt = 0;
8628
8629        // Caculate TX/RX TP:
8630         //curTxOkCnt = Adapter->TxStats.NumTxBytesUnicast - pMgntInfo->lastTxOkCnt;
8631         //curRxOkCnt = Adapter->RxStats.NumRxBytesUnicast - pMgntInfo->lastRxOkCnt;
8632         curTxOkCnt = Adapter->TxStats.NumTxBytesUnicast - pDM_Odm->lastTxOkCnt;
8633         curRxOkCnt = Adapter->RxStats.NumRxBytesUnicast - pDM_Odm->lastRxOkCnt;
8634         pDM_Odm->lastTxOkCnt = Adapter->TxStats.NumTxBytesUnicast;
8635         pDM_Odm->lastRxOkCnt = Adapter->RxStats.NumRxBytesUnicast;
8636
8637         if(pExtAdapter == NULL)
8638                 pExtAdapter = pDefaultAdapter;
8639
8640         Ext_curTxOkCnt = pExtAdapter->TxStats.NumTxBytesUnicast - pMgntInfo->Ext_lastTxOkCnt;
8641         Ext_curRxOkCnt = pExtAdapter->RxStats.NumRxBytesUnicast - pMgntInfo->Ext_lastRxOkCnt;
8642         GetTwoPortSharedResource(Adapter,TWO_PORT_SHARED_OBJECT__STATUS,NULL,&TwoPortStatus);
8643         //For future Win7  Enable Default Port to modify AMPDU size dynamically, 2009.08.20, Bohn.
8644         if(TwoPortStatus == TWO_PORT_STATUS__EXTENSION_ONLY)
8645         {
8646                 curTxOkCnt = Ext_curTxOkCnt ;
8647                 curRxOkCnt = Ext_curRxOkCnt ;
8648         }
8649         //
8650         IOTPeer=pMgntInfo->IOTPeer;
8651         bBiasOnRx=(pMgntInfo->IOTAction & HT_IOT_ACT_EDCA_BIAS_ON_RX)?TRUE:FALSE;
8652         bEdcaTurboOn=((!pHalData->bIsAnyNonBEPkts) && (!pMgntInfo->bDisableFrameBursting))?TRUE:FALSE;
8653         ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("bIsAnyNonBEPkts : 0x%lx  bDisableFrameBursting : 0x%lx  \n",pHalData->bIsAnyNonBEPkts,pMgntInfo->bDisableFrameBursting));
8654
8655
8656 ////===============================
8657 ////check if edca turbo is disabled
8658 ////===============================
8659         if(odm_IsEdcaTurboDisable(pDM_Odm))
8660                 goto dm_CheckEdcaTurbo_EXIT;
8661
8662
8663 ////===============================
8664 ////remove iot case out
8665 ////===============================
8666         ODM_EdcaParaSelByIot(pDM_Odm, &EDCA_BE_UL, &EDCA_BE_DL);
8667
8668
8669 ////===============================
8670 ////Check if the status needs to be changed.
8671 ////===============================
8672         if(bEdcaTurboOn)
8673         {
8674                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("bEdcaTurboOn : 0x%x bBiasOnRx : 0x%x\n",bEdcaTurboOn,bBiasOnRx));
8675                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("curTxOkCnt : 0x%lx \n",curTxOkCnt));
8676                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("curRxOkCnt : 0x%lx \n",curRxOkCnt));
8677                 if(bBiasOnRx)
8678                         odm_EdcaChooseTrafficIdx(pDM_Odm,curTxOkCnt, curRxOkCnt,   TRUE,  pbIsCurRDLState);
8679                 else
8680                         odm_EdcaChooseTrafficIdx(pDM_Odm,curTxOkCnt, curRxOkCnt,   FALSE,  pbIsCurRDLState);
8681
8682 //modify by Guo.Mingzhi 2011-12-29
8683                         EDCA_BE=((*pbIsCurRDLState)==TRUE)?EDCA_BE_DL:EDCA_BE_UL;
8684                         if(IS_HARDWARE_TYPE_8821U(Adapter))
8685                         {
8686                                 if(pMgntInfo->RegTxDutyEnable)
8687                                 {
8688                                         //2013.01.23 LukeLee: debug for 8811AU thermal issue (reduce Tx duty cycle)
8689                                         if(!pMgntInfo->ForcedDataRate) //auto rate
8690                                         {
8691                                                 if(pDM_Odm->TxRate != 0xFF)
8692                                                         TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate);
8693                                         }
8694                                         else //force rate
8695                                         {
8696                                                 TxRate = (u1Byte) pMgntInfo->ForcedDataRate;
8697                                         }
8698
8699                                         value64 = (curRxOkCnt<<2);
8700                                         if(curTxOkCnt < value64) //Downlink
8701                                                 ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,EDCA_BE);
8702                                         else //Uplink
8703                                         {
8704                                                 //DbgPrint("pDM_Odm->RFCalibrateInfo.ThermalValue = 0x%X\n", pDM_Odm->RFCalibrateInfo.ThermalValue);
8705                                                 //if(pDM_Odm->RFCalibrateInfo.ThermalValue < pHalData->EEPROMThermalMeter)
8706                                                 if((pDM_Odm->RFCalibrateInfo.ThermalValue < 0x2c) || (*pDM_Odm->pBandType == BAND_ON_2_4G))
8707                                                         ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,EDCA_BE);
8708                                                 else
8709                                                 {
8710                                                         switch (TxRate)
8711                                                         {
8712                                                                 case MGN_VHT1SS_MCS6:
8713                                                                 case MGN_VHT1SS_MCS5:
8714                                                                 case MGN_MCS6:
8715                                                                 case MGN_MCS5:
8716                                                                 case MGN_48M:
8717                                                                 case MGN_54M:
8718                                                                         ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0x1ea42b);
8719                                                                 break;
8720                                                                 case MGN_VHT1SS_MCS4:
8721                                                                 case MGN_MCS4:
8722                                                                 case MGN_36M:
8723                                                                         ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0xa42b);
8724                                                                 break;
8725                                                                 case MGN_VHT1SS_MCS3:
8726                                                                 case MGN_MCS3:
8727                                                                 case MGN_24M:
8728                                                                         ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0xa47f);
8729                                                                 break;
8730                                                                 case MGN_VHT1SS_MCS2:
8731                                                                 case MGN_MCS2:
8732                                                                 case MGN_18M:
8733                                                                         ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0xa57f);
8734                                                                 break;
8735                                                                 case MGN_VHT1SS_MCS1:
8736                                                                 case MGN_MCS1:
8737                                                                 case MGN_9M:
8738                                                                 case MGN_12M:
8739                                                                         ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0xa77f);
8740                                                                 break;
8741                                                                 case MGN_VHT1SS_MCS0:
8742                                                                 case MGN_MCS0:
8743                                                                 case MGN_6M:
8744                                                                         ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0xa87f);
8745                                                                 break;
8746                                                                 default:
8747                                                                         ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,EDCA_BE);
8748                                                                 break;
8749                                                         }
8750                                                 }
8751                                         }
8752                                 }
8753                                 else
8754                                 {
8755                                         ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,EDCA_BE);
8756                                 }
8757
8758                         }
8759                         else if (IS_HARDWARE_TYPE_8812AU(Adapter)){
8760                                 if(pMgntInfo->RegTxDutyEnable)
8761                                 {
8762                                         //2013.07.26 Wilson: debug for 8812AU thermal issue (reduce Tx duty cycle)
8763                                         // it;s the same issue as 8811AU
8764                                         if(!pMgntInfo->ForcedDataRate) //auto rate
8765                                         {
8766                                                 if(pDM_Odm->TxRate != 0xFF)
8767                                                         TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate);
8768                                         }
8769                                         else //force rate
8770                                         {
8771                                                 TxRate = (u1Byte) pMgntInfo->ForcedDataRate;
8772                                         }
8773
8774                                         value64 = (curRxOkCnt<<2);
8775                                         if(curTxOkCnt < value64) //Downlink
8776                                                 ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,EDCA_BE);
8777                                         else //Uplink
8778                                         {
8779                                                 //DbgPrint("pDM_Odm->RFCalibrateInfo.ThermalValue = 0x%X\n", pDM_Odm->RFCalibrateInfo.ThermalValue);
8780                                                 //if(pDM_Odm->RFCalibrateInfo.ThermalValue < pHalData->EEPROMThermalMeter)
8781                                                 if((pDM_Odm->RFCalibrateInfo.ThermalValue < 0x2c) || (*pDM_Odm->pBandType == BAND_ON_2_4G))
8782                                                         ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,EDCA_BE);
8783                                                 else
8784                                                 {
8785                                                         switch (TxRate)
8786                                                         {
8787                                                                 case MGN_VHT2SS_MCS9:
8788                                                                 case MGN_VHT1SS_MCS9:
8789                                                                 case MGN_VHT1SS_MCS8:
8790                                                                 case MGN_MCS15:
8791                                                                 case MGN_MCS7:
8792                                                                         ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0x1ea44f);
8793                                                                 case MGN_VHT2SS_MCS8:
8794                                                                 case MGN_VHT1SS_MCS7:
8795                                                                 case MGN_MCS14:
8796                                                                 case MGN_MCS6:
8797                                                                 case MGN_54M:
8798                                                                         ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0xa44f);
8799                                                                 case MGN_VHT2SS_MCS7:
8800                                                                 case MGN_VHT2SS_MCS6:
8801                                                                 case MGN_VHT1SS_MCS6:
8802                                                                 case MGN_VHT1SS_MCS5:
8803                                                                 case MGN_MCS13:
8804                                                                 case MGN_MCS5:
8805                                                                 case MGN_48M:
8806                                                                         ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0xa630);
8807                                                                 break;
8808                                                                 case MGN_VHT2SS_MCS5:
8809                                                                 case MGN_VHT2SS_MCS4:
8810                                                                 case MGN_VHT1SS_MCS4:
8811                                                                 case MGN_VHT1SS_MCS3:
8812                                                                 case MGN_MCS12:
8813                                                                 case MGN_MCS4:
8814                                                                 case MGN_MCS3:
8815                                                                 case MGN_36M:
8816                                                                 case MGN_24M:
8817                                                                         ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0xa730);
8818                                                                 break;
8819                                                                 case MGN_VHT2SS_MCS3:
8820                                                                 case MGN_VHT2SS_MCS2:
8821                                                                 case MGN_VHT2SS_MCS1:
8822                                                                 case MGN_VHT1SS_MCS2:
8823                                                                 case MGN_VHT1SS_MCS1:
8824                                                                 case MGN_MCS11:
8825                                                                 case MGN_MCS10:
8826                                                                 case MGN_MCS9:
8827                                                                 case MGN_MCS2:
8828                                                                 case MGN_MCS1:
8829                                                                 case MGN_18M:
8830                                                                 case MGN_12M:
8831                                                                         ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0xa830);
8832                                                                 break;
8833                                                                 case MGN_VHT2SS_MCS0:
8834                                                                 case MGN_VHT1SS_MCS0:
8835                                                                 case MGN_MCS0:
8836                                                                 case MGN_MCS8:
8837                                                                 case MGN_9M:
8838                                                                 case MGN_6M:
8839                                                                         ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,0xa87f);
8840                                                                 break;
8841                                                                 default:
8842                                                                         ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,EDCA_BE);
8843                                                                 break;
8844                                                         }
8845                                                 }
8846                                         }
8847                                 }
8848                                 else
8849                                 {
8850                                         ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,EDCA_BE);
8851                                 }
8852                         }
8853                         else
8854                                 ODM_Write4Byte(pDM_Odm,ODM_EDCA_BE_PARAM,EDCA_BE);
8855
8856                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("EDCA Turbo on: EDCA_BE:0x%lx\n",EDCA_BE));
8857
8858                 pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = TRUE;
8859
8860                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("EDCA_BE_DL : 0x%lx  EDCA_BE_UL : 0x%lx  EDCA_BE : 0x%lx  \n",EDCA_BE_DL,EDCA_BE_UL,EDCA_BE));
8861
8862         }
8863         else
8864         {
8865                 // Turn Off EDCA turbo here.
8866                 // Restore original EDCA according to the declaration of AP.
8867                  if(pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA)
8868                 {
8869                         Adapter->HalFunc.SetHwRegHandler(Adapter, HW_VAR_AC_PARAM, GET_WMM_PARAM_ELE_SINGLE_AC_PARAM(pStaQos->WMMParamEle, AC0_BE) );
8870
8871                         pDM_Odm->DM_EDCA_Table.bCurrentTurboEDCA = FALSE;
8872                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Restore EDCA BE: 0x%lx  \n",pDM_Odm->WMMEDCA_BE));
8873
8874                 }
8875         }
8876
8877 ////===============================
8878 ////Set variables for next time.
8879 ////===============================
8880 dm_CheckEdcaTurbo_EXIT:
8881 #if (DM_ODM_SUPPORT_TYPE==ODM_WIN)
8882         pHalData->bIsAnyNonBEPkts = FALSE;
8883         pMgntInfo->lastTxOkCnt = Adapter->TxStats.NumTxBytesUnicast;
8884         pMgntInfo->lastRxOkCnt = Adapter->RxStats.NumRxBytesUnicast;
8885         pMgntInfo->Ext_lastTxOkCnt = pExtAdapter->TxStats.NumTxBytesUnicast;
8886         pMgntInfo->Ext_lastRxOkCnt = pExtAdapter->RxStats.NumRxBytesUnicast;
8887 #elif (DM_ODM_SUPPORT_TYPE==ODM_CE)
8888         precvpriv->bIsAnyNonBEPkts = FALSE;
8889         pxmitpriv->last_tx_bytes = pxmitpriv->tx_bytes;
8890         precvpriv->last_rx_bytes = precvpriv->rx_bytes;
8891 #endif
8892
8893 }
8894
8895
8896 //check if edca turbo is disabled
8897 BOOLEAN
8898 odm_IsEdcaTurboDisable(
8899         IN      PDM_ODM_T       pDM_Odm
8900 )
8901 {
8902         PADAPTER                       Adapter = pDM_Odm->Adapter;
8903
8904 #if(DM_ODM_SUPPORT_TYPE==ODM_WIN)
8905         PMGNT_INFO                      pMgntInfo = &Adapter->MgntInfo;
8906         u4Byte                          IOTPeer=pMgntInfo->IOTPeer;
8907 #elif (DM_ODM_SUPPORT_TYPE==ODM_CE)
8908         struct registry_priv    *pregpriv = &Adapter->registrypriv;
8909         struct mlme_ext_priv    *pmlmeext = &(Adapter->mlmeextpriv);
8910         struct mlme_ext_info    *pmlmeinfo = &(pmlmeext->mlmext_info);
8911         u4Byte                         IOTPeer=pmlmeinfo->assoc_AP_vendor;
8912         u1Byte                         WirelessMode=0xFF;                   //invalid value
8913
8914         if(pDM_Odm->pWirelessMode!=NULL)
8915                 WirelessMode=*(pDM_Odm->pWirelessMode);
8916
8917 #endif
8918
8919         if(pDM_Odm->bBtDisableEdcaTurbo)
8920         {
8921                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD, ("EdcaTurboDisable for BT!!\n"));
8922                 return TRUE;
8923         }
8924
8925         if((!(pDM_Odm->SupportAbility& ODM_MAC_EDCA_TURBO ))||
8926                 (pDM_Odm->bWIFITest)||
8927                 (IOTPeer>= HT_IOT_PEER_MAX))
8928         {
8929                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD, ("EdcaTurboDisable\n"));
8930                 return TRUE;
8931         }
8932
8933
8934 #if (DM_ODM_SUPPORT_TYPE ==ODM_WIN)
8935         // 1. We do not turn on EDCA turbo mode for some AP that has IOT issue
8936         // 2. User may disable EDCA Turbo mode with OID settings.
8937         if(pMgntInfo->IOTAction & HT_IOT_ACT_DISABLE_EDCA_TURBO){
8938                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD, ("IOTAction:EdcaTurboDisable\n"));
8939                 return  TRUE;
8940                 }
8941
8942 #elif(DM_ODM_SUPPORT_TYPE==ODM_CE)
8943         //suggested by Jr.Luke: open TXOP for B/G/BG/A mode 2012-0215
8944         if((WirelessMode==ODM_WM_B)||(WirelessMode==(ODM_WM_B|ODM_WM_G)||(WirelessMode==ODM_WM_G)||(WirelessMode=ODM_WM_A))
8945                 ODM_Write4Byte(pDM_Odm, ODM_EDCA_BE_PARAM, ODM_Read4Byte(pDM_Odm, ODM_EDCA_BE_PARAM)|0x5E0000);
8946
8947         if(pDM_Odm->SupportICType==ODM_RTL8192D)                {
8948                 if ((pregpriv->wifi_spec == 1)  || (pmlmeext->cur_wireless_mode == WIRELESS_11B)) {
8949                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD, ("92D:EdcaTurboDisable\n"));
8950                         return TRUE;
8951                 }
8952         }
8953         else
8954         {
8955                 if((pregpriv->wifi_spec == 1) || (pmlmeinfo->HT_enable == 0)){
8956                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD, ("Others:EdcaTurboDisable\n"));
8957                         return TRUE;
8958                 }
8959         }
8960
8961 #endif
8962
8963         return  FALSE;
8964
8965
8966 }
8967
8968 //add iot case here: for MP/CE
8969 VOID
8970 ODM_EdcaParaSelByIot(
8971         IN      PDM_ODM_T       pDM_Odm,
8972         OUT     u4Byte          *EDCA_BE_UL,
8973         OUT u4Byte              *EDCA_BE_DL
8974         )
8975 {
8976
8977         PADAPTER                       Adapter = pDM_Odm->Adapter;
8978         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(Adapter);
8979         u4Byte                         IOTPeer=0;
8980         u4Byte                         ICType=pDM_Odm->SupportICType;
8981         u1Byte                         WirelessMode=0xFF;                   //invalid value
8982         u4Byte                          RFType=pDM_Odm->RFType;
8983           u4Byte                         IOTPeerSubType=0;
8984
8985 #if(DM_ODM_SUPPORT_TYPE==ODM_WIN)
8986         PMGNT_INFO                      pMgntInfo = &Adapter->MgntInfo;
8987         u1Byte                          TwoPortStatus = (u1Byte)TWO_PORT_STATUS__WITHOUT_ANY_ASSOCIATE;
8988
8989 #elif(DM_ODM_SUPPORT_TYPE==ODM_CE)
8990         struct mlme_ext_info    *pmlmeinfo = &(pmlmeext->mlmext_info);
8991         #ifdef CONFIG_BT_COEXIST
8992         struct btcoexist_priv   *pbtpriv = &(pHalData->bt_coexist);
8993         #endif
8994        u1Byte bbtchange =FALSE;
8995 #endif
8996
8997         if(pDM_Odm->pWirelessMode!=NULL)
8998                 WirelessMode=*(pDM_Odm->pWirelessMode);
8999
9000 ///////////////////////////////////////////////////////////
9001 ////list paramter for different platform
9002 #if (DM_ODM_SUPPORT_TYPE==ODM_WIN)
9003         IOTPeer=pMgntInfo->IOTPeer;
9004         IOTPeerSubType=pMgntInfo->IOTPeerSubtype;
9005         GetTwoPortSharedResource(Adapter,TWO_PORT_SHARED_OBJECT__STATUS,NULL,&TwoPortStatus);
9006
9007 #elif(DM_ODM_SUPPORT_TYPE==ODM_CE)
9008         IOTPeer=pmlmeinfo->assoc_AP_vendor;
9009         #ifdef CONFIG_BT_COEXIST
9010         if(pbtpriv->BT_Coexist)
9011         {
9012                 if( (pbtpriv->BT_EDCA[UP_LINK]!=0) ||  (pbtpriv->BT_EDCA[DOWN_LINK]!=0))
9013                         bbtchange = TRUE;
9014         }
9015         #endif
9016
9017 #endif
9018
9019         if(ICType==ODM_RTL8192D)
9020         {
9021                 // Single PHY
9022                 if(pDM_Odm->RFType==ODM_2T2R)
9023                 {
9024                         (*EDCA_BE_UL) = 0x60a42b;    //0x5ea42b;
9025                         (*EDCA_BE_DL) = 0x60a42b;    //0x5ea42b;
9026
9027                 }
9028                 else
9029                 {
9030                         (*EDCA_BE_UL) = 0x6ea42b;
9031                         (*EDCA_BE_DL) = 0x6ea42b;
9032                 }
9033
9034         }
9035 ////============================
9036 /// IOT case for MP
9037 ////============================
9038 #if (DM_ODM_SUPPORT_TYPE==ODM_WIN)
9039         else
9040         {
9041
9042                 if(pDM_Odm->SupportInterface==ODM_ITRF_PCIE){
9043                         if((ICType==ODM_RTL8192C)&&(pDM_Odm->RFType==ODM_2T2R))                 {
9044                                 (*EDCA_BE_UL) = 0x60a42b;
9045                                 (*EDCA_BE_DL) = 0x60a42b;
9046                         }
9047                         else
9048                         {
9049                                 (*EDCA_BE_UL) = 0x6ea42b;
9050                                 (*EDCA_BE_DL) = 0x6ea42b;
9051                         }
9052                 }
9053         }
9054
9055         if(TwoPortStatus == TWO_PORT_STATUS__EXTENSION_ONLY)
9056         {
9057                 (*EDCA_BE_UL) = 0x5ea42b;//Parameter suggested by Scott  //edca_setting_UL[ExtAdapter->MgntInfo.IOTPeer];
9058                 (*EDCA_BE_DL) = 0x5ea42b;//Parameter suggested by Scott  //edca_setting_DL[ExtAdapter->MgntInfo.IOTPeer];
9059         }
9060
9061         #if (INTEL_PROXIMITY_SUPPORT == 1)
9062         if(pMgntInfo->IntelClassModeInfo.bEnableCA == TRUE)
9063         {
9064                 (*EDCA_BE_UL) = (*EDCA_BE_DL) = 0xa44f;
9065         }
9066         else
9067         #endif
9068         {
9069                 if((!pMgntInfo->bDisableFrameBursting) &&
9070                         (pMgntInfo->IOTAction & (HT_IOT_ACT_FORCED_ENABLE_BE_TXOP|HT_IOT_ACT_AMSDU_ENABLE)))
9071                 {// To check whether we shall force turn on TXOP configuration.
9072                         if(!((*EDCA_BE_UL) & 0xffff0000))
9073                                 (*EDCA_BE_UL) |= 0x005e0000; // Force TxOP limit to 0x005e for UL.
9074                         if(!((*EDCA_BE_DL) & 0xffff0000))
9075                                 (*EDCA_BE_DL) |= 0x005e0000; // Force TxOP limit to 0x005e for DL.
9076                 }
9077
9078                 //92D txop can't be set to 0x3e for cisco1250
9079                 if((ICType!=ODM_RTL8192D) && (IOTPeer== HT_IOT_PEER_CISCO) &&(WirelessMode==ODM_WM_N24G))
9080                 {
9081                         (*EDCA_BE_DL) = edca_setting_DL[IOTPeer];
9082                         (*EDCA_BE_UL) = edca_setting_UL[IOTPeer];
9083                 }
9084                 //merge from 92s_92c_merge temp brunch v2445    20120215
9085                 else if((IOTPeer == HT_IOT_PEER_CISCO) &&((WirelessMode==ODM_WM_G)||(WirelessMode==(ODM_WM_B|ODM_WM_G))||(WirelessMode==ODM_WM_A)||(WirelessMode==ODM_WM_B)))
9086                 {
9087                         (*EDCA_BE_DL) = edca_setting_DL_GMode[IOTPeer];
9088                 }
9089                 else if((IOTPeer== HT_IOT_PEER_AIRGO )&& ((WirelessMode==ODM_WM_G)||(WirelessMode==ODM_WM_A)))
9090                 {
9091                         (*EDCA_BE_DL) = 0xa630;
9092                 }
9093
9094                 else if(IOTPeer == HT_IOT_PEER_MARVELL)
9095                 {
9096                         (*EDCA_BE_DL) = edca_setting_DL[IOTPeer];
9097                         (*EDCA_BE_UL) = edca_setting_UL[IOTPeer];
9098                 }
9099                 else if(IOTPeer == HT_IOT_PEER_ATHEROS)
9100                 {
9101                         // Set DL EDCA for Atheros peer to 0x3ea42b. Suggested by SD3 Wilson for ASUS TP issue.
9102                         (*EDCA_BE_DL) = edca_setting_DL[IOTPeer];
9103
9104                         if(ICType == ODM_RTL8821)
9105                                  (*EDCA_BE_DL) = 0x5ea630;
9106
9107                 }
9108         }
9109
9110         if((ICType == ODM_RTL8192D)&&(IOTPeerSubType == HT_IOT_PEER_LINKSYS_E4200_V1)&&((WirelessMode==ODM_WM_N5G)))
9111         {
9112                 (*EDCA_BE_DL) = 0x432b;
9113                 (*EDCA_BE_UL) = 0x432b;
9114         }
9115
9116
9117
9118         if((ICType==ODM_RTL8812)||(ICType==ODM_RTL8192E))           //add 8812AU/8812AE
9119         {
9120                 (*EDCA_BE_UL) = 0x5ea42b;
9121                 (*EDCA_BE_DL) = 0x5ea42b;
9122
9123                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("8812A: EDCA_BE_UL=0x%lx EDCA_BE_DL =0x%lx",(*EDCA_BE_UL),(*EDCA_BE_DL)));
9124         }
9125
9126         // Revised for Atheros DIR-655 IOT issue to improve down link TP, added by Roger, 2013.03.22.
9127         if((ICType == ODM_RTL8723A) && (IOTPeerSubType== HT_IOT_PEER_ATHEROS_DIR655) &&
9128                 (pMgntInfo->dot11CurrentChannelNumber == 6))
9129         {
9130                 (*EDCA_BE_DL) = 0xa92b;
9131         }
9132
9133 ////============================
9134 /// IOT case for CE
9135 ////============================
9136 #elif (DM_ODM_SUPPORT_TYPE==ODM_CE)
9137
9138         if(RFType==ODM_RTL8192D)
9139         {
9140                 if((IOTPeer == HT_IOT_PEER_CISCO) &&(WirelessMode==ODM_WM_N24G))
9141                 {
9142                         (*EDCA_BE_UL) = EDCAParam[IOTPeer][UP_LINK];
9143                         (*EDCA_BE_DL)=EDCAParam[IOTPeer][DOWN_LINK];
9144                 }
9145                 else if((IOTPeer == HT_IOT_PEER_AIRGO) &&
9146                         ((WirelessMode==ODM_WM_B)||(WirelessMode==(ODM_WM_B|ODM_WM_G))))
9147                         (*EDCA_BE_DL)=0x00a630;
9148
9149                 else if((IOTPeer== HT_IOT_PEER_ATHEROS) &&
9150                                         (WirelessMode&ODM_WM_N5G) &&
9151                                         (Adapter->securitypriv.dot11PrivacyAlgrthm == _AES_ ))
9152                         (*EDCA_BE_DL)=0xa42b;
9153
9154         }
9155         //92C IOT case:
9156         else
9157         {
9158                 #ifdef CONFIG_BT_COEXIST
9159                 if(bbtchange)
9160                 {
9161                         (*EDCA_BE_UL) = pbtpriv->BT_EDCA[UP_LINK];
9162                         (*EDCA_BE_DL) = pbtpriv->BT_EDCA[DOWN_LINK];
9163                 }
9164                 else
9165                 #endif
9166                 {
9167                         if((IOTPeer == HT_IOT_PEER_CISCO) &&(WirelessMode==ODM_WM_N24G))
9168                         {
9169                                 (*EDCA_BE_UL) = EDCAParam[IOTPeer][UP_LINK];
9170                                 (*EDCA_BE_DL)=EDCAParam[IOTPeer][DOWN_LINK];
9171                         }
9172                         else
9173                         {
9174                                 (*EDCA_BE_UL)=EDCAParam[HT_IOT_PEER_UNKNOWN][UP_LINK];
9175                                 (*EDCA_BE_DL)=EDCAParam[HT_IOT_PEER_UNKNOWN][DOWN_LINK];
9176                         }
9177                 }
9178                 if(pDM_Odm->SupportInterface==ODM_ITRF_PCIE){
9179                         if((ICType==ODM_RTL8192C)&&(pDM_Odm->RFType==ODM_2T2R))
9180                         {
9181                                 (*EDCA_BE_UL) = 0x60a42b;
9182                                 (*EDCA_BE_DL) = 0x60a42b;
9183                         }
9184                         else
9185                         {
9186                                 (*EDCA_BE_UL) = 0x6ea42b;
9187                                 (*EDCA_BE_DL) = 0x6ea42b;
9188                         }
9189                 }
9190
9191         }
9192 #endif
9193
9194         ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Special: EDCA_BE_UL=0x%lx EDCA_BE_DL =0x%lx",(*EDCA_BE_UL),(*EDCA_BE_DL)));
9195
9196 }
9197
9198
9199 VOID
9200 odm_EdcaChooseTrafficIdx(
9201         IN      PDM_ODM_T               pDM_Odm,
9202         IN      u8Byte                          cur_tx_bytes,
9203         IN      u8Byte                          cur_rx_bytes,
9204         IN      BOOLEAN                 bBiasOnRx,
9205         OUT BOOLEAN             *pbIsCurRDLState
9206         )
9207 {
9208
9209
9210         if(bBiasOnRx)
9211         {
9212
9213                 if(cur_tx_bytes>(cur_rx_bytes*4))
9214                 {
9215                         *pbIsCurRDLState=FALSE;
9216                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Uplink Traffic\n "));
9217
9218                 }
9219                 else
9220                 {
9221                         *pbIsCurRDLState=TRUE;
9222                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Balance Traffic\n"));
9223
9224                 }
9225         }
9226         else
9227         {
9228                 if(cur_rx_bytes>(cur_tx_bytes*4))
9229                 {
9230                         *pbIsCurRDLState=TRUE;
9231                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Downlink        Traffic\n"));
9232
9233                 }
9234                 else
9235                 {
9236                         *pbIsCurRDLState=FALSE;
9237                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_EDCA_TURBO,ODM_DBG_LOUD,("Balance Traffic\n"));
9238                 }
9239         }
9240
9241         return ;
9242 }
9243
9244 #endif
9245
9246 #if((DM_ODM_SUPPORT_TYPE==ODM_AP)||(DM_ODM_SUPPORT_TYPE==ODM_ADSL))
9247
9248 void odm_EdcaParaInit(
9249         IN      PDM_ODM_T       pDM_Odm
9250         )
9251 {
9252         prtl8192cd_priv priv            = pDM_Odm->priv;
9253         int   mode=priv->pmib->dot11BssType.net_work_type;
9254
9255         static unsigned int slot_time, VO_TXOP, VI_TXOP, sifs_time;
9256         struct ParaRecord EDCA[4];
9257
9258          memset(EDCA, 0, 4*sizeof(struct ParaRecord));
9259
9260         sifs_time = 10;
9261         slot_time = 20;
9262
9263         if (mode & (ODM_WM_N24G|ODM_WM_N5G))
9264                 sifs_time = 16;
9265
9266         if (mode & (ODM_WM_N24G|ODM_WM_N5G| ODM_WM_G|ODM_WM_A))
9267                 slot_time = 9;
9268
9269
9270 #if((defined(RTL_MANUAL_EDCA))&&(DM_ODM_SUPPORT_TYPE==ODM_AP))
9271          if( priv->pmib->dot11QosEntry.ManualEDCA ) {
9272                  if( OPMODE & WIFI_AP_STATE )
9273                          memcpy(EDCA, priv->pmib->dot11QosEntry.AP_manualEDCA, 4*sizeof(struct ParaRecord));
9274                  else
9275                          memcpy(EDCA, priv->pmib->dot11QosEntry.STA_manualEDCA, 4*sizeof(struct ParaRecord));
9276
9277                 #ifdef WIFI_WMM
9278                 if (QOS_ENABLE)
9279                         ODM_Write4Byte(pDM_Odm, ODM_EDCA_VI_PARAM, (EDCA[VI].TXOPlimit<< 16) | (EDCA[VI].ECWmax<< 12) | (EDCA[VI].ECWmin<< 8) | (sifs_time + EDCA[VI].AIFSN* slot_time));
9280                 else
9281                 #endif
9282                         ODM_Write4Byte(pDM_Odm, ODM_EDCA_VI_PARAM, (EDCA[BE].TXOPlimit<< 16) | (EDCA[BE].ECWmax<< 12) | (EDCA[BE].ECWmin<< 8) | (sifs_time + EDCA[VI].AIFSN* slot_time));
9283
9284         }else
9285         #endif //RTL_MANUAL_EDCA
9286         {
9287
9288                  if(OPMODE & WIFI_AP_STATE)
9289                  {
9290                         memcpy(EDCA, rtl_ap_EDCA, 2*sizeof(struct ParaRecord));
9291
9292                         if(mode & (ODM_WM_A|ODM_WM_G|ODM_WM_N24G|ODM_WM_N5G))
9293                                 memcpy(&EDCA[VI], &rtl_ap_EDCA[VI_AG], 2*sizeof(struct ParaRecord));
9294                         else
9295                                 memcpy(&EDCA[VI], &rtl_ap_EDCA[VI], 2*sizeof(struct ParaRecord));
9296                  }
9297                  else
9298                  {
9299                         memcpy(EDCA, rtl_sta_EDCA, 2*sizeof(struct ParaRecord));
9300
9301                         if(mode & (ODM_WM_A|ODM_WM_G|ODM_WM_N24G|ODM_WM_N5G))
9302                                 memcpy(&EDCA[VI], &rtl_sta_EDCA[VI_AG], 2*sizeof(struct ParaRecord));
9303                         else
9304                                 memcpy(&EDCA[VI], &rtl_sta_EDCA[VI], 2*sizeof(struct ParaRecord));
9305                  }
9306
9307         #ifdef WIFI_WMM
9308                 if (QOS_ENABLE)
9309                         ODM_Write4Byte(pDM_Odm, ODM_EDCA_VI_PARAM, (EDCA[VI].TXOPlimit<< 16) | (EDCA[VI].ECWmax<< 12) | (EDCA[VI].ECWmin<< 8) | (sifs_time + EDCA[VI].AIFSN* slot_time));
9310                 else
9311         #endif
9312
9313 #if (DM_ODM_SUPPORT_TYPE==ODM_AP)
9314                         ODM_Write4Byte(pDM_Odm, ODM_EDCA_VI_PARAM,  (EDCA[BK].ECWmax<< 12) | (EDCA[BK].ECWmin<< 8) | (sifs_time + EDCA[VI].AIFSN* slot_time));
9315 #elif(DM_ODM_SUPPORT_TYPE==ODM_ADSL)
9316                         ODM_Write4Byte(pDM_Odm, ODM_EDCA_VI_PARAM,  (EDCA[BK].ECWmax<< 12) | (EDCA[BK].ECWmin<< 8) | (sifs_time + 2* slot_time));
9317 #endif
9318
9319
9320         }
9321
9322         ODM_Write4Byte(pDM_Odm, ODM_EDCA_VO_PARAM, (EDCA[VO].TXOPlimit<< 16) | (EDCA[VO].ECWmax<< 12) | (EDCA[VO].ECWmin<< 8) | (sifs_time + EDCA[VO].AIFSN* slot_time));
9323         ODM_Write4Byte(pDM_Odm, ODM_EDCA_BE_PARAM,  (EDCA[BE].TXOPlimit<< 16) | (EDCA[BE].ECWmax<< 12) | (EDCA[BE].ECWmin<< 8) | (sifs_time + EDCA[BE].AIFSN* slot_time));
9324         ODM_Write4Byte(pDM_Odm, ODM_EDCA_BK_PARAM, (EDCA[BK].TXOPlimit<< 16) | (EDCA[BK].ECWmax<< 12) | (EDCA[BK].ECWmin<< 8) | (sifs_time + EDCA[BK].AIFSN* slot_time));
9325 //      ODM_Write1Byte(pDM_Odm,ACMHWCTRL, 0x00);
9326
9327         priv->pshare->iot_mode_enable = 0;
9328 #if(DM_ODM_SUPPORT_TYPE==ODM_AP)
9329         if (priv->pshare->rf_ft_var.wifi_beq_iot)
9330                 priv->pshare->iot_mode_VI_exist = 0;
9331
9332         #ifdef WMM_VIBE_PRI
9333         priv->pshare->iot_mode_BE_exist = 0;
9334         #endif
9335
9336         #ifdef LOW_TP_TXOP
9337         priv->pshare->BE_cwmax_enhance = 0;
9338         #endif
9339
9340 #elif (DM_ODM_SUPPORT_TYPE==ODM_ADSL)
9341       priv->pshare->iot_mode_BE_exist = 0;
9342 #endif
9343         priv->pshare->iot_mode_VO_exist = 0;
9344 }
9345
9346 BOOLEAN
9347 ODM_ChooseIotMainSTA(
9348         IN      PDM_ODM_T               pDM_Odm,
9349         IN      PSTA_INFO_T             pstat
9350         )
9351 {
9352         prtl8192cd_priv priv = pDM_Odm->priv;
9353         BOOLEAN         bhighTP_found_pstat=FALSE;
9354
9355         if ((GET_ROOT(priv)->up_time % 2) == 0) {
9356                 unsigned int tx_2s_avg = 0;
9357                 unsigned int rx_2s_avg = 0;
9358                 int i=0, aggReady=0;
9359                 unsigned long total_sum = (priv->pshare->current_tx_bytes+priv->pshare->current_rx_bytes);
9360
9361                 pstat->current_tx_bytes += pstat->tx_byte_cnt;
9362                 pstat->current_rx_bytes += pstat->rx_byte_cnt;
9363
9364                 if (total_sum != 0) {
9365                         if (total_sum <= 100) {
9366                         tx_2s_avg = (unsigned int)((pstat->current_tx_bytes*100) / total_sum);
9367                         rx_2s_avg = (unsigned int)((pstat->current_rx_bytes*100) / total_sum);
9368                         } else {
9369                                 tx_2s_avg = (unsigned int)(pstat->current_tx_bytes / (total_sum / 100));
9370                                 rx_2s_avg = (unsigned int)(pstat->current_rx_bytes / (total_sum / 100));
9371                         }
9372
9373                 }
9374
9375 #if(DM_ODM_SUPPORT_TYPE==ODM_ADSL)
9376                 if (pstat->ht_cap_len) {
9377                         if ((tx_2s_avg + rx_2s_avg) >=25 /*50*/) {
9378
9379                                         priv->pshare->highTP_found_pstat = pstat;
9380                                         bhighTP_found_pstat=TRUE;
9381                                 }
9382                         }
9383 #elif(DM_ODM_SUPPORT_TYPE==ODM_AP)
9384                 for(i=0; i<8; i++)
9385                         aggReady += (pstat->ADDBA_ready[i]);
9386                 if (pstat->ht_cap_len && aggReady)
9387                 {
9388                         if ((tx_2s_avg + rx_2s_avg >= 25)) {
9389                                 priv->pshare->highTP_found_pstat = pstat;
9390                         }
9391
9392                 #ifdef CLIENT_MODE
9393                         if (OPMODE & WIFI_STATION_STATE) {
9394 #if (DM_ODM_SUPPORT_TYPE &ODM_AP) && defined(USE_OUT_SRC)
9395                                 if ((pstat->IOTPeer==HT_IOT_PEER_RALINK) && ((tx_2s_avg + rx_2s_avg) >= 45))
9396 #else
9397                                 if(pstat->is_ralink_sta && ((tx_2s_avg + rx_2s_avg) >= 45))
9398 #endif
9399                                         priv->pshare->highTP_found_pstat = pstat;
9400                 }
9401                 #endif
9402         }
9403 #endif
9404         } else {
9405                 pstat->current_tx_bytes = pstat->tx_byte_cnt;
9406                 pstat->current_rx_bytes = pstat->rx_byte_cnt;
9407         }
9408
9409         return bhighTP_found_pstat;
9410 }
9411
9412
9413 #ifdef WIFI_WMM
9414 VOID
9415 ODM_IotEdcaSwitch(
9416         IN      PDM_ODM_T               pDM_Odm,
9417         IN      unsigned char           enable
9418         )
9419 {
9420         prtl8192cd_priv priv    = pDM_Odm->priv;
9421         int   mode=priv->pmib->dot11BssType.net_work_type;
9422         unsigned int slot_time = 20, sifs_time = 10, BE_TXOP = 47, VI_TXOP = 94;
9423         unsigned int vi_cw_max = 4, vi_cw_min = 3, vi_aifs;
9424
9425 #if (DM_ODM_SUPPORT_TYPE==ODM_AP)
9426         if (!(!priv->pmib->dot11OperationEntry.wifi_specific ||
9427                 ((OPMODE & WIFI_AP_STATE) && (priv->pmib->dot11OperationEntry.wifi_specific == 2))
9428         #ifdef CLIENT_MODE
9429                 || ((OPMODE & WIFI_STATION_STATE) && (priv->pmib->dot11OperationEntry.wifi_specific == 2))
9430         #endif
9431                 ))
9432                 return;
9433 #endif
9434
9435         if ((mode & (ODM_WM_N24G|ODM_WM_N5G)) && (priv->pshare->ht_sta_num
9436         #ifdef WDS
9437                 || ((OPMODE & WIFI_AP_STATE) && priv->pmib->dot11WdsInfo.wdsEnabled && priv->pmib->dot11WdsInfo.wdsNum)
9438         #endif
9439                 ))
9440                 sifs_time = 16;
9441
9442         if (mode & (ODM_WM_N24G|ODM_WM_N5G|ODM_WM_G|ODM_WM_A)) {
9443                 slot_time = 9;
9444         }
9445         else
9446         {
9447                 BE_TXOP = 94;
9448                 VI_TXOP = 188;
9449         }
9450
9451 #if (DM_ODM_SUPPORT_TYPE==ODM_ADSL)
9452         if (priv->pshare->iot_mode_VO_exist) {
9453                 // to separate AC_VI and AC_BE to avoid using the same EDCA settings
9454                 if (priv->pshare->iot_mode_BE_exist) {
9455                         vi_cw_max = 5;
9456                         vi_cw_min = 3;
9457                 } else {
9458                         vi_cw_max = 6;
9459                         vi_cw_min = 4;
9460                 }
9461         }
9462         vi_aifs = (sifs_time + ((OPMODE & WIFI_AP_STATE)?1:2) * slot_time);
9463
9464         ODM_Write4Byte(pDM_Odm, ODM_EDCA_VI_PARAM, ((VI_TXOP*(1-priv->pshare->iot_mode_VO_exist)) << 16)| (vi_cw_max << 12) | (vi_cw_min << 8) | vi_aifs);
9465
9466
9467 #elif (DM_ODM_SUPPORT_TYPE==ODM_AP)
9468         if ((OPMODE & WIFI_AP_STATE) && priv->pmib->dot11OperationEntry.wifi_specific) {
9469                 if (priv->pshare->iot_mode_VO_exist) {
9470         #ifdef WMM_VIBE_PRI
9471                         if (priv->pshare->iot_mode_BE_exist)
9472                         {
9473                                 vi_cw_max = 5;
9474                                 vi_cw_min = 3;
9475                                 vi_aifs = (sifs_time + ((OPMODE & WIFI_AP_STATE)?1:2) * slot_time);
9476                         }
9477                         else
9478         #endif
9479                         {
9480                         vi_cw_max = 6;
9481                         vi_cw_min = 4;
9482                         vi_aifs = 0x2b;
9483                         }
9484                 }
9485                 else {
9486                         vi_aifs = (sifs_time + ((OPMODE & WIFI_AP_STATE)?1:2) * slot_time);
9487                 }
9488
9489                 ODM_Write4Byte(pDM_Odm, ODM_EDCA_VI_PARAM, ((VI_TXOP*(1-priv->pshare->iot_mode_VO_exist)) << 16)
9490                         | (vi_cw_max << 12) | (vi_cw_min << 8) | vi_aifs);
9491         }
9492 #endif
9493
9494
9495
9496 #if (DM_ODM_SUPPORT_TYPE==ODM_AP)
9497         if (priv->pshare->rf_ft_var.wifi_beq_iot && priv->pshare->iot_mode_VI_exist)
9498                 ODM_Write4Byte(pDM_Odm, ODM_EDCA_BE_PARAM, (10 << 12) | (4 << 8) | 0x4f);
9499         else if(!enable)
9500 #elif(DM_ODM_SUPPORT_TYPE==ODM_ADSL)
9501         if(!enable)                                 //if iot is disable ,maintain original BEQ PARAM
9502 #endif
9503                 ODM_Write4Byte(pDM_Odm, ODM_EDCA_BE_PARAM, (((OPMODE & WIFI_AP_STATE)?6:10) << 12) | (4 << 8)
9504                         | (sifs_time + 3 * slot_time));
9505         else
9506         {
9507                 int txop_enlarge;
9508                 int txop;
9509                 unsigned int cw_max;
9510                 unsigned int txop_close;
9511
9512         #if((DM_ODM_SUPPORT_TYPE==ODM_AP)&&(defined LOW_TP_TXOP))
9513                         cw_max = ((priv->pshare->BE_cwmax_enhance) ? 10 : 6);
9514                         txop_close = ((priv->pshare->rf_ft_var.low_tp_txop && priv->pshare->rf_ft_var.low_tp_txop_close) ? 1 : 0);
9515
9516                         if(priv->pshare->txop_enlarge == 0xe)   //if intel case
9517                                 txop = (txop_close ? 0 : (BE_TXOP*2));
9518                         else                                                        //if other case
9519                                 txop = (txop_close ? 0: (BE_TXOP*priv->pshare->txop_enlarge));
9520         #else
9521                         cw_max=6;
9522                         if((priv->pshare->txop_enlarge==0xe)||(priv->pshare->txop_enlarge==0xd))
9523                                 txop=BE_TXOP*2;
9524                         else
9525                                 txop=BE_TXOP*priv->pshare->txop_enlarge;
9526
9527         #endif
9528
9529                 if (priv->pshare->ht_sta_num
9530         #ifdef WDS
9531                         || ((OPMODE & WIFI_AP_STATE) && (mode & (ODM_WM_N24G|ODM_WM_N5G)) &&
9532                         priv->pmib->dot11WdsInfo.wdsEnabled && priv->pmib->dot11WdsInfo.wdsNum)
9533         #endif
9534                         )
9535                         {
9536
9537                         if (priv->pshare->txop_enlarge == 0xe) {
9538                                 // is intel client, use a different edca value
9539                                 ODM_Write4Byte(pDM_Odm, ODM_EDCA_BE_PARAM, (txop<< 16) | (cw_max<< 12) | (4 << 8) | 0x1f);
9540                                 priv->pshare->txop_enlarge = 2;
9541                         }
9542 #if(DM_ODM_SUPPORT_TYPE==ODM_AP)
9543         #ifndef LOW_TP_TXOP
9544                          else if (priv->pshare->txop_enlarge == 0xd) {
9545                                 // is intel ralink, use a different edca value
9546                                 ODM_Write4Byte(pDM_Odm, ODM_EDCA_BE_PARAM, (txop << 16) | (4 << 12) | (3 << 8) | 0x19);
9547                                 priv->pshare->txop_enlarge = 2;
9548                         }
9549         #endif
9550 #endif
9551                         else
9552                         {
9553                                 if (pDM_Odm->RFType==ODM_2T2R)
9554                                         ODM_Write4Byte(pDM_Odm, ODM_EDCA_BE_PARAM, (txop << 16) |
9555                                                 (cw_max << 12) | (4 << 8) | (sifs_time + 3 * slot_time));
9556                                 else
9557                                 #if(DM_ODM_SUPPORT_TYPE==ODM_AP)&&(defined LOW_TP_TXOP)
9558                                         ODM_Write4Byte(pDM_Odm, ODM_EDCA_BE_PARAM, (txop << 16) |
9559                                                 (((priv->pshare->BE_cwmax_enhance) ? 10 : 5) << 12) | (3 << 8) | (sifs_time + 2 * slot_time));
9560                                 #else
9561                                         ODM_Write4Byte(pDM_Odm, ODM_EDCA_BE_PARAM, (txop << 16) |
9562                                                 (5 << 12) | (3 << 8) | (sifs_time + 2 * slot_time));
9563
9564                                 #endif
9565                         }
9566                 }
9567               else
9568               {
9569  #if((DM_ODM_SUPPORT_TYPE==ODM_AP)&&(defined LOW_TP_TXOP))
9570                          ODM_Write4Byte(pDM_Odm, ODM_EDCA_BE_PARAM, (BE_TXOP << 16) | (cw_max << 12) | (4 << 8) | (sifs_time + 3 * slot_time));
9571  #else
9572                 #if defined(CONFIG_RTL_8196D) || defined(CONFIG_RTL_8196E) || (defined(CONFIG_RTL_8197D) && !defined(CONFIG_PORT0_EXT_GIGA))
9573                         ODM_Write4Byte(pDM_Odm, ODM_EDCA_BE_PARAM,  (BE_TXOP*2 << 16) | (cw_max << 12) | (5 << 8) | (sifs_time + 3 * slot_time));
9574                 #else
9575                         ODM_Write4Byte(pDM_Odm, ODM_EDCA_BE_PARAM,  (BE_TXOP*2 << 16) | (cw_max << 12) | (4 << 8) | (sifs_time + 3 * slot_time));
9576                 #endif
9577
9578  #endif
9579               }
9580
9581         }
9582 }
9583 #endif
9584
9585 VOID
9586 odm_IotEngine(
9587         IN      PDM_ODM_T       pDM_Odm
9588         )
9589 {
9590
9591         struct rtl8192cd_priv *priv=pDM_Odm->priv;
9592         PSTA_INFO_T pstat = NULL;
9593         u4Byte i;
9594
9595 #ifdef WIFI_WMM
9596         unsigned int switch_turbo = 0;
9597 #endif
9598 ////////////////////////////////////////////////////////
9599 //  if EDCA Turbo function is not supported or Manual EDCA Setting
9600 //  then return
9601 ////////////////////////////////////////////////////////
9602         if(!(pDM_Odm->SupportAbility&ODM_MAC_EDCA_TURBO)){
9603                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("ODM_MAC_EDCA_TURBO NOT SUPPORTED\n"));
9604                 return;
9605         }
9606
9607 #if((DM_ODM_SUPPORT_TYPE==ODM_AP)&& defined(RTL_MANUAL_EDCA) && defined(WIFI_WMM))
9608         if(priv->pmib->dot11QosEntry.ManualEDCA){
9609                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("ODM_MAC_EDCA_TURBO OFF: MANUAL SETTING\n"));
9610                 return ;
9611         }
9612 #endif
9613
9614 #if !(DM_ODM_SUPPORT_TYPE &ODM_AP)
9615  //////////////////////////////////////////////////////
9616  //find high TP STA every 2s
9617 //////////////////////////////////////////////////////
9618         if ((GET_ROOT(priv)->up_time % 2) == 0)
9619                 priv->pshare->highTP_found_pstat==NULL;
9620
9621 #if 0
9622         phead = &priv->asoc_list;
9623         plist = phead->next;
9624         while(plist != phead)   {
9625                 pstat = list_entry(plist, struct stat_info, asoc_list);
9626
9627                 if(ODM_ChooseIotMainSTA(pDM_Odm, pstat));              //find the correct station
9628                         break;
9629                 if (plist == plist->next)                                          //the last plist
9630                         break;
9631                 plist = plist->next;
9632         };
9633 #endif
9634
9635         //find highTP STA
9636         for(i=0; i<ODM_ASSOCIATE_ENTRY_NUM; i++) {
9637                 pstat = pDM_Odm->pODM_StaInfo[i];
9638                 if(IS_STA_VALID(pstat) && (ODM_ChooseIotMainSTA(pDM_Odm, pstat)))        //find the correct station
9639                                 break;
9640         }
9641
9642  //////////////////////////////////////////////////////
9643  //if highTP STA is not found, then return
9644  //////////////////////////////////////////////////////
9645         if(priv->pshare->highTP_found_pstat==NULL)      {
9646                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_EDCA_TURBO, ODM_DBG_LOUD, ("ODM_MAC_EDCA_TURBO OFF: NO HT STA FOUND\n"));
9647                 return;
9648         }
9649 #endif
9650
9651         pstat=priv->pshare->highTP_found_pstat;
9652
9653
9654 #ifdef WIFI_WMM
9655         if (QOS_ENABLE) {
9656                 if (!priv->pmib->dot11OperationEntry.wifi_specific
9657                 #if(DM_ODM_SUPPORT_TYPE==ODM_AP)
9658                         ||((OPMODE & WIFI_AP_STATE) && (priv->pmib->dot11OperationEntry.wifi_specific == 2))
9659                 #elif(DM_ODM_SUPPORT_TYPE==ODM_ADSL)
9660                         || (priv->pmib->dot11OperationEntry.wifi_specific == 2)
9661                 #endif
9662                         ) {
9663                         if (priv->pshare->iot_mode_enable &&
9664                                 ((priv->pshare->phw->VO_pkt_count > 50) ||
9665                                  (priv->pshare->phw->VI_pkt_count > 50) ||
9666                                  (priv->pshare->phw->BK_pkt_count > 50))) {
9667                                 priv->pshare->iot_mode_enable = 0;
9668                                 switch_turbo++;
9669                         } else if ((!priv->pshare->iot_mode_enable) &&
9670                                 ((priv->pshare->phw->VO_pkt_count < 50) &&
9671                                  (priv->pshare->phw->VI_pkt_count < 50) &&
9672                                  (priv->pshare->phw->BK_pkt_count < 50))) {
9673                                 priv->pshare->iot_mode_enable++;
9674                                 switch_turbo++;
9675                         }
9676                 }
9677
9678
9679                 #if(DM_ODM_SUPPORT_TYPE==ODM_AP)
9680                 if ((OPMODE & WIFI_AP_STATE) && priv->pmib->dot11OperationEntry.wifi_specific)
9681                 #elif (DM_ODM_SUPPORT_TYPE==ODM_ADSL)
9682                 if (priv->pmib->dot11OperationEntry.wifi_specific)
9683                 #endif
9684                 {
9685                         if (!priv->pshare->iot_mode_VO_exist && (priv->pshare->phw->VO_pkt_count > 50)) {
9686                                 priv->pshare->iot_mode_VO_exist++;
9687                                 switch_turbo++;
9688                         } else if (priv->pshare->iot_mode_VO_exist && (priv->pshare->phw->VO_pkt_count < 50)) {
9689                                 priv->pshare->iot_mode_VO_exist = 0;
9690                                 switch_turbo++;
9691                         }
9692 #if((DM_ODM_SUPPORT_TYPE==ODM_ADSL)||((DM_ODM_SUPPORT_TYPE==ODM_AP)&&(defined WMM_VIBE_PRI)))
9693                         if (priv->pshare->iot_mode_VO_exist) {
9694                                 //printk("[%s %d] BE_pkt_count=%d\n", __FUNCTION__, __LINE__, priv->pshare->phw->BE_pkt_count);
9695                                 if (!priv->pshare->iot_mode_BE_exist && (priv->pshare->phw->BE_pkt_count > 250)) {
9696                                         priv->pshare->iot_mode_BE_exist++;
9697                                         switch_turbo++;
9698                                 } else if (priv->pshare->iot_mode_BE_exist && (priv->pshare->phw->BE_pkt_count < 250)) {
9699                                         priv->pshare->iot_mode_BE_exist = 0;
9700                                         switch_turbo++;
9701                                 }
9702                         }
9703 #endif
9704
9705 #if (DM_ODM_SUPPORT_TYPE==ODM_AP)
9706                         if (priv->pshare->rf_ft_var.wifi_beq_iot)
9707                         {
9708                                 if (!priv->pshare->iot_mode_VI_exist && (priv->pshare->phw->VI_rx_pkt_count > 50)) {
9709                                         priv->pshare->iot_mode_VI_exist++;
9710                                         switch_turbo++;
9711                                 } else if (priv->pshare->iot_mode_VI_exist && (priv->pshare->phw->VI_rx_pkt_count < 50)) {
9712                                         priv->pshare->iot_mode_VI_exist = 0;
9713                                         switch_turbo++;
9714                                 }
9715                         }
9716 #endif
9717
9718                 }
9719                 else if (!pstat || pstat->rssi < priv->pshare->rf_ft_var.txop_enlarge_lower) {
9720                    if (priv->pshare->txop_enlarge) {
9721                            priv->pshare->txop_enlarge = 0;
9722                            if (priv->pshare->iot_mode_enable)
9723                                         switch_turbo++;
9724                                 }
9725                 }
9726
9727 #if(defined(CLIENT_MODE) && (DM_ODM_SUPPORT_TYPE==ODM_AP))
9728         if ((OPMODE & WIFI_STATION_STATE) && (priv->pmib->dot11OperationEntry.wifi_specific == 2))
9729         {
9730             if (priv->pshare->iot_mode_enable &&
9731                 (((priv->pshare->phw->VO_pkt_count > 50) ||
9732                  (priv->pshare->phw->VI_pkt_count > 50) ||
9733                  (priv->pshare->phw->BK_pkt_count > 50)) ||
9734                  (pstat && (!pstat->ADDBA_ready[0]) & (!pstat->ADDBA_ready[3]))))
9735             {
9736                 priv->pshare->iot_mode_enable = 0;
9737                 switch_turbo++;
9738             }
9739             else if ((!priv->pshare->iot_mode_enable) &&
9740                 (((priv->pshare->phw->VO_pkt_count < 50) &&
9741                  (priv->pshare->phw->VI_pkt_count < 50) &&
9742                  (priv->pshare->phw->BK_pkt_count < 50)) &&
9743                  (pstat && (pstat->ADDBA_ready[0] | pstat->ADDBA_ready[3]))))
9744             {
9745                 priv->pshare->iot_mode_enable++;
9746                 switch_turbo++;
9747             }
9748         }
9749 #endif
9750
9751                 priv->pshare->phw->VO_pkt_count = 0;
9752                 priv->pshare->phw->VI_pkt_count = 0;
9753                 priv->pshare->phw->BK_pkt_count = 0;
9754
9755         #if((DM_ODM_SUPPORT_TYPE==ODM_ADSL)||((DM_ODM_SUPPORT_TYPE==ODM_AP)&&(defined WMM_VIBE_PRI)))
9756                 priv->pshare->phw->BE_pkt_count = 0;
9757         #endif
9758
9759         #if(DM_ODM_SUPPORT_TYPE==ODM_AP)
9760                 if (priv->pshare->rf_ft_var.wifi_beq_iot)
9761                         priv->pshare->phw->VI_rx_pkt_count = 0;
9762                 #endif
9763
9764         }
9765 #endif
9766
9767         if ((priv->up_time % 2) == 0) {
9768                 /*
9769                  * decide EDCA content for different chip vendor
9770                  */
9771 #ifdef WIFI_WMM
9772         #if(DM_ODM_SUPPORT_TYPE==ODM_ADSL)
9773                 if (QOS_ENABLE && (!priv->pmib->dot11OperationEntry.wifi_specific || (priv->pmib->dot11OperationEntry.wifi_specific == 2)
9774
9775         #elif(DM_ODM_SUPPORT_TYPE==ODM_AP)
9776                 if (QOS_ENABLE && (!priv->pmib->dot11OperationEntry.wifi_specific ||
9777                         ((OPMODE & WIFI_AP_STATE) && (priv->pmib->dot11OperationEntry.wifi_specific == 2))
9778                 #ifdef CLIENT_MODE
9779             || ((OPMODE & WIFI_STATION_STATE) && (priv->pmib->dot11OperationEntry.wifi_specific == 2))
9780                 #endif
9781         #endif
9782                 ))
9783
9784                 {
9785
9786                         if (pstat && pstat->rssi >= priv->pshare->rf_ft_var.txop_enlarge_upper) {
9787 #ifdef LOW_TP_TXOP
9788 #if (DM_ODM_SUPPORT_TYPE &ODM_AP) && defined(USE_OUT_SRC)
9789                                 if (pstat->IOTPeer==HT_IOT_PEER_INTEL)
9790 #else
9791                                 if (pstat->is_intel_sta)
9792 #endif
9793                                 {
9794                                         if (priv->pshare->txop_enlarge != 0xe)
9795                                         {
9796                                                 priv->pshare->txop_enlarge = 0xe;
9797
9798                                                 if (priv->pshare->iot_mode_enable)
9799                                                         switch_turbo++;
9800                                         }
9801                                 }
9802                                 else if (priv->pshare->txop_enlarge != 2)
9803                                 {
9804                                         priv->pshare->txop_enlarge = 2;
9805                                         if (priv->pshare->iot_mode_enable)
9806                                                 switch_turbo++;
9807                                 }
9808 #else
9809                                 if (priv->pshare->txop_enlarge != 2)
9810                                 {
9811 #if (DM_ODM_SUPPORT_TYPE &ODM_AP) && defined(USE_OUT_SRC)
9812                                         if (pstat->IOTPeer==HT_IOT_PEER_INTEL)
9813 #else
9814                                         if (pstat->is_intel_sta)
9815 #endif
9816                                                 priv->pshare->txop_enlarge = 0xe;
9817 #if (DM_ODM_SUPPORT_TYPE &ODM_AP) && defined(USE_OUT_SRC)
9818                                         else if (pstat->IOTPeer==HT_IOT_PEER_RALINK)
9819 #else
9820                                         else if (pstat->is_ralink_sta)
9821 #endif
9822                                                 priv->pshare->txop_enlarge = 0xd;
9823                                         else
9824                                                 priv->pshare->txop_enlarge = 2;
9825
9826                                         if (priv->pshare->iot_mode_enable)
9827                                                 switch_turbo++;
9828                                 }
9829 #endif
9830 #if 0
9831                                 if (priv->pshare->txop_enlarge != 2)
9832                                 {
9833                                 #if(DM_ODM_SUPPORT_TYPE==ODM_AP)
9834                                         if (pstat->IOTPeer==HT_IOT_PEER_INTEL)
9835                                 #else
9836                                         if (pstat->is_intel_sta)
9837                                 #endif
9838                                                 priv->pshare->txop_enlarge = 0xe;
9839                                 #if(DM_ODM_SUPPORT_TYPE==ODM_AP)
9840                                         else if (pstat->IOTPeer==HT_IOT_PEER_RALINK)
9841                                                 priv->pshare->txop_enlarge = 0xd;
9842                                 #endif
9843                                         else
9844                                                 priv->pshare->txop_enlarge = 2;
9845                                         if (priv->pshare->iot_mode_enable)
9846                                                 switch_turbo++;
9847                                 }
9848 #endif
9849                         }
9850                         else if (!pstat || pstat->rssi < priv->pshare->rf_ft_var.txop_enlarge_lower)
9851                         {
9852                                 if (priv->pshare->txop_enlarge) {
9853                                         priv->pshare->txop_enlarge = 0;
9854                                         if (priv->pshare->iot_mode_enable)
9855                                                 switch_turbo++;
9856                                 }
9857                         }
9858
9859 #if((DM_ODM_SUPPORT_TYPE==ODM_AP)&&( defined LOW_TP_TXOP))
9860                         // for Intel IOT, need to enlarge CW MAX from 6 to 10
9861                         if (pstat && pstat->is_intel_sta && (((pstat->tx_avarage+pstat->rx_avarage)>>10) <
9862                                         priv->pshare->rf_ft_var.cwmax_enhance_thd))
9863                         {
9864                                 if (!priv->pshare->BE_cwmax_enhance && priv->pshare->iot_mode_enable)
9865                                 {
9866                                         priv->pshare->BE_cwmax_enhance = 1;
9867                                         switch_turbo++;
9868                                 }
9869                         } else {
9870                                 if (priv->pshare->BE_cwmax_enhance) {
9871                                         priv->pshare->BE_cwmax_enhance = 0;
9872                                         switch_turbo++;
9873                                 }
9874                         }
9875 #endif
9876                 }
9877 #endif
9878                 priv->pshare->current_tx_bytes = 0;
9879                 priv->pshare->current_rx_bytes = 0;
9880         }
9881
9882 #if((DM_ODM_SUPPORT_TYPE==ODM_AP)&& defined( SW_TX_QUEUE))
9883         if ((priv->assoc_num > 1) && (AMPDU_ENABLE))
9884         {
9885         if (priv->swq_txmac_chg >= priv->pshare->rf_ft_var.swq_en_highthd){
9886                         if ((priv->swq_en == 0)){
9887                                 switch_turbo++;
9888                                 if (priv->pshare->txop_enlarge == 0)
9889                                         priv->pshare->txop_enlarge = 2;
9890                                 priv->swq_en = 1;
9891                                 }
9892                         else
9893                         {
9894                                 if ((switch_turbo > 0) && (priv->pshare->txop_enlarge == 0) && (priv->pshare->iot_mode_enable != 0))
9895                                 {
9896                                         priv->pshare->txop_enlarge = 2;
9897                                         switch_turbo--;
9898                                 }
9899                         }
9900                 }
9901                 else if(priv->swq_txmac_chg <= priv->pshare->rf_ft_var.swq_dis_lowthd){
9902                         priv->swq_en = 0;
9903                 }
9904                 else if ((priv->swq_en == 1) && (switch_turbo > 0) && (priv->pshare->txop_enlarge == 0) && (priv->pshare->iot_mode_enable != 0))        {
9905                         priv->pshare->txop_enlarge = 2;
9906                         switch_turbo--;
9907                 }
9908     }
9909 #if ((DM_ODM_SUPPORT_TYPE==ODM_AP)&&(defined CONFIG_RTL_819XD))
9910     else if( (priv->assoc_num == 1) && (AMPDU_ENABLE)) {
9911         if (pstat) {
9912                         int en_thd = 14417920>>(priv->up_time % 2);
9913             if ((priv->swq_en == 0) && (pstat->current_tx_bytes > en_thd) && (pstat->current_rx_bytes > en_thd) )  { //50Mbps
9914                 priv->swq_en = 1;
9915                                 priv->swqen_keeptime = priv->up_time;
9916             }
9917             else if ((priv->swq_en == 1) && ((pstat->tx_avarage < 4587520) || (pstat->rx_avarage < 4587520))) { //35Mbps
9918                 priv->swq_en = 0;
9919                                 priv->swqen_keeptime = 0;
9920             }
9921         }
9922         else {
9923             priv->swq_en = 0;
9924                         priv->swqen_keeptime = 0;
9925         }
9926     }
9927 #endif
9928 #endif
9929
9930 #ifdef WIFI_WMM
9931 #ifdef LOW_TP_TXOP
9932         if ((!priv->pmib->dot11OperationEntry.wifi_specific || (priv->pmib->dot11OperationEntry.wifi_specific == 2))
9933                 && QOS_ENABLE) {
9934                 if (switch_turbo || priv->pshare->rf_ft_var.low_tp_txop) {
9935                         unsigned int thd_tp;
9936                         unsigned char under_thd;
9937                         unsigned int curr_tp;
9938
9939                         if (priv->pmib->dot11BssType.net_work_type & (ODM_WM_N24G|ODM_WM_N5G| ODM_WM_G))
9940                         {
9941                                 // Determine the upper bound throughput threshold.
9942                                 if (priv->pmib->dot11BssType.net_work_type & (ODM_WM_N24G|ODM_WM_N5G)) {
9943                                         if (priv->assoc_num && priv->assoc_num != priv->pshare->ht_sta_num)
9944                                                 thd_tp = priv->pshare->rf_ft_var.low_tp_txop_thd_g;
9945                                         else
9946                                                 thd_tp = priv->pshare->rf_ft_var.low_tp_txop_thd_n;
9947                                 }
9948                                 else
9949                                         thd_tp = priv->pshare->rf_ft_var.low_tp_txop_thd_g;
9950
9951                                 // Determine to close txop.
9952                                 curr_tp = (unsigned int)(priv->ext_stats.tx_avarage>>17) + (unsigned int)(priv->ext_stats.rx_avarage>>17);
9953                                 if (curr_tp <= thd_tp && curr_tp >= priv->pshare->rf_ft_var.low_tp_txop_thd_low)
9954                                         under_thd = 1;
9955                                 else
9956                                         under_thd = 0;
9957                         }
9958                         else
9959                         {
9960                                 under_thd = 0;
9961                         }
9962
9963                         if (switch_turbo)
9964                         {
9965                                 priv->pshare->rf_ft_var.low_tp_txop_close = under_thd;
9966                                 priv->pshare->rf_ft_var.low_tp_txop_count = 0;
9967                         }
9968                         else if (priv->pshare->iot_mode_enable && (priv->pshare->rf_ft_var.low_tp_txop_close != under_thd)) {
9969                                 priv->pshare->rf_ft_var.low_tp_txop_count++;
9970                                 if (priv->pshare->rf_ft_var.low_tp_txop_close) {
9971                                         priv->pshare->rf_ft_var.low_tp_txop_count = priv->pshare->rf_ft_var.low_tp_txop_delay;
9972                                 }
9973                                 if (priv->pshare->rf_ft_var.low_tp_txop_count ==priv->pshare->rf_ft_var.low_tp_txop_delay)
9974
9975                                 {
9976                                         priv->pshare->rf_ft_var.low_tp_txop_count = 0;
9977                                         priv->pshare->rf_ft_var.low_tp_txop_close = under_thd;
9978                                         switch_turbo++;
9979                                 }
9980                         }
9981                         else
9982                         {
9983                                 priv->pshare->rf_ft_var.low_tp_txop_count = 0;
9984                         }
9985                 }
9986         }
9987 #endif
9988
9989         if (switch_turbo)
9990                 ODM_IotEdcaSwitch( pDM_Odm, priv->pshare->iot_mode_enable );
9991 #endif
9992 }
9993 #endif
9994
9995
9996 #if( DM_ODM_SUPPORT_TYPE == ODM_WIN)
9997 //
9998 // 2011/07/26 MH Add an API for testing IQK fail case.
9999 //
10000 BOOLEAN
10001 ODM_CheckPowerStatus(
10002         IN      PADAPTER                Adapter)
10003 {
10004
10005         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(Adapter);
10006         PDM_ODM_T                       pDM_Odm = &pHalData->DM_OutSrc;
10007         RT_RF_POWER_STATE       rtState;
10008         PMGNT_INFO                      pMgntInfo       = &(Adapter->MgntInfo);
10009
10010         // 2011/07/27 MH We are not testing ready~~!! We may fail to get correct value when init sequence.
10011         if (pMgntInfo->init_adpt_in_progress == TRUE)
10012         {
10013                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ODM_CheckPowerStatus Return TRUE, due to initadapter"));
10014                 return  TRUE;
10015         }
10016
10017         //
10018         //      2011/07/19 MH We can not execute tx pwoer tracking/ LLC calibrate or IQK.
10019         //
10020         Adapter->HalFunc.GetHwRegHandler(Adapter, HW_VAR_RF_STATE, (pu1Byte)(&rtState));
10021         if(Adapter->bDriverStopped || Adapter->bDriverIsGoingToPnpSetPowerSleep || rtState == eRfOff)
10022         {
10023                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("ODM_CheckPowerStatus Return FALSE, due to %d/%d/%d\n",
10024                 Adapter->bDriverStopped, Adapter->bDriverIsGoingToPnpSetPowerSleep, rtState));
10025                 return  FALSE;
10026         }
10027         return  TRUE;
10028 }
10029 #endif
10030
10031 // need to ODM CE Platform
10032 //move to here for ANT detection mechanism using
10033
10034 #if ((DM_ODM_SUPPORT_TYPE == ODM_WIN)||(DM_ODM_SUPPORT_TYPE == ODM_CE))
10035 u4Byte
10036 GetPSDData(
10037         IN PDM_ODM_T    pDM_Odm,
10038         unsigned int    point,
10039         u1Byte initial_gain_psd)
10040 {
10041         //unsigned int  val, rfval;
10042         //int   psd_report;
10043         u4Byte  psd_report;
10044
10045         //HAL_DATA_TYPE         *pHalData = GET_HAL_DATA(Adapter);
10046         //Debug Message
10047         //val = PHY_QueryBBReg(Adapter,0x908, bMaskDWord);
10048         //DbgPrint("Reg908 = 0x%x\n",val);
10049         //val = PHY_QueryBBReg(Adapter,0xDF4, bMaskDWord);
10050         //rfval = PHY_QueryRFReg(Adapter, ODM_RF_PATH_A, 0x00, bRFRegOffsetMask);
10051         //DbgPrint("RegDF4 = 0x%x, RFReg00 = 0x%x\n",val, rfval);
10052         //DbgPrint("PHYTXON = %x, OFDMCCA_PP = %x, CCKCCA_PP = %x, RFReg00 = %x\n",
10053                 //(val&BIT25)>>25, (val&BIT14)>>14, (val&BIT15)>>15, rfval);
10054
10055         //Set DCO frequency index, offset=(40MHz/SamplePts)*point
10056         ODM_SetBBReg(pDM_Odm, 0x808, 0x3FF, point);
10057
10058         //Start PSD calculation, Reg808[22]=0->1
10059         ODM_SetBBReg(pDM_Odm, 0x808, BIT22, 1);
10060         //Need to wait for HW PSD report
10061         ODM_StallExecution(1000);
10062         ODM_SetBBReg(pDM_Odm, 0x808, BIT22, 0);
10063         //Read PSD report, Reg8B4[15:0]
10064         psd_report = ODM_GetBBReg(pDM_Odm,0x8B4, bMaskDWord) & 0x0000FFFF;
10065
10066 #if 1//(DEV_BUS_TYPE == RT_PCI_INTERFACE) && ( (RT_PLATFORM == PLATFORM_LINUX) || (RT_PLATFORM == PLATFORM_MACOSX))
10067         psd_report = (u4Byte) (ConvertTo_dB(psd_report))+(u4Byte)(initial_gain_psd-0x1c);
10068 #else
10069         psd_report = (int) (20*log10((double)psd_report))+(int)(initial_gain_psd-0x1c);
10070 #endif
10071
10072         return psd_report;
10073
10074 }
10075
10076 u4Byte
10077 ConvertTo_dB(
10078         u4Byte  Value)
10079 {
10080         u1Byte i;
10081         u1Byte j;
10082         u4Byte dB;
10083
10084         Value = Value & 0xFFFF;
10085
10086         for (i=0;i<8;i++)
10087         {
10088                 if (Value <= dB_Invert_Table[i][11])
10089                 {
10090                         break;
10091                 }
10092         }
10093
10094         if (i >= 8)
10095         {
10096                 return (96);    // maximum 96 dB
10097         }
10098
10099         for (j=0;j<12;j++)
10100         {
10101                 if (Value <= dB_Invert_Table[i][j])
10102                 {
10103                         break;
10104                 }
10105         }
10106
10107         dB = i*12 + j + 1;
10108
10109         return (dB);
10110 }
10111
10112 #endif
10113
10114 //
10115 // LukeLee:
10116 // PSD function will be moved to FW in future IC, but now is only implemented in MP platform
10117 // So PSD function will not be incorporated to common ODM
10118 //
10119 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
10120
10121 #define AFH_PSD         1       //0:normal PSD scan, 1: only do 20 pts PSD
10122 #define MODE_40M                0       //0:20M, 1:40M
10123 #define PSD_TH2         3
10124 #define PSD_CHMIN               20   // Minimum channel number for BT AFH
10125 #define SIR_STEP_SIZE   3
10126 #define   Smooth_Size_1         5
10127 #define Smooth_TH_1     3
10128 #define   Smooth_Size_2         10
10129 #define Smooth_TH_2     4
10130 #define   Smooth_Size_3         20
10131 #define Smooth_TH_3     4
10132 #define   Smooth_Step_Size 5
10133 #define Adaptive_SIR    1
10134 //#if(RTL8723_FPGA_VERIFICATION == 1)
10135 //#define       PSD_RESCAN              1
10136 //#else
10137 //#define       PSD_RESCAN              4
10138 //#endif
10139 #define SCAN_INTERVAL   1500 //ms
10140 #define SYN_Length              5    // for 92D
10141
10142 #define LNA_Low_Gain_1                      0x64
10143 #define LNA_Low_Gain_2                      0x5A
10144 #define LNA_Low_Gain_3                      0x58
10145
10146 #define pw_th_10dB                                      0x0
10147 #define pw_th_16dB                                      0x3
10148
10149 #define FA_RXHP_TH1                           5000
10150 #define FA_RXHP_TH2                           1500
10151 #define FA_RXHP_TH3                             800
10152 #define FA_RXHP_TH4                             600
10153 #define FA_RXHP_TH5                             500
10154
10155 #define Idle_Mode                                       0
10156 #define High_TP_Mode                            1
10157 #define Low_TP_Mode                             2
10158
10159
10160 VOID
10161 odm_PSDMonitorInit(
10162         IN PDM_ODM_T    pDM_Odm)
10163 {
10164 #if (DEV_BUS_TYPE == RT_PCI_INTERFACE)|(DEV_BUS_TYPE == RT_USB_INTERFACE)
10165         //HAL_DATA_TYPE         *pHalData = GET_HAL_DATA(Adapter);
10166         //PSD Monitor Setting
10167         //Which path in ADC/DAC is turnned on for PSD: both I/Q
10168         ODM_SetBBReg(pDM_Odm, ODM_PSDREG, BIT10|BIT11, 0x3);
10169         //Ageraged number: 8
10170         ODM_SetBBReg(pDM_Odm, ODM_PSDREG, BIT12|BIT13, 0x1);
10171         pDM_Odm->bPSDinProcess = FALSE;
10172         pDM_Odm->bUserAssignLevel = FALSE;
10173         pDM_Odm->bPSDactive = FALSE;
10174         //pDM_Odm->bDMInitialGainEnable=TRUE;           //change the initialization to DIGinit
10175         //Set Debug Port
10176         //PHY_SetBBReg(Adapter, 0x908, bMaskDWord, 0x803);
10177         //PHY_SetBBReg(Adapter, 0xB34, bMaskByte0, 0x00); // pause PSD
10178         //PHY_SetBBReg(Adapter, 0xB38, bMaskByte0, 10); //rescan
10179         //PHY_SetBBReg(Adapter, 0xB38, bMaskByte2|bMaskByte3, 100); //interval
10180
10181         //PlatformSetTimer( Adapter, &pHalData->PSDTriggerTimer, 0); //ms
10182 #endif
10183 }
10184
10185 VOID
10186 PatchDCTone(
10187         IN      PDM_ODM_T       pDM_Odm,
10188         pu4Byte         PSD_report,
10189         u1Byte          initial_gain_psd
10190 )
10191 {
10192         //HAL_DATA_TYPE         *pHalData = GET_HAL_DATA(Adapter);
10193         //PADAPTER      pAdapter;
10194
10195         u4Byte  psd_report;
10196
10197         //2 Switch to CH11 to patch CH9 and CH13 DC tone
10198         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, 0x3FF, 11);
10199
10200         if(pDM_Odm->SupportICType== ODM_RTL8192D)
10201         {
10202                 if((*(pDM_Odm->pMacPhyMode) == ODM_SMSP)||(*(pDM_Odm->pMacPhyMode) == ODM_DMSP))
10203                 {
10204                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_CHNLBW, 0x3FF, 11);
10205                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x25, 0xfffff, 0x643BC);
10206                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x26, 0xfffff, 0xFC038);
10207                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x27, 0xfffff, 0x77C1A);
10208                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x2B, 0xfffff, 0x41289);
10209                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x2C, 0xfffff, 0x01840);
10210                 }
10211                 else
10212                 {
10213                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x25, 0xfffff, 0x643BC);
10214                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x26, 0xfffff, 0xFC038);
10215                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x27, 0xfffff, 0x77C1A);
10216                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x2B, 0xfffff, 0x41289);
10217                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x2C, 0xfffff, 0x01840);
10218                 }
10219         }
10220
10221         //Ch9 DC tone patch
10222         psd_report = GetPSDData(pDM_Odm, 96, initial_gain_psd);
10223         PSD_report[50] = psd_report;
10224         //Ch13 DC tone patch
10225         psd_report = GetPSDData(pDM_Odm, 32, initial_gain_psd);
10226         PSD_report[70] = psd_report;
10227
10228         //2 Switch to CH3 to patch CH1 and CH5 DC tone
10229         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, 0x3FF, 3);
10230
10231
10232         if(pDM_Odm->SupportICType==ODM_RTL8192D)
10233         {
10234                 if((*(pDM_Odm->pMacPhyMode) == ODM_SMSP)||(*(pDM_Odm->pMacPhyMode) == ODM_DMSP))
10235                 {
10236                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_CHNLBW, 0x3FF, 3);
10237                         //PHY_SetRFReg(Adapter, ODM_RF_PATH_B, 0x25, 0xfffff, 0x643BC);
10238                         //PHY_SetRFReg(Adapter, ODM_RF_PATH_B, 0x26, 0xfffff, 0xFC038);
10239                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x27, 0xfffff, 0x07C1A);
10240                         //PHY_SetRFReg(Adapter, ODM_RF_PATH_B, 0x2B, 0xfffff, 0x61289);
10241                         //PHY_SetRFReg(Adapter, ODM_RF_PATH_B, 0x2C, 0xfffff, 0x01C41);
10242                 }
10243                 else
10244                 {
10245                         //PHY_SetRFReg(Adapter, ODM_RF_PATH_A, 0x25, 0xfffff, 0x643BC);
10246                         //PHY_SetRFReg(Adapter, ODM_RF_PATH_A, 0x26, 0xfffff, 0xFC038);
10247                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x27, 0xfffff, 0x07C1A);
10248                         //PHY_SetRFReg(Adapter, ODM_RF_PATH_A, 0x2B, 0xfffff, 0x61289);
10249                         //PHY_SetRFReg(Adapter, ODM_RF_PATH_A, 0x2C, 0xfffff, 0x01C41);
10250                 }
10251         }
10252
10253         //Ch1 DC tone patch
10254         psd_report = GetPSDData(pDM_Odm, 96, initial_gain_psd);
10255         PSD_report[10] = psd_report;
10256         //Ch5 DC tone patch
10257         psd_report = GetPSDData(pDM_Odm, 32, initial_gain_psd);
10258         PSD_report[30] = psd_report;
10259
10260 }
10261
10262
10263 VOID
10264 GoodChannelDecision(
10265         PDM_ODM_T       pDM_Odm,
10266         pu4Byte         PSD_report,
10267         pu1Byte         PSD_bitmap,
10268         u1Byte          RSSI_BT,
10269         pu1Byte         PSD_bitmap_memory)
10270 {
10271         pRXHP_T                 pRX_HP_Table = &pDM_Odm->DM_RXHP_Table;
10272         //s4Byte        TH1 =  SSBT-0x15;    // modify TH by Neil Chen
10273         s4Byte  TH1= RSSI_BT+0x14;
10274         s4Byte  TH2 = RSSI_BT+85;
10275         //u2Byte    TH3;
10276 //      s4Byte  RegB34;
10277         u1Byte  bitmap, Smooth_size[3], Smooth_TH[3];
10278         //u1Byte        psd_bit;
10279         u4Byte  i,n,j, byte_idx, bit_idx, good_cnt, good_cnt_smoothing, Smooth_Interval[3];
10280         int             start_byte_idx,start_bit_idx,cur_byte_idx, cur_bit_idx,NOW_byte_idx ;
10281
10282 //      RegB34 = PHY_QueryBBReg(Adapter,0xB34, bMaskDWord)&0xFF;
10283
10284         if((pDM_Odm->SupportICType == ODM_RTL8192C)||(pDM_Odm->SupportICType == ODM_RTL8192D))
10285        {
10286             TH1 = RSSI_BT + 0x14;
10287         }
10288
10289         Smooth_size[0]=Smooth_Size_1;
10290         Smooth_size[1]=Smooth_Size_2;
10291         Smooth_size[2]=Smooth_Size_3;
10292         Smooth_TH[0]=Smooth_TH_1;
10293         Smooth_TH[1]=Smooth_TH_2;
10294         Smooth_TH[2]=Smooth_TH_3;
10295         Smooth_Interval[0]=16;
10296         Smooth_Interval[1]=15;
10297         Smooth_Interval[2]=13;
10298         good_cnt = 0;
10299         if(pDM_Odm->SupportICType==ODM_RTL8723A)
10300         {
10301                 //2 Threshold
10302
10303                 if(RSSI_BT >=41)
10304                         TH1 = 113;
10305                 else if(RSSI_BT >=38)   // >= -15dBm
10306                         TH1 = 105;                              //0x69
10307                 else if((RSSI_BT >=33)&(RSSI_BT <38))
10308                         TH1 = 99+(RSSI_BT-33);         //0x63
10309                 else if((RSSI_BT >=26)&(RSSI_BT<33))
10310                         TH1 = 99-(33-RSSI_BT)+2;     //0x5e
10311                 else if((RSSI_BT >=24)&(RSSI_BT<26))
10312                         TH1 = 88-((RSSI_BT-24)*3);   //0x58
10313                 else if((RSSI_BT >=18)&(RSSI_BT<24))
10314                         TH1 = 77+((RSSI_BT-18)*2);
10315                 else if((RSSI_BT >=14)&(RSSI_BT<18))
10316                         TH1 = 63+((RSSI_BT-14)*2);
10317                 else if((RSSI_BT >=8)&(RSSI_BT<14))
10318                         TH1 = 58+((RSSI_BT-8)*2);
10319                 else if((RSSI_BT >=3)&(RSSI_BT<8))
10320                         TH1 = 52+(RSSI_BT-3);
10321                 else
10322                         TH1 = 51;
10323         }
10324
10325         for (i = 0; i< 10; i++)
10326                 PSD_bitmap[i] = 0;
10327
10328
10329          // Add By Gary
10330        for (i=0; i<80; i++)
10331                 pRX_HP_Table->PSD_bitmap_RXHP[i] = 0;
10332         // End
10333
10334
10335
10336         if(pDM_Odm->SupportICType==ODM_RTL8723A)
10337         {
10338                 TH1 =TH1-SIR_STEP_SIZE;
10339         }
10340         while (good_cnt < PSD_CHMIN)
10341         {
10342                 good_cnt = 0;
10343                 if(pDM_Odm->SupportICType==ODM_RTL8723A)
10344                 {
10345                 if(TH1 ==TH2)
10346                         break;
10347                 if((TH1+SIR_STEP_SIZE) < TH2)
10348                         TH1 += SIR_STEP_SIZE;
10349                 else
10350                         TH1 = TH2;
10351                 }
10352                 else
10353                 {
10354                         if(TH1==(RSSI_BT+0x1E))
10355                              break;
10356                         if((TH1+2) < (RSSI_BT+0x1E))
10357                                 TH1+=3;
10358                         else
10359                                 TH1 = RSSI_BT+0x1E;
10360
10361                 }
10362                 ODM_RT_TRACE(pDM_Odm,COMP_PSD,DBG_LOUD,("PSD: decision threshold is: %d", TH1));
10363
10364                 for (i = 0; i< 80; i++)
10365                 {
10366                         if((s4Byte)(PSD_report[i]) < TH1)
10367                         {
10368                                 byte_idx = i / 8;
10369                                 bit_idx = i -8*byte_idx;
10370                                 bitmap = PSD_bitmap[byte_idx];
10371                                 PSD_bitmap[byte_idx] = bitmap | (u1Byte) (1 << bit_idx);
10372                         }
10373                 }
10374
10375 #if DBG
10376                 ODM_RT_TRACE(pDM_Odm,COMP_PSD, DBG_LOUD,("PSD: before smoothing\n"));
10377                 for(n=0;n<10;n++)
10378                 {
10379                         //DbgPrint("PSD_bitmap[%u]=%x\n", n, PSD_bitmap[n]);
10380                         for (i = 0; i<8; i++)
10381                                 ODM_RT_TRACE(pDM_Odm,COMP_PSD, DBG_LOUD,("PSD_bitmap[%u] =   %d\n", 2402+n*8+i, (PSD_bitmap[n]&BIT(i))>>i));
10382                 }
10383 #endif
10384
10385                 //1 Start of smoothing function
10386
10387                 for (j=0;j<3;j++)
10388                 {
10389                         start_byte_idx=0;
10390                         start_bit_idx=0;
10391                         for(n=0; n<Smooth_Interval[j]; n++)
10392                         {
10393                                 good_cnt_smoothing = 0;
10394                                 cur_bit_idx = start_bit_idx;
10395                                 cur_byte_idx = start_byte_idx;
10396                                 for ( i=0; i < Smooth_size[j]; i++)
10397                                 {
10398                                         NOW_byte_idx = cur_byte_idx + (i+cur_bit_idx)/8;
10399                                         if ( (PSD_bitmap[NOW_byte_idx]& BIT( (cur_bit_idx + i)%8)) != 0)
10400                                                 good_cnt_smoothing++;
10401
10402                                 }
10403
10404                                 if( good_cnt_smoothing < Smooth_TH[j] )
10405                                 {
10406                                         cur_bit_idx = start_bit_idx;
10407                                         cur_byte_idx = start_byte_idx;
10408                                         for ( i=0; i< Smooth_size[j] ; i++)
10409                                         {
10410                                                 NOW_byte_idx = cur_byte_idx + (i+cur_bit_idx)/8;
10411                                                 PSD_bitmap[NOW_byte_idx] = PSD_bitmap[NOW_byte_idx] & (~BIT( (cur_bit_idx + i)%8));
10412                                         }
10413                                 }
10414                                 start_bit_idx =  start_bit_idx + Smooth_Step_Size;
10415                                 while ( (start_bit_idx)  > 7 )
10416                                 {
10417                                         start_byte_idx= start_byte_idx+start_bit_idx/8;
10418                                         start_bit_idx = start_bit_idx%8;
10419                                 }
10420                         }
10421
10422                         ODM_RT_TRACE(   pDM_Odm,COMP_PSD, DBG_LOUD,("PSD: after %u smoothing", j+1));
10423                         for(n=0;n<10;n++)
10424                         {
10425                                 for (i = 0; i<8; i++)
10426                                 {
10427                                         ODM_RT_TRACE(pDM_Odm,COMP_PSD, DBG_LOUD,("PSD_bitmap[%u] =   %d\n", 2402+n*8+i, (PSD_bitmap[n]&BIT(i))>>i));
10428
10429                                         if ( ((PSD_bitmap[n]&BIT(i))>>i) ==1)  //----- Add By Gary
10430                                         {
10431                                            pRX_HP_Table->PSD_bitmap_RXHP[8*n+i] = 1;
10432                                         }                                                  // ------end by Gary
10433                                 }
10434                         }
10435
10436                 }
10437
10438
10439                 good_cnt = 0;
10440                 for ( i = 0; i < 10; i++)
10441                 {
10442                         for (n = 0; n < 8; n++)
10443                                 if((PSD_bitmap[i]& BIT(n)) != 0)
10444                                         good_cnt++;
10445                 }
10446                 ODM_RT_TRACE(pDM_Odm,COMP_PSD, DBG_LOUD,("PSD: good channel cnt = %u",good_cnt));
10447         }
10448
10449         //RT_TRACE(COMP_PSD, DBG_LOUD,("PSD: SSBT=%d, TH2=%d, TH1=%d",SSBT,TH2,TH1));
10450         for (i = 0; i <10; i++)
10451                 ODM_RT_TRACE(pDM_Odm,COMP_PSD, DBG_LOUD,("PSD: PSD_bitmap[%u]=%x",i,PSD_bitmap[i]));
10452 /*
10453         //Update bitmap memory
10454         for(i = 0; i < 80; i++)
10455         {
10456                 byte_idx = i / 8;
10457                 bit_idx = i -8*byte_idx;
10458                 psd_bit = (PSD_bitmap[byte_idx] & BIT(bit_idx)) >> bit_idx;
10459                 bitmap = PSD_bitmap_memory[i];
10460                 PSD_bitmap_memory[i] = (bitmap << 1) |psd_bit;
10461         }
10462 */
10463 }
10464
10465
10466
10467 VOID
10468 odm_PSD_Monitor(
10469         PDM_ODM_T       pDM_Odm
10470 )
10471 {
10472         //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
10473         //PDM_ODM_T             pDM_Odm = &pHalData->DM_OutSrc;
10474
10475         unsigned int            pts, start_point, stop_point;
10476         u1Byte                  initial_gain ;
10477         static u1Byte           PSD_bitmap_memory[80], init_memory = 0;
10478         static u1Byte           psd_cnt=0;
10479         static u4Byte           PSD_report[80], PSD_report_tmp;
10480         static u8Byte           lastTxOkCnt=0, lastRxOkCnt=0;
10481         u1Byte                  H2C_PSD_DATA[5]={0,0,0,0,0};
10482         static u1Byte           H2C_PSD_DATA_last[5] ={0,0,0,0,0};
10483         u1Byte                  idx[20]={96,99,102,106,109,112,115,118,122,125,
10484                                         0,3,6,10,13,16,19,22,26,29};
10485         u1Byte                  n, i, channel, BBReset,tone_idx;
10486         u1Byte                  PSD_bitmap[10], SSBT=0,initial_gain_psd=0, RSSI_BT=0, initialGainUpper;
10487         s4Byte                          PSD_skip_start, PSD_skip_stop;
10488         u4Byte                  CurrentChannel, RXIQI, RxIdleLowPwr, wlan_channel;
10489         u4Byte                  ReScan, Interval, Is40MHz;
10490         u8Byte                  curTxOkCnt, curRxOkCnt;
10491         int                             cur_byte_idx, cur_bit_idx;
10492         PADAPTER                Adapter = pDM_Odm->Adapter;
10493         PMGNT_INFO              pMgntInfo = &Adapter->MgntInfo;
10494
10495         if( (*(pDM_Odm->pbScanInProcess)) ||
10496                 pDM_Odm->bLinkInProcess)
10497         {
10498                 if((pDM_Odm->SupportICType==ODM_RTL8723A)&(pDM_Odm->SupportInterface==ODM_ITRF_PCIE))
10499                 {
10500                         ODM_SetTimer( pDM_Odm, &pDM_Odm->PSDTimer, 1500); //ms
10501                         //psd_cnt=0;
10502                 }
10503                 return;
10504         }
10505
10506         if(pDM_Odm->bBtHsOperation)
10507         {
10508                 ReScan = 1;
10509                 Interval = SCAN_INTERVAL;
10510         }
10511         else
10512         {
10513         ReScan = PSD_RESCAN;
10514         Interval = SCAN_INTERVAL;
10515         }
10516
10517         //1 Initialization
10518         if(init_memory == 0)
10519         {
10520                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("Init memory\n"));
10521                 for(i = 0; i < 80; i++)
10522                         PSD_bitmap_memory[i] = 0xFF; // channel is always good
10523                 init_memory = 1;
10524         }
10525         if(psd_cnt == 0)
10526         {
10527                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("Enter dm_PSD_Monitor\n"));
10528                 for(i = 0; i < 80; i++)
10529                         PSD_report[i] = 0;
10530         }
10531
10532         //1 Backup Current Settings
10533         CurrentChannel = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask);
10534 /*
10535         if(pDM_Odm->SupportICType==ODM_RTL8192D)
10536         {
10537                 //2 Record Current synthesizer parameters based on current channel
10538                 if((*pDM_Odm->MacPhyMode92D == SINGLEMAC_SINGLEPHY)||(*pDM_Odm->MacPhyMode92D == DUALMAC_SINGLEPHY))
10539                 {
10540                         SYN_RF25 = ODM_GetRFReg(Adapter, ODM_RF_PATH_B, 0x25, bMaskDWord);
10541                         SYN_RF26 = ODM_GetRFReg(Adapter, ODM_RF_PATH_B, 0x26, bMaskDWord);
10542                         SYN_RF27 = ODM_GetRFReg(Adapter, ODM_RF_PATH_B, 0x27, bMaskDWord);
10543                         SYN_RF2B = ODM_GetRFReg(Adapter, ODM_RF_PATH_B, 0x2B, bMaskDWord);
10544                         SYN_RF2C = ODM_GetRFReg(Adapter, ODM_RF_PATH_B, 0x2C, bMaskDWord);
10545         }
10546                 else     // DualMAC_DualPHY 2G
10547                 {
10548                         SYN_RF25 = ODM_GetRFReg(Adapter, ODM_RF_PATH_A, 0x25, bMaskDWord);
10549                         SYN_RF26 = ODM_GetRFReg(Adapter, ODM_RF_PATH_A, 0x26, bMaskDWord);
10550                         SYN_RF27 = ODM_GetRFReg(Adapter, ODM_RF_PATH_A, 0x27, bMaskDWord);
10551                         SYN_RF2B = ODM_GetRFReg(Adapter, ODM_RF_PATH_A, 0x2B, bMaskDWord);
10552                         SYN_RF2C = ODM_GetRFReg(Adapter, ODM_RF_PATH_A, 0x2C, bMaskDWord);
10553                 }
10554         }
10555 */
10556         //RXIQI = PHY_QueryBBReg(Adapter, 0xC14, bMaskDWord);
10557         RXIQI = ODM_GetBBReg(pDM_Odm, 0xC14, bMaskDWord);
10558
10559         //RxIdleLowPwr = (PHY_QueryBBReg(Adapter, 0x818, bMaskDWord)&BIT28)>>28;
10560         RxIdleLowPwr = (ODM_GetBBReg(pDM_Odm, 0x818, bMaskDWord)&BIT28)>>28;
10561
10562         //2???
10563         if(CHNL_RUN_ABOVE_40MHZ(pMgntInfo))
10564                 Is40MHz = TRUE;
10565         else
10566                 Is40MHz = FALSE;
10567
10568         ODM_RT_TRACE(pDM_Odm,   ODM_COMP_PSD, DBG_LOUD,("PSD Scan Start\n"));
10569         //1 Turn off CCK
10570         //PHY_SetBBReg(Adapter, rFPGA0_RFMOD, BIT24, 0);
10571         ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 0);
10572         //1 Turn off TX
10573         //Pause TX Queue
10574         //PlatformEFIOWrite1Byte(Adapter, REG_TXPAUSE, 0xFF);
10575         ODM_Write1Byte(pDM_Odm,REG_TXPAUSE, 0xFF);
10576
10577         //Force RX to stop TX immediately
10578         //PHY_SetRFReg(Adapter, ODM_RF_PATH_A, RF_AC, bRFRegOffsetMask, 0x32E13);
10579
10580         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bRFRegOffsetMask, 0x32E13);
10581         //1 Turn off RX
10582         //Rx AGC off  RegC70[0]=0, RegC7C[20]=0
10583         //PHY_SetBBReg(Adapter, 0xC70, BIT0, 0);
10584         //PHY_SetBBReg(Adapter, 0xC7C, BIT20, 0);
10585
10586         ODM_SetBBReg(pDM_Odm, 0xC70, BIT0, 0);
10587         ODM_SetBBReg(pDM_Odm, 0xC7C, BIT20, 0);
10588
10589
10590         //Turn off CCA
10591         //PHY_SetBBReg(Adapter, 0xC14, bMaskDWord, 0x0);
10592         ODM_SetBBReg(pDM_Odm, 0xC14, bMaskDWord, 0x0);
10593
10594         //BB Reset
10595         //BBReset = PlatformEFIORead1Byte(Adapter, 0x02);
10596         BBReset = ODM_Read1Byte(pDM_Odm, 0x02);
10597
10598         //PlatformEFIOWrite1Byte(Adapter, 0x02, BBReset&(~BIT0));
10599         //PlatformEFIOWrite1Byte(Adapter, 0x02, BBReset|BIT0);
10600         ODM_SetBBReg(pDM_Odm, 0x87C, BIT31, 1); //clock gated to prevent from AGC table mess
10601         ODM_Write1Byte(pDM_Odm,  0x02, BBReset&(~BIT0));
10602         ODM_Write1Byte(pDM_Odm,  0x02, BBReset|BIT0);
10603         ODM_SetBBReg(pDM_Odm, 0x87C, BIT31, 0);
10604
10605         //1 Leave RX idle low power
10606         //PHY_SetBBReg(Adapter, 0x818, BIT28, 0x0);
10607
10608         ODM_SetBBReg(pDM_Odm, 0x818, BIT28, 0x0);
10609         //1 Fix initial gain
10610         //if (IS_HARDWARE_TYPE_8723AE(Adapter))
10611         //RSSI_BT = pHalData->RSSI_BT;
10612        //else if((IS_HARDWARE_TYPE_8192C(Adapter))||(IS_HARDWARE_TYPE_8192D(Adapter)))      // Add by Gary
10613        //    RSSI_BT = RSSI_BT_new;
10614
10615         if((pDM_Odm->SupportICType==ODM_RTL8723A)&(pDM_Odm->SupportInterface==ODM_ITRF_PCIE))
10616         RSSI_BT=pDM_Odm->RSSI_BT;               //need to check C2H to pDM_Odm RSSI BT
10617
10618         if(RSSI_BT>=47)
10619                 RSSI_BT=47;
10620
10621         ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("PSD: RSSI_BT= %d\n", RSSI_BT));
10622
10623         if(pDM_Odm->SupportICType==ODM_RTL8723A)
10624         {
10625                //Neil add--2011--10--12
10626                 //2 Initial Gain index
10627                 if(RSSI_BT >=35)   // >= -15dBm
10628                         initial_gain_psd = RSSI_BT*2;
10629                 else if((RSSI_BT >=33)&(RSSI_BT<35))
10630                         initial_gain_psd = RSSI_BT*2+6;
10631                 else if((RSSI_BT >=24)&(RSSI_BT<33))
10632                         initial_gain_psd = 70-(33-RSSI_BT);
10633                 else if((RSSI_BT >=19)&(RSSI_BT<24))
10634                         initial_gain_psd = 64-((24-RSSI_BT)*4);
10635                 else if((RSSI_BT >=14)&(RSSI_BT<19))
10636                         initial_gain_psd = 44-((18-RSSI_BT)*2);
10637                 else if((RSSI_BT >=8)&(RSSI_BT<14))
10638                         initial_gain_psd = 35-(14-RSSI_BT);
10639                 else
10640                         initial_gain_psd = 0x1B;
10641         }
10642         else
10643         {
10644
10645                 //need to do
10646                 initial_gain_psd = pDM_Odm->RSSI_Min;    // PSD report based on RSSI
10647                 //}
10648         }
10649         //if(RSSI_BT<0x17)
10650         //      RSSI_BT +=3;
10651         //DbgPrint("PSD: RSSI_BT= %d\n", RSSI_BT);
10652         ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("PSD: RSSI_BT= %d\n", RSSI_BT));
10653
10654         //initialGainUpper = 0x5E;  //Modify by neil chen
10655
10656         if(pDM_Odm->bUserAssignLevel)
10657         {
10658                 pDM_Odm->bUserAssignLevel = FALSE;
10659                 initialGainUpper = 0x7f;
10660         }
10661         else
10662         {
10663                 initialGainUpper = 0x5E;
10664         }
10665
10666         /*
10667         if (initial_gain_psd < 0x1a)
10668                 initial_gain_psd = 0x1a;
10669         if (initial_gain_psd > initialGainUpper)
10670                 initial_gain_psd = initialGainUpper;
10671         */
10672
10673         //if(pDM_Odm->SupportICType==ODM_RTL8723A)
10674         SSBT = RSSI_BT  * 2 +0x3E;
10675
10676
10677         //if(IS_HARDWARE_TYPE_8723AE(Adapter))
10678         //      SSBT = RSSI_BT  * 2 +0x3E;
10679         //else if((IS_HARDWARE_TYPE_8192C(Adapter))||(IS_HARDWARE_TYPE_8192D(Adapter)))   // Add by Gary
10680         //{
10681         //      RSSI_BT = initial_gain_psd;
10682         //      SSBT = RSSI_BT;
10683         //}
10684         ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("PSD: SSBT= %d\n", SSBT));
10685         ODM_RT_TRACE(   pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("PSD: initial gain= 0x%x\n", initial_gain_psd));
10686         //DbgPrint("PSD: SSBT= %d", SSBT);
10687         //need to do
10688         //pMgntInfo->bDMInitialGainEnable = FALSE;
10689         pDM_Odm->bDMInitialGainEnable = FALSE;
10690         initial_gain =(u1Byte) (ODM_GetBBReg(pDM_Odm, 0xc50, bMaskDWord) & 0x7F);
10691
10692         // make sure the initial gain is under the correct range.
10693         //initial_gain_psd &= 0x7f;
10694         ODM_Write_DIG(pDM_Odm, initial_gain_psd);
10695         //1 Turn off 3-wire
10696         ODM_SetBBReg(pDM_Odm, 0x88c, BIT20|BIT21|BIT22|BIT23, 0xF);
10697
10698         //pts value = 128, 256, 512, 1024
10699         pts = 128;
10700
10701         if(pts == 128)
10702         {
10703                 ODM_SetBBReg(pDM_Odm, 0x808, BIT14|BIT15, 0x0);
10704                 start_point = 64;
10705                 stop_point = 192;
10706         }
10707         else if(pts == 256)
10708         {
10709                 ODM_SetBBReg(pDM_Odm, 0x808, BIT14|BIT15, 0x1);
10710                 start_point = 128;
10711                 stop_point = 384;
10712         }
10713         else if(pts == 512)
10714         {
10715                 ODM_SetBBReg(pDM_Odm, 0x808, BIT14|BIT15, 0x2);
10716                 start_point = 256;
10717                 stop_point = 768;
10718         }
10719         else
10720         {
10721                 ODM_SetBBReg(pDM_Odm, 0x808, BIT14|BIT15, 0x3);
10722                 start_point = 512;
10723                 stop_point = 1536;
10724         }
10725
10726
10727 //3 Skip WLAN channels if WLAN busy
10728
10729         curTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast) - lastTxOkCnt;
10730         curRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast) - lastRxOkCnt;
10731         lastTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast);
10732         lastRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast);
10733
10734         PSD_skip_start=80;
10735         PSD_skip_stop = 0;
10736         wlan_channel = CurrentChannel & 0x0f;
10737
10738         ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD,DBG_LOUD,("PSD: current channel: %x, BW:%d \n", wlan_channel, Is40MHz));
10739         if(pDM_Odm->SupportICType==ODM_RTL8723A)
10740         {
10741                 if(pDM_Odm->bBtHsOperation)
10742                 {
10743                         if(pDM_Odm->bLinked)
10744                         {
10745                                 if(Is40MHz)
10746                                 {
10747                                         PSD_skip_start = ((wlan_channel-1)*5 -Is40MHz*10)-2;  // Modify by Neil to add 10 chs to mask
10748                                         PSD_skip_stop = (PSD_skip_start + (1+Is40MHz)*20)+4;
10749                                 }
10750                                 else
10751                                 {
10752                                         PSD_skip_start = ((wlan_channel-1)*5 -Is40MHz*10)-10;  // Modify by Neil to add 10 chs to mask
10753                                         PSD_skip_stop = (PSD_skip_start + (1+Is40MHz)*20)+18;
10754                                 }
10755                         }
10756                         else
10757                         {
10758                                 // mask for 40MHz
10759                                 PSD_skip_start = ((wlan_channel-1)*5 -Is40MHz*10)-2;  // Modify by Neil to add 10 chs to mask
10760                                 PSD_skip_stop = (PSD_skip_start + (1+Is40MHz)*20)+4;
10761                         }
10762                         if(PSD_skip_start < 0)
10763                                 PSD_skip_start = 0;
10764                         if(PSD_skip_stop >80)
10765                                 PSD_skip_stop = 80;
10766                 }
10767                 else
10768                 {
10769                         if((curRxOkCnt+curTxOkCnt) > 5)
10770                         {
10771                                 if(Is40MHz)
10772                                 {
10773                                         PSD_skip_start = ((wlan_channel-1)*5 -Is40MHz*10)-2;  // Modify by Neil to add 10 chs to mask
10774                                         PSD_skip_stop = (PSD_skip_start + (1+Is40MHz)*20)+4;
10775                                 }
10776                                 else
10777                                 {
10778                                         PSD_skip_start = ((wlan_channel-1)*5 -Is40MHz*10)-10;  // Modify by Neil to add 10 chs to mask
10779                                         PSD_skip_stop = (PSD_skip_start + (1+Is40MHz)*20)+18;
10780                                 }
10781
10782                                 if(PSD_skip_start < 0)
10783                                         PSD_skip_start = 0;
10784                                 if(PSD_skip_stop >80)
10785                                         PSD_skip_stop = 80;
10786                         }
10787                 }
10788         }
10789 #if 0
10790         else
10791         {
10792                 if((curRxOkCnt+curTxOkCnt) > 1000)
10793                 {
10794                         PSD_skip_start = (wlan_channel-1)*5 -Is40MHz*10;
10795                         PSD_skip_stop = PSD_skip_start + (1+Is40MHz)*20;
10796                 }
10797         }
10798 #endif  //Reove RXHP Issue
10799         ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD,DBG_LOUD,("PSD: Skip tone from %d to %d \n", PSD_skip_start, PSD_skip_stop));
10800
10801         for (n=0;n<80;n++)
10802         {
10803                 if((n%20)==0)
10804                 {
10805                         channel = (n/20)*4 + 1;
10806
10807                                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, 0x3FF, channel);
10808                                 }
10809                 tone_idx = n%20;
10810                 if ((n>=PSD_skip_start) && (n<PSD_skip_stop))
10811                 {
10812                         PSD_report[n] = SSBT;
10813                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD,DBG_LOUD,("PSD:Tone %d skipped \n", n));
10814                 }
10815                 else
10816                 {
10817                         PSD_report_tmp =  GetPSDData(pDM_Odm, idx[tone_idx], initial_gain_psd);
10818
10819                         if ( PSD_report_tmp > PSD_report[n])
10820                                 PSD_report[n] = PSD_report_tmp;
10821
10822                 }
10823         }
10824
10825         PatchDCTone(pDM_Odm, PSD_report, initial_gain_psd);
10826
10827        //----end
10828         //1 Turn on RX
10829         //Rx AGC on
10830         ODM_SetBBReg(pDM_Odm, 0xC70, BIT0, 1);
10831         ODM_SetBBReg(pDM_Odm, 0xC7C, BIT20, 1);
10832         //CCK on
10833         ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 1);
10834         //1 Turn on TX
10835         //Resume TX Queue
10836
10837         ODM_Write1Byte(pDM_Odm,REG_TXPAUSE, 0x00);
10838         //Turn on 3-wire
10839         ODM_SetBBReg(pDM_Odm, 0x88c, BIT20|BIT21|BIT22|BIT23, 0x0);
10840         //1 Restore Current Settings
10841         //Resume DIG
10842         pDM_Odm->bDMInitialGainEnable = TRUE;
10843
10844         ODM_Write_DIG(pDM_Odm, initial_gain);
10845
10846         // restore originl center frequency
10847         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, CurrentChannel);
10848
10849         //Turn on CCA
10850         ODM_SetBBReg(pDM_Odm, 0xC14, bMaskDWord, RXIQI);
10851         //Restore RX idle low power
10852         if(RxIdleLowPwr == TRUE)
10853                 ODM_SetBBReg(pDM_Odm, 0x818, BIT28, 1);
10854
10855         psd_cnt++;
10856         ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("PSD:psd_cnt = %d \n",psd_cnt));
10857         if (psd_cnt < ReScan)
10858                 ODM_SetTimer(pDM_Odm, &pDM_Odm->PSDTimer, Interval);
10859         else
10860         {
10861                 psd_cnt = 0;
10862                 for(i=0;i<80;i++)
10863                         //DbgPrint("psd_report[%d]=     %d \n", 2402+i, PSD_report[i]);
10864                         RT_TRACE(       COMP_PSD, DBG_LOUD,("psd_report[%d]=     %d \n", 2402+i, PSD_report[i]));
10865
10866
10867                 GoodChannelDecision(pDM_Odm, PSD_report, PSD_bitmap,RSSI_BT, PSD_bitmap_memory);
10868
10869                 if(pDM_Odm->SupportICType==ODM_RTL8723A)
10870                 {
10871                         cur_byte_idx=0;
10872                         cur_bit_idx=0;
10873
10874                         //2 Restore H2C PSD Data to Last Data
10875                         H2C_PSD_DATA_last[0] = H2C_PSD_DATA[0];
10876                         H2C_PSD_DATA_last[1] = H2C_PSD_DATA[1];
10877                         H2C_PSD_DATA_last[2] = H2C_PSD_DATA[2];
10878                         H2C_PSD_DATA_last[3] = H2C_PSD_DATA[3];
10879                         H2C_PSD_DATA_last[4] = H2C_PSD_DATA[4];
10880
10881
10882                         //2 Translate 80bit channel map to 40bit channel
10883                         for ( i=0;i<5;i++)
10884                         {
10885                                 for(n=0;n<8;n++)
10886                                 {
10887                                         cur_byte_idx = i*2 + n/4;
10888                                         cur_bit_idx = (n%4)*2;
10889                                         if ( ((PSD_bitmap[cur_byte_idx]& BIT(cur_bit_idx)) != 0) && ((PSD_bitmap[cur_byte_idx]& BIT(cur_bit_idx+1)) != 0))
10890                                                 H2C_PSD_DATA[i] = H2C_PSD_DATA[i] | (u1Byte) (1 << n);
10891                                 }
10892                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("H2C_PSD_DATA[%d]=0x%x\n" ,i, H2C_PSD_DATA[i]));
10893                         }
10894
10895                         //3 To Compare the difference
10896                         for ( i=0;i<5;i++)
10897                         {
10898                                 if(H2C_PSD_DATA[i] !=H2C_PSD_DATA_last[i])
10899                                 {
10900                                         FillH2CCmd(Adapter, H2C_92C_PSD_RESULT, 5, H2C_PSD_DATA);
10901                                         ODM_RT_TRACE(pDM_Odm, ODM_COMP_PSD, DBG_LOUD,("Need to Update the AFH Map \n"));
10902                                         break;
10903                                 }
10904                                 else
10905                                 {
10906                                         if(i==5)
10907                                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("Not need to Update\n"));
10908                                 }
10909                         }
10910                         if(pDM_Odm->bBtHsOperation)
10911                         {
10912                                 ODM_SetTimer(pDM_Odm, &pDM_Odm->PSDTimer, 10000);
10913                                 ODM_RT_TRACE(   pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("Leave dm_PSD_Monitor\n"));
10914                         }
10915                         else
10916                         {
10917                                 ODM_SetTimer(pDM_Odm, &pDM_Odm->PSDTimer, 1500);
10918                                 ODM_RT_TRACE(   pDM_Odm,ODM_COMP_PSD, DBG_LOUD,("Leave dm_PSD_Monitor\n"));
10919                 }
10920         }
10921     }
10922 }
10923 /*
10924 //Neil for Get BT RSSI
10925 // Be Triggered by BT C2H CMD
10926 VOID
10927 ODM_PSDGetRSSI(
10928         IN      u1Byte  RSSI_BT)
10929 {
10930
10931
10932 }
10933
10934 */
10935
10936 VOID
10937 ODM_PSDMonitor(
10938         IN      PDM_ODM_T       pDM_Odm
10939         )
10940 {
10941         //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
10942
10943         //if(IS_HARDWARE_TYPE_8723AE(Adapter))
10944
10945         if(pDM_Odm->SupportICType == ODM_RTL8723A)   //may need to add other IC type
10946         {
10947                 if(pDM_Odm->SupportInterface==ODM_ITRF_PCIE)
10948                 {
10949                         if(pDM_Odm->bBtDisabled) //need to check upper layer connection
10950                         {
10951                                 pDM_Odm->bPSDactive=FALSE;
10952                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, DBG_LOUD, ("odm_PSDMonitor, return for BT is disabled!!!\n"));
10953                                 return;
10954                         }
10955
10956                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_PSD, DBG_LOUD, ("odm_PSDMonitor\n"));
10957                 //{
10958                         pDM_Odm->bPSDinProcess = TRUE;
10959                         pDM_Odm->bPSDactive=TRUE;
10960                         odm_PSD_Monitor(pDM_Odm);
10961                         pDM_Odm->bPSDinProcess = FALSE;
10962                 }
10963         }
10964
10965 }
10966 VOID
10967 odm_PSDMonitorCallback(
10968         PRT_TIMER               pTimer
10969 )
10970 {
10971         PADAPTER                Adapter = (PADAPTER)pTimer->Adapter;
10972        HAL_DATA_TYPE    *pHalData = GET_HAL_DATA(Adapter);
10973
10974         PlatformScheduleWorkItem(&pHalData->PSDMonitorWorkitem);
10975 }
10976
10977 VOID
10978 odm_PSDMonitorWorkItemCallback(
10979     IN PVOID            pContext
10980     )
10981 {
10982         PADAPTER        Adapter = (PADAPTER)pContext;
10983         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
10984         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;
10985
10986         ODM_PSDMonitor(pDM_Odm);
10987 }
10988
10989 // <20130108, Kordan> E.g., With LNA used, we make the Rx power smaller to have a better EVM. (Asked by Willis)
10990 VOID
10991 odm_RFEControl(
10992         IN      PDM_ODM_T       pDM_Odm,
10993         IN  u8Byte              RSSIVal
10994         )
10995 {
10996         PADAPTER                Adapter = (PADAPTER)pDM_Odm->Adapter;
10997     HAL_DATA_TYPE       *pHalData = GET_HAL_DATA(Adapter);
10998         static u1Byte   TRSW_HighPwr = 0;
10999
11000         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, DBG_LOUD, ("===> odm_RFEControl, RSSI = %d, TRSW_HighPwr = 0x%X, pHalData->RFEType = %d\n",
11001                          RSSIVal, TRSW_HighPwr, pHalData->RFEType ));
11002
11003     if (pHalData->RFEType == 3) {
11004
11005         pDM_Odm->RSSI_TRSW = RSSIVal;
11006
11007         if (pDM_Odm->RSSI_TRSW >= pDM_Odm->RSSI_TRSW_H)
11008                 {
11009             TRSW_HighPwr = 1; // Switch to
11010             PHY_SetBBReg(Adapter, r_ANTSEL_SW_Jaguar, BIT1|BIT0, 0x1);  // Set ANTSW=1/ANTSWB=0  for SW control
11011             PHY_SetBBReg(Adapter, r_ANTSEL_SW_Jaguar, BIT9|BIT8, 0x3);  // Set ANTSW=1/ANTSWB=0  for SW control
11012
11013         }
11014                 else if (pDM_Odm->RSSI_TRSW <= pDM_Odm->RSSI_TRSW_L)
11015         {
11016             TRSW_HighPwr = 0; // Switched back
11017             PHY_SetBBReg(Adapter, r_ANTSEL_SW_Jaguar, BIT1|BIT0, 0x1);  // Set ANTSW=1/ANTSWB=0  for SW control
11018             PHY_SetBBReg(Adapter, r_ANTSEL_SW_Jaguar, BIT9|BIT8, 0x0);  // Set ANTSW=1/ANTSWB=0  for SW control
11019
11020         }
11021     }
11022
11023
11024         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, DBG_LOUD, ("(pDM_Odm->RSSI_TRSW_H, pDM_Odm->RSSI_TRSW_L) = (%d, %d)\n", pDM_Odm->RSSI_TRSW_H, pDM_Odm->RSSI_TRSW_L));
11025         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, DBG_LOUD, ("(RSSIVal, RSSIVal, pDM_Odm->RSSI_TRSW_iso) = (%d, %d, %d)\n",
11026                                  RSSIVal, pDM_Odm->RSSI_TRSW_iso, pDM_Odm->RSSI_TRSW));
11027         ODM_RT_TRACE(pDM_Odm, ODM_COMP_DIG, DBG_LOUD, ("<=== odm_RFEControl, RSSI = %d, TRSW_HighPwr = 0x%X\n", RSSIVal, TRSW_HighPwr));
11028 }
11029
11030 VOID
11031 ODM_MPT_DIG(
11032         IN      PDM_ODM_T       pDM_Odm
11033         )
11034 {
11035         pDIG_T                                          pDM_DigTable = &pDM_Odm->DM_DigTable;
11036         PFALSE_ALARM_STATISTICS         pFalseAlmCnt = &pDM_Odm->FalseAlmCnt;
11037         u1Byte                                          CurrentIGI = (u1Byte)pDM_DigTable->CurIGValue;
11038         u1Byte                                          DIG_Upper = 0x40, DIG_Lower = 0x20, C50, E50;
11039         u8Byte                                          RXOK_cal;
11040         u1Byte                                          IGI_A = 0x20, IGI_B = 0x20;
11041
11042 #if ODM_FIX_2G_DIG
11043         IGI_A = 0x22;
11044         IGI_B = 0x24;
11045 #endif
11046
11047         ODM_RT_TRACE(pDM_Odm,ODM_COMP_MP, DBG_LOUD, ("===> ODM_MPT_DIG, pBandType = %d\n", *pDM_Odm->pBandType));
11048
11049         odm_FalseAlarmCounterStatistics( pDM_Odm);
11050         pDM_Odm->LastNumQryPhyStatusAll = pDM_Odm->NumQryPhyStatusAll;
11051         pDM_Odm->NumQryPhyStatusAll = pDM_Odm->PhyDbgInfo.NumQryPhyStatusCCK + pDM_Odm->PhyDbgInfo.NumQryPhyStatusOFDM;
11052         RXOK_cal = pDM_Odm->NumQryPhyStatusAll - pDM_Odm->LastNumQryPhyStatusAll;
11053
11054         if (RXOK_cal == 0)
11055                 pDM_Odm->RxPWDBAve_final= 0;
11056         else
11057                 pDM_Odm->RxPWDBAve_final= pDM_Odm->RxPWDBAve/RXOK_cal;
11058
11059         pDM_Odm->RxPWDBAve = 0;
11060         ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, DBG_LOUD, ("RX OK = %d\n", RXOK_cal));
11061         ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, DBG_LOUD, ("pDM_Odm->RxPWDBAve_final = %d\n", pDM_Odm->RxPWDBAve_final));
11062
11063         // <20130315, Kordan> Except Cameo, we should always trun on 2.4G/5G DIG.
11064         // (Cameo fixes the IGI of 2.4G, so only DIG on 5G. Asked by James.)
11065 #if ODM_FIX_2G_DIG
11066         if (*pDM_Odm->pBandType == BAND_ON_5G){  // for 5G
11067 #else
11068         if (1){ // for both 2G/5G
11069 #endif
11070                 pDM_Odm->MPDIG_2G = FALSE;
11071                 pDM_Odm->Times_2G = 0;
11072
11073                 if (RXOK_cal >= 70 && pDM_Odm->RxPWDBAve_final<= 30)
11074                 {
11075                         if (CurrentIGI > 0x24){
11076                                 ODM_Write1Byte( pDM_Odm, rA_IGI_Jaguar, 0x24);
11077                                 ODM_Write1Byte( pDM_Odm, rB_IGI_Jaguar, 0x24);
11078                         }
11079                 }
11080                 else
11081                 {
11082                         if(pFalseAlmCnt->Cnt_all > 1000){
11083                                 CurrentIGI = CurrentIGI + 8;
11084                         }
11085                         else if(pFalseAlmCnt->Cnt_all > 200){
11086                                 CurrentIGI = CurrentIGI + 4;
11087                         }
11088                         else if (pFalseAlmCnt->Cnt_all > 50){
11089                                 CurrentIGI = CurrentIGI + 2;
11090                         }
11091                         else if (pFalseAlmCnt->Cnt_all < 2){
11092                                 CurrentIGI = CurrentIGI - 2;
11093                         }
11094
11095                         if (CurrentIGI < DIG_Lower ){
11096                                 CurrentIGI = DIG_Lower;
11097                         }
11098                         else if(CurrentIGI > DIG_Upper){
11099                                 CurrentIGI = DIG_Upper;
11100                         }
11101
11102                         pDM_DigTable->CurIGValue = CurrentIGI;
11103
11104                         ODM_Write1Byte( pDM_Odm, rA_IGI_Jaguar, (u1Byte)CurrentIGI);
11105                         ODM_Write1Byte( pDM_Odm, rB_IGI_Jaguar, (u1Byte)CurrentIGI);
11106
11107                         C50 = ODM_Read1Byte( pDM_Odm, 0xc50);
11108                         E50 = ODM_Read1Byte( pDM_Odm, 0xe50);
11109                         //pDM_Odm->MPDIG_2G = FALSE;
11110                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_MP, DBG_LOUD, ("DIG = (%x, %x), Cnt_all = %d, Cnt_Ofdm_fail = %d, Cnt_Cck_fail = %d\n", C50, E50, pFalseAlmCnt->Cnt_all, pFalseAlmCnt->Cnt_Ofdm_fail, pFalseAlmCnt->Cnt_Cck_fail));
11111                 }
11112
11113         }
11114         else
11115         {       //2G
11116                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_MP, DBG_LOUD, ("MPDIG_2G = %d,\n", pDM_Odm->MPDIG_2G));
11117
11118                 if(pDM_Odm->MPDIG_2G == FALSE){
11119                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_MP, DBG_LOUD, ("===> Fix IGI\n"));
11120                         ODM_Write1Byte( pDM_Odm, rA_IGI_Jaguar, (u1Byte)IGI_A);
11121                         ODM_Write1Byte( pDM_Odm, rB_IGI_Jaguar, (u1Byte)IGI_B);
11122                 }
11123                 if (pDM_Odm->Times_2G == 2)
11124                         pDM_Odm->MPDIG_2G = TRUE;
11125                 pDM_Odm->Times_2G++;
11126         }
11127         ODM_RT_TRACE(pDM_Odm,ODM_COMP_DIG, DBG_LOUD, ("pDM_Odm->RxPWDBAve_final = %d\n", pDM_Odm->RxPWDBAve_final));
11128
11129         if (pDM_Odm->SupportICType == ODM_RTL8812)
11130                 odm_RFEControl(pDM_Odm, pDM_Odm->RxPWDBAve_final);
11131
11132         ODM_SetTimer(pDM_Odm, &pDM_Odm->MPT_DIGTimer, 700);
11133
11134 }
11135
11136 VOID
11137 odm_MPT_DIGCallback(
11138         PRT_TIMER               pTimer
11139 )
11140 {
11141         PADAPTER                Adapter = (PADAPTER)pTimer->Adapter;
11142        HAL_DATA_TYPE    *pHalData = GET_HAL_DATA(Adapter);
11143           PDM_ODM_T             pDM_Odm = &pHalData->DM_OutSrc;
11144
11145
11146         #if DEV_BUS_TYPE==RT_PCI_INTERFACE
11147                 #if USE_WORKITEM
11148                         PlatformScheduleWorkItem(&pDM_Odm->MPT_DIGWorkitem);
11149                 #else
11150                         ODM_MPT_DIG(pDM_Odm);
11151                 #endif
11152         #else
11153                 PlatformScheduleWorkItem(&pDM_Odm->MPT_DIGWorkitem);
11154         #endif
11155
11156 }
11157
11158 VOID
11159 odm_MPT_DIGWorkItemCallback(
11160     IN PVOID            pContext
11161     )
11162 {
11163         PADAPTER        Adapter = (PADAPTER)pContext;
11164         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
11165         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;
11166
11167         ODM_MPT_DIG(pDM_Odm);
11168 }
11169
11170
11171
11172
11173  //cosa debug tool need to modify
11174
11175 VOID
11176 ODM_PSDDbgControl(
11177         IN      PADAPTER        Adapter,
11178         IN      u4Byte          mode,
11179         IN      u4Byte          btRssi
11180         )
11181 {
11182 #if (DEV_BUS_TYPE == RT_PCI_INTERFACE)
11183         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
11184         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;
11185
11186         ODM_RT_TRACE(pDM_Odm,COMP_PSD, DBG_LOUD, (" Monitor mode=%d, btRssi=%d\n", mode, btRssi));
11187         if(mode)
11188         {
11189                 pDM_Odm->RSSI_BT = (u1Byte)btRssi;
11190                 pDM_Odm->bUserAssignLevel = TRUE;
11191                 ODM_SetTimer( pDM_Odm, &pDM_Odm->PSDTimer, 0); //ms
11192         }
11193         else
11194         {
11195                 ODM_CancelTimer(pDM_Odm, &pDM_Odm->PSDTimer);
11196         }
11197 #endif
11198 }
11199
11200
11201 //#if(DEV_BUS_TYPE == RT_PCI_INTERFACE)|(DEV_BUS_TYPE == RT_USB_INTERFACE)
11202
11203 void    odm_RXHPInit(
11204         IN              PDM_ODM_T               pDM_Odm)
11205 {
11206 #if (DEV_BUS_TYPE == RT_PCI_INTERFACE)|(DEV_BUS_TYPE == RT_USB_INTERFACE)
11207         pRXHP_T                 pRX_HP_Table  = &pDM_Odm->DM_RXHP_Table;
11208         u1Byte                  index;
11209
11210         pRX_HP_Table->RXHP_enable = TRUE;
11211         pRX_HP_Table->RXHP_flag = 0;
11212         pRX_HP_Table->PSD_func_trigger = 0;
11213         pRX_HP_Table->Pre_IGI = 0x20;
11214         pRX_HP_Table->Cur_IGI = 0x20;
11215         pRX_HP_Table->Cur_pw_th = pw_th_10dB;
11216         pRX_HP_Table->Pre_pw_th = pw_th_10dB;
11217         for(index=0; index<80; index++)
11218                 pRX_HP_Table->PSD_bitmap_RXHP[index] = 1;
11219
11220 #if(DEV_BUS_TYPE == RT_USB_INTERFACE)
11221         pRX_HP_Table->TP_Mode = Idle_Mode;
11222 #endif
11223 #endif
11224 }
11225
11226 void odm_RXHP(
11227         IN              PDM_ODM_T               pDM_Odm)
11228 {
11229 #if( DM_ODM_SUPPORT_TYPE & (ODM_WIN))
11230 #if (DEV_BUS_TYPE == RT_PCI_INTERFACE) | (DEV_BUS_TYPE == RT_USB_INTERFACE)
11231         PADAPTER        Adapter =  pDM_Odm->Adapter;
11232         PMGNT_INFO      pMgntInfo = &(Adapter->MgntInfo);
11233         pDIG_T          pDM_DigTable = &pDM_Odm->DM_DigTable;
11234         pRXHP_T         pRX_HP_Table  = &pDM_Odm->DM_RXHP_Table;
11235        PFALSE_ALARM_STATISTICS          FalseAlmCnt = &(pDM_Odm->FalseAlmCnt);
11236
11237         u1Byte                  i, j, sum;
11238         u1Byte                  Is40MHz;
11239         s1Byte                  Intf_diff_idx, MIN_Intf_diff_idx = 16;
11240        s4Byte                   cur_channel;
11241        u1Byte                   ch_map_intf_5M[17] = {0};
11242        static u4Byte            FA_TH = 0;
11243         static u1Byte           psd_intf_flag = 0;
11244         static s4Byte           curRssi = 0;
11245        static s4Byte            preRssi = 0;
11246         static u1Byte           PSDTriggerCnt = 1;
11247
11248         u1Byte                  RX_HP_enable = (u1Byte)(ODM_GetBBReg(pDM_Odm, rOFDM0_XAAGCCore2, bMaskDWord)>>31);   // for debug!!
11249
11250 #if(DEV_BUS_TYPE == RT_USB_INTERFACE)
11251         static s8Byte           lastTxOkCnt = 0, lastRxOkCnt = 0;
11252        s8Byte                   curTxOkCnt, curRxOkCnt;
11253         s8Byte                  curTPOkCnt;
11254         s8Byte                  TP_Acc3, TP_Acc5;
11255         static s8Byte           TP_Buff[5] = {0};
11256         static u1Byte           pre_state = 0, pre_state_flag = 0;
11257         static u1Byte           Intf_HighTP_flag = 0, De_counter = 16;
11258         static u1Byte           TP_Degrade_flag = 0;
11259 #endif
11260         static u1Byte           LatchCnt = 0;
11261
11262         if(pDM_Odm->SupportICType & (ODM_RTL8723A|ODM_RTL8188E))
11263                 return;
11264         //AGC RX High Power Mode is only applied on 2G band in 92D!!!
11265         if(pDM_Odm->SupportICType == ODM_RTL8192D)
11266         {
11267                 if(*(pDM_Odm->pBandType) != ODM_BAND_2_4G)
11268                         return;
11269         }
11270
11271         if(!(pDM_Odm->SupportAbility==ODM_BB_RXHP))
11272                 return;
11273
11274
11275         //RX HP ON/OFF
11276         if(RX_HP_enable == 1)
11277                 pRX_HP_Table->RXHP_enable = FALSE;
11278         else
11279                 pRX_HP_Table->RXHP_enable = TRUE;
11280
11281         if(pRX_HP_Table->RXHP_enable == FALSE)
11282         {
11283                 if(pRX_HP_Table->RXHP_flag == 1)
11284                 {
11285                         pRX_HP_Table->RXHP_flag = 0;
11286                         psd_intf_flag = 0;
11287                 }
11288                 return;
11289         }
11290
11291 #if(DEV_BUS_TYPE == RT_USB_INTERFACE)
11292         //2 Record current TP for USB interface
11293         curTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast)-lastTxOkCnt;
11294         curRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast)-lastRxOkCnt;
11295         lastTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast);
11296         lastRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast);
11297
11298         curTPOkCnt = curTxOkCnt+curRxOkCnt;
11299         TP_Buff[0] = curTPOkCnt;    // current TP
11300         TP_Acc3 = PlatformDivision64((TP_Buff[1]+TP_Buff[2]+TP_Buff[3]), 3);
11301         TP_Acc5 = PlatformDivision64((TP_Buff[0]+TP_Buff[1]+TP_Buff[2]+TP_Buff[3]+TP_Buff[4]), 5);
11302
11303         if(TP_Acc5 < 1000)
11304                 pRX_HP_Table->TP_Mode = Idle_Mode;
11305         else if((1000 < TP_Acc5)&&(TP_Acc5 < 3750000))
11306                 pRX_HP_Table->TP_Mode = Low_TP_Mode;
11307         else
11308                 pRX_HP_Table->TP_Mode = High_TP_Mode;
11309
11310         ODM_RT_TRACE(pDM_Odm,   ODM_COMP_RXHP, ODM_DBG_LOUD, ("RX HP TP Mode = %d\n", pRX_HP_Table->TP_Mode));
11311         // Since TP result would be sampled every 2 sec, it needs to delay 4sec to wait PSD processing.
11312         // When LatchCnt = 0, we would Get PSD result.
11313         if(TP_Degrade_flag == 1)
11314         {
11315                 LatchCnt--;
11316                 if(LatchCnt == 0)
11317                 {
11318                         TP_Degrade_flag = 0;
11319                 }
11320         }
11321         // When PSD function triggered by TP degrade 20%, and Interference Flag = 1
11322         // Set a De_counter to wait IGI = upper bound. If time is UP, the Interference flag will be pull down.
11323         if(Intf_HighTP_flag == 1)
11324         {
11325                 De_counter--;
11326                 if(De_counter == 0)
11327                 {
11328                         Intf_HighTP_flag = 0;
11329                         psd_intf_flag = 0;
11330                 }
11331         }
11332 #endif
11333
11334         //2 AGC RX High Power Mode by PSD only applied to STA Mode
11335         //3 NOT applied 1. Ad Hoc Mode.
11336         //3 NOT applied 2. AP Mode
11337         if ((pMgntInfo->mAssoc) && (!pMgntInfo->mIbss) && (!ACTING_AS_AP(Adapter)))
11338         {
11339                 Is40MHz = *(pDM_Odm->pBandWidth);
11340                 curRssi = pDM_Odm->RSSI_Min;
11341                 cur_channel = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, 0x0fff) & 0x0f;
11342                 ODM_RT_TRACE(pDM_Odm,   ODM_COMP_RXHP, ODM_DBG_LOUD, ("RXHP RX HP flag = %d\n", pRX_HP_Table->RXHP_flag));
11343                 ODM_RT_TRACE(pDM_Odm,   ODM_COMP_RXHP, ODM_DBG_LOUD, ("RXHP FA = %d\n", FalseAlmCnt->Cnt_all));
11344                 ODM_RT_TRACE(pDM_Odm,   ODM_COMP_RXHP, ODM_DBG_LOUD, ("RXHP cur RSSI = %d, pre RSSI=%d\n", curRssi, preRssi));
11345                 ODM_RT_TRACE(pDM_Odm,   ODM_COMP_RXHP, ODM_DBG_LOUD, ("RXHP current CH = %d\n", cur_channel));
11346                 ODM_RT_TRACE(pDM_Odm,   ODM_COMP_RXHP, ODM_DBG_LOUD, ("RXHP Is 40MHz = %d\n", Is40MHz));
11347         //2 PSD function would be triggered
11348         //3 1. Every 4 sec for PCIE
11349         //3 2. Before TP Mode (Idle TP<4kbps) for USB
11350         //3 3. After TP Mode (High TP) for USB
11351                 if((curRssi > 68) && (pRX_HP_Table->RXHP_flag == 0))    // Only RSSI>TH and RX_HP_flag=0 will Do PSD process
11352                 {
11353 #if (DEV_BUS_TYPE == RT_USB_INTERFACE)
11354                         //2 Before TP Mode ==> PSD would be trigger every 4 sec
11355                         if(pRX_HP_Table->TP_Mode == Idle_Mode)          //2.1 less wlan traffic <4kbps
11356                         {
11357 #endif
11358                                 if(PSDTriggerCnt == 1)
11359                                 {
11360                                         odm_PSD_RXHP(pDM_Odm);
11361                                         pRX_HP_Table->PSD_func_trigger = 1;
11362                                         PSDTriggerCnt = 0;
11363                                 }
11364                                 else
11365                                 {
11366                                         PSDTriggerCnt++;
11367                                 }
11368 #if(DEV_BUS_TYPE == RT_USB_INTERFACE)
11369                         }
11370                         //2 After TP Mode ==> Check if TP degrade larger than 20% would trigger PSD function
11371                         if(pRX_HP_Table->TP_Mode == High_TP_Mode)
11372                         {
11373                                 if((pre_state_flag == 0)&&(LatchCnt == 0))
11374                                 {
11375                                         // TP var < 5%
11376                                         if((((curTPOkCnt-TP_Acc3)*20)<(TP_Acc3))&&(((curTPOkCnt-TP_Acc3)*20)>(-TP_Acc3)))
11377                                         {
11378                                                 pre_state++;
11379                                                 if(pre_state == 3)      // hit pre_state condition => consecutive 3 times
11380                                                 {
11381                                                         pre_state_flag = 1;
11382                                                         pre_state = 0;
11383                                                 }
11384
11385                                         }
11386                                         else
11387                                         {
11388                                                 pre_state = 0;
11389                                         }
11390                                 }
11391                                 //3 If pre_state_flag=1 ==> start to monitor TP degrade 20%
11392                                 if(pre_state_flag == 1)
11393                                 {
11394                                         if(((TP_Acc3-curTPOkCnt)*5)>(TP_Acc3))      // degrade 20%
11395                                         {
11396                                                 odm_PSD_RXHP(pDM_Odm);
11397                                                 pRX_HP_Table->PSD_func_trigger = 1;
11398                                                 TP_Degrade_flag = 1;
11399                                                 LatchCnt = 2;
11400                                                 pre_state_flag = 0;
11401                                         }
11402                                         else if(((TP_Buff[2]-curTPOkCnt)*5)>TP_Buff[2])
11403                                         {
11404                                                 odm_PSD_RXHP(pDM_Odm);
11405                                                 pRX_HP_Table->PSD_func_trigger = 1;
11406                                                 TP_Degrade_flag = 1;
11407                                                 LatchCnt = 2;
11408                                                 pre_state_flag = 0;
11409                                         }
11410                                         else if(((TP_Buff[3]-curTPOkCnt)*5)>TP_Buff[3])
11411                                         {
11412                                                 odm_PSD_RXHP(pDM_Odm);
11413                                                 pRX_HP_Table->PSD_func_trigger = 1;
11414                                                 TP_Degrade_flag = 1;
11415                                                 LatchCnt = 2;
11416                                                 pre_state_flag = 0;
11417                                         }
11418                                 }
11419                         }
11420 #endif
11421 }
11422
11423 #if (DEV_BUS_TYPE == RT_USB_INTERFACE)
11424                 for (i=0;i<4;i++)
11425                 {
11426                         TP_Buff[4-i] = TP_Buff[3-i];
11427                 }
11428 #endif
11429                 //2 Update PSD bitmap according to PSD report
11430                 if((pRX_HP_Table->PSD_func_trigger == 1)&&(LatchCnt == 0))
11431                 {
11432                         //2 Separate 80M bandwidth into 16 group with smaller 5M BW.
11433                         for (i = 0 ; i < 16 ; i++)
11434                         {
11435                                 sum = 0;
11436                                 for(j = 0; j < 5 ; j++)
11437                                         sum += pRX_HP_Table->PSD_bitmap_RXHP[5*i + j];
11438
11439                                 if(sum < 5)
11440                                 {
11441                                         ch_map_intf_5M[i] = 1;  // interference flag
11442                                 }
11443                         }
11444                         //=============just for debug=========================
11445                         //for(i=0;i<16;i++)
11446                                 //DbgPrint("RX HP: ch_map_intf_5M[%d] = %d\n", i, ch_map_intf_5M[i]);
11447                         //===============================================
11448                         //2 Mask target channel 5M index
11449                         for(i = 0; i < (4+4*Is40MHz) ; i++)
11450                         {
11451                                 ch_map_intf_5M[cur_channel - (1+2*Is40MHz) + i] = 0;
11452                         }
11453
11454                         psd_intf_flag = 0;
11455                         for(i = 0; i < 16; i++)
11456                         {
11457                                 if(ch_map_intf_5M[i] == 1)
11458                         {
11459                                 psd_intf_flag = 1;            // interference is detected!!!
11460                                 break;
11461                                 }
11462                         }
11463
11464 #if (DEV_BUS_TYPE == RT_USB_INTERFACE)
11465                         if(pRX_HP_Table->TP_Mode!=Idle_Mode)
11466                         {
11467                                 if(psd_intf_flag == 1)     // to avoid psd_intf_flag always 1
11468                                 {
11469                                         Intf_HighTP_flag = 1;
11470                                         De_counter = 32;     // 0x1E -> 0x3E needs 32 times by each IGI step =1
11471                                 }
11472                         }
11473 #endif
11474                         ODM_RT_TRACE(pDM_Odm,   ODM_COMP_RXHP, ODM_DBG_LOUD, ("RX HP psd_intf_flag = %d\n", psd_intf_flag));
11475                         //2 Distance between target channel and interference
11476                         for(i = 0; i < 16; i++)
11477                         {
11478                                 if(ch_map_intf_5M[i] == 1)
11479                                 {
11480                                         Intf_diff_idx = ((cur_channel+Is40MHz-(i+1))>0) ? (s1Byte)(cur_channel-2*Is40MHz-(i-2)) : (s1Byte)((i+1)-(cur_channel+2*Is40MHz));
11481                                 if(Intf_diff_idx < MIN_Intf_diff_idx)
11482                                                 MIN_Intf_diff_idx = Intf_diff_idx;    // the min difference index between interference and target
11483                                 }
11484                         }
11485                         ODM_RT_TRACE(pDM_Odm,   ODM_COMP_RXHP, ODM_DBG_LOUD, ("RX HP MIN_Intf_diff_idx = %d\n", MIN_Intf_diff_idx));
11486                         //2 Choose False Alarm Threshold
11487                         switch (MIN_Intf_diff_idx){
11488                                 case 0:
11489                                 case 1:
11490                                 case 2:
11491                                 case 3:
11492                                         FA_TH = FA_RXHP_TH1;
11493                                 break;
11494                                 case 4:                         // CH5
11495                                 case 5:                         // CH6
11496                                         FA_TH = FA_RXHP_TH2;
11497                                 break;
11498                                 case 6:                         // CH7
11499                                 case 7:                         // CH8
11500                                         FA_TH = FA_RXHP_TH3;
11501                                         break;
11502                         case 8:                         // CH9
11503                                 case 9:                         //CH10
11504                                         FA_TH = FA_RXHP_TH4;
11505                                         break;
11506                                 case 10:
11507                                 case 11:
11508                                 case 12:
11509                                 case 13:
11510                                 case 14:
11511                                 case 15:
11512                                         FA_TH = FA_RXHP_TH5;
11513                                         break;
11514                 }
11515                         ODM_RT_TRACE(pDM_Odm,   ODM_COMP_RXHP, ODM_DBG_LOUD, ("RX HP FA_TH = %d\n", FA_TH));
11516                         pRX_HP_Table->PSD_func_trigger = 0;
11517                 }
11518                 //1 Monitor RSSI variation to choose the suitable IGI or Exit AGC RX High Power Mode
11519                 if(pRX_HP_Table->RXHP_flag == 1)
11520                 {
11521                 if ((curRssi > 80)&&(preRssi < 80))
11522                 {
11523                                 pRX_HP_Table->Cur_IGI = LNA_Low_Gain_1;
11524                 }
11525                 else if ((curRssi < 80)&&(preRssi > 80))
11526                 {
11527                                 pRX_HP_Table->Cur_IGI = LNA_Low_Gain_2;
11528                         }
11529                 else if ((curRssi > 72)&&(preRssi < 72))
11530                         {
11531                                 pRX_HP_Table->Cur_IGI = LNA_Low_Gain_2;
11532                 }
11533                 else if ((curRssi < 72)&&( preRssi > 72))
11534                         {
11535                                 pRX_HP_Table->Cur_IGI = LNA_Low_Gain_3;
11536                 }
11537                 else if (curRssi < 68)           //RSSI is NOT large enough!!==> Exit AGC RX High Power Mode
11538                 {
11539                                 pRX_HP_Table->Cur_pw_th = pw_th_10dB;
11540                                 pRX_HP_Table->RXHP_flag = 0;    // Back to Normal DIG Mode
11541                                 psd_intf_flag = 0;
11542                         }
11543                 }
11544                 else    // pRX_HP_Table->RXHP_flag == 0
11545                 {
11546                         //1 Decide whether to enter AGC RX High Power Mode
11547                         if ((curRssi > 70) && (psd_intf_flag == 1) && (FalseAlmCnt->Cnt_all > FA_TH) &&
11548                                 (pDM_DigTable->CurIGValue == pDM_DigTable->rx_gain_range_max))
11549                         {
11550                                 if (curRssi > 80)
11551                                 {
11552                                         pRX_HP_Table->Cur_IGI = LNA_Low_Gain_1;
11553                                 }
11554                                 else if (curRssi > 72)
11555                         {
11556                                 pRX_HP_Table->Cur_IGI = LNA_Low_Gain_2;
11557                                 }
11558                                 else
11559                                 {
11560                                         pRX_HP_Table->Cur_IGI = LNA_Low_Gain_3;
11561                                 }
11562                                 pRX_HP_Table->Cur_pw_th = pw_th_16dB;           //RegC54[9:8]=2'b11: to enter AGC Flow 3
11563                                 pRX_HP_Table->First_time_enter = TRUE;
11564                                 pRX_HP_Table->RXHP_flag = 1;    //      RXHP_flag=1: AGC RX High Power Mode, RXHP_flag=0: Normal DIG Mode
11565                         }
11566                 }
11567                 preRssi = curRssi;
11568                 odm_Write_RXHP(pDM_Odm);
11569         }
11570 #endif //#if( DM_ODM_SUPPORT_TYPE & (ODM_WIN))
11571 #endif //#if (DEV_BUS_TYPE == RT_PCI_INTERFACE) | (DEV_BUS_TYPE == RT_USB_INTERFACE)
11572 }
11573
11574 void odm_Write_RXHP(
11575         IN      PDM_ODM_T       pDM_Odm)
11576 {
11577         pRXHP_T         pRX_HP_Table = &pDM_Odm->DM_RXHP_Table;
11578         u4Byte          currentIGI;
11579
11580         if(pRX_HP_Table->Cur_IGI != pRX_HP_Table->Pre_IGI)
11581         {
11582                 ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskByte0, pRX_HP_Table->Cur_IGI);
11583                 ODM_SetBBReg(pDM_Odm, rOFDM0_XBAGCCore1, bMaskByte0, pRX_HP_Table->Cur_IGI);
11584         }
11585
11586         if(pRX_HP_Table->Cur_pw_th != pRX_HP_Table->Pre_pw_th)
11587 {
11588                 ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore2, BIT8|BIT9, pRX_HP_Table->Cur_pw_th);  // RegC54[9:8]=2'b11:  AGC Flow 3
11589         }
11590
11591         if(pRX_HP_Table->RXHP_flag == 0)
11592         {
11593                 pRX_HP_Table->Cur_IGI = 0x20;
11594         }
11595         else
11596         {
11597                 currentIGI = ODM_GetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskByte0);
11598                 if(currentIGI<0x50)
11599                 {
11600                         ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskByte0, pRX_HP_Table->Cur_IGI);
11601                         ODM_SetBBReg(pDM_Odm, rOFDM0_XBAGCCore1, bMaskByte0, pRX_HP_Table->Cur_IGI);
11602                 }
11603         }
11604         pRX_HP_Table->Pre_IGI = pRX_HP_Table->Cur_IGI;
11605         pRX_HP_Table->Pre_pw_th = pRX_HP_Table->Cur_pw_th;
11606
11607 }
11608
11609 VOID
11610 odm_PSD_RXHP(
11611         IN      PDM_ODM_T       pDM_Odm
11612 )
11613 {
11614         pRXHP_T                 pRX_HP_Table  = &pDM_Odm->DM_RXHP_Table;
11615         PADAPTER                Adapter =  pDM_Odm->Adapter;
11616         PMGNT_INFO              pMgntInfo = &(Adapter->MgntInfo);
11617         unsigned int            pts, start_point, stop_point, initial_gain ;
11618         static u1Byte           PSD_bitmap_memory[80], init_memory = 0;
11619         static u1Byte           psd_cnt=0;
11620         static u4Byte           PSD_report[80], PSD_report_tmp;
11621         static u8Byte           lastTxOkCnt=0, lastRxOkCnt=0;
11622         u1Byte                  idx[20]={96,99,102,106,109,112,115,118,122,125,
11623                                         0,3,6,10,13,16,19,22,26,29};
11624         u1Byte                  n, i, channel, BBReset,tone_idx;
11625         u1Byte                  PSD_bitmap[10]/*, SSBT=0*/,initial_gain_psd=0, RSSI_BT=0, initialGainUpper;
11626         s4Byte                          PSD_skip_start, PSD_skip_stop;
11627         u4Byte                  CurrentChannel, RXIQI, RxIdleLowPwr, wlan_channel;
11628         u4Byte                  ReScan, Interval, Is40MHz;
11629         u8Byte                  curTxOkCnt, curRxOkCnt;
11630         //--------------2G band synthesizer for 92D switch RF channel using-----------------
11631         u1Byte                  group_idx=0;
11632         u4Byte                  SYN_RF25=0, SYN_RF26=0, SYN_RF27=0, SYN_RF2B=0, SYN_RF2C=0;
11633         u4Byte                  SYN[5] = {0x25, 0x26, 0x27, 0x2B, 0x2C};    // synthesizer RF register for 2G channel
11634         u4Byte                  SYN_group[3][5] = {{0x643BC, 0xFC038, 0x77C1A, 0x41289, 0x01840},     // For CH1,2,4,9,10.11.12   {0x643BC, 0xFC038, 0x77C1A, 0x41289, 0x01840}
11635                                                                             {0x643BC, 0xFC038, 0x07C1A, 0x41289, 0x01840},     // For CH3,13,14
11636                                                                             {0x243BC, 0xFC438, 0x07C1A, 0x4128B, 0x0FC41}};   // For Ch5,6,7,8
11637        //--------------------- Add by Gary for Debug setting ----------------------
11638         u1Byte                 RSSI_BT_new = (u1Byte) ODM_GetBBReg(pDM_Odm, 0xB9C, 0xFF);
11639        u1Byte                 rssi_ctrl = (u1Byte) ODM_GetBBReg(pDM_Odm, 0xB38, 0xFF);
11640        //---------------------------------------------------------------------
11641
11642         if(pMgntInfo->bScanInProgress)
11643         {
11644                 return;
11645         }
11646
11647         ReScan = PSD_RESCAN;
11648         Interval = SCAN_INTERVAL;
11649
11650
11651         //1 Initialization
11652         if(init_memory == 0)
11653         {
11654                 RT_TRACE(       COMP_PSD, DBG_LOUD,("Init memory\n"));
11655                 for(i = 0; i < 80; i++)
11656                         PSD_bitmap_memory[i] = 0xFF; // channel is always good
11657                 init_memory = 1;
11658         }
11659         if(psd_cnt == 0)
11660         {
11661                 RT_TRACE(COMP_PSD, DBG_LOUD,("Enter dm_PSD_Monitor\n"));
11662                 for(i = 0; i < 80; i++)
11663                         PSD_report[i] = 0;
11664         }
11665
11666         //1 Backup Current Settings
11667         CurrentChannel = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask);
11668         if(pDM_Odm->SupportICType == ODM_RTL8192D)
11669         {
11670                 //2 Record Current synthesizer parameters based on current channel
11671                 if((*(pDM_Odm->pMacPhyMode)==ODM_SMSP)||(*(pDM_Odm->pMacPhyMode)==ODM_DMSP))
11672                 {
11673                         SYN_RF25 = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x25, bMaskDWord);
11674                         SYN_RF26 = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x26, bMaskDWord);
11675                         SYN_RF27 = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x27, bMaskDWord);
11676                         SYN_RF2B = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x2B, bMaskDWord);
11677                         SYN_RF2C = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x2C, bMaskDWord);
11678         }
11679                 else     // DualMAC_DualPHY 2G
11680                 {
11681                         SYN_RF25 = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x25, bMaskDWord);
11682                         SYN_RF26 = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x26, bMaskDWord);
11683                         SYN_RF27 = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x27, bMaskDWord);
11684                         SYN_RF2B = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x2B, bMaskDWord);
11685                         SYN_RF2C = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x2C, bMaskDWord);
11686                 }
11687         }
11688         RXIQI = ODM_GetBBReg(pDM_Odm, 0xC14, bMaskDWord);
11689         RxIdleLowPwr = (ODM_GetBBReg(pDM_Odm, 0x818, bMaskDWord)&BIT28)>>28;
11690         Is40MHz = *(pDM_Odm->pBandWidth);
11691         ODM_RT_TRACE(pDM_Odm,   COMP_PSD, DBG_LOUD,("PSD Scan Start\n"));
11692         //1 Turn off CCK
11693         ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 0);
11694         //1 Turn off TX
11695         //Pause TX Queue
11696         ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0xFF);
11697         //Force RX to stop TX immediately
11698         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bRFRegOffsetMask, 0x32E13);
11699         //1 Turn off RX
11700         //Rx AGC off  RegC70[0]=0, RegC7C[20]=0
11701         ODM_SetBBReg(pDM_Odm, 0xC70, BIT0, 0);
11702         ODM_SetBBReg(pDM_Odm, 0xC7C, BIT20, 0);
11703         //Turn off CCA
11704         ODM_SetBBReg(pDM_Odm, 0xC14, bMaskDWord, 0x0);
11705         //BB Reset
11706         ODM_SetBBReg(pDM_Odm, 0x87C, BIT31, 1); //clock gated to prevent from AGC table mess
11707         BBReset = ODM_Read1Byte(pDM_Odm, 0x02);
11708         ODM_Write1Byte(pDM_Odm, 0x02, BBReset&(~BIT0));
11709         ODM_Write1Byte(pDM_Odm, 0x02, BBReset|BIT0);
11710         ODM_SetBBReg(pDM_Odm, 0x87C, BIT31, 0);
11711         //1 Leave RX idle low power
11712         ODM_SetBBReg(pDM_Odm, 0x818, BIT28, 0x0);
11713         //1 Fix initial gain
11714         RSSI_BT = RSSI_BT_new;
11715         RT_TRACE(COMP_PSD, DBG_LOUD,("PSD: RSSI_BT= %d\n", RSSI_BT));
11716
11717         if(rssi_ctrl == 1)        // just for debug!!
11718                 initial_gain_psd = RSSI_BT_new;
11719         else
11720                 initial_gain_psd = pDM_Odm->RSSI_Min;    // PSD report based on RSSI
11721
11722         RT_TRACE(COMP_PSD, DBG_LOUD,("PSD: RSSI_BT= %d\n", RSSI_BT));
11723
11724         initialGainUpper = 0x54;
11725
11726         RSSI_BT = initial_gain_psd;
11727         //SSBT = RSSI_BT;
11728
11729         //RT_TRACE(     COMP_PSD, DBG_LOUD,("PSD: SSBT= %d\n", SSBT));
11730         RT_TRACE(       COMP_PSD, DBG_LOUD,("PSD: initial gain= 0x%x\n", initial_gain_psd));
11731
11732         pDM_Odm->bDMInitialGainEnable = FALSE;
11733         initial_gain = ODM_GetBBReg(pDM_Odm, 0xc50, bMaskDWord) & 0x7F;
11734         //ODM_SetBBReg(pDM_Odm, 0xc50, 0x7F, initial_gain_psd);
11735         ODM_Write_DIG(pDM_Odm, initial_gain_psd);
11736         //1 Turn off 3-wire
11737         ODM_SetBBReg(pDM_Odm, 0x88c, BIT20|BIT21|BIT22|BIT23, 0xF);
11738
11739         //pts value = 128, 256, 512, 1024
11740         pts = 128;
11741
11742         if(pts == 128)
11743         {
11744                 ODM_SetBBReg(pDM_Odm, 0x808, BIT14|BIT15, 0x0);
11745                 start_point = 64;
11746                 stop_point = 192;
11747         }
11748         else if(pts == 256)
11749         {
11750                 ODM_SetBBReg(pDM_Odm, 0x808, BIT14|BIT15, 0x1);
11751                 start_point = 128;
11752                 stop_point = 384;
11753         }
11754         else if(pts == 512)
11755         {
11756                 ODM_SetBBReg(pDM_Odm, 0x808, BIT14|BIT15, 0x2);
11757                 start_point = 256;
11758                 stop_point = 768;
11759         }
11760         else
11761         {
11762                 ODM_SetBBReg(pDM_Odm, 0x808, BIT14|BIT15, 0x3);
11763                 start_point = 512;
11764                 stop_point = 1536;
11765         }
11766
11767
11768 //3 Skip WLAN channels if WLAN busy
11769         curTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast) - lastTxOkCnt;
11770         curRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast) - lastRxOkCnt;
11771         lastTxOkCnt = *(pDM_Odm->pNumTxBytesUnicast);
11772         lastRxOkCnt = *(pDM_Odm->pNumRxBytesUnicast);
11773
11774         PSD_skip_start=80;
11775         PSD_skip_stop = 0;
11776         wlan_channel = CurrentChannel & 0x0f;
11777
11778         RT_TRACE(COMP_PSD,DBG_LOUD,("PSD: current channel: %x, BW:%d \n", wlan_channel, Is40MHz));
11779
11780         if((curRxOkCnt+curTxOkCnt) > 1000)
11781         {
11782                 PSD_skip_start = (wlan_channel-1)*5 -Is40MHz*10;
11783                 PSD_skip_stop = PSD_skip_start + (1+Is40MHz)*20;
11784         }
11785
11786         RT_TRACE(COMP_PSD,DBG_LOUD,("PSD: Skip tone from %d to %d \n", PSD_skip_start, PSD_skip_stop));
11787
11788         for (n=0;n<80;n++)
11789         {
11790                 if((n%20)==0)
11791                 {
11792                         channel = (n/20)*4 + 1;
11793                         if(pDM_Odm->SupportICType == ODM_RTL8192D)
11794                         {
11795                                 switch(channel)
11796                                 {
11797                                         case 1:
11798                                         case 9:
11799                                                 group_idx = 0;
11800                                                 break;
11801                                         case 5:
11802                                                 group_idx = 2;
11803                                                 break;
11804                                         case 13:
11805                                                 group_idx = 1;
11806                                                 break;
11807                                 }
11808                                 if((*(pDM_Odm->pMacPhyMode)==ODM_SMSP)||(*(pDM_Odm->pMacPhyMode)==ODM_DMSP))
11809                 {
11810                                         for(i = 0; i < SYN_Length; i++)
11811                                                 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, SYN[i], bMaskDWord, SYN_group[group_idx][i]);
11812
11813                                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, 0x3FF, channel);
11814                                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_CHNLBW, 0x3FF, channel);
11815                                 }
11816                                 else  // DualMAC_DualPHY 2G
11817                         {
11818                                         for(i = 0; i < SYN_Length; i++)
11819                                                 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, SYN[i], bMaskDWord, SYN_group[group_idx][i]);
11820
11821                                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, 0x3FF, channel);
11822                                 }
11823                         }
11824                         else
11825                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, 0x3FF, channel);
11826                         }
11827                 tone_idx = n%20;
11828                 if ((n>=PSD_skip_start) && (n<PSD_skip_stop))
11829                 {
11830                         PSD_report[n] = initial_gain_psd;//SSBT;
11831                         ODM_RT_TRACE(pDM_Odm,COMP_PSD,DBG_LOUD,("PSD:Tone %d skipped \n", n));
11832                 }
11833                 else
11834                 {
11835                         PSD_report_tmp =  GetPSDData(pDM_Odm, idx[tone_idx], initial_gain_psd);
11836
11837                         if ( PSD_report_tmp > PSD_report[n])
11838                                 PSD_report[n] = PSD_report_tmp;
11839
11840                 }
11841         }
11842
11843         PatchDCTone(pDM_Odm, PSD_report, initial_gain_psd);
11844
11845        //----end
11846         //1 Turn on RX
11847         //Rx AGC on
11848         ODM_SetBBReg(pDM_Odm, 0xC70, BIT0, 1);
11849         ODM_SetBBReg(pDM_Odm, 0xC7C, BIT20, 1);
11850         //CCK on
11851         ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 1);
11852         //1 Turn on TX
11853         //Resume TX Queue
11854         ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0x00);
11855         //Turn on 3-wire
11856         ODM_SetBBReg(pDM_Odm, 0x88c, BIT20|BIT21|BIT22|BIT23, 0x0);
11857         //1 Restore Current Settings
11858         //Resume DIG
11859         pDM_Odm->bDMInitialGainEnable= TRUE;
11860         //ODM_SetBBReg(pDM_Odm, 0xc50, 0x7F, initial_gain);
11861         ODM_Write_DIG(pDM_Odm,(u1Byte) initial_gain);
11862         // restore originl center frequency
11863         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask, CurrentChannel);
11864         if(pDM_Odm->SupportICType == ODM_RTL8192D)
11865         {
11866                 if((*(pDM_Odm->pMacPhyMode)==ODM_SMSP)||(*(pDM_Odm->pMacPhyMode)==ODM_DMSP))
11867                 {
11868                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_CHNLBW, bMaskDWord, CurrentChannel);
11869                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x25, bMaskDWord, SYN_RF25);
11870                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x26, bMaskDWord, SYN_RF26);
11871                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x27, bMaskDWord, SYN_RF27);
11872                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x2B, bMaskDWord, SYN_RF2B);
11873                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x2C, bMaskDWord, SYN_RF2C);
11874                 }
11875                 else     // DualMAC_DualPHY
11876                 {
11877                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x25, bMaskDWord, SYN_RF25);
11878                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x26, bMaskDWord, SYN_RF26);
11879                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x27, bMaskDWord, SYN_RF27);
11880                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x2B, bMaskDWord, SYN_RF2B);
11881                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x2C, bMaskDWord, SYN_RF2C);
11882                 }
11883         }
11884         //Turn on CCA
11885         ODM_SetBBReg(pDM_Odm, 0xC14, bMaskDWord, RXIQI);
11886         //Restore RX idle low power
11887         if(RxIdleLowPwr == TRUE)
11888                 ODM_SetBBReg(pDM_Odm, 0x818, BIT28, 1);
11889
11890         psd_cnt++;
11891         //gPrint("psd cnt=%d\n", psd_cnt);
11892         ODM_RT_TRACE(pDM_Odm,COMP_PSD, DBG_LOUD,("PSD:psd_cnt = %d \n",psd_cnt));
11893         if (psd_cnt < ReScan)
11894         {
11895                 ODM_SetTimer(pDM_Odm, &pRX_HP_Table->PSDTimer, Interval);  //ms
11896         }
11897         else
11898                         {
11899                 psd_cnt = 0;
11900                 for(i=0;i<80;i++)
11901                         RT_TRACE(       COMP_PSD, DBG_LOUD,("psd_report[%d]=     %d \n", 2402+i, PSD_report[i]));
11902                         //DbgPrint("psd_report[%d]=     %d \n", 2402+i, PSD_report[i]);
11903
11904                 GoodChannelDecision(pDM_Odm, PSD_report, PSD_bitmap,RSSI_BT, PSD_bitmap_memory);
11905
11906                         }
11907                 }
11908
11909 VOID
11910 odm_PSD_RXHPCallback(
11911         PRT_TIMER               pTimer
11912 )
11913 {
11914         PADAPTER                Adapter = (PADAPTER)pTimer->Adapter;
11915         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
11916         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;
11917         pRXHP_T                 pRX_HP_Table  = &pDM_Odm->DM_RXHP_Table;
11918
11919 #if DEV_BUS_TYPE==RT_PCI_INTERFACE
11920         #if USE_WORKITEM
11921         ODM_ScheduleWorkItem(&pRX_HP_Table->PSDTimeWorkitem);
11922         #else
11923         odm_PSD_RXHP(pDM_Odm);
11924         #endif
11925 #else
11926         ODM_ScheduleWorkItem(&pRX_HP_Table->PSDTimeWorkitem);
11927 #endif
11928
11929         }
11930
11931 VOID
11932 odm_PSD_RXHPWorkitemCallback(
11933     IN PVOID            pContext
11934     )
11935 {
11936         PADAPTER        pAdapter = (PADAPTER)pContext;
11937         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);
11938         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;
11939
11940         odm_PSD_RXHP(pDM_Odm);
11941 }
11942
11943 #endif //#if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
11944
11945 VOID
11946 odm_PathDiversityInit(
11947         IN      PDM_ODM_T       pDM_Odm
11948 )
11949 {
11950         if(!(pDM_Odm->SupportAbility & ODM_BB_PATH_DIV))
11951         {
11952                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_PATH_DIV,ODM_DBG_LOUD,("Return: Not Support PathDiv\n"));
11953                 return;
11954         }
11955
11956 #if RTL8812A_SUPPORT
11957
11958         if(pDM_Odm->SupportICType & ODM_RTL8812)
11959                 ODM_PathDiversityInit_8812A(pDM_Odm);
11960 #endif
11961 }
11962
11963
11964 VOID
11965 odm_PathDiversity(
11966         IN      PDM_ODM_T       pDM_Odm
11967 )
11968 {
11969         if(!(pDM_Odm->SupportAbility & ODM_BB_PATH_DIV))
11970         {
11971                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_PATH_DIV,ODM_DBG_LOUD,("Return: Not Support PathDiv\n"));
11972                 return;
11973         }
11974
11975 #if RTL8812A_SUPPORT
11976
11977         if(pDM_Odm->SupportICType & ODM_RTL8812)
11978                 ODM_PathDiversity_8812A(pDM_Odm);
11979 #endif
11980 }
11981
11982
11983 //
11984 // 2011/12/02 MH Copy from MP oursrc for temporarily test.
11985 //
11986 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
11987 VOID
11988 odm_OFDMTXPathDiversity_92C(
11989         IN      PADAPTER        Adapter)
11990 {
11991 //      HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(Adapter);
11992         PMGNT_INFO              pMgntInfo = &(Adapter->MgntInfo);
11993         PRT_WLAN_STA    pEntry;
11994         u1Byte  i, DefaultRespPath = 0;
11995         s4Byte  MinRSSI = 0xFF;
11996         pPD_T   pDM_PDTable = &Adapter->DM_PDTable;
11997         pDM_PDTable->OFDMTXPath = 0;
11998
11999         //1 Default Port
12000         if(pMgntInfo->mAssoc)
12001         {
12002                 RT_TRACE(       COMP_SWAS, DBG_LOUD, ("odm_OFDMTXPathDiversity_92C: Default port RSSI[0]=%d, RSSI[1]=%d\n",
12003                         Adapter->RxStats.RxRSSIPercentage[0], Adapter->RxStats.RxRSSIPercentage[1]));
12004                 if(Adapter->RxStats.RxRSSIPercentage[0] > Adapter->RxStats.RxRSSIPercentage[1])
12005                 {
12006                         pDM_PDTable->OFDMTXPath = pDM_PDTable->OFDMTXPath & (~BIT0);
12007                         MinRSSI =  Adapter->RxStats.RxRSSIPercentage[1];
12008                         DefaultRespPath = 0;
12009                         RT_TRACE(       COMP_SWAS, DBG_LOUD, ("odm_OFDMTXPathDiversity_92C: Default port Select Path-0\n"));
12010                 }
12011                 else
12012                 {
12013                         pDM_PDTable->OFDMTXPath =  pDM_PDTable->OFDMTXPath | BIT0;
12014                         MinRSSI =  Adapter->RxStats.RxRSSIPercentage[0];
12015                         DefaultRespPath = 1;
12016                         RT_TRACE(       COMP_SWAS, DBG_LOUD, ("odm_OFDMTXPathDiversity_92C: Default port Select Path-1\n"));
12017                 }
12018                 //RT_TRACE(     COMP_SWAS, DBG_LOUD, ("pDM_PDTable->OFDMTXPath =0x%x\n",pDM_PDTable->OFDMTXPath));
12019         }
12020         //1 Extension Port
12021         for(i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++)
12022         {
12023                 if(IsAPModeExist(Adapter)  && GetFirstExtAdapter(Adapter) != NULL)
12024                         pEntry = AsocEntry_EnumStation(GetFirstExtAdapter(Adapter), i);
12025                 else
12026                         pEntry = AsocEntry_EnumStation(GetDefaultAdapter(Adapter), i);
12027
12028                 if(pEntry!=NULL)
12029                 {
12030                         if(pEntry->bAssociated)
12031                         {
12032                                 RT_TRACE(       COMP_SWAS, DBG_LOUD, ("odm_OFDMTXPathDiversity_92C: MACID=%d, RSSI_0=%d, RSSI_1=%d\n",
12033                                         pEntry->AssociatedMacId, pEntry->rssi_stat.RxRSSIPercentage[0], pEntry->rssi_stat.RxRSSIPercentage[1]));
12034
12035                                 if(pEntry->rssi_stat.RxRSSIPercentage[0] > pEntry->rssi_stat.RxRSSIPercentage[1])
12036                                 {
12037                                         pDM_PDTable->OFDMTXPath = pDM_PDTable->OFDMTXPath & ~(BIT(pEntry->AssociatedMacId));
12038                                         //pHalData->TXPath = pHalData->TXPath & ~(1<<(pEntry->AssociatedMacId));
12039                                         RT_TRACE(       COMP_SWAS, DBG_LOUD, ("odm_OFDMTXPathDiversity_92C: MACID=%d Select Path-0\n", pEntry->AssociatedMacId));
12040                                         if(pEntry->rssi_stat.RxRSSIPercentage[1] < MinRSSI)
12041                                         {
12042                                                 MinRSSI = pEntry->rssi_stat.RxRSSIPercentage[1];
12043                                                 DefaultRespPath = 0;
12044                                         }
12045                                 }
12046                                 else
12047                                 {
12048                                         pDM_PDTable->OFDMTXPath = pDM_PDTable->OFDMTXPath | BIT(pEntry->AssociatedMacId);
12049                                         //pHalData->TXPath = pHalData->TXPath | (1 << (pEntry->AssociatedMacId));
12050                                         RT_TRACE(       COMP_SWAS, DBG_LOUD, ("odm_OFDMTXPathDiversity_92C: MACID=%d Select Path-1\n", pEntry->AssociatedMacId));
12051                                         if(pEntry->rssi_stat.RxRSSIPercentage[0] < MinRSSI)
12052                                         {
12053                                                 MinRSSI = pEntry->rssi_stat.RxRSSIPercentage[0];
12054                                                 DefaultRespPath = 1;
12055                                         }
12056                                 }
12057                         }
12058                 }
12059                 else
12060                 {
12061                         break;
12062                 }
12063         }
12064
12065         pDM_PDTable->OFDMDefaultRespPath = DefaultRespPath;
12066 }
12067
12068
12069 BOOLEAN
12070 odm_IsConnected_92C(
12071         IN      PADAPTER        Adapter
12072 )
12073 {
12074         PRT_WLAN_STA    pEntry;
12075         PMGNT_INFO              pMgntInfo = &(Adapter->MgntInfo);
12076         u4Byte          i;
12077         BOOLEAN         bConnected=FALSE;
12078
12079         if(pMgntInfo->mAssoc)
12080         {
12081                 bConnected = TRUE;
12082         }
12083         else
12084         {
12085                 for(i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++)
12086                 {
12087                         if(IsAPModeExist(Adapter)  && GetFirstExtAdapter(Adapter) != NULL)
12088                                 pEntry = AsocEntry_EnumStation(GetFirstExtAdapter(Adapter), i);
12089                         else
12090                                 pEntry = AsocEntry_EnumStation(GetDefaultAdapter(Adapter), i);
12091
12092                         if(pEntry!=NULL)
12093                         {
12094                                 if(pEntry->bAssociated)
12095                                 {
12096                                         bConnected = TRUE;
12097                                         break;
12098                                 }
12099                         }
12100                         else
12101                         {
12102                                 break;
12103                         }
12104                 }
12105         }
12106         return  bConnected;
12107 }
12108
12109
12110 VOID
12111 odm_ResetPathDiversity_92C(
12112                 IN      PADAPTER        Adapter
12113 )
12114 {
12115         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
12116         pPD_T   pDM_PDTable = &Adapter->DM_PDTable;
12117         PRT_WLAN_STA    pEntry;
12118         u4Byte  i,j;
12119
12120         pHalData->RSSI_test = FALSE;
12121         pDM_PDTable->CCK_Pkt_Cnt = 0;
12122         pDM_PDTable->OFDM_Pkt_Cnt = 0;
12123         pHalData->CCK_Pkt_Cnt =0;
12124         pHalData->OFDM_Pkt_Cnt =0;
12125
12126         if(pDM_PDTable->CCKPathDivEnable == TRUE)
12127                 PHY_SetBBReg(Adapter, rCCK0_AFESetting  , 0x0F000000, 0x01); //RX path = PathAB
12128
12129         for(i=0; i<2; i++)
12130         {
12131                 pDM_PDTable->RSSI_CCK_Path_cnt[i]=0;
12132                 pDM_PDTable->RSSI_CCK_Path[i] = 0;
12133         }
12134         for(i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++)
12135         {
12136                 if(IsAPModeExist(Adapter)  && GetFirstExtAdapter(Adapter) != NULL)
12137                         pEntry = AsocEntry_EnumStation(GetFirstExtAdapter(Adapter), i);
12138                 else
12139                         pEntry = AsocEntry_EnumStation(GetDefaultAdapter(Adapter), i);
12140
12141                 if(pEntry!=NULL)
12142                 {
12143                         pEntry->rssi_stat.CCK_Pkt_Cnt = 0;
12144                         pEntry->rssi_stat.OFDM_Pkt_Cnt = 0;
12145                         for(j=0; j<2; j++)
12146                         {
12147                                 pEntry->rssi_stat.RSSI_CCK_Path_cnt[j] = 0;
12148                                 pEntry->rssi_stat.RSSI_CCK_Path[j] = 0;
12149                         }
12150                 }
12151                 else
12152                         break;
12153         }
12154 }
12155
12156
12157 VOID
12158 odm_CCKTXPathDiversity_92C(
12159         IN      PADAPTER        Adapter
12160 )
12161 {
12162         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(Adapter);
12163         PMGNT_INFO              pMgntInfo = &(Adapter->MgntInfo);
12164         PRT_WLAN_STA    pEntry;
12165         s4Byte  MinRSSI = 0xFF;
12166         u1Byte  i, DefaultRespPath = 0;
12167 //      BOOLEAN bBModePathDiv = FALSE;
12168         pPD_T   pDM_PDTable = &Adapter->DM_PDTable;
12169
12170         //1 Default Port
12171         if(pMgntInfo->mAssoc)
12172         {
12173                 if(pHalData->OFDM_Pkt_Cnt == 0)
12174                 {
12175                         for(i=0; i<2; i++)
12176                         {
12177                                 if(pDM_PDTable->RSSI_CCK_Path_cnt[i] > 1) //Because the first packet is discarded
12178                                         pDM_PDTable->RSSI_CCK_Path[i] = pDM_PDTable->RSSI_CCK_Path[i] / (pDM_PDTable->RSSI_CCK_Path_cnt[i]-1);
12179                                 else
12180                                         pDM_PDTable->RSSI_CCK_Path[i] = 0;
12181                         }
12182                         RT_TRACE(       COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: pDM_PDTable->RSSI_CCK_Path[0]=%d, pDM_PDTable->RSSI_CCK_Path[1]=%d\n",
12183                                 pDM_PDTable->RSSI_CCK_Path[0], pDM_PDTable->RSSI_CCK_Path[1]));
12184                         RT_TRACE(       COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: pDM_PDTable->RSSI_CCK_Path_cnt[0]=%d, pDM_PDTable->RSSI_CCK_Path_cnt[1]=%d\n",
12185                                 pDM_PDTable->RSSI_CCK_Path_cnt[0], pDM_PDTable->RSSI_CCK_Path_cnt[1]));
12186
12187                         if(pDM_PDTable->RSSI_CCK_Path[0] > pDM_PDTable->RSSI_CCK_Path[1])
12188                         {
12189                                 pDM_PDTable->CCKTXPath = pDM_PDTable->CCKTXPath & (~BIT0);
12190                                 MinRSSI =  pDM_PDTable->RSSI_CCK_Path[1];
12191                                 DefaultRespPath = 0;
12192                                 RT_TRACE(       COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: Default port Select CCK Path-0\n"));
12193                         }
12194                         else if(pDM_PDTable->RSSI_CCK_Path[0] < pDM_PDTable->RSSI_CCK_Path[1])
12195                         {
12196                                 pDM_PDTable->CCKTXPath =  pDM_PDTable->CCKTXPath | BIT0;
12197                                 MinRSSI =  pDM_PDTable->RSSI_CCK_Path[0];
12198                                 DefaultRespPath = 1;
12199                                 RT_TRACE(       COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: Default port Select CCK Path-1\n"));
12200                         }
12201                         else
12202                         {
12203                                 if((pDM_PDTable->RSSI_CCK_Path[0] != 0) && (pDM_PDTable->RSSI_CCK_Path[0] < MinRSSI))
12204                                 {
12205                                         pDM_PDTable->CCKTXPath = pDM_PDTable->CCKTXPath & (~BIT0);
12206                                         RT_TRACE(       COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: Default port Select CCK Path-0\n"));
12207                                         MinRSSI =  pDM_PDTable->RSSI_CCK_Path[1];
12208                                         DefaultRespPath = 0;
12209                                 }
12210                                 else
12211                                 {
12212                                         RT_TRACE(       COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: Default port unchange CCK Path\n"));
12213                                 }
12214                         }
12215                 }
12216                 else //Follow OFDM decision
12217                 {
12218                         pDM_PDTable->CCKTXPath = (pDM_PDTable->CCKTXPath & (~BIT0)) | (pDM_PDTable->OFDMTXPath &BIT0);
12219                         RT_TRACE(       COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: Follow OFDM decision, Default port Select CCK Path-%d\n",
12220                                 pDM_PDTable->CCKTXPath &BIT0));
12221                 }
12222         }
12223         //1 Extension Port
12224         for(i = 0; i < ODM_ASSOCIATE_ENTRY_NUM; i++)
12225         {
12226                 if(IsAPModeExist(Adapter)  && GetFirstExtAdapter(Adapter) != NULL)
12227                         pEntry = AsocEntry_EnumStation(GetFirstExtAdapter(Adapter), i);
12228                 else
12229                         pEntry = AsocEntry_EnumStation(GetDefaultAdapter(Adapter), i);
12230
12231                 if(pEntry!=NULL)
12232                 {
12233                         if(pEntry->bAssociated)
12234                         {
12235                                 if(pEntry->rssi_stat.OFDM_Pkt_Cnt == 0)
12236                                 {
12237                                         u1Byte j=0;
12238                                         for(j=0; j<2; j++)
12239                                         {
12240                                                 if(pEntry->rssi_stat.RSSI_CCK_Path_cnt[j] > 1)
12241                                                         pEntry->rssi_stat.RSSI_CCK_Path[j] = pEntry->rssi_stat.RSSI_CCK_Path[j] / (pEntry->rssi_stat.RSSI_CCK_Path_cnt[j]-1);
12242                                                 else
12243                                                         pEntry->rssi_stat.RSSI_CCK_Path[j] = 0;
12244                                         }
12245                                         RT_TRACE(       COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: MACID=%d, RSSI_CCK0=%d, RSSI_CCK1=%d\n",
12246                                                 pEntry->AssociatedMacId, pEntry->rssi_stat.RSSI_CCK_Path[0], pEntry->rssi_stat.RSSI_CCK_Path[1]));
12247
12248                                         if(pEntry->rssi_stat.RSSI_CCK_Path[0] >pEntry->rssi_stat.RSSI_CCK_Path[1])
12249                                         {
12250                                                 pDM_PDTable->CCKTXPath = pDM_PDTable->CCKTXPath & ~(BIT(pEntry->AssociatedMacId));
12251                                                 RT_TRACE(       COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: MACID=%d Select CCK Path-0\n", pEntry->AssociatedMacId));
12252                                                 if(pEntry->rssi_stat.RSSI_CCK_Path[1] < MinRSSI)
12253                                                 {
12254                                                         MinRSSI = pEntry->rssi_stat.RSSI_CCK_Path[1];
12255                                                         DefaultRespPath = 0;
12256                                                 }
12257                                         }
12258                                         else if(pEntry->rssi_stat.RSSI_CCK_Path[0] <pEntry->rssi_stat.RSSI_CCK_Path[1])
12259                                         {
12260                                                 pDM_PDTable->CCKTXPath = pDM_PDTable->CCKTXPath | BIT(pEntry->AssociatedMacId);
12261                                                 RT_TRACE(       COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: MACID=%d Select CCK Path-1\n", pEntry->AssociatedMacId));
12262                                                 if(pEntry->rssi_stat.RSSI_CCK_Path[0] < MinRSSI)
12263                                                 {
12264                                                         MinRSSI = pEntry->rssi_stat.RSSI_CCK_Path[0];
12265                                                         DefaultRespPath = 1;
12266                                                 }
12267                                         }
12268                                         else
12269                                         {
12270                                                 if((pEntry->rssi_stat.RSSI_CCK_Path[0] != 0) && (pEntry->rssi_stat.RSSI_CCK_Path[0] < MinRSSI))
12271                                                 {
12272                                                         pDM_PDTable->CCKTXPath = pDM_PDTable->CCKTXPath & ~(BIT(pEntry->AssociatedMacId));
12273                                                         MinRSSI = pEntry->rssi_stat.RSSI_CCK_Path[1];
12274                                                         DefaultRespPath = 0;
12275                                                         RT_TRACE(       COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: MACID=%d Select CCK Path-0\n", pEntry->AssociatedMacId));
12276                                                 }
12277                                                 else
12278                                                 {
12279                                                         RT_TRACE(       COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: MACID=%d unchange CCK Path\n", pEntry->AssociatedMacId));
12280                                                 }
12281                                         }
12282                                 }
12283                                 else //Follow OFDM decision
12284                                 {
12285                                         pDM_PDTable->CCKTXPath = (pDM_PDTable->CCKTXPath & (~(BIT(pEntry->AssociatedMacId)))) | (pDM_PDTable->OFDMTXPath & BIT(pEntry->AssociatedMacId));
12286                                         RT_TRACE(       COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: Follow OFDM decision, MACID=%d Select CCK Path-%d\n",
12287                                                 pEntry->AssociatedMacId, (pDM_PDTable->CCKTXPath & BIT(pEntry->AssociatedMacId))>>(pEntry->AssociatedMacId)));
12288                                 }
12289                         }
12290                 }
12291                 else
12292                 {
12293                         break;
12294                 }
12295         }
12296
12297         RT_TRACE(       COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C:MinRSSI=%d\n",MinRSSI));
12298
12299         if(MinRSSI == 0xFF)
12300                 DefaultRespPath = pDM_PDTable->CCKDefaultRespPath;
12301
12302         pDM_PDTable->CCKDefaultRespPath = DefaultRespPath;
12303 }
12304
12305
12306
12307 VOID
12308 odm_PathDiversityAfterLink_92C(
12309         IN      PADAPTER        Adapter
12310 )
12311 {
12312         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(Adapter);
12313         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;
12314         pPD_T           pDM_PDTable = &Adapter->DM_PDTable;
12315         u1Byte          DefaultRespPath=0;
12316
12317         if((!IS_92C_SERIAL(pHalData->VersionID)) || (pHalData->PathDivCfg != 1) || (pHalData->eRFPowerState == eRfOff))
12318         {
12319                 if(pHalData->PathDivCfg == 0)
12320                 {
12321                         RT_TRACE(       COMP_SWAS, DBG_LOUD, ("No ODM_TXPathDiversity()\n"));
12322                 }
12323                 else
12324                 {
12325                         RT_TRACE(       COMP_SWAS, DBG_LOUD, ("2T ODM_TXPathDiversity()\n"));
12326                 }
12327                 return;
12328         }
12329         if(!odm_IsConnected_92C(Adapter))
12330         {
12331                 RT_TRACE(       COMP_SWAS, DBG_LOUD, ("ODM_TXPathDiversity(): No Connections\n"));
12332                 return;
12333         }
12334
12335
12336         if(pDM_PDTable->TrainingState == 0)
12337         {
12338                 RT_TRACE(       COMP_SWAS, DBG_LOUD, ("ODM_TXPathDiversity() ==>\n"));
12339                 odm_OFDMTXPathDiversity_92C(Adapter);
12340
12341                 if((pDM_PDTable->CCKPathDivEnable == TRUE) && (pDM_PDTable->OFDM_Pkt_Cnt < 100))
12342                 {
12343                         //RT_TRACE(     COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: TrainingState=0\n"));
12344
12345                         if(pDM_PDTable->CCK_Pkt_Cnt > 300)
12346                                 pDM_PDTable->Timer = 20;
12347                         else if(pDM_PDTable->CCK_Pkt_Cnt > 100)
12348                                 pDM_PDTable->Timer = 60;
12349                         else
12350                                 pDM_PDTable->Timer = 250;
12351                         RT_TRACE(       COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: timer=%d\n",pDM_PDTable->Timer));
12352
12353                         PHY_SetBBReg(Adapter, rCCK0_AFESetting  , 0x0F000000, 0x00); // RX path = PathA
12354                         pDM_PDTable->TrainingState = 1;
12355                         pHalData->RSSI_test = TRUE;
12356                         ODM_SetTimer( pDM_Odm, &pDM_Odm->CCKPathDiversityTimer, pDM_PDTable->Timer); //ms
12357                 }
12358                 else
12359                 {
12360                         pDM_PDTable->CCKTXPath = pDM_PDTable->OFDMTXPath;
12361                         DefaultRespPath = pDM_PDTable->OFDMDefaultRespPath;
12362                         RT_TRACE(       COMP_SWAS, DBG_LOUD, ("odm_SetRespPath_92C: Skip odm_CCKTXPathDiversity_92C, DefaultRespPath is OFDM\n"));
12363                         odm_SetRespPath_92C(Adapter, DefaultRespPath);
12364                         odm_ResetPathDiversity_92C(Adapter);
12365                         RT_TRACE(       COMP_SWAS, DBG_LOUD, ("ODM_TXPathDiversity() <==\n"));
12366                 }
12367         }
12368         else if(pDM_PDTable->TrainingState == 1)
12369         {
12370                 //RT_TRACE(     COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: TrainingState=1\n"));
12371                 PHY_SetBBReg(Adapter, rCCK0_AFESetting  , 0x0F000000, 0x05); // RX path = PathB
12372                 pDM_PDTable->TrainingState = 2;
12373                 ODM_SetTimer( pDM_Odm, &pDM_Odm->CCKPathDiversityTimer, pDM_PDTable->Timer); //ms
12374         }
12375         else
12376         {
12377                 //RT_TRACE(     COMP_SWAS, DBG_LOUD, ("odm_CCKTXPathDiversity_92C: TrainingState=2\n"));
12378                 pDM_PDTable->TrainingState = 0;
12379                 odm_CCKTXPathDiversity_92C(Adapter);
12380                 if(pDM_PDTable->OFDM_Pkt_Cnt != 0)
12381                 {
12382                         DefaultRespPath = pDM_PDTable->OFDMDefaultRespPath;
12383                         RT_TRACE(       COMP_SWAS, DBG_LOUD, ("odm_SetRespPath_92C: DefaultRespPath is OFDM\n"));
12384                 }
12385                 else
12386                 {
12387                         DefaultRespPath = pDM_PDTable->CCKDefaultRespPath;
12388                         RT_TRACE(       COMP_SWAS, DBG_LOUD, ("odm_SetRespPath_92C: DefaultRespPath is CCK\n"));
12389                 }
12390                 odm_SetRespPath_92C(Adapter, DefaultRespPath);
12391                 odm_ResetPathDiversity_92C(Adapter);
12392                 RT_TRACE(       COMP_SWAS, DBG_LOUD, ("ODM_TXPathDiversity() <==\n"));
12393         }
12394
12395 }
12396
12397
12398
12399 VOID
12400 odm_CCKTXPathDiversityCallback(
12401         PRT_TIMER               pTimer
12402 )
12403 {
12404 #if USE_WORKITEM
12405        PADAPTER Adapter = (PADAPTER)pTimer->Adapter;
12406        HAL_DATA_TYPE    *pHalData = GET_HAL_DATA(Adapter);
12407            PDM_ODM_T            pDM_Odm = &pHalData->DM_OutSrc;
12408 #else
12409         PADAPTER        Adapter = (PADAPTER)pTimer->Adapter;
12410 #endif
12411
12412 #if DEV_BUS_TYPE==RT_PCI_INTERFACE
12413 #if USE_WORKITEM
12414         PlatformScheduleWorkItem(&pDM_Odm->CCKPathDiversityWorkitem);
12415 #else
12416         odm_PathDiversityAfterLink_92C(Adapter);
12417 #endif
12418 #else
12419         PlatformScheduleWorkItem(&pDM_Odm->CCKPathDiversityWorkitem);
12420 #endif
12421
12422 }
12423
12424
12425 VOID
12426 odm_CCKTXPathDiversityWorkItemCallback(
12427     IN PVOID            pContext
12428     )
12429 {
12430         PADAPTER        Adapter = (PADAPTER)pContext;
12431
12432         odm_CCKTXPathDiversity_92C(Adapter);
12433 }
12434
12435
12436 VOID
12437 ODM_CCKPathDiversityChkPerPktRssi(
12438         PADAPTER                Adapter,
12439         BOOLEAN                 bIsDefPort,
12440         BOOLEAN                 bMatchBSSID,
12441         PRT_WLAN_STA    pEntry,
12442         PRT_RFD                 pRfd,
12443         pu1Byte                 pDesc
12444         )
12445 {
12446         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
12447         BOOLEAN                 bCount = FALSE;
12448         pPD_T   pDM_PDTable = &Adapter->DM_PDTable;
12449         //BOOLEAN       isCCKrate = RX_HAL_IS_CCK_RATE_92C(pDesc);
12450 #if DEV_BUS_TYPE != RT_SDIO_INTERFACE
12451         BOOLEAN isCCKrate = RX_HAL_IS_CCK_RATE(Adapter, pDesc);
12452 #else  //below code would be removed if we have verified SDIO
12453         BOOLEAN isCCKrate = IS_HARDWARE_TYPE_8188E(Adapter) ? RX_HAL_IS_CCK_RATE_88E(pDesc) : RX_HAL_IS_CCK_RATE_92C(pDesc);
12454 #endif
12455
12456         if((pHalData->PathDivCfg != 1) || (pHalData->RSSI_test == FALSE))
12457                 return;
12458
12459         if(pHalData->RSSI_target==NULL && bIsDefPort && bMatchBSSID)
12460                 bCount = TRUE;
12461         else if(pHalData->RSSI_target!=NULL && pEntry!=NULL && pHalData->RSSI_target==pEntry)
12462                 bCount = TRUE;
12463
12464         if(bCount && isCCKrate)
12465         {
12466                 if(pDM_PDTable->TrainingState == 1 )
12467                 {
12468                         if(pEntry)
12469                         {
12470                                 if(pEntry->rssi_stat.RSSI_CCK_Path_cnt[0] != 0)
12471                                         pEntry->rssi_stat.RSSI_CCK_Path[0] += pRfd->Status.RxPWDBAll;
12472                                 pEntry->rssi_stat.RSSI_CCK_Path_cnt[0]++;
12473                         }
12474                         else
12475                         {
12476                                 if(pDM_PDTable->RSSI_CCK_Path_cnt[0] != 0)
12477                                         pDM_PDTable->RSSI_CCK_Path[0] += pRfd->Status.RxPWDBAll;
12478                                 pDM_PDTable->RSSI_CCK_Path_cnt[0]++;
12479                         }
12480                 }
12481                 else if(pDM_PDTable->TrainingState == 2 )
12482                 {
12483                         if(pEntry)
12484                         {
12485                                 if(pEntry->rssi_stat.RSSI_CCK_Path_cnt[1] != 0)
12486                                         pEntry->rssi_stat.RSSI_CCK_Path[1] += pRfd->Status.RxPWDBAll;
12487                                 pEntry->rssi_stat.RSSI_CCK_Path_cnt[1]++;
12488                         }
12489                         else
12490                         {
12491                                 if(pDM_PDTable->RSSI_CCK_Path_cnt[1] != 0)
12492                                         pDM_PDTable->RSSI_CCK_Path[1] += pRfd->Status.RxPWDBAll;
12493                                 pDM_PDTable->RSSI_CCK_Path_cnt[1]++;
12494                         }
12495                 }
12496         }
12497 }
12498
12499
12500 BOOLEAN
12501 ODM_PathDiversityBeforeLink92C(
12502         //IN    PADAPTER        Adapter
12503         IN              PDM_ODM_T               pDM_Odm
12504         )
12505 {
12506 #if (RT_MEM_SIZE_LEVEL != RT_MEM_SIZE_MINIMUM)
12507         PADAPTER                Adapter = pDM_Odm->Adapter;
12508         HAL_DATA_TYPE*  pHalData = NULL;
12509         PMGNT_INFO              pMgntInfo = NULL;
12510         //pSWAT_T               pDM_SWAT_Table = &Adapter->DM_SWAT_Table;
12511         pPD_T                   pDM_PDTable = NULL;
12512
12513         s1Byte                  Score = 0;
12514         PRT_WLAN_BSS    pTmpBssDesc;
12515         PRT_WLAN_BSS    pTestBssDesc;
12516
12517         u1Byte                  target_chnl = 0;
12518         u1Byte                  index;
12519
12520         if (pDM_Odm->Adapter == NULL)  //For BSOD when plug/unplug fast.  //By YJ,120413
12521         {       // The ODM structure is not initialized.
12522                 return FALSE;
12523         }
12524         pHalData = GET_HAL_DATA(Adapter);
12525         pMgntInfo = &Adapter->MgntInfo;
12526         pDM_PDTable = &Adapter->DM_PDTable;
12527
12528         // Condition that does not need to use path diversity.
12529         if((!IS_92C_SERIAL(pHalData->VersionID)) || (pHalData->PathDivCfg!=1) || pMgntInfo->AntennaTest )
12530         {
12531                 RT_TRACE(COMP_SWAS, DBG_LOUD,
12532                                 ("ODM_PathDiversityBeforeLink92C(): No PathDiv Mechanism before link.\n"));
12533                 return FALSE;
12534         }
12535
12536         // Since driver is going to set BB register, it shall check if there is another thread controlling BB/RF.
12537         PlatformAcquireSpinLock(Adapter, RT_RF_STATE_SPINLOCK);
12538         if(pHalData->eRFPowerState!=eRfOn || pMgntInfo->RFChangeInProgress || pMgntInfo->bMediaConnect)
12539         {
12540                 PlatformReleaseSpinLock(Adapter, RT_RF_STATE_SPINLOCK);
12541
12542                 RT_TRACE(COMP_SWAS, DBG_LOUD,
12543                                 ("ODM_PathDiversityBeforeLink92C(): RFChangeInProgress(%x), eRFPowerState(%x)\n",
12544                                 pMgntInfo->RFChangeInProgress,
12545                                 pHalData->eRFPowerState));
12546
12547                 //pDM_SWAT_Table->SWAS_NoLink_State = 0;
12548                 pDM_PDTable->PathDiv_NoLink_State = 0;
12549
12550                 return FALSE;
12551         }
12552         else
12553         {
12554                 PlatformReleaseSpinLock(Adapter, RT_RF_STATE_SPINLOCK);
12555         }
12556
12557         //1 Run AntDiv mechanism "Before Link" part.
12558         //if(pDM_SWAT_Table->SWAS_NoLink_State == 0)
12559         if(pDM_PDTable->PathDiv_NoLink_State == 0)
12560         {
12561                 //1 Prepare to do Scan again to check current antenna state.
12562
12563                 // Set check state to next step.
12564                 //pDM_SWAT_Table->SWAS_NoLink_State = 1;
12565                 pDM_PDTable->PathDiv_NoLink_State = 1;
12566
12567                 // Copy Current Scan list.
12568                 Adapter->MgntInfo.tmpNumBssDesc = pMgntInfo->NumBssDesc;
12569                 PlatformMoveMemory((PVOID)Adapter->MgntInfo.tmpbssDesc, (PVOID)pMgntInfo->bssDesc, sizeof(RT_WLAN_BSS)*MAX_BSS_DESC);
12570
12571                 // Switch Antenna to another one.
12572                 if(pDM_PDTable->DefaultRespPath == 0)
12573                 {
12574                         PHY_SetBBReg(Adapter, rCCK0_AFESetting  , 0x0F000000, 0x05); // TRX path = PathB
12575                         odm_SetRespPath_92C(Adapter, 1);
12576                         pDM_PDTable->OFDMTXPath = 0xFFFFFFFF;
12577                         pDM_PDTable->CCKTXPath = 0xFFFFFFFF;
12578                 }
12579                 else
12580                 {
12581                         PHY_SetBBReg(Adapter, rCCK0_AFESetting  , 0x0F000000, 0x00); // TRX path = PathA
12582                         odm_SetRespPath_92C(Adapter, 0);
12583                         pDM_PDTable->OFDMTXPath = 0x0;
12584                         pDM_PDTable->CCKTXPath = 0x0;
12585                 }
12586 #if 0
12587
12588                 pDM_SWAT_Table->PreAntenna = pDM_SWAT_Table->CurAntenna;
12589                 pDM_SWAT_Table->CurAntenna = (pDM_SWAT_Table->CurAntenna==Antenna_A)?Antenna_B:Antenna_A;
12590
12591                 RT_TRACE(COMP_SWAS, DBG_LOUD,
12592                         ("ODM_SwAntDivCheckBeforeLink: Change to Ant(%s) for testing.\n", (pDM_SWAT_Table->CurAntenna==Antenna_A)?"A":"B"));
12593                 //PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, 0x300, DM_SWAT_Table.CurAntenna);
12594                 pDM_SWAT_Table->SWAS_NoLink_BK_Reg860 = ((pDM_SWAT_Table->SWAS_NoLink_BK_Reg860 & 0xfffffcff) | (pDM_SWAT_Table->CurAntenna<<8));
12595                 PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, bMaskDWord, pDM_SWAT_Table->SWAS_NoLink_BK_Reg860);
12596 #endif
12597
12598                 // Go back to scan function again.
12599                 RT_TRACE(COMP_SWAS, DBG_LOUD, ("ODM_PathDiversityBeforeLink92C: Scan one more time\n"));
12600                 pMgntInfo->ScanStep=0;
12601                 target_chnl = odm_SwAntDivSelectScanChnl(Adapter);
12602                 odm_SwAntDivConstructScanChnl(Adapter, target_chnl);
12603                 PlatformSetTimer(Adapter, &pMgntInfo->ScanTimer, 5);
12604
12605                 return TRUE;
12606         }
12607         else
12608         {
12609                 //1 ScanComple() is called after antenna swiched.
12610                 //1 Check scan result and determine which antenna is going
12611                 //1 to be used.
12612
12613                 for(index=0; index<Adapter->MgntInfo.tmpNumBssDesc; index++)
12614                 {
12615                         pTmpBssDesc = &(Adapter->MgntInfo.tmpbssDesc[index]);
12616                         pTestBssDesc = &(pMgntInfo->bssDesc[index]);
12617
12618                         if(PlatformCompareMemory(pTestBssDesc->bdBssIdBuf, pTmpBssDesc->bdBssIdBuf, 6)!=0)
12619                         {
12620                                 RT_TRACE(COMP_SWAS, DBG_LOUD, ("ODM_PathDiversityBeforeLink92C(): ERROR!! This shall not happen.\n"));
12621                                 continue;
12622                         }
12623
12624                         if(pTmpBssDesc->RecvSignalPower > pTestBssDesc->RecvSignalPower)
12625                         {
12626                                 RT_TRACE(COMP_SWAS, DBG_LOUD, ("ODM_PathDiversityBeforeLink92C: Compare scan entry: Score++\n"));
12627                                 RT_PRINT_STR(COMP_SWAS, DBG_LOUD, "SSID: ", pTestBssDesc->bdSsIdBuf, pTestBssDesc->bdSsIdLen);
12628                                 RT_TRACE(COMP_SWAS, DBG_LOUD, ("Original: %d, Test: %d\n", pTmpBssDesc->RecvSignalPower, pTestBssDesc->RecvSignalPower));
12629
12630                                 Score++;
12631                                 PlatformMoveMemory(pTestBssDesc, pTmpBssDesc, sizeof(RT_WLAN_BSS));
12632                         }
12633                         else if(pTmpBssDesc->RecvSignalPower < pTestBssDesc->RecvSignalPower)
12634                         {
12635                                 RT_TRACE(COMP_SWAS, DBG_LOUD, ("ODM_PathDiversityBeforeLink92C: Compare scan entry: Score--\n"));
12636                                 RT_PRINT_STR(COMP_SWAS, DBG_LOUD, "SSID: ", pTestBssDesc->bdSsIdBuf, pTestBssDesc->bdSsIdLen);
12637                                 RT_TRACE(COMP_SWAS, DBG_LOUD, ("Original: %d, Test: %d\n", pTmpBssDesc->RecvSignalPower, pTestBssDesc->RecvSignalPower));
12638                                 Score--;
12639                         }
12640
12641                 }
12642
12643                 if(pMgntInfo->NumBssDesc!=0 && Score<=0)
12644                 {
12645                         RT_TRACE(COMP_SWAS, DBG_LOUD,
12646                                 ("ODM_PathDiversityBeforeLink92C(): DefaultRespPath=%d\n", pDM_PDTable->DefaultRespPath));
12647
12648                         //pDM_SWAT_Table->PreAntenna = pDM_SWAT_Table->CurAntenna;
12649                 }
12650                 else
12651                 {
12652                         RT_TRACE(COMP_SWAS, DBG_LOUD,
12653                                 ("ODM_PathDiversityBeforeLink92C(): DefaultRespPath=%d\n", pDM_PDTable->DefaultRespPath));
12654
12655                         if(pDM_PDTable->DefaultRespPath == 0)
12656                         {
12657                                 pDM_PDTable->OFDMTXPath = 0xFFFFFFFF;
12658                                 pDM_PDTable->CCKTXPath = 0xFFFFFFFF;
12659                                 odm_SetRespPath_92C(Adapter, 1);
12660                         }
12661                         else
12662                         {
12663                                 pDM_PDTable->OFDMTXPath = 0x0;
12664                                 pDM_PDTable->CCKTXPath = 0x0;
12665                                 odm_SetRespPath_92C(Adapter, 0);
12666                         }
12667                         PHY_SetBBReg(Adapter, rCCK0_AFESetting  , 0x0F000000, 0x01); // RX path = PathAB
12668
12669                         //pDM_SWAT_Table->CurAntenna = pDM_SWAT_Table->PreAntenna;
12670
12671                         //PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, 0x300, DM_SWAT_Table.CurAntenna);
12672                         //pDM_SWAT_Table->SWAS_NoLink_BK_Reg860 = ((pDM_SWAT_Table->SWAS_NoLink_BK_Reg860 & 0xfffffcff) | (pDM_SWAT_Table->CurAntenna<<8));
12673                         //PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, bMaskDWord, pDM_SWAT_Table->SWAS_NoLink_BK_Reg860);
12674                 }
12675
12676                 // Check state reset to default and wait for next time.
12677                 //pDM_SWAT_Table->SWAS_NoLink_State = 0;
12678                 pDM_PDTable->PathDiv_NoLink_State = 0;
12679
12680                 return FALSE;
12681         }
12682 #else
12683                 return  FALSE;
12684 #endif
12685
12686 }
12687
12688
12689 //Neil Chen---2011--06--22
12690 //----92D Path Diversity----//
12691 //#ifdef PathDiv92D
12692 //==================================
12693 //3 Path Diversity
12694 //==================================
12695 //
12696 // 20100514 Luke/Joseph:
12697 // Add new function for antenna diversity after link.
12698 // This is the main function of antenna diversity after link.
12699 // This function is called in HalDmWatchDog() and ODM_SwAntDivChkAntSwitchCallback().
12700 // HalDmWatchDog() calls this function with SWAW_STEP_PEAK to initialize the antenna test.
12701 // In SWAW_STEP_PEAK, another antenna and a 500ms timer will be set for testing.
12702 // After 500ms, ODM_SwAntDivChkAntSwitchCallback() calls this function to compare the signal just
12703 // listened on the air with the RSSI of original antenna.
12704 // It chooses the antenna with better RSSI.
12705 // There is also a aged policy for error trying. Each error trying will cost more 5 seconds waiting
12706 // penalty to get next try.
12707 //
12708 //
12709 // 20100503 Joseph:
12710 // Add new function SwAntDivCheck8192C().
12711 // This is the main function of Antenna diversity function before link.
12712 // Mainly, it just retains last scan result and scan again.
12713 // After that, it compares the scan result to see which one gets better RSSI.
12714 // It selects antenna with better receiving power and returns better scan result.
12715 //
12716
12717
12718 //
12719 // 20100514 Luke/Joseph:
12720 // This function is used to gather the RSSI information for antenna testing.
12721 // It selects the RSSI of the peer STA that we want to know.
12722 //
12723 VOID
12724 ODM_PathDivChkPerPktRssi(
12725         PADAPTER                Adapter,
12726         BOOLEAN                 bIsDefPort,
12727         BOOLEAN                 bMatchBSSID,
12728         PRT_WLAN_STA    pEntry,
12729         PRT_RFD                 pRfd
12730         )
12731 {
12732         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
12733         BOOLEAN                 bCount = FALSE;
12734         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;
12735         pSWAT_T                 pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
12736
12737         if(pHalData->RSSI_target==NULL && bIsDefPort && bMatchBSSID)
12738                 bCount = TRUE;
12739         else if(pHalData->RSSI_target!=NULL && pEntry!=NULL && pHalData->RSSI_target==pEntry)
12740                 bCount = TRUE;
12741
12742         if(bCount)
12743         {
12744                 //1 RSSI for SW Antenna Switch
12745                 if(pDM_SWAT_Table->CurAntenna == MAIN_ANT)
12746                 {
12747                         pHalData->RSSI_sum_A += pRfd->Status.RxPWDBAll;
12748                         pHalData->RSSI_cnt_A++;
12749                 }
12750                 else
12751                 {
12752                         pHalData->RSSI_sum_B += pRfd->Status.RxPWDBAll;
12753                         pHalData->RSSI_cnt_B++;
12754
12755                 }
12756         }
12757 }
12758
12759
12760
12761 //
12762 // 20100514 Luke/Joseph:
12763 // Add new function to reset antenna diversity state after link.
12764 //
12765 VOID
12766 ODM_PathDivRestAfterLink(
12767         IN      PDM_ODM_T               pDM_Odm
12768         )
12769 {
12770         PADAPTER                Adapter=pDM_Odm->Adapter;
12771         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
12772         pSWAT_T                 pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
12773
12774         pHalData->RSSI_cnt_A = 0;
12775         pHalData->RSSI_cnt_B = 0;
12776         pHalData->RSSI_test = FALSE;
12777         pDM_SWAT_Table->try_flag = 0x0;       // NOT 0xff
12778         pDM_SWAT_Table->RSSI_Trying = 0;
12779         pDM_SWAT_Table->SelectAntennaMap=0xAA;
12780         pDM_SWAT_Table->CurAntenna = MAIN_ANT;
12781 }
12782
12783
12784 //
12785 // 20100514 Luke/Joseph:
12786 // Callback function for 500ms antenna test trying.
12787 //
12788 VOID
12789 odm_PathDivChkAntSwitchCallback(
12790         PRT_TIMER               pTimer
12791 )
12792 {
12793         PADAPTER                Adapter = (PADAPTER)pTimer->Adapter;
12794         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
12795         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;
12796
12797 #if DEV_BUS_TYPE==RT_PCI_INTERFACE
12798
12799 #if USE_WORKITEM
12800         PlatformScheduleWorkItem(&pDM_Odm->PathDivSwitchWorkitem);
12801 #else
12802         odm_PathDivChkAntSwitch(pDM_Odm);
12803 #endif
12804 #else
12805         PlatformScheduleWorkItem(&pDM_Odm->PathDivSwitchWorkitem);
12806 #endif
12807
12808 //odm_SwAntDivChkAntSwitch(Adapter, SWAW_STEP_DETERMINE);
12809
12810 }
12811
12812
12813 VOID
12814 odm_PathDivChkAntSwitchWorkitemCallback(
12815     IN PVOID            pContext
12816     )
12817 {
12818         PADAPTER        pAdapter = (PADAPTER)pContext;
12819         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);
12820         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;
12821
12822         odm_PathDivChkAntSwitch(pDM_Odm);
12823 }
12824
12825
12826  //MAC0_ACCESS_PHY1
12827
12828 // 2011-06-22 Neil Chen & Gary Hsin
12829 // Refer to Jr.Luke's SW ANT DIV
12830 // 92D Path Diversity Main function
12831 // refer to 88C software antenna diversity
12832 //
12833 VOID
12834 odm_PathDivChkAntSwitch(
12835         PDM_ODM_T               pDM_Odm
12836         //PADAPTER              Adapter,
12837         //u1Byte                        Step
12838 )
12839 {
12840         PADAPTER                Adapter = pDM_Odm->Adapter;
12841         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
12842         PMGNT_INFO              pMgntInfo = &Adapter->MgntInfo;
12843
12844
12845         pSWAT_T                 pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
12846         s4Byte                  curRSSI=100, RSSI_A, RSSI_B;
12847         u1Byte                  nextAntenna=AUX_ANT;
12848         static u8Byte           lastTxOkCnt=0, lastRxOkCnt=0;
12849         u8Byte                  curTxOkCnt, curRxOkCnt;
12850         static u8Byte           TXByteCnt_A=0, TXByteCnt_B=0, RXByteCnt_A=0, RXByteCnt_B=0;
12851         u8Byte                  CurByteCnt=0, PreByteCnt=0;
12852         static u1Byte           TrafficLoad = TRAFFIC_LOW;
12853         u1Byte                  Score_A=0, Score_B=0;
12854         u1Byte                  i=0x0;
12855        // Neil Chen
12856        static u1Byte        pathdiv_para=0x0;
12857        static u1Byte        switchfirsttime=0x00;
12858         // u1Byte                 regB33 = (u1Byte) PHY_QueryBBReg(Adapter, 0xB30,BIT27);
12859         u1Byte                  regB33 = (u1Byte)ODM_GetBBReg(pDM_Odm, PATHDIV_REG, BIT27);
12860
12861
12862        //u1Byte                 reg637 =0x0;
12863        static u1Byte        fw_value=0x0;
12864         //u8Byte                        curTxOkCnt_tmp, curRxOkCnt_tmp;
12865        PADAPTER            BuddyAdapter = Adapter->BuddyAdapter;     // another adapter MAC
12866         // Path Diversity   //Neil Chen--2011--06--22
12867
12868         //u1Byte                 PathDiv_Trigger = (u1Byte) PHY_QueryBBReg(Adapter, 0xBA0,BIT31);
12869         u1Byte                 PathDiv_Trigger = (u1Byte) ODM_GetBBReg(pDM_Odm, PATHDIV_TRI,BIT31);
12870         u1Byte                 PathDiv_Enable = pHalData->bPathDiv_Enable;
12871
12872
12873         //DbgPrint("Path Div PG Value:%x \n",PathDiv_Enable);
12874        if((BuddyAdapter==NULL)||(!PathDiv_Enable)||(PathDiv_Trigger)||(pHalData->CurrentBandType == BAND_ON_2_4G))
12875        {
12876            return;
12877        }
12878         ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD,("===================>odm_PathDivChkAntSwitch()\n"));
12879
12880        // The first time to switch path excluding 2nd, 3rd, ....etc....
12881         if(switchfirsttime==0)
12882         {
12883             if(regB33==0)
12884             {
12885                pDM_SWAT_Table->CurAntenna = MAIN_ANT;    // Default MAC0_5G-->Path A (current antenna)
12886             }
12887         }
12888
12889         // Condition that does not need to use antenna diversity.
12890         if(pDM_Odm->SupportICType != ODM_RTL8192D)
12891         {
12892                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("odm_PathDiversityMechanims(): No PathDiv Mechanism.\n"));
12893                 return;
12894         }
12895
12896         // Radio off: Status reset to default and return.
12897         if(pHalData->eRFPowerState==eRfOff)
12898         {
12899                 //ODM_SwAntDivRestAfterLink(Adapter);
12900                 return;
12901         }
12902
12903        /*
12904         // Handling step mismatch condition.
12905         // Peak step is not finished at last time. Recover the variable and check again.
12906         if(     Step != pDM_SWAT_Table->try_flag        )
12907         {
12908                 ODM_SwAntDivRestAfterLink(Adapter);
12909         } */
12910
12911         if(pDM_SWAT_Table->try_flag == 0xff)
12912         {
12913                 // Select RSSI checking target
12914                 if(pMgntInfo->mAssoc && !ACTING_AS_AP(Adapter))
12915                 {
12916                         // Target: Infrastructure mode AP.
12917                         pHalData->RSSI_target = NULL;
12918                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("odm_PathDivMechanism(): RSSI_target is DEF AP!\n"));
12919                 }
12920                 else
12921                 {
12922                         u1Byte                  index = 0;
12923                         PRT_WLAN_STA    pEntry = NULL;
12924                         PADAPTER                pTargetAdapter = NULL;
12925
12926                         if(     pMgntInfo->mIbss || ACTING_AS_AP(Adapter) )
12927                         {
12928                                 // Target: AP/IBSS peer.
12929                                 pTargetAdapter = Adapter;
12930                         }
12931                         else if(IsAPModeExist(Adapter)  && GetFirstExtAdapter(Adapter) != NULL)
12932                         {
12933                                 // Target: VWIFI peer.
12934                                 pTargetAdapter = GetFirstExtAdapter(Adapter);
12935                         }
12936
12937                         if(pTargetAdapter != NULL)
12938                         {
12939                                 for(index=0; index<ODM_ASSOCIATE_ENTRY_NUM; index++)
12940                                 {
12941                                         pEntry = AsocEntry_EnumStation(pTargetAdapter, index);
12942                                         if(pEntry != NULL)
12943                                         {
12944                                                 if(pEntry->bAssociated)
12945                                                         break;
12946                                         }
12947                                 }
12948                         }
12949
12950                         if(pEntry == NULL)
12951                         {
12952                                 ODM_PathDivRestAfterLink(pDM_Odm);
12953                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("odm_SwAntDivChkAntSwitch(): No Link.\n"));
12954                                 return;
12955                         }
12956                         else
12957                         {
12958                                 pHalData->RSSI_target = pEntry;
12959                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("odm_SwAntDivChkAntSwitch(): RSSI_target is PEER STA\n"));
12960                         }
12961                 }
12962
12963                 pHalData->RSSI_cnt_A = 0;
12964                 pHalData->RSSI_cnt_B = 0;
12965                 pDM_SWAT_Table->try_flag = 0;
12966                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("odm_SwAntDivChkAntSwitch(): Set try_flag to 0 prepare for peak!\n"));
12967                 return;
12968         }
12969         else
12970         {
12971                // 1st step
12972                 curTxOkCnt = Adapter->TxStats.NumTxBytesUnicast - lastTxOkCnt;
12973                 curRxOkCnt = Adapter->RxStats.NumRxBytesUnicast - lastRxOkCnt;
12974                 lastTxOkCnt = Adapter->TxStats.NumTxBytesUnicast;
12975                 lastRxOkCnt = Adapter->RxStats.NumRxBytesUnicast;
12976
12977                 if(pDM_SWAT_Table->try_flag == 1)   // Training State
12978                 {
12979                         if(pDM_SWAT_Table->CurAntenna == MAIN_ANT)
12980                         {
12981                                 TXByteCnt_A += curTxOkCnt;
12982                                 RXByteCnt_A += curRxOkCnt;
12983                         }
12984                         else
12985                         {
12986                                 TXByteCnt_B += curTxOkCnt;
12987                                 RXByteCnt_B += curRxOkCnt;
12988                         }
12989
12990                         nextAntenna = (pDM_SWAT_Table->CurAntenna == MAIN_ANT)? AUX_ANT : MAIN_ANT;
12991                         pDM_SWAT_Table->RSSI_Trying--;
12992                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH DIV=: RSSI_Trying = %d\n",pDM_SWAT_Table->RSSI_Trying));
12993                         if(pDM_SWAT_Table->RSSI_Trying == 0)
12994                         {
12995                                 CurByteCnt = (pDM_SWAT_Table->CurAntenna == MAIN_ANT)? (TXByteCnt_A+RXByteCnt_A) : (TXByteCnt_B+RXByteCnt_B);
12996                                 PreByteCnt = (pDM_SWAT_Table->CurAntenna == MAIN_ANT)? (TXByteCnt_B+RXByteCnt_B) : (TXByteCnt_A+RXByteCnt_A);
12997
12998                                 if(TrafficLoad == TRAFFIC_HIGH)
12999                                 {
13000                                         //CurByteCnt = PlatformDivision64(CurByteCnt, 9);
13001                                         PreByteCnt =PreByteCnt*9;
13002                                 }
13003                                 else if(TrafficLoad == TRAFFIC_LOW)
13004                                 {
13005                                         //CurByteCnt = PlatformDivision64(CurByteCnt, 2);
13006                                         PreByteCnt =PreByteCnt*2;
13007                                 }
13008                                 if(pHalData->RSSI_cnt_A > 0)
13009                                         RSSI_A = pHalData->RSSI_sum_A/pHalData->RSSI_cnt_A;
13010                                 else
13011                                         RSSI_A = 0;
13012                                 if(pHalData->RSSI_cnt_B > 0)
13013                                         RSSI_B = pHalData->RSSI_sum_B/pHalData->RSSI_cnt_B;
13014                              else
13015                                         RSSI_B = 0;
13016                                 curRSSI = (pDM_SWAT_Table->CurAntenna == MAIN_ANT)? RSSI_A : RSSI_B;
13017                                 pDM_SWAT_Table->PreRSSI =  (pDM_SWAT_Table->CurAntenna == MAIN_ANT)? RSSI_B : RSSI_A;
13018                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH DIV=: PreRSSI = %d, CurRSSI = %d\n",pDM_SWAT_Table->PreRSSI, curRSSI));
13019                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH DIV=: preAntenna= %s, curAntenna= %s \n",
13020                                 (pDM_SWAT_Table->PreAntenna == MAIN_ANT?"MAIN":"AUX"), (pDM_SWAT_Table->CurAntenna == MAIN_ANT?"MAIN":"AUX")));
13021                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH DIV=: RSSI_A= %d, RSSI_cnt_A = %d, RSSI_B= %d, RSSI_cnt_B = %d\n",
13022                                         RSSI_A, pHalData->RSSI_cnt_A, RSSI_B, pHalData->RSSI_cnt_B));
13023                         }
13024
13025                 }
13026                 else   // try_flag=0
13027                 {
13028
13029                         if(pHalData->RSSI_cnt_A > 0)
13030                                 RSSI_A = pHalData->RSSI_sum_A/pHalData->RSSI_cnt_A;
13031                         else
13032                                 RSSI_A = 0;
13033                         if(pHalData->RSSI_cnt_B > 0)
13034                                 RSSI_B = pHalData->RSSI_sum_B/pHalData->RSSI_cnt_B;
13035                         else
13036                                 RSSI_B = 0;
13037                         curRSSI = (pDM_SWAT_Table->CurAntenna == MAIN_ANT)? RSSI_A : RSSI_B;
13038                         pDM_SWAT_Table->PreRSSI =  (pDM_SWAT_Table->PreAntenna == MAIN_ANT)? RSSI_A : RSSI_B;
13039                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH DIV=: PreRSSI = %d, CurRSSI = %d\n", pDM_SWAT_Table->PreRSSI, curRSSI));
13040                        ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH DIV=: preAntenna= %s, curAntenna= %s \n",
13041                         (pDM_SWAT_Table->PreAntenna == MAIN_ANT?"MAIN":"AUX"), (pDM_SWAT_Table->CurAntenna == MAIN_ANT?"MAIN":"AUX")));
13042
13043                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH DIV=: RSSI_A= %d, RSSI_cnt_A = %d, RSSI_B= %d, RSSI_cnt_B = %d\n",
13044                                 RSSI_A, pHalData->RSSI_cnt_A, RSSI_B, pHalData->RSSI_cnt_B));
13045                         //RT_TRACE(COMP_SWAS, DBG_LOUD, ("Ekul:curTxOkCnt = %d\n", curTxOkCnt));
13046                         //RT_TRACE(COMP_SWAS, DBG_LOUD, ("Ekul:curRxOkCnt = %d\n", curRxOkCnt));
13047                 }
13048
13049                 //1 Trying State
13050                 if((pDM_SWAT_Table->try_flag == 1)&&(pDM_SWAT_Table->RSSI_Trying == 0))
13051                 {
13052
13053                         if(pDM_SWAT_Table->TestMode == TP_MODE)
13054                         {
13055                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: TestMode = TP_MODE"));
13056                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH= TRY:CurByteCnt = %"i64fmt"d,", CurByteCnt));
13057                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH= TRY:PreByteCnt = %"i64fmt"d\n",PreByteCnt));
13058                                 if(CurByteCnt < PreByteCnt)
13059                                 {
13060                                         if(pDM_SWAT_Table->CurAntenna == MAIN_ANT)
13061                                                 pDM_SWAT_Table->SelectAntennaMap=pDM_SWAT_Table->SelectAntennaMap<<1;
13062                                         else
13063                                                 pDM_SWAT_Table->SelectAntennaMap=(pDM_SWAT_Table->SelectAntennaMap<<1)+1;
13064                                 }
13065                                 else
13066                                 {
13067                                         if(pDM_SWAT_Table->CurAntenna == MAIN_ANT)
13068                                                 pDM_SWAT_Table->SelectAntennaMap=(pDM_SWAT_Table->SelectAntennaMap<<1)+1;
13069                                         else
13070                                                 pDM_SWAT_Table->SelectAntennaMap=pDM_SWAT_Table->SelectAntennaMap<<1;
13071                                 }
13072                                 for (i= 0; i<8; i++)
13073                                 {
13074                                         if(((pDM_SWAT_Table->SelectAntennaMap>>i)&BIT0) == 1)
13075                                                 Score_A++;
13076                                         else
13077                                                 Score_B++;
13078                                 }
13079                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("SelectAntennaMap=%x\n ",pDM_SWAT_Table->SelectAntennaMap));
13080                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: Score_A=%d, Score_B=%d\n", Score_A, Score_B));
13081
13082                                 if(pDM_SWAT_Table->CurAntenna == MAIN_ANT)
13083                                 {
13084                                         nextAntenna = (Score_A >= Score_B)?MAIN_ANT:AUX_ANT;
13085                                 }
13086                                 else
13087                                 {
13088                                         nextAntenna = (Score_B >= Score_A)?AUX_ANT:MAIN_ANT;
13089                                 }
13090                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: nextAntenna=%s\n",(nextAntenna==MAIN_ANT)?"MAIN":"AUX"));
13091                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: preAntenna= %s, curAntenna= %s \n",
13092                                 (pDM_SWAT_Table->PreAntenna == MAIN_ANT?"MAIN":"AUX"), (pDM_SWAT_Table->CurAntenna == MAIN_ANT?"MAIN":"AUX")));
13093
13094                                 if(nextAntenna != pDM_SWAT_Table->CurAntenna)
13095                                 {
13096                                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: Switch back to another antenna"));
13097                                 }
13098                                 else
13099                                 {
13100                                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: current anntena is good\n"));
13101                                 }
13102                         }
13103
13104
13105                         if(pDM_SWAT_Table->TestMode == RSSI_MODE)
13106                         {
13107                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: TestMode = RSSI_MODE"));
13108                                 pDM_SWAT_Table->SelectAntennaMap=0xAA;
13109                                 if(curRSSI < pDM_SWAT_Table->PreRSSI) //Current antenna is worse than previous antenna
13110                                 {
13111                                         //RT_TRACE(COMP_SWAS, DBG_LOUD, ("SWAS: Switch back to another antenna"));
13112                                         nextAntenna = (pDM_SWAT_Table->CurAntenna == MAIN_ANT)?AUX_ANT : MAIN_ANT;
13113                                 }
13114                                 else // current anntena is good
13115                                 {
13116                                         nextAntenna =pDM_SWAT_Table->CurAntenna;
13117                                         //RT_TRACE(COMP_SWAS, DBG_LOUD, ("SWAS: current anntena is good\n"));
13118                                 }
13119                         }
13120
13121                         pDM_SWAT_Table->try_flag = 0;
13122                         pHalData->RSSI_test = FALSE;
13123                         pHalData->RSSI_sum_A = 0;
13124                         pHalData->RSSI_cnt_A = 0;
13125                         pHalData->RSSI_sum_B = 0;
13126                         pHalData->RSSI_cnt_B = 0;
13127                         TXByteCnt_A = 0;
13128                         TXByteCnt_B = 0;
13129                         RXByteCnt_A = 0;
13130                         RXByteCnt_B = 0;
13131
13132                 }
13133
13134                 //1 Normal State
13135                 else if(pDM_SWAT_Table->try_flag == 0)
13136                 {
13137                         if(TrafficLoad == TRAFFIC_HIGH)
13138                         {
13139                                 if ((curTxOkCnt+curRxOkCnt) > 3750000)//if(PlatformDivision64(curTxOkCnt+curRxOkCnt, 2) > 1875000)
13140                                         TrafficLoad = TRAFFIC_HIGH;
13141                                 else
13142                                         TrafficLoad = TRAFFIC_LOW;
13143                         }
13144                         else if(TrafficLoad == TRAFFIC_LOW)
13145                                 {
13146                                 if ((curTxOkCnt+curRxOkCnt) > 3750000)//if(PlatformDivision64(curTxOkCnt+curRxOkCnt, 2) > 1875000)
13147                                         TrafficLoad = TRAFFIC_HIGH;
13148                                 else
13149                                         TrafficLoad = TRAFFIC_LOW;
13150                         }
13151                         if(TrafficLoad == TRAFFIC_HIGH)
13152                                 pDM_SWAT_Table->bTriggerAntennaSwitch = 0;
13153                         //RT_TRACE(COMP_SWAS, DBG_LOUD, ("Normal:TrafficLoad = %llu\n", curTxOkCnt+curRxOkCnt));
13154
13155                         //Prepare To Try Antenna
13156                                 nextAntenna = (pDM_SWAT_Table->CurAntenna == MAIN_ANT)? AUX_ANT : MAIN_ANT;
13157                                 pDM_SWAT_Table->try_flag = 1;
13158                                 pHalData->RSSI_test = TRUE;
13159                         if((curRxOkCnt+curTxOkCnt) > 1000)
13160                         {
13161 #if DEV_BUS_TYPE==RT_PCI_INTERFACE
13162                             pDM_SWAT_Table->RSSI_Trying = 4;
13163 #else
13164                             pDM_SWAT_Table->RSSI_Trying = 2;
13165 #endif
13166                                 pDM_SWAT_Table->TestMode = TP_MODE;
13167                         }
13168                         else
13169                         {
13170                                 pDM_SWAT_Table->RSSI_Trying = 2;
13171                                 pDM_SWAT_Table->TestMode = RSSI_MODE;
13172
13173                         }
13174
13175                         //RT_TRACE(COMP_SWAS, DBG_LOUD, ("SWAS: Normal State -> Begin Trying!\n"));
13176                         pHalData->RSSI_sum_A = 0;
13177                         pHalData->RSSI_cnt_A = 0;
13178                         pHalData->RSSI_sum_B = 0;
13179                         pHalData->RSSI_cnt_B = 0;
13180                 } // end of try_flag=0
13181         }
13182
13183         //1 4.Change TRX antenna
13184         if(nextAntenna != pDM_SWAT_Table->CurAntenna)
13185         {
13186
13187                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: Change TX Antenna!\n "));
13188                 //PHY_SetBBReg(Adapter, rFPGA0_XA_RFInterfaceOE, 0x300, nextAntenna); for 88C
13189                 if(nextAntenna==MAIN_ANT)
13190                 {
13191                     ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: Next Antenna is RF PATH A\n "));
13192                     pathdiv_para = 0x02;   //02 to switchback to RF path A
13193                     fw_value = 0x03;
13194 #if DEV_BUS_TYPE==RT_PCI_INTERFACE
13195                  odm_PathDiversity_8192D(pDM_Odm, pathdiv_para);
13196 #else
13197                  ODM_FillH2CCmd(Adapter, ODM_H2C_PathDiv,1,(pu1Byte)(&fw_value));
13198 #endif
13199                 }
13200                else if(nextAntenna==AUX_ANT)
13201                {
13202                    ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: Next Antenna is RF PATH B\n "));
13203                    if(switchfirsttime==0)  // First Time To Enter Path Diversity
13204                    {
13205                        switchfirsttime=0x01;
13206                       pathdiv_para = 0x00;
13207                           fw_value=0x00;    // to backup RF Path A Releated Registers
13208
13209 #if DEV_BUS_TYPE==RT_PCI_INTERFACE
13210                      odm_PathDiversity_8192D(pDM_Odm, pathdiv_para);
13211 #else
13212                      ODM_FillH2CCmd(Adapter, ODM_H2C_PathDiv,1,(pu1Byte)(&fw_value));
13213                      //for(u1Byte n=0; n<80,n++)
13214                      //{
13215                      //delay_us(500);
13216                           ODM_delay_ms(500);
13217                      odm_PathDiversity_8192D(pDM_Odm, pathdiv_para);
13218
13219                          fw_value=0x01;         // to backup RF Path A Releated Registers
13220                      ODM_FillH2CCmd(Adapter, ODM_H2C_PathDiv,1,(pu1Byte)(&fw_value));
13221 #endif
13222                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: FIRST TIME To DO PATH SWITCH!\n "));
13223                    }
13224                     else
13225                     {
13226                         pathdiv_para = 0x01;
13227                          fw_value = 0x02;
13228 #if DEV_BUS_TYPE==RT_PCI_INTERFACE
13229                      odm_PathDiversity_8192D(pDM_Odm, pathdiv_para);
13230 #else
13231                      ODM_FillH2CCmd(Adapter, ODM_H2C_PathDiv,1,(pu1Byte)(&fw_value));
13232 #endif
13233                     }
13234                }
13235            //   odm_PathDiversity_8192D(Adapter, pathdiv_para);
13236         }
13237
13238         //1 5.Reset Statistics
13239         pDM_SWAT_Table->PreAntenna = pDM_SWAT_Table->CurAntenna;
13240         pDM_SWAT_Table->CurAntenna = nextAntenna;
13241         pDM_SWAT_Table->PreRSSI = curRSSI;
13242
13243         //1 6.Set next timer
13244
13245         if(pDM_SWAT_Table->RSSI_Trying == 0)
13246                 return;
13247
13248         if(pDM_SWAT_Table->RSSI_Trying%2 == 0)
13249         {
13250                 if(pDM_SWAT_Table->TestMode == TP_MODE)
13251                 {
13252                         if(TrafficLoad == TRAFFIC_HIGH)
13253                         {
13254 #if DEV_BUS_TYPE==RT_PCI_INTERFACE
13255                                 ODM_SetTimer( pDM_Odm, &pDM_Odm->PathDivSwitchTimer, 10 ); //ms
13256                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: Test another antenna for 10 ms\n"));
13257 #else
13258                                 ODM_SetTimer( pDM_Odm, &pDM_Odm->PathDivSwitchTimer, 20 ); //ms
13259                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: Test another antenna for 20 ms\n"));
13260 #endif
13261                         }
13262                         else if(TrafficLoad == TRAFFIC_LOW)
13263                         {
13264                                 ODM_SetTimer( pDM_Odm, &pDM_Odm->PathDivSwitchTimer, 50 ); //ms
13265                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: Test another antenna for 50 ms\n"));
13266                         }
13267                 }
13268                 else   // TestMode == RSSI_MODE
13269                 {
13270                         ODM_SetTimer( pDM_Odm, &pDM_Odm->PathDivSwitchTimer, 500 ); //ms
13271                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: Test another antenna for 500 ms\n"));
13272                 }
13273         }
13274         else
13275         {
13276                 if(pDM_SWAT_Table->TestMode == TP_MODE)
13277                 {
13278                         if(TrafficLoad == TRAFFIC_HIGH)
13279
13280 #if DEV_BUS_TYPE==RT_PCI_INTERFACE
13281                                 ODM_SetTimer( pDM_Odm, &pDM_Odm->PathDivSwitchTimer, 90 ); //ms
13282                                 //ODM_RT_TRACE(pDM_Odm,ODM_COMP_PATH_DIV, ODM_DBG_LOUD, ("=PATH=: Test another antenna for 90 ms\n"));
13283 #else
13284                                 ODM_SetTimer( pDM_Odm, &pDM_Odm->PathDivSwitchTimer, 180); //ms
13285 #endif
13286                         else if(TrafficLoad == TRAFFIC_LOW)
13287                                 ODM_SetTimer( pDM_Odm, &pDM_Odm->PathDivSwitchTimer, 100 ); //ms
13288                 }
13289                 else
13290                         ODM_SetTimer( pDM_Odm, &pDM_Odm->PathDivSwitchTimer, 500 ); //ms
13291         }
13292 }
13293
13294 //==================================================
13295 //3 PathDiv End
13296 //==================================================
13297
13298 VOID
13299 odm_SetRespPath_92C(
13300         IN      PADAPTER        Adapter,
13301         IN      u1Byte  DefaultRespPath
13302         )
13303 {
13304         pPD_T   pDM_PDTable = &Adapter->DM_PDTable;
13305
13306         RT_TRACE(       COMP_SWAS, DBG_LOUD, ("odm_SetRespPath_92C: Select Response Path=%d\n",DefaultRespPath));
13307         if(DefaultRespPath != pDM_PDTable->DefaultRespPath)
13308         {
13309                 if(DefaultRespPath == 0)
13310                 {
13311                         PlatformEFIOWrite1Byte(Adapter, 0x6D8, (PlatformEFIORead1Byte(Adapter, 0x6D8)&0xc0)|0x15);
13312                 }
13313                 else
13314                 {
13315                         PlatformEFIOWrite1Byte(Adapter, 0x6D8, (PlatformEFIORead1Byte(Adapter, 0x6D8)&0xc0)|0x2A);
13316                 }
13317         }
13318         pDM_PDTable->DefaultRespPath = DefaultRespPath;
13319 }
13320
13321
13322 VOID
13323 ODM_FillTXPathInTXDESC(
13324                 IN      PADAPTER        Adapter,
13325                 IN      PRT_TCB         pTcb,
13326                 IN      pu1Byte         pDesc
13327 )
13328 {
13329         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
13330         u4Byte  TXPath;
13331         pPD_T   pDM_PDTable = &Adapter->DM_PDTable;
13332
13333         //2011.09.05  Add by Luke Lee for path diversity
13334         if(pHalData->PathDivCfg == 1)
13335         {
13336                 TXPath = (pDM_PDTable->OFDMTXPath >> pTcb->macId) & BIT0;
13337                 //RT_TRACE(     COMP_SWAS, DBG_LOUD, ("Fill TXDESC: macID=%d, TXPath=%d\n", pTcb->macId, TXPath));
13338                 //SET_TX_DESC_TX_ANT_CCK(pDesc,TXPath);
13339                 if(TXPath == 0)
13340                 {
13341                         SET_TX_DESC_TX_ANTL_92C(pDesc,1);
13342                         SET_TX_DESC_TX_ANT_HT_92C(pDesc,1);
13343                 }
13344                 else
13345                 {
13346                         SET_TX_DESC_TX_ANTL_92C(pDesc,2);
13347                         SET_TX_DESC_TX_ANT_HT_92C(pDesc,2);
13348                 }
13349                 TXPath = (pDM_PDTable->CCKTXPath >> pTcb->macId) & BIT0;
13350                 if(TXPath == 0)
13351                 {
13352                         SET_TX_DESC_TX_ANT_CCK_92C(pDesc,1);
13353                 }
13354                 else
13355                 {
13356                         SET_TX_DESC_TX_ANT_CCK_92C(pDesc,2);
13357                 }
13358         }
13359 }
13360
13361 //Only for MP //Neil Chen--2012--0502--
13362 VOID
13363 odm_PathDivInit_92D(
13364 IN      PDM_ODM_T       pDM_Odm)
13365 {
13366         pPATHDIV_PARA   pathIQK = &pDM_Odm->pathIQK;
13367
13368         pathIQK->org_2g_RegC14=0x0;
13369         pathIQK->org_2g_RegC4C=0x0;
13370         pathIQK->org_2g_RegC80=0x0;
13371         pathIQK->org_2g_RegC94=0x0;
13372         pathIQK->org_2g_RegCA0=0x0;
13373         pathIQK->org_5g_RegC14=0x0;
13374         pathIQK->org_5g_RegCA0=0x0;
13375         pathIQK->org_5g_RegE30=0x0;
13376         pathIQK->swt_2g_RegC14=0x0;
13377         pathIQK->swt_2g_RegC4C=0x0;
13378         pathIQK->swt_2g_RegC80=0x0;
13379         pathIQK->swt_2g_RegC94=0x0;
13380         pathIQK->swt_2g_RegCA0=0x0;
13381         pathIQK->swt_5g_RegC14=0x0;
13382         pathIQK->swt_5g_RegCA0=0x0;
13383         pathIQK->swt_5g_RegE30=0x0;
13384
13385 }
13386
13387 #endif  // #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
13388
13389 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN| ODM_CE))
13390
13391 VOID
13392 odm_PHY_SaveAFERegisters(
13393         IN      PDM_ODM_T       pDM_Odm,
13394         IN      pu4Byte         AFEReg,
13395         IN      pu4Byte         AFEBackup,
13396         IN      u4Byte          RegisterNum
13397         )
13398 {
13399         u4Byte  i;
13400
13401         //RT_DISP(FINIT, INIT_IQK, ("Save ADDA parameters.\n"));
13402         for( i = 0 ; i < RegisterNum ; i++){
13403                 AFEBackup[i] = ODM_GetBBReg(pDM_Odm, AFEReg[i], bMaskDWord);
13404         }
13405 }
13406
13407 VOID
13408 odm_PHY_ReloadAFERegisters(
13409         IN      PDM_ODM_T       pDM_Odm,
13410         IN      pu4Byte         AFEReg,
13411         IN      pu4Byte         AFEBackup,
13412         IN      u4Byte          RegiesterNum
13413         )
13414 {
13415         u4Byte  i;
13416
13417         //RT_DISP(FINIT, INIT_IQK, ("Reload ADDA power saving parameters !\n"));
13418         for(i = 0 ; i < RegiesterNum; i++)
13419         {
13420
13421                 ODM_SetBBReg(pDM_Odm, AFEReg[i], bMaskDWord, AFEBackup[i]);
13422         }
13423 }
13424
13425 //
13426 // Description:
13427 //      Set Single/Dual Antenna default setting for products that do not do detection in advance.
13428 //
13429 // Added by Joseph, 2012.03.22
13430 //
13431 VOID
13432 ODM_SingleDualAntennaDefaultSetting(
13433         IN              PDM_ODM_T               pDM_Odm
13434         )
13435 {
13436         pSWAT_T         pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
13437         PADAPTER        pAdapter         =  pDM_Odm->Adapter;
13438         u1Byte btAntNum = 2;
13439 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))
13440         btAntNum=BT_GetPgAntNum(pAdapter);
13441 #elif (DM_ODM_SUPPORT_TYPE & (ODM_CE))
13442 #ifdef CONFIG_BT_COEXIST
13443         btAntNum = hal_btcoex_GetPgAntNum(pAdapter);
13444 #endif
13445 #endif
13446
13447         // Set default antenna A and B status
13448         if(btAntNum == 2)
13449         {
13450                 pDM_SWAT_Table->ANTA_ON=TRUE;
13451                 pDM_SWAT_Table->ANTB_ON=TRUE;
13452                 //RT_TRACE(COMP_ANTENNA, DBG_LOUD, ("Dual antenna\n"));
13453         }
13454         else if(btAntNum == 1)
13455         {// Set antenna A as default
13456                 pDM_SWAT_Table->ANTA_ON=TRUE;
13457                 pDM_SWAT_Table->ANTB_ON=FALSE;
13458                 //RT_TRACE(COMP_ANTENNA, DBG_LOUD, ("Single antenna\n"));
13459         }
13460         else
13461         {
13462                 //RT_ASSERT(FALSE, ("Incorrect antenna number!!\n"));
13463         }
13464 }
13465
13466
13467
13468 //2 8723A ANT DETECT
13469 //
13470 // Description:
13471 //      Implement IQK single tone for RF DPK loopback and BB PSD scanning.
13472 //      This function is cooperated with BB team Neil.
13473 //
13474 // Added by Roger, 2011.12.15
13475 //
13476 BOOLEAN
13477 ODM_SingleDualAntennaDetection(
13478         IN              PDM_ODM_T               pDM_Odm,
13479         IN              u1Byte                  mode
13480         )
13481 {
13482         PADAPTER        pAdapter         =  pDM_Odm->Adapter;
13483         pSWAT_T         pDM_SWAT_Table = &pDM_Odm->DM_SWAT_Table;
13484         u4Byte          CurrentChannel,RfLoopReg;
13485         u1Byte          n;
13486         u4Byte          Reg88c, Regc08, Reg874, Regc50, Reg948=0, Regb2c=0, Reg92c=0, AFE_rRx_Wait_CCA=0;
13487         u1Byte          initial_gain = 0x5a;
13488         u4Byte          PSD_report_tmp;
13489         u4Byte          AntA_report = 0x0, AntB_report = 0x0,AntO_report=0x0;
13490         BOOLEAN         bResult = TRUE;
13491         u4Byte          AFE_Backup[16];
13492         u4Byte          AFE_REG_8723A[16] = {
13493                                         rRx_Wait_CCA,   rTx_CCK_RFON,
13494                                         rTx_CCK_BBON,   rTx_OFDM_RFON,
13495                                         rTx_OFDM_BBON,  rTx_To_Rx,
13496                                         rTx_To_Tx,              rRx_CCK,
13497                                         rRx_OFDM,               rRx_Wait_RIFS,
13498                                         rRx_TO_Rx,              rStandby,
13499                                         rSleep,                 rPMPD_ANAEN,
13500                                         rFPGA0_XCD_SwitchControl, rBlue_Tooth};
13501
13502         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection()============> \n"));
13503
13504
13505         if(!(pDM_Odm->SupportICType & (ODM_RTL8723A|ODM_RTL8192C|ODM_RTL8723B)))
13506                 return bResult;
13507
13508         // Retrieve antenna detection registry info, added by Roger, 2012.11.27.
13509         if(!IS_ANT_DETECT_SUPPORT_SINGLE_TONE(pAdapter))
13510                 return bResult;
13511
13512         if(pDM_Odm->SupportICType == ODM_RTL8192C)
13513         {
13514                 //Which path in ADC/DAC is turnned on for PSD: both I/Q
13515                 ODM_SetBBReg(pDM_Odm, 0x808, BIT10|BIT11, 0x3);
13516                 //Ageraged number: 8
13517                 ODM_SetBBReg(pDM_Odm, 0x808, BIT12|BIT13, 0x1);
13518                 //pts = 128;
13519                 ODM_SetBBReg(pDM_Odm, 0x808, BIT14|BIT15, 0x0);
13520         }
13521
13522         //1 Backup Current RF/BB Settings
13523
13524         CurrentChannel = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, ODM_CHANNEL, bRFRegOffsetMask);
13525         RfLoopReg = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x00, bRFRegOffsetMask);
13526         if(!(pDM_Odm->SupportICType == ODM_RTL8723B))
13527         ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, ODM_DPDT, Antenna_A);  // change to Antenna A
13528 #if (RTL8723B_SUPPORT == 1)
13529         else
13530         {
13531                 Reg92c = ODM_GetBBReg(pDM_Odm, 0x92c, bMaskDWord);
13532                 Reg948 = ODM_GetBBReg(pDM_Odm, rS0S1_PathSwitch, bMaskDWord);
13533                 Regb2c = ODM_GetBBReg(pDM_Odm, AGC_table_select, bMaskDWord);
13534                 ODM_SetBBReg(pDM_Odm, rDPDT_control, 0x3, 0x1);
13535                 ODM_SetBBReg(pDM_Odm, rfe_ctrl_anta_src, 0xff, 0x77);
13536                 ODM_SetBBReg(pDM_Odm, rS0S1_PathSwitch, 0x3ff, 0x000);
13537                 ODM_SetBBReg(pDM_Odm, AGC_table_select, BIT31, 0x0);
13538         }
13539 #endif
13540         ODM_StallExecution(10);
13541
13542         //Store A Path Register 88c, c08, 874, c50
13543         Reg88c = ODM_GetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, bMaskDWord);
13544         Regc08 = ODM_GetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord);
13545         Reg874 = ODM_GetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord);
13546         Regc50 = ODM_GetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskDWord);
13547
13548         // Store AFE Registers
13549         if(pDM_Odm->SupportICType & (ODM_RTL8723A|ODM_RTL8192C))
13550         odm_PHY_SaveAFERegisters(pDM_Odm, AFE_REG_8723A, AFE_Backup, 16);
13551         else if(pDM_Odm->SupportICType == ODM_RTL8723B)
13552                 AFE_rRx_Wait_CCA = ODM_GetBBReg(pDM_Odm, rRx_Wait_CCA,bMaskDWord);
13553
13554         //Set PSD 128 pts
13555         ODM_SetBBReg(pDM_Odm, rFPGA0_PSDFunction, BIT14|BIT15, 0x0);  //128 pts
13556
13557         // To SET CH1 to do
13558         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, ODM_CHANNEL, bRFRegOffsetMask, 0x7401);     //Channel 1
13559
13560         // AFE all on step
13561         if(pDM_Odm->SupportICType & (ODM_RTL8723A|ODM_RTL8192C))
13562         {
13563                 ODM_SetBBReg(pDM_Odm, rRx_Wait_CCA, bMaskDWord, 0x6FDB25A4);
13564                 ODM_SetBBReg(pDM_Odm, rTx_CCK_RFON, bMaskDWord, 0x6FDB25A4);
13565                 ODM_SetBBReg(pDM_Odm, rTx_CCK_BBON, bMaskDWord, 0x6FDB25A4);
13566                 ODM_SetBBReg(pDM_Odm, rTx_OFDM_RFON, bMaskDWord, 0x6FDB25A4);
13567                 ODM_SetBBReg(pDM_Odm, rTx_OFDM_BBON, bMaskDWord, 0x6FDB25A4);
13568                 ODM_SetBBReg(pDM_Odm, rTx_To_Rx, bMaskDWord, 0x6FDB25A4);
13569                 ODM_SetBBReg(pDM_Odm, rTx_To_Tx, bMaskDWord, 0x6FDB25A4);
13570                 ODM_SetBBReg(pDM_Odm, rRx_CCK, bMaskDWord, 0x6FDB25A4);
13571                 ODM_SetBBReg(pDM_Odm, rRx_OFDM, bMaskDWord, 0x6FDB25A4);
13572                 ODM_SetBBReg(pDM_Odm, rRx_Wait_RIFS, bMaskDWord, 0x6FDB25A4);
13573                 ODM_SetBBReg(pDM_Odm, rRx_TO_Rx, bMaskDWord, 0x6FDB25A4);
13574                 ODM_SetBBReg(pDM_Odm, rStandby, bMaskDWord, 0x6FDB25A4);
13575                 ODM_SetBBReg(pDM_Odm, rSleep, bMaskDWord, 0x6FDB25A4);
13576                 ODM_SetBBReg(pDM_Odm, rPMPD_ANAEN, bMaskDWord, 0x6FDB25A4);
13577                 ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_SwitchControl, bMaskDWord, 0x6FDB25A4);
13578                 ODM_SetBBReg(pDM_Odm, rBlue_Tooth, bMaskDWord, 0x6FDB25A4);
13579         }
13580         else if(pDM_Odm->SupportICType == ODM_RTL8723B)
13581         {
13582                 ODM_SetBBReg(pDM_Odm, rRx_Wait_CCA, bMaskDWord, 0x01c00016);
13583         }
13584
13585         // 3 wire Disable
13586         ODM_SetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, bMaskDWord, 0xCCF000C0);
13587
13588         //BB IQK Setting
13589         ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, 0x000800E4);
13590         ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22208000);
13591
13592         //IQK setting tone@ 4.34Mhz
13593         ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x10008C1C);
13594         ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00);
13595
13596         //Page B init
13597         ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x00080000);
13598         ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x0f600000);
13599         ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800);
13600         ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x10008c1f);
13601         ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82150008);
13602         ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28150008);
13603         ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x001028d0);
13604
13605         //RF loop Setting
13606         if(pDM_Odm->SupportICType & (ODM_RTL8723A|ODM_RTL8192C))
13607         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x0, 0xFFFFF, 0x50008);
13608
13609         //IQK Single tone start
13610         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x80800000);
13611         ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);
13612         ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
13613
13614         ODM_StallExecution(10000);
13615
13616         // PSD report of antenna A
13617         PSD_report_tmp=0x0;
13618         for (n=0;n<2;n++)
13619         {
13620                 PSD_report_tmp =  GetPSDData(pDM_Odm, 14, initial_gain);
13621                 if(PSD_report_tmp >AntA_report)
13622                         AntA_report=PSD_report_tmp;
13623         }
13624
13625          // change to Antenna B
13626         if(pDM_Odm->SupportICType & (ODM_RTL8723A|ODM_RTL8192C))
13627                 ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, ODM_DPDT, Antenna_B);
13628 #if (RTL8723B_SUPPORT == 1)
13629         else if(pDM_Odm->SupportICType == ODM_RTL8723B)
13630                 ODM_SetBBReg(pDM_Odm, rDPDT_control, 0x3, 0x2);
13631 #endif
13632
13633         ODM_StallExecution(10);
13634
13635         // PSD report of antenna B
13636         PSD_report_tmp=0x0;
13637         for (n=0;n<2;n++)
13638         {
13639                 PSD_report_tmp =  GetPSDData(pDM_Odm, 14, initial_gain);
13640                 if(PSD_report_tmp > AntB_report)
13641                         AntB_report=PSD_report_tmp;
13642         }
13643
13644         // change to open case
13645         if(pDM_Odm->SupportICType & (ODM_RTL8723A|ODM_RTL8192C))
13646                 ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, ODM_DPDT, 0);  // change to Antenna A
13647 #if (RTL8723B_SUPPORT == 1)
13648         else if(pDM_Odm->SupportICType == ODM_RTL8723B)
13649                 ODM_SetBBReg(pDM_Odm, rDPDT_control, 0x3, 0x0);
13650 #endif
13651
13652         ODM_StallExecution(10);
13653
13654         // PSD report of open case
13655         PSD_report_tmp=0x0;
13656         for (n=0;n<2;n++)
13657         {
13658                 PSD_report_tmp =  GetPSDData(pDM_Odm, 14, initial_gain);
13659                 if(PSD_report_tmp > AntO_report)
13660                         AntO_report=PSD_report_tmp;
13661         }
13662
13663         //Close IQK Single Tone function
13664         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000);
13665
13666         //1 Return to antanna A
13667         if(pDM_Odm->SupportICType & (ODM_RTL8723A|ODM_RTL8192C))
13668                 ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, ODM_DPDT, Antenna_A);  // change to Antenna A
13669 #if (RTL8723B_SUPPORT == 1)
13670         else if(pDM_Odm->SupportICType == ODM_RTL8723B)
13671         {
13672                 // external DPDT
13673                 ODM_SetBBReg(pDM_Odm, rDPDT_control, bMaskDWord, Reg92c);
13674
13675                 //internal S0/S1
13676                 ODM_SetBBReg(pDM_Odm, rS0S1_PathSwitch, bMaskDWord, Reg948);
13677                 ODM_SetBBReg(pDM_Odm, AGC_table_select, bMaskDWord, Regb2c);
13678         }
13679 #endif
13680         ODM_SetBBReg(pDM_Odm, rFPGA0_AnalogParameter4, bMaskDWord, Reg88c);
13681         ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, Regc08);
13682         ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, Reg874);
13683         ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, 0x7F, 0x40);
13684         ODM_SetBBReg(pDM_Odm, rOFDM0_XAAGCCore1, bMaskDWord, Regc50);
13685         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bRFRegOffsetMask,CurrentChannel);
13686         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x00, bRFRegOffsetMask,RfLoopReg);
13687
13688         //Reload AFE Registers
13689         if(pDM_Odm->SupportICType & (ODM_RTL8723A|ODM_RTL8192C))
13690         odm_PHY_ReloadAFERegisters(pDM_Odm, AFE_REG_8723A, AFE_Backup, 16);
13691         else if(pDM_Odm->SupportICType == ODM_RTL8723B)
13692                 ODM_SetBBReg(pDM_Odm, rRx_Wait_CCA, bMaskDWord, AFE_rRx_Wait_CCA);
13693
13694         if(pDM_Odm->SupportICType == ODM_RTL8723A)
13695         {
13696                 //2 Test Ant B based on Ant A is ON
13697                 if(mode==ANTTESTB)
13698                 {
13699                         if(AntA_report >=       100)
13700                         {
13701                                 if(AntB_report > (AntA_report+1))
13702                                 {
13703                                         pDM_SWAT_Table->ANTB_ON=FALSE;
13704                                                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Single Antenna A\n"));
13705                                 }
13706                                 else
13707                                 {
13708                                         pDM_SWAT_Table->ANTB_ON=TRUE;
13709                                                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Dual Antenna is A and B\n"));
13710                                 }
13711                         }
13712                         else
13713                         {
13714                                                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Need to check again\n"));
13715                                 pDM_SWAT_Table->ANTB_ON=FALSE; // Set Antenna B off as default
13716                                 bResult = FALSE;
13717                         }
13718                 }
13719                 //2 Test Ant A and B based on DPDT Open
13720                 else if(mode==ANTTESTALL)
13721                 {
13722                         if((AntO_report >=100) && (AntO_report <=118))
13723                         {
13724                                 if(AntA_report > (AntO_report+1))
13725                                 {
13726                                         pDM_SWAT_Table->ANTA_ON=FALSE;
13727                                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("Ant A is OFF\n"));
13728                                 }
13729                                 else
13730                                 {
13731                                         pDM_SWAT_Table->ANTA_ON=TRUE;
13732                                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("Ant A is ON\n"));
13733                                 }
13734
13735                                 if(AntB_report > (AntO_report+2))
13736                                 {
13737                                         pDM_SWAT_Table->ANTB_ON=FALSE;
13738                                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("Ant B is OFF\n"));
13739                                 }
13740                                 else
13741                                 {
13742                                         pDM_SWAT_Table->ANTB_ON=TRUE;
13743                                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("Ant B is ON\n"));
13744                                 }
13745
13746                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_A[%d]= %d \n", 2416, AntA_report));
13747                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_B[%d]= %d \n", 2416, AntB_report));
13748                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_O[%d]= %d \n", 2416, AntO_report));
13749
13750                                 pDM_Odm->AntDetectedInfo.bAntDetected= TRUE;
13751                                 pDM_Odm->AntDetectedInfo.dBForAntA = AntA_report;
13752                                 pDM_Odm->AntDetectedInfo.dBForAntB = AntB_report;
13753                                 pDM_Odm->AntDetectedInfo.dBForAntO = AntO_report;
13754
13755                                 }
13756                         else
13757                                 {
13758                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("return FALSE!!\n"));
13759                                 bResult = FALSE;
13760                         }
13761                 }
13762         }
13763         else if(pDM_Odm->SupportICType == ODM_RTL8192C)
13764         {
13765                 if(AntA_report >=       100)
13766                 {
13767                         if(AntB_report > (AntA_report+2))
13768                         {
13769                                 pDM_SWAT_Table->ANTA_ON=FALSE;
13770                                 pDM_SWAT_Table->ANTB_ON=TRUE;
13771                                 ODM_SetBBReg(pDM_Odm,  rFPGA0_XA_RFInterfaceOE, 0x300, Antenna_B);
13772                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Single Antenna B\n"));
13773                         }
13774                         else if(AntA_report > (AntB_report+2))
13775                         {
13776                                 pDM_SWAT_Table->ANTA_ON=TRUE;
13777                                 pDM_SWAT_Table->ANTB_ON=FALSE;
13778                                 ODM_SetBBReg(pDM_Odm,  rFPGA0_XA_RFInterfaceOE, 0x300, Antenna_A);
13779                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Single Antenna A\n"));
13780                         }
13781                         else
13782                         {
13783                                 pDM_SWAT_Table->ANTA_ON=TRUE;
13784                                 pDM_SWAT_Table->ANTB_ON=TRUE;
13785                                 RT_TRACE(COMP_ANTENNA, DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Dual Antenna \n"));
13786                         }
13787                 }
13788                 else
13789                 {
13790                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Need to check again\n"));
13791                         pDM_SWAT_Table->ANTA_ON=TRUE; // Set Antenna A on as default
13792                         pDM_SWAT_Table->ANTB_ON=FALSE; // Set Antenna B off as default
13793                         bResult = FALSE;
13794                 }
13795         }
13796         else if(pDM_Odm->SupportICType == ODM_RTL8723B)
13797         {
13798                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_A[%d]= %d \n", 2416, AntA_report));
13799                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_B[%d]= %d \n", 2416, AntB_report));
13800                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("psd_report_O[%d]= %d \n", 2416, AntO_report));
13801
13802                 //2 Test Ant B based on Ant A is ON
13803                 if(mode==ANTTESTB)
13804                 {
13805                         if(AntA_report >=100 && AntA_report <= 116)
13806                         {
13807                                 if(AntB_report >= (AntA_report+4) && AntB_report > 116)
13808                                 {
13809                                         pDM_SWAT_Table->ANTB_ON=FALSE;
13810                                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Single Antenna A\n"));
13811                                 }
13812                                 else if(AntB_report >=100 && AntB_report <= 116)
13813                                 {
13814                                         pDM_SWAT_Table->ANTB_ON=TRUE;
13815                                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Dual Antenna is A and B\n"));
13816                                 }
13817                                 else
13818                                 {
13819                                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Need to check again\n"));
13820                                         pDM_SWAT_Table->ANTB_ON=FALSE; // Set Antenna B off as default
13821                                         bResult = FALSE;
13822                                 }
13823                         }
13824                         else
13825                         {
13826                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Need to check again\n"));
13827                                 pDM_SWAT_Table->ANTB_ON=FALSE; // Set Antenna B off as default
13828                                 bResult = FALSE;
13829                         }
13830                 }
13831                 //2 Test Ant A and B based on DPDT Open
13832                 else if(mode==ANTTESTALL)
13833                 {
13834                         if((AntA_report >= 100) && (AntB_report >= 100) && (AntA_report <= 120) && (AntB_report <= 120))
13835                         {
13836                                 if((AntA_report - AntB_report < 2) || (AntB_report - AntA_report < 2))
13837                                 {
13838                                         pDM_SWAT_Table->ANTA_ON=TRUE;
13839                                         pDM_SWAT_Table->ANTB_ON=TRUE;
13840                                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("ODM_SingleDualAntennaDetection(): Dual Antenna\n"));
13841                                 }
13842                                 else if(((AntA_report - AntB_report >= 2) && (AntA_report - AntB_report <= 4)) ||
13843                                         ((AntB_report - AntA_report >= 2) && (AntB_report - AntA_report <= 4)))
13844                                 {
13845                                         pDM_SWAT_Table->ANTA_ON=FALSE;
13846                                         pDM_SWAT_Table->ANTB_ON=FALSE;
13847                                         bResult = FALSE;
13848                                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD, ("ODM_SingleDualAntennaDetection(): Need to check again\n"));
13849                                 }
13850                                 else
13851                                 {
13852                                         pDM_SWAT_Table->ANTA_ON = TRUE;
13853                                         pDM_SWAT_Table->ANTB_ON=FALSE;
13854                                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("ODM_SingleDualAntennaDetection(): Single Antenna A\n"));
13855                                 }
13856
13857                                 pDM_Odm->AntDetectedInfo.bAntDetected= TRUE;
13858                                 pDM_Odm->AntDetectedInfo.dBForAntA = AntA_report;
13859                                 pDM_Odm->AntDetectedInfo.dBForAntB = AntB_report;
13860                                 pDM_Odm->AntDetectedInfo.dBForAntO = AntO_report;
13861
13862                         }
13863                         else
13864                         {
13865                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_ANT_DIV, ODM_DBG_LOUD,("return FALSE!!\n"));
13866                                 bResult = FALSE;
13867                         }
13868                 }
13869         }
13870
13871         return bResult;
13872
13873 }
13874
13875
13876 #endif   // end odm_CE
13877
13878 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN| ODM_CE))
13879
13880 VOID
13881 odm_Set_RA_DM_ARFB_by_Noisy(
13882         IN      PDM_ODM_T       pDM_Odm
13883 )
13884 {
13885         //DbgPrint("DM_ARFB ====> \n");
13886         if (pDM_Odm->bNoisyState){
13887                 ODM_Write4Byte(pDM_Odm,0x430,0x00000000);
13888                 ODM_Write4Byte(pDM_Odm,0x434,0x05040200);
13889                 //DbgPrint("DM_ARFB ====> Noisy State\n");
13890         }
13891         else{
13892                 ODM_Write4Byte(pDM_Odm,0x430,0x02010000);
13893                 ODM_Write4Byte(pDM_Odm,0x434,0x07050403);
13894                 //DbgPrint("DM_ARFB ====> Clean State\n");
13895         }
13896
13897 }
13898
13899 VOID
13900 ODM_UpdateNoisyState(
13901         IN      PDM_ODM_T       pDM_Odm,
13902         IN      BOOLEAN         bNoisyStateFromC2H
13903         )
13904 {
13905         //DbgPrint("Get C2H Command! NoisyState=0x%x\n ", bNoisyStateFromC2H);
13906         if(pDM_Odm->SupportICType == ODM_RTL8821  || pDM_Odm->SupportICType == ODM_RTL8812  ||
13907            pDM_Odm->SupportICType == ODM_RTL8723B || pDM_Odm->SupportICType == ODM_RTL8192E || pDM_Odm->SupportICType == ODM_RTL8188E)
13908         {
13909                 pDM_Odm->bNoisyState = bNoisyStateFromC2H;
13910         }
13911         odm_Set_RA_DM_ARFB_by_Noisy(pDM_Odm);
13912 };
13913
13914 u4Byte
13915 Set_RA_DM_Ratrbitmap_by_Noisy(
13916         IN      PDM_ODM_T       pDM_Odm,
13917         IN      WIRELESS_MODE   WirelessMode,
13918         IN      u4Byte                  ratr_bitmap,
13919         IN      u1Byte                  rssi_level
13920 )
13921 {
13922         u4Byte ret_bitmap = ratr_bitmap;
13923         switch (WirelessMode)
13924         {
13925                 case WIRELESS_MODE_AC_24G :
13926                 case WIRELESS_MODE_AC_5G :
13927                 case WIRELESS_MODE_AC_ONLY:
13928                         if (pDM_Odm->bNoisyState){ // in Noisy State
13929                                 if (rssi_level==1)
13930                                         ret_bitmap&=0xfe3f0e08;
13931                                 else if (rssi_level==2)
13932                                         ret_bitmap&=0xff3f8f8c;
13933                                 else if (rssi_level==3)
13934                                         ret_bitmap&=0xffffffcc ;
13935                                 else
13936                                         ret_bitmap&=0xffffffff ;
13937                         }
13938                         else{                                   // in SNR State
13939                                 if (rssi_level==1){
13940                                         ret_bitmap&=0xfc3e0c08;
13941                                 }
13942                                 else if (rssi_level==2){
13943                                         ret_bitmap&=0xfe3f0e08;
13944                                 }
13945                                 else if (rssi_level==3){
13946                                         ret_bitmap&=0xffbfefcc;
13947                                 }
13948                                 else{
13949                                         ret_bitmap&=0x0fffffff;
13950                                 }
13951                         }
13952                         break;
13953                 case WIRELESS_MODE_B:
13954                 case WIRELESS_MODE_A:
13955                 case WIRELESS_MODE_G:
13956                 case WIRELESS_MODE_N_24G:
13957                 case WIRELESS_MODE_N_5G:
13958                         if (pDM_Odm->bNoisyState){
13959                                 if (rssi_level==1)
13960                                         ret_bitmap&=0x0f0e0c08;
13961                                 else if (rssi_level==2)
13962                                         ret_bitmap&=0x0f8f0e0c;
13963                                 else if (rssi_level==3)
13964                                         ret_bitmap&=0x0fefefcc ;
13965                                 else
13966                                         ret_bitmap&=0xffffffff ;
13967                         }
13968                         else{
13969                                 if (rssi_level==1){
13970                                         ret_bitmap&=0x0f8f0e08;
13971                                 }
13972                                 else if (rssi_level==2){
13973                                         ret_bitmap&=0x0fcf8f8c;
13974                                 }
13975                                 else if (rssi_level==3){
13976                                         ret_bitmap&=0x0fffffcc;
13977                                 }
13978                                 else{
13979                                         ret_bitmap&=0x0fffffff;
13980                                 }
13981                         }
13982                         break;
13983                 default:
13984                         break;
13985         }
13986         //DbgPrint("DM_RAMask ====> rssi_LV = %d, BITMAP = %x \n", rssi_level, ret_bitmap);
13987         return ret_bitmap;
13988
13989 }
13990
13991
13992
13993 VOID
13994 ODM_UpdateInitRate(
13995         IN      PDM_ODM_T       pDM_Odm,
13996         IN      u1Byte          Rate
13997         )
13998 {
13999         u1Byte                  p = 0;
14000
14001         ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("Get C2H Command! Rate=0x%x\n", Rate));
14002
14003         if(pDM_Odm->SupportICType == ODM_RTL8821  || pDM_Odm->SupportICType == ODM_RTL8812  ||
14004            pDM_Odm->SupportICType == ODM_RTL8723B || pDM_Odm->SupportICType == ODM_RTL8192E || pDM_Odm->SupportICType == ODM_RTL8188E)
14005         {
14006                 pDM_Odm->TxRate = Rate;
14007 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
14008         #if DEV_BUS_TYPE==RT_PCI_INTERFACE
14009                 #if USE_WORKITEM
14010                 PlatformScheduleWorkItem(&pDM_Odm->RaRptWorkitem);
14011                 #else
14012                 if(pDM_Odm->SupportICType == ODM_RTL8821)
14013                 {
14014                         ODM_TxPwrTrackSetPwr8821A(pDM_Odm, MIX_MODE, ODM_RF_PATH_A, 0);
14015                 }
14016                 else if(pDM_Odm->SupportICType == ODM_RTL8812)
14017                 {
14018                         for (p = ODM_RF_PATH_A; p < MAX_PATH_NUM_8812A; p++)
14019                         {
14020                                 ODM_TxPwrTrackSetPwr8812A(pDM_Odm, MIX_MODE, p, 0);
14021                         }
14022                 }
14023                 else if(pDM_Odm->SupportICType == ODM_RTL8723B)
14024                 {
14025                         ODM_TxPwrTrackSetPwr_8723B(pDM_Odm, MIX_MODE, ODM_RF_PATH_A, 0);
14026                 }
14027                 else if(pDM_Odm->SupportICType == ODM_RTL8192E)
14028                 {
14029                         for (p = ODM_RF_PATH_A; p < MAX_PATH_NUM_8192E; p++)
14030                         {
14031                                 ODM_TxPwrTrackSetPwr92E(pDM_Odm, MIX_MODE, p, 0);
14032                         }
14033                 }
14034                 else if(pDM_Odm->SupportICType == ODM_RTL8188E)
14035                 {
14036                         ODM_TxPwrTrackSetPwr88E(pDM_Odm, MIX_MODE, ODM_RF_PATH_A, 0);
14037                 }
14038                 #endif
14039         #else
14040                 PlatformScheduleWorkItem(&pDM_Odm->RaRptWorkitem);
14041         #endif
14042 #endif
14043         }
14044         else
14045                 return;
14046 }
14047
14048 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)
14049 VOID
14050 ODM_UpdateInitRateWorkItemCallback(
14051     IN PVOID            pContext
14052     )
14053 {
14054         PADAPTER        Adapter = (PADAPTER)pContext;
14055         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
14056         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;
14057
14058         u1Byte                  p = 0;
14059
14060         if(pDM_Odm->SupportICType == ODM_RTL8821)
14061         {
14062                 ODM_TxPwrTrackSetPwr8821A(pDM_Odm, MIX_MODE, ODM_RF_PATH_A, 0);
14063         }
14064         else if(pDM_Odm->SupportICType == ODM_RTL8812)
14065         {
14066                 for (p = ODM_RF_PATH_A; p < MAX_PATH_NUM_8812A; p++)    //DOn't know how to include &c
14067                 {
14068                         ODM_TxPwrTrackSetPwr8812A(pDM_Odm, MIX_MODE, p, 0);
14069                 }
14070         }
14071         else if(pDM_Odm->SupportICType == ODM_RTL8723B)
14072         {
14073                         ODM_TxPwrTrackSetPwr_8723B(pDM_Odm, MIX_MODE, ODM_RF_PATH_A, 0);
14074         }
14075         else if(pDM_Odm->SupportICType == ODM_RTL8192E)
14076         {
14077                 for (p = ODM_RF_PATH_A; p < MAX_PATH_NUM_8192E; p++)    //DOn't know how to include &c
14078                 {
14079                         ODM_TxPwrTrackSetPwr92E(pDM_Odm, MIX_MODE, p, 0);
14080                 }
14081         }
14082         else if(pDM_Odm->SupportICType == ODM_RTL8188E)
14083         {
14084                         ODM_TxPwrTrackSetPwr88E(pDM_Odm, MIX_MODE, ODM_RF_PATH_A, 0);
14085         }
14086 }
14087 #endif
14088 #endif
14089
14090 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)
14091 /* Justin: According to the current RRSI to adjust Response Frame TX power, 2012/11/05 */
14092 void odm_dtc(PDM_ODM_T pDM_Odm)
14093 {
14094 #ifdef CONFIG_DM_RESP_TXAGC
14095         #define DTC_BASE            35  /* RSSI higher than this value, start to decade TX power */
14096         #define DTC_DWN_BASE       (DTC_BASE-5) /* RSSI lower than this value, start to increase TX power */
14097
14098         /* RSSI vs TX power step mapping: decade TX power */
14099         static const u8 dtc_table_down[]={
14100                 DTC_BASE,
14101                 (DTC_BASE+5),
14102                 (DTC_BASE+10),
14103                 (DTC_BASE+15),
14104                 (DTC_BASE+20),
14105                 (DTC_BASE+25)
14106         };
14107
14108         /* RSSI vs TX power step mapping: increase TX power */
14109         static const u8 dtc_table_up[]={
14110                 DTC_DWN_BASE,
14111                 (DTC_DWN_BASE-5),
14112                 (DTC_DWN_BASE-10),
14113                 (DTC_DWN_BASE-15),
14114                 (DTC_DWN_BASE-15),
14115                 (DTC_DWN_BASE-20),
14116                 (DTC_DWN_BASE-20),
14117                 (DTC_DWN_BASE-25),
14118                 (DTC_DWN_BASE-25),
14119                 (DTC_DWN_BASE-30),
14120                 (DTC_DWN_BASE-35)
14121         };
14122
14123         u8 i;
14124         u8 dtc_steps=0;
14125         u8 sign;
14126         u8 resp_txagc=0;
14127
14128         #if 0
14129         /* As DIG is disabled, DTC is also disable */
14130         if(!(pDM_Odm->SupportAbility & ODM_XXXXXX))
14131                 return;
14132         #endif
14133
14134         if (DTC_BASE < pDM_Odm->RSSI_Min) {
14135                 /* need to decade the CTS TX power */
14136                 sign = 1;
14137                 for (i=0;i<ARRAY_SIZE(dtc_table_down);i++)
14138                 {
14139                         if ((dtc_table_down[i] >= pDM_Odm->RSSI_Min) || (dtc_steps >= 6))
14140                                 break;
14141                         else
14142                                 dtc_steps++;
14143                 }
14144         }
14145 #if 0
14146         else if (DTC_DWN_BASE > pDM_Odm->RSSI_Min)
14147         {
14148                 /* needs to increase the CTS TX power */
14149                 sign = 0;
14150                 dtc_steps = 1;
14151                 for (i=0;i<ARRAY_SIZE(dtc_table_up);i++)
14152                 {
14153                         if ((dtc_table_up[i] <= pDM_Odm->RSSI_Min) || (dtc_steps>=10))
14154                                 break;
14155                         else
14156                                 dtc_steps++;
14157                 }
14158         }
14159 #endif
14160         else
14161         {
14162                 sign = 0;
14163                 dtc_steps = 0;
14164         }
14165
14166         resp_txagc = dtc_steps | (sign << 4);
14167         resp_txagc = resp_txagc | (resp_txagc << 5);
14168         ODM_Write1Byte(pDM_Odm, 0x06d9, resp_txagc);
14169
14170         DBG_871X("%s RSSI_Min:%u, set RESP_TXAGC to %s %u\n",
14171                 __func__, pDM_Odm->RSSI_Min, sign?"minus":"plus", dtc_steps);
14172 #endif /* CONFIG_RESP_TXAGC_ADJUST */
14173 }
14174
14175 #endif /* #if (DM_ODM_SUPPORT_TYPE == ODM_CE) */
14176