drivers/net/wireless/rtl8723au/include/rtl8723a_spec.h

   1 /******************************************************************************\r
   2  *\r
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.\r
   4  *\r
   5  * This program is free software; you can redistribute it and/or modify it\r
   6  * under the terms of version 2 of the GNU General Public License as\r
   7  * published by the Free Software Foundation.\r
   8  *\r
   9  * This program is distributed in the hope that it will be useful, but WITHOUT\r
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
  12  * more details.\r
  13  *\r
  14  * You should have received a copy of the GNU General Public License along with\r
  15  * this program; if not, write to the Free Software Foundation, Inc.,\r
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA\r
  17  *\r
  18  *******************************************************************************/\r
  19 #ifndef __RTL8723A_SPEC_H__\r
  20 #define __RTL8723A_SPEC_H__\r
  21 \r
  22 #include <rtl8192c_spec.h>\r
  23 \r
  24 \r
  25 //============================================================================\r
  26 //      8723A Regsiter offset definition\r
  27 //============================================================================\r
  28 #define HAL_8723A_NAV_UPPER_UNIT        128             // micro-second\r
  29 \r
  30 //-----------------------------------------------------\r
  31 //\r
  32 //      0x0000h ~ 0x00FFh       System Configuration\r
  33 //\r
  34 //-----------------------------------------------------\r
  35 #define REG_SYSON_REG_LOCK              0x001C\r
  36 \r
  37 \r
  38 //-----------------------------------------------------\r
  39 //\r
  40 //      0x0100h ~ 0x01FFh       MACTOP General Configuration\r
  41 //\r
  42 //-----------------------------------------------------\r
  43 #define REG_FTIMR                       0x0138\r
  44 \r
  45 \r
  46 //-----------------------------------------------------\r
  47 //\r
  48 //      0x0200h ~ 0x027Fh       TXDMA Configuration\r
  49 //\r
  50 //-----------------------------------------------------\r
  51 \r
  52 \r
  53 //-----------------------------------------------------\r
  54 //\r
  55 //      0x0280h ~ 0x02FFh       RXDMA Configuration\r
  56 //\r
  57 //-----------------------------------------------------\r
  58 \r
  59 \r
  60 //-----------------------------------------------------\r
  61 //\r
  62 //      0x0300h ~ 0x03FFh       PCIe\r
  63 //\r
  64 //-----------------------------------------------------\r
  65 \r
  66 \r
  67 //-----------------------------------------------------\r
  68 //\r
  69 //      0x0400h ~ 0x047Fh       Protocol Configuration\r
  70 //\r
  71 //-----------------------------------------------------\r
  72 //#define REG_EARLY_MODE_CONTROL                0x4D0\r
  73 #define REG_MACID_NO_LINK 0x4D0\r
  74 \r
  75 //-----------------------------------------------------\r
  76 //\r
  77 //      0x0500h ~ 0x05FFh       EDCA Configuration\r
  78 //\r
  79 //-----------------------------------------------------\r
  80 \r
  81 //2 BCN_CTRL\r
  82 #define DIS_ATIM                                        BIT(0)\r
  83 #define DIS_BCNQ_SUB                            BIT(1)\r
  84 #define DIS_TSF_UDT                                     BIT(4)\r
  85 \r
  86 \r
  87 //-----------------------------------------------------\r
  88 //\r
  89 //      0x0600h ~ 0x07FFh       WMAC Configuration\r
  90 //\r
  91 //-----------------------------------------------------\r
  92 //\r
  93 // Note:\r
  94 //      The NAV upper value is very important to WiFi 11n 5.2.3 NAV test. The default value is\r
  95 //      always too small, but the WiFi TestPlan test by 25,000 microseconds of NAV through sending\r
  96 //      CTS in the air. We must update this value greater than 25,000 microseconds to pass the item.\r
  97 //      The offset of NAV_UPPER in 8192C Spec is incorrect, and the offset should be 0x0652. Commented\r
  98 //      by SD1 Scott.\r
  99 // By Bruce, 2011-07-18.\r
 100 //\r
 101 #define REG_NAV_UPPER                   0x0652  // unit of 128\r
 102 \r
 103 #define REG_BT_COEX_TABLE_1             0x06C0\r
 104 #define REG_BT_COEX_TABLE_2             0x06C4\r
 105 \r
 106 //============================================================================\r
 107 //      8723 Regsiter Bit and Content definition\r
 108 //============================================================================\r
 109 \r
 110 //-----------------------------------------------------\r
 111 //\r
 112 //      0x0000h ~ 0x00FFh       System Configuration\r
 113 //\r
 114 //-----------------------------------------------------\r
 115 \r
 116 //2 SPS0_CTRL\r
 117 \r
 118 //2 SYS_ISO_CTRL\r
 119 \r
 120 //2 SYS_FUNC_EN\r
 121 \r
 122 //2 APS_FSMCO\r
 123 #define EN_WLON                 BIT(16)\r
 124 \r
 125 //2 SYS_CLKR\r
 126 \r
 127 //2 9346CR\r
 128 \r
 129 //2 AFE_MISC\r
 130 \r
 131 //2 SPS0_CTRL\r
 132 \r
 133 //2 SPS_OCP_CFG\r
 134 \r
 135 //2 SYSON_REG_LOCK\r
 136 #define WLOCK_ALL               BIT(0)\r
 137 #define WLOCK_00                BIT(1)\r
 138 #define WLOCK_04                BIT(2)\r
 139 #define WLOCK_08                BIT(3)\r
 140 #define WLOCK_40                BIT(4)\r
 141 #define WLOCK_1C_B6             BIT(5)\r
 142 #define R_DIS_PRST_1            BIT(6)\r
 143 #define LOCK_ALL_EN             BIT(7)\r
 144 \r
 145 //2 RF_CTRL\r
 146 \r
 147 //2 LDOA15_CTRL\r
 148 \r
 149 //2 LDOV12D_CTRL\r
 150 \r
 151 //2 AFE_XTAL_CTRL\r
 152 \r
 153 //2 AFE_PLL_CTRL\r
 154 \r
 155 //2 EFUSE_CTRL\r
 156 \r
 157 //2 EFUSE_TEST (For RTL8723 partially)\r
 158 \r
 159 //2 PWR_DATA\r
 160 \r
 161 //2 CAL_TIMER\r
 162 \r
 163 //2 ACLK_MON\r
 164 \r
 165 //2 GPIO_MUXCFG\r
 166 \r
 167 //2 GPIO_PIN_CTRL\r
 168 \r
 169 //2 GPIO_INTM\r
 170 \r
 171 //2 LEDCFG\r
 172 \r
 173 //2 FSIMR\r
 174 \r
 175 //2 FSISR\r
 176 \r
 177 //2 HSIMR\r
 178 // 8723 Host System Interrupt Mask Register (offset 0x58, 32 byte)\r
 179 #define HSIMR_GPIO12_0_INT_EN   BIT(0)\r
 180 #define HSIMR_SPS_OCP_INT_EN    BIT(5)\r
 181 #define HSIMR_RON_INT_EN                BIT(6)\r
 182 #define HSIMR_PDNINT_EN         BIT(7)\r
 183 #define HSIMR_GPIO9_INT_EN              BIT(25)\r
 184 \r
 185 //2 HSISR\r
 186 // 8723 Host System Interrupt Status Register (offset 0x5C, 32 byte)\r
 187 #define HSISR_GPIO12_0_INT              BIT(0)\r
 188 #define HSISR_SPS_OCP_INT               BIT(5)\r
 189 #define HSISR_RON_INT                   BIT(6)\r
 190 #define HSISR_PDNINT                    BIT(7)\r
 191 #define HSISR_GPIO9_INT                 BIT(25)\r
 192 \r
 193 // interrupt mask which needs to clear\r
 194 #define MASK_HSISR_CLEAR                (HSISR_GPIO12_0_INT |\\r
 195                                                                 HSISR_SPS_OCP_INT |\\r
 196                                                                 HSISR_RON_INT |\\r
 197                                                                 HSISR_PDNINT |\\r
 198                                                                 HSISR_GPIO9_INT)\r
 199 \r
 200 //2 MCUFWDL\r
 201 #define RAM_DL_SEL                              BIT7    // 1:RAM, 0:ROM\r
 202 \r
 203 //2 HPON_FSM\r
 204 \r
 205 //2 SYS_CFG\r
 206 #define RTL_ID                                  BIT(23) // TestChip ID, 1:Test(RLE); 0:MP(RL)\r
 207 #define SPS_SEL                                 BIT(24) // 1:LDO regulator mode; 0:Switching regulator mode\r
 208 \r
 209 \r
 210 //-----------------------------------------------------\r
 211 //\r
 212 //      0x0100h ~ 0x01FFh       MACTOP General Configuration\r
 213 //\r
 214 //-----------------------------------------------------\r
 215 \r
 216 //2 Function Enable Registers\r
 217 \r
 218 //2 CR\r
 219 #define CALTMR_EN                                       BIT(10)\r
 220 \r
 221 //2 PBP - Page Size Register\r
 222 \r
 223 //2 TX/RXDMA\r
 224 \r
 225 //2 TRXFF_BNDY\r
 226 \r
 227 //2 LLT_INIT\r
 228 \r
 229 //2 BB_ACCESS_CTRL\r
 230 \r
 231 \r
 232 //-----------------------------------------------------\r
 233 //\r
 234 //      0x0200h ~ 0x027Fh       TXDMA Configuration\r
 235 //\r
 236 //-----------------------------------------------------\r
 237 \r
 238 //2 RQPN\r
 239 \r
 240 //2 TDECTRL\r
 241 \r
 242 //2 TDECTL\r
 243 \r
 244 //2 TXDMA_OFFSET_CHK\r
 245 \r
 246 \r
 247 //-----------------------------------------------------\r
 248 //\r
 249 //      0x0400h ~ 0x047Fh       Protocol Configuration\r
 250 //\r
 251 //-----------------------------------------------------\r
 252 \r
 253 //2 FWHW_TXQ_CTRL\r
 254 \r
 255 //2 INIRTSMCS_SEL\r
 256 \r
 257 //2 SPEC SIFS\r
 258 \r
 259 //2 RRSR\r
 260 \r
 261 //2 ARFR\r
 262 \r
 263 //2 AGGLEN_LMT_L\r
 264 \r
 265 //2 RL\r
 266 \r
 267 //2 DARFRC\r
 268 \r
 269 //2 RARFRC\r
 270 \r
 271 \r
 272 //-----------------------------------------------------\r
 273 //\r
 274 //      0x0500h ~ 0x05FFh       EDCA Configuration\r
 275 //\r
 276 //-----------------------------------------------------\r
 277 \r
 278 //2 EDCA setting\r
 279 \r
 280 //2 EDCA_VO_PARAM\r
 281 \r
 282 //2 SIFS_CCK\r
 283 \r
 284 //2 SIFS_OFDM\r
 285 \r
 286 //2 TBTT PROHIBIT\r
 287 \r
 288 //2 REG_RD_CTRL\r
 289 \r
 290 //2 BCN_CTRL\r
 291 \r
 292 //2 ACMHWCTRL\r
 293 \r
 294 \r
 295 //-----------------------------------------------------\r
 296 //\r
 297 //      0x0600h ~ 0x07FFh       WMAC Configuration\r
 298 //\r
 299 //-----------------------------------------------------\r
 300 \r
 301 //2 APSD_CTRL\r
 302 \r
 303 //2 BWOPMODE\r
 304 \r
 305 //2 TCR\r
 306 \r
 307 //2 RCR\r
 308 \r
 309 //2 RX_PKT_LIMIT\r
 310 \r
 311 //2 RX_DLK_TIME\r
 312 \r
 313 //2 MBIDCAMCFG\r
 314 \r
 315 //2 AMPDU_MIN_SPACE\r
 316 \r
 317 //2 RXERR_RPT\r
 318 \r
 319 //2 SECCFG\r
 320 \r
 321 \r
 322 //-----------------------------------------------------\r
 323 //\r
 324 //      0xFE00h ~ 0xFE55h       RTL8723 SDIO Configuration\r
 325 //\r
 326 //-----------------------------------------------------\r
 327 \r
 328 // I/O bus domain address mapping\r
 329 #define SDIO_LOCAL_BASE                         0x10250000\r
 330 #define WLAN_IOREG_BASE                         0x10260000\r
 331 #define FIRMWARE_FIFO_BASE                      0x10270000\r
 332 #define TX_HIQ_BASE                             0x10310000\r
 333 #define TX_MIQ_BASE                             0x10320000\r
 334 #define TX_LOQ_BASE                             0x10330000\r
 335 #define RX_RX0FF_BASE                           0x10340000\r
 336 \r
 337 // SDIO host local register space mapping.\r
 338 #define SDIO_LOCAL_MSK                          0x0FFF\r
 339 #define WLAN_IOREG_MSK                          0x7FFF\r
 340 #define WLAN_FIFO_MSK                           0x1FFF  // Aggregation Length[12:0]\r
 341 #define WLAN_RX0FF_MSK                          0x0003\r
 342 \r
 343 #define SDIO_WITHOUT_REF_DEVICE_ID              0       // Without reference to the SDIO Device ID\r
 344 #define SDIO_LOCAL_DEVICE_ID                    0       // 0b[16], 000b[15:13]\r
 345 #define WLAN_TX_HIQ_DEVICE_ID                   4       // 0b[16], 100b[15:13]\r
 346 #define WLAN_TX_MIQ_DEVICE_ID                   5       // 0b[16], 101b[15:13]\r
 347 #define WLAN_TX_LOQ_DEVICE_ID                   6       // 0b[16], 110b[15:13]\r
 348 #define WLAN_RX0FF_DEVICE_ID                    7       // 0b[16], 111b[15:13]\r
 349 #define WLAN_IOREG_DEVICE_ID                    8       // 1b[16]\r
 350 \r
 351 // SDIO Tx Free Page Index\r
 352 #define HI_QUEUE_IDX                            0\r
 353 #define MID_QUEUE_IDX                           1\r
 354 #define LOW_QUEUE_IDX                           2\r
 355 #define PUBLIC_QUEUE_IDX                        3\r
 356 \r
 357 #define SDIO_MAX_TX_QUEUE                       3               // HIQ, MIQ and LOQ\r
 358 #define SDIO_MAX_RX_QUEUE                       1\r
 359 \r
 360 #define SDIO_REG_TX_CTRL                        0x0000 // SDIO Tx Control\r
 361 #define SDIO_REG_HIMR                           0x0014 // SDIO Host Interrupt Mask\r
 362 #define SDIO_REG_HISR                           0x0018 // SDIO Host Interrupt Service Routine\r
 363 #define SDIO_REG_HCPWM                          0x0019 // HCI Current Power Mode\r
 364 #define SDIO_REG_RX0_REQ_LEN                    0x001C // RXDMA Request Length\r
 365 #define SDIO_REG_FREE_TXPG                      0x0020 // Free Tx Buffer Page\r
 366 #define SDIO_REG_HCPWM1                         0x0024 // HCI Current Power Mode 1\r
 367 #define SDIO_REG_HCPWM2                         0x0026 // HCI Current Power Mode 2\r
 368 #define SDIO_REG_HTSFR_INFO                     0x0030 // HTSF Informaion\r
 369 #define SDIO_REG_HRPWM1                         0x0080 // HCI Request Power Mode 1\r
 370 #define SDIO_REG_HRPWM2                         0x0082 // HCI Request Power Mode 2\r
 371 #define SDIO_REG_HPS_CLKR                       0x0084 // HCI Power Save Clock\r
 372 #define SDIO_REG_HSUS_CTRL                      0x0086 // SDIO HCI Suspend Control\r
 373 #define SDIO_REG_HIMR_ON                        0x0090 // SDIO Host Extension Interrupt Mask Always\r
 374 #define SDIO_REG_HISR_ON                        0x0091 // SDIO Host Extension Interrupt Status Always\r
 375 \r
 376 #define SDIO_HIMR_DISABLED                      0\r
 377 \r
 378 // SDIO Host Interrupt Mask Register\r
 379 #define SDIO_HIMR_RX_REQUEST_MSK                BIT0\r
 380 #define SDIO_HIMR_AVAL_MSK                      BIT1\r
 381 #define SDIO_HIMR_TXERR_MSK                     BIT2\r
 382 #define SDIO_HIMR_RXERR_MSK                     BIT3\r
 383 #define SDIO_HIMR_TXFOVW_MSK                    BIT4\r
 384 #define SDIO_HIMR_RXFOVW_MSK                    BIT5\r
 385 #define SDIO_HIMR_TXBCNOK_MSK                   BIT6\r
 386 #define SDIO_HIMR_TXBCNERR_MSK                  BIT7\r
 387 #define SDIO_HIMR_BCNERLY_INT_MSK               BIT16\r
 388 #define SDIO_HIMR_C2HCMD_MSK                    BIT17\r
 389 #define SDIO_HIMR_CPWM1_MSK                     BIT18\r
 390 #define SDIO_HIMR_CPWM2_MSK                     BIT19\r
 391 #define SDIO_HIMR_HSISR_IND_MSK                 BIT20\r
 392 #define SDIO_HIMR_GTINT3_IND_MSK                BIT21\r
 393 #define SDIO_HIMR_GTINT4_IND_MSK                BIT22\r
 394 #define SDIO_HIMR_PSTIMEOUT_MSK                 BIT23\r
 395 #define SDIO_HIMR_OCPINT_MSK                    BIT24\r
 396 #define SDIO_HIMR_ATIMEND_MSK                   BIT25\r
 397 #define SDIO_HIMR_ATIMEND_E_MSK                 BIT26\r
 398 #define SDIO_HIMR_CTWEND_MSK                    BIT27\r
 399 \r
 400 // SDIO Host Interrupt Service Routine\r
 401 #define SDIO_HISR_RX_REQUEST                    BIT0\r
 402 #define SDIO_HISR_AVAL                          BIT1\r
 403 #define SDIO_HISR_TXERR                         BIT2\r
 404 #define SDIO_HISR_RXERR                         BIT3\r
 405 #define SDIO_HISR_TXFOVW                        BIT4\r
 406 #define SDIO_HISR_RXFOVW                        BIT5\r
 407 #define SDIO_HISR_TXBCNOK                       BIT6\r
 408 #define SDIO_HISR_TXBCNERR                      BIT7\r
 409 #define SDIO_HISR_BCNERLY_INT                   BIT16\r
 410 #define SDIO_HISR_C2HCMD                        BIT17\r
 411 #define SDIO_HISR_CPWM1                         BIT18\r
 412 #define SDIO_HISR_CPWM2                         BIT19\r
 413 #define SDIO_HISR_HSISR_IND                     BIT20\r
 414 #define SDIO_HISR_GTINT3_IND                    BIT21\r
 415 #define SDIO_HISR_GTINT4_IND                    BIT22\r
 416 #define SDIO_HISR_PSTIMEOUT                     BIT23\r
 417 #define SDIO_HISR_OCPINT                        BIT24\r
 418 #define SDIO_HISR_ATIMEND                       BIT25\r
 419 #define SDIO_HISR_ATIMEND_E                     BIT26\r
 420 #define SDIO_HISR_CTWEND                        BIT27\r
 421 \r
 422 #define MASK_SDIO_HISR_CLEAR            (SDIO_HISR_TXERR |\\r
 423                                                                         SDIO_HISR_RXERR |\\r
 424                                                                         SDIO_HISR_TXFOVW |\\r
 425                                                                         SDIO_HISR_RXFOVW |\\r
 426                                                                         SDIO_HISR_TXBCNOK |\\r
 427                                                                         SDIO_HISR_TXBCNERR |\\r
 428                                                                         SDIO_HISR_C2HCMD |\\r
 429                                                                         SDIO_HISR_CPWM1 |\\r
 430                                                                         SDIO_HISR_CPWM2 |\\r
 431                                                                         SDIO_HISR_HSISR_IND |\\r
 432                                                                         SDIO_HISR_GTINT3_IND |\\r
 433                                                                         SDIO_HISR_GTINT4_IND |\\r
 434                                                                         SDIO_HISR_PSTIMEOUT |\\r
 435                                                                         SDIO_HISR_OCPINT)\r
 436 \r
 437 // SDIO HCI Suspend Control Register\r
 438 #define HCI_RESUME_PWR_RDY                      BIT1\r
 439 #define HCI_SUS_CTRL                            BIT0\r
 440 \r
 441 // SDIO Tx FIFO related\r
 442 #define SDIO_TX_FREE_PG_QUEUE                   4       // The number of Tx FIFO free page\r
 443 #define SDIO_TX_FIFO_PAGE_SZ                    128\r
 444 \r
 445 // vivi added for new cam search flow, 20091028\r
 446 #define SCR_TxUseBroadcastDK                    BIT6    // Force Tx Use Broadcast Default Key\r
 447 #define SCR_RxUseBroadcastDK                    BIT7    // Force Rx Use Broadcast Default Key\r
 448 \r
 449 \r
 450 //----------------------------------------------------------------------------\r
 451 // 8723 EFUSE\r
 452 //----------------------------------------------------------------------------\r
 453 #ifdef HWSET_MAX_SIZE\r
 454 #undef HWSET_MAX_SIZE\r
 455 #endif\r
 456 #define HWSET_MAX_SIZE                          256\r
 457 \r
 458 \r
 459 //-----------------------------------------------------------------------------\r
 460 //USB interrupt\r
 461 //-----------------------------------------------------------------------------\r
 462 #define UHIMR_TIMEOUT2                                  BIT31\r
 463 #define UHIMR_TIMEOUT1                                  BIT30\r
 464 #define UHIMR_PSTIMEOUT                                 BIT29\r
 465 #define UHIMR_GTINT4                                    BIT28\r
 466 #define UHIMR_GTINT3                                    BIT27\r
 467 #define UHIMR_TXBCNERR                                  BIT26\r
 468 #define UHIMR_TXBCNOK                                   BIT25\r
 469 #define UHIMR_TSF_BIT32_TOGGLE                  BIT24\r
 470 #define UHIMR_BCNDMAINT3                                BIT23\r
 471 #define UHIMR_BCNDMAINT2                                BIT22\r
 472 #define UHIMR_BCNDMAINT1                                BIT21\r
 473 #define UHIMR_BCNDMAINT0                                BIT20\r
 474 #define UHIMR_BCNDOK3                                   BIT19\r
 475 #define UHIMR_BCNDOK2                                   BIT18\r
 476 #define UHIMR_BCNDOK1                                   BIT17\r
 477 #define UHIMR_BCNDOK0                                   BIT16\r
 478 #define UHIMR_HSISR_IND                                 BIT15\r
 479 #define UHIMR_BCNDMAINT_E                               BIT14\r
 480 //RSVD  BIT13\r
 481 #define UHIMR_CTW_END                                   BIT12\r
 482 //RSVD  BIT11\r
 483 #define UHIMR_C2HCMD                                    BIT10\r
 484 #define UHIMR_CPWM2                                     BIT9\r
 485 #define UHIMR_CPWM                                      BIT8\r
 486 #define UHIMR_HIGHDOK                                   BIT7            // High Queue DMA OK Interrupt\r
 487 #define UHIMR_MGNTDOK                                   BIT6            // Management Queue DMA OK Interrupt\r
 488 #define UHIMR_BKDOK                                     BIT5            // AC_BK DMA OK Interrupt\r
 489 #define UHIMR_BEDOK                                     BIT4            // AC_BE DMA OK Interrupt\r
 490 #define UHIMR_VIDOK                                             BIT3            // AC_VI DMA OK Interrupt\r
 491 #define UHIMR_VODOK                                     BIT2            // AC_VO DMA Interrupt\r
 492 #define UHIMR_RDU                                               BIT1            // Receive Descriptor Unavailable\r
 493 #define UHIMR_ROK                                               BIT0            // Receive DMA OK Interrupt\r
 494 \r
 495 // USB Host Interrupt Status Extension bit\r
 496 #define UHIMR_BCNDMAINT7                                BIT23\r
 497 #define UHIMR_BCNDMAINT6                                BIT22\r
 498 #define UHIMR_BCNDMAINT5                                BIT21\r
 499 #define UHIMR_BCNDMAINT4                                BIT20\r
 500 #define UHIMR_BCNDOK7                                   BIT19\r
 501 #define UHIMR_BCNDOK6                                   BIT18\r
 502 #define UHIMR_BCNDOK5                                   BIT17\r
 503 #define UHIMR_BCNDOK4                                   BIT16\r
 504 // bit14-15: RSVD\r
 505 #define UHIMR_ATIMEND_E                         BIT13\r
 506 #define UHIMR_ATIMEND                                   BIT12\r
 507 #define UHIMR_TXERR                                             BIT11\r
 508 #define UHIMR_RXERR                                             BIT10\r
 509 #define UHIMR_TXFOVW                                    BIT9\r
 510 #define UHIMR_RXFOVW                                    BIT8\r
 511 // bit2-7: RSVD\r
 512 #define UHIMR_OCPINT                                    BIT1\r
 513 // bit0: RSVD\r
 514 \r
 515 #define REG_USB_HIMR                            0xFE38\r
 516 #define REG_USB_HIMRE                           0xFE3C\r
 517 #define REG_USB_HISR                                    0xFE78\r
 518 #define REG_USB_HISRE                           0xFE7C\r
 519 \r
 520 #define USB_INTR_CPWM_OFFSET            16\r
 521 #define USB_INTR_CONTENT_HISR_OFFSET            48\r
 522 #define USB_INTR_CONTENT_HISRE_OFFSET           52\r
 523 #define USB_INTR_CONTENT_LENGTH                 56\r
 524 #define USB_C2H_CMDID_OFFSET            0\r
 525 #define USB_C2H_SEQ_OFFSET              1\r
 526 #define USB_C2H_EVENT_OFFSET            2\r
 527 //============================================================================\r
 528 //      General definitions\r
 529 //============================================================================\r
 530 \r
 531 #ifdef CONFIG_RF_GAIN_OFFSET\r
 532 #define EEPROM_RF_GAIN_OFFSET                   0x2F\r
 533 #define EEPROM_RF_GAIN_VAL                              0x1F6\r
 534 #endif //CONFIG_RF_GAIN_OFFSET\r
 535 \r
 536 \r
 537 #endif\r
 538 \r