drivers/net/wireless/rtl8723au/include/pci_hal.h

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  *
  19  ******************************************************************************/
  20 #ifndef __PCI_HAL_H__
  21 #define __PCI_HAL_H__
  22
  23
  24 #define INTEL_VENDOR_ID                         0x8086
  25 #define SIS_VENDOR_ID                                   0x1039
  26 #define ATI_VENDOR_ID                                   0x1002
  27 #define ATI_DEVICE_ID                                   0x7914
  28 #define AMD_VENDOR_ID                                   0x1022
  29
  30 #define PCI_MAX_BRIDGE_NUMBER                   255
  31 #define PCI_MAX_DEVICES                         32
  32 #define PCI_MAX_FUNCTION                                8
  33
  34 #define PCI_CONF_ADDRESS                                0x0CF8   // PCI Configuration Space Address
  35 #define PCI_CONF_DATA                                   0x0CFC   // PCI Configuration Space Data
  36
  37 #define PCI_CLASS_BRIDGE_DEV                    0x06
  38 #define PCI_SUBCLASS_BR_PCI_TO_PCI      0x04
  39
  40 #define         PCI_CAPABILITY_ID_PCI_EXPRESS   0x10
  41
  42 #define U1DONTCARE                                      0xFF
  43 #define U2DONTCARE                                      0xFFFF
  44 #define U4DONTCARE                                      0xFFFFFFFF
  45
  46 #define PCI_VENDER_ID_REALTEK           0x10ec
  47
  48 #define HAL_HW_PCI_8180_DEVICE_ID               0x8180
  49 #define HAL_HW_PCI_8185_DEVICE_ID               0x8185  //8185 or 8185b
  50 #define HAL_HW_PCI_8188_DEVICE_ID               0x8188  //8185b
  51 #define HAL_HW_PCI_8198_DEVICE_ID               0x8198  //8185b
  52 #define HAL_HW_PCI_8190_DEVICE_ID               0x8190  //8190
  53 #define HAL_HW_PCI_8723E_DEVICE_ID              0x8723  //8723E
  54 #define HAL_HW_PCI_8192_DEVICE_ID               0x8192  //8192 PCI-E
  55 #define HAL_HW_PCI_8192SE_DEVICE_ID             0x8192  //8192 SE
  56 #define HAL_HW_PCI_8174_DEVICE_ID               0x8174  //8192 SE
  57 #define HAL_HW_PCI_8173_DEVICE_ID               0x8173  //8191 SE Crab
  58 #define HAL_HW_PCI_8172_DEVICE_ID               0x8172  //8191 SE RE
  59 #define HAL_HW_PCI_8171_DEVICE_ID               0x8171  //8191 SE Unicron
  60 #define HAL_HW_PCI_0045_DEVICE_ID                       0x0045  //8190 PCI for Ceraga
  61 #define HAL_HW_PCI_0046_DEVICE_ID                       0x0046  //8190 Cardbus for Ceraga
  62 #define HAL_HW_PCI_0044_DEVICE_ID                       0x0044  //8192e PCIE for Ceraga
  63 #define HAL_HW_PCI_0047_DEVICE_ID                       0x0047  //8192e Express Card for Ceraga
  64 #define HAL_HW_PCI_700F_DEVICE_ID                       0x700F
  65 #define HAL_HW_PCI_701F_DEVICE_ID                       0x701F
  66 #define HAL_HW_PCI_DLINK_DEVICE_ID              0x3304
  67 #define HAL_HW_PCI_8192CET_DEVICE_ID            0x8191  //8192ce
  68 #define HAL_HW_PCI_8192CE_DEVICE_ID             0x8178  //8192ce
  69 #define HAL_HW_PCI_8191CE_DEVICE_ID             0x8177  //8192ce
  70 #define HAL_HW_PCI_8188CE_DEVICE_ID             0x8176  //8192ce
  71 #define HAL_HW_PCI_8192CU_DEVICE_ID             0x8191  //8192ce
  72 #define HAL_HW_PCI_8192DE_DEVICE_ID             0x8193  //8192de
  73 #define HAL_HW_PCI_002B_DEVICE_ID                       0x002B  //8192de, provided by HW SD
  74 #define HAL_HW_PCI_8188EE_DEVICE_ID             0x8179
  75
  76 #define HAL_MEMORY_MAPPED_IO_RANGE_8190PCI              0x1000     //8190 support 16 pages of IO registers
  77 #define HAL_HW_PCI_REVISION_ID_8190PCI                  0x00
  78 #define HAL_MEMORY_MAPPED_IO_RANGE_8192PCIE     0x4000  //8192 support 16 pages of IO registers
  79 #define HAL_HW_PCI_REVISION_ID_8192PCIE                 0x01
  80 #define HAL_MEMORY_MAPPED_IO_RANGE_8192SE               0x4000  //8192 support 16 pages of IO registers
  81 #define HAL_HW_PCI_REVISION_ID_8192SE                   0x10
  82 #define HAL_HW_PCI_REVISION_ID_8192CE                   0x1
  83 #define HAL_MEMORY_MAPPED_IO_RANGE_8192CE               0x4000  //8192 support 16 pages of IO registers
  84 #define HAL_HW_PCI_REVISION_ID_8192DE                   0x0
  85 #define HAL_MEMORY_MAPPED_IO_RANGE_8192DE               0x4000  //8192 support 16 pages of IO registers
  86
  87 enum pci_bridge_vendor {
  88         PCI_BRIDGE_VENDOR_INTEL = 0x0,//0b'0000,0001
  89         PCI_BRIDGE_VENDOR_ATI, //= 0x02,//0b'0000,0010
  90         PCI_BRIDGE_VENDOR_AMD, //= 0x04,//0b'0000,0100
  91         PCI_BRIDGE_VENDOR_SIS ,//= 0x08,//0b'0000,1000
  92         PCI_BRIDGE_VENDOR_UNKNOWN, //= 0x40,//0b'0100,0000
  93         PCI_BRIDGE_VENDOR_MAX ,//= 0x80
  94 } ;
  95
  96 struct rt_pci_capabilities_header {
  97         u8      capability_id;
  98         u8      next;
  99 };
 100
 101 struct pci_priv{
 102         u8      linkctrl_reg;
 103
 104         u8      busnumber;
 105         u8      devnumber;
 106         u8      funcnumber;
 107
 108         u8      pcibridge_busnum;
 109         u8      pcibridge_devnum;
 110         u8      pcibridge_funcnum;
 111         u8      pcibridge_vendor;
 112         u16     pcibridge_vendorid;
 113         u16     pcibridge_deviceid;
 114         u8      pcibridge_pciehdr_offset;
 115         u8      pcibridge_linkctrlreg;
 116
 117         u8      amd_l1_patch;
 118 };
 119
 120 typedef struct _RT_ISR_CONTENT
 121 {
 122         union{
 123                 u32                     IntArray[2];
 124                 u32                     IntReg4Byte;
 125                 u16                     IntReg2Byte;
 126         };
 127 }RT_ISR_CONTENT, *PRT_ISR_CONTENT;
 128
 129 //#define RegAddr(addr)           (addr + 0xB2000000UL)
 130 //some platform macros will def here
 131 static inline void NdisRawWritePortUlong(u32 port,  u32 val)
 132 {
 133         outl(val, port);
 134         //writel(val, (u8 *)RegAddr(port));
 135 }
 136
 137 static inline void NdisRawWritePortUchar(u32 port,  u8 val)
 138 {
 139         outb(val, port);
 140         //writeb(val, (u8 *)RegAddr(port));
 141 }
 142
 143 static inline void NdisRawReadPortUchar(u32 port, u8 *pval)
 144 {
 145         *pval = inb(port);
 146         //*pval = readb((u8 *)RegAddr(port));
 147 }
 148
 149 static inline void NdisRawReadPortUshort(u32 port, u16 *pval)
 150 {
 151         *pval = inw(port);
 152         //*pval = readw((u8 *)RegAddr(port));
 153 }
 154
 155 static inline void NdisRawReadPortUlong(u32 port, u32 *pval)
 156 {
 157         *pval = inl(port);
 158         //*pval = readl((u8 *)RegAddr(port));
 159 }
 160
 161 #ifdef CONFIG_RTL8192C
 162 void rtl8192ce_set_hal_ops(_adapter * padapter);
 163 #define hal_set_hal_ops rtl8192ce_set_hal_ops
 164 #endif
 165 #ifdef CONFIG_RTL8192D
 166 void rtl8192de_set_hal_ops(_adapter * padapter);
 167 #define hal_set_hal_ops rtl8192de_set_hal_ops
 168 #endif
 169
 170
 171 #ifdef CONFIG_RTL8188E
 172 void rtl8188ee_set_hal_ops(_adapter * padapter);
 173 #define hal_set_hal_ops rtl8188ee_set_hal_ops
 174 #endif
 175
 176 #endif //__PCIE_HAL_H__
 177