1 /******************************************************************************
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
19 ******************************************************************************/
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20 /*****************************************************************************
\r
22 * Module: __INC_HAL8192DPHYREG_H
\r
25 * Note: 1. Define PMAC/BB register map
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26 * 2. Define RF register map
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27 * 3. PMAC/BB register bit mask.
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28 * 4. RF reg bit mask.
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29 * 5. Other BB/RF relative definition.
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32 * Export: Constants, macro, functions(API), global variables(None).
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38 * 08/07/2007 MHC 1. Porting from 9x series PHYCFG.h.
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39 * 2. Reorganize code architecture.
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40 * 09/25/2008 MH 1. Add RL6052 register definition
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42 *****************************************************************************/
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43 #ifndef __INC_HAL8192DPHYREG_H
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44 #define __INC_HAL8192DPHYREG_H
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47 /*--------------------------Define Parameters-------------------------------*/
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49 //============================================================
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50 // 8192S Regsiter offset definition
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51 //============================================================
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54 // BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF
\r
55 // 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
\r
56 // 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00
\r
57 // 3. RF register 0x00-2E
\r
58 // 4. Bit Mask for BB/RF register
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59 // 5. Other defintion for BB/RF R/W
\r
64 // 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
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67 #define rPMAC_Reset 0x100
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68 #define rPMAC_TxStart 0x104
\r
69 #define rPMAC_TxLegacySIG 0x108
\r
70 #define rPMAC_TxHTSIG1 0x10c
\r
71 #define rPMAC_TxHTSIG2 0x110
\r
72 #define rPMAC_PHYDebug 0x114
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73 #define rPMAC_TxPacketNum 0x118
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74 #define rPMAC_TxIdle 0x11c
\r
75 #define rPMAC_TxMACHeader0 0x120
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76 #define rPMAC_TxMACHeader1 0x124
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77 #define rPMAC_TxMACHeader2 0x128
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78 #define rPMAC_TxMACHeader3 0x12c
\r
79 #define rPMAC_TxMACHeader4 0x130
\r
80 #define rPMAC_TxMACHeader5 0x134
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81 #define rPMAC_TxDataType 0x138
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82 #define rPMAC_TxRandomSeed 0x13c
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83 #define rPMAC_CCKPLCPPreamble 0x140
\r
84 #define rPMAC_CCKPLCPHeader 0x144
\r
85 #define rPMAC_CCKCRC16 0x148
\r
86 #define rPMAC_OFDMRxCRC32OK 0x170
\r
87 #define rPMAC_OFDMRxCRC32Er 0x174
\r
88 #define rPMAC_OFDMRxParityEr 0x178
\r
89 #define rPMAC_OFDMRxCRC8Er 0x17c
\r
90 #define rPMAC_CCKCRxRC16Er 0x180
\r
91 #define rPMAC_CCKCRxRC32Er 0x184
\r
92 #define rPMAC_CCKCRxRC32OK 0x188
\r
93 #define rPMAC_TxStatus 0x18c
\r
98 // The following two definition are only used for USB interface.
\r
99 #define RF_BB_CMD_ADDR 0x02c0 // RF/BB read/write command address.
\r
100 #define RF_BB_CMD_DATA 0x02c4 // RF/BB read/write command data.
\r
105 #define rFPGA0_RFMOD 0x800 //RF mode & CCK TxSC // RF BW Setting??
\r
107 #define rFPGA0_TxInfo 0x804 // Status report??
\r
108 #define rFPGA0_PSDFunction 0x808
\r
110 #define rFPGA0_TxGainStage 0x80c // Set TX PWR init gain?
\r
112 #define rFPGA0_RFTiming1 0x810 // Useless now
\r
113 #define rFPGA0_RFTiming2 0x814
\r
115 #define rFPGA0_XA_HSSIParameter1 0x820 // RF 3 wire register
\r
116 #define rFPGA0_XA_HSSIParameter2 0x824
\r
117 #define rFPGA0_XB_HSSIParameter1 0x828
\r
118 #define rFPGA0_XB_HSSIParameter2 0x82c
\r
120 #define rFPGA0_XA_LSSIParameter 0x840
\r
121 #define rFPGA0_XB_LSSIParameter 0x844
\r
123 #define rFPGA0_RFWakeUpParameter 0x850 // Useless now
\r
124 #define rFPGA0_RFSleepUpParameter 0x854
\r
126 #define rFPGA0_XAB_SwitchControl 0x858 // RF Channel switch
\r
127 #define rFPGA0_XCD_SwitchControl 0x85c
\r
129 #define rFPGA0_XA_RFInterfaceOE 0x860 // RF Channel switch
\r
130 #define rFPGA0_XB_RFInterfaceOE 0x864
\r
132 #define rFPGA0_XAB_RFInterfaceSW 0x870 // RF Interface Software Control
\r
133 #define rFPGA0_XCD_RFInterfaceSW 0x874
\r
135 #define rFPGA0_XAB_RFParameter 0x878 // RF Parameter
\r
136 #define rFPGA0_XCD_RFParameter 0x87c
\r
138 #define rFPGA0_AnalogParameter1 0x880 // Crystal cap setting RF-R/W protection for parameter4??
\r
139 #define rFPGA0_AnalogParameter2 0x884
\r
140 #define rFPGA0_AnalogParameter3 0x888
\r
141 #define rFPGA0_AdDaClockEn 0x888 // enable ad/da clock1 for dual-phy
\r
142 #define rFPGA0_AnalogParameter4 0x88c
\r
144 #define rFPGA0_XA_LSSIReadBack 0x8a0 // Tranceiver LSSI Readback
\r
145 #define rFPGA0_XB_LSSIReadBack 0x8a4
\r
146 #define rFPGA0_XC_LSSIReadBack 0x8a8
\r
147 #define rFPGA0_XD_LSSIReadBack 0x8ac
\r
149 #define rFPGA0_PSDReport 0x8b4 // Useless now
\r
150 #define TransceiverA_HSPI_Readback 0x8b8 // Transceiver A HSPI Readback
\r
151 #define TransceiverB_HSPI_Readback 0x8bc // Transceiver B HSPI Readback
\r
152 #define rFPGA0_XAB_RFInterfaceRB 0x8e0 // Useless now // RF Interface Readback Value
\r
153 #define rFPGA0_XCD_RFInterfaceRB 0x8e4 // Useless now
\r
158 #define rFPGA1_RFMOD 0x900 //RF mode & OFDM TxSC // RF BW Setting??
\r
160 #define rFPGA1_TxBlock 0x904 // Useless now
\r
161 #define rFPGA1_DebugSelect 0x908 // Useless now
\r
162 #define rFPGA1_TxInfo 0x90c // Useless now // Status report??
\r
167 // Set Control channel to upper or lower. These settings are required only for 40MHz
\r
168 #define rCCK0_System 0xa00
\r
170 #define rCCK0_AFESetting 0xa04 // Disable init gain now // Select RX path by RSSI
\r
171 #define rCCK0_CCA 0xa08 // Disable init gain now // Init gain
\r
173 #define rCCK0_RxAGC1 0xa0c //AGC default value, saturation level // Antenna Diversity, RX AGC, LNA Threshold, RX LNA Threshold useless now. Not the same as 90 series
\r
174 #define rCCK0_RxAGC2 0xa10 //AGC & DAGC
\r
176 #define rCCK0_RxHP 0xa14
\r
178 #define rCCK0_DSPParameter1 0xa18 //Timing recovery & Channel estimation threshold
\r
179 #define rCCK0_DSPParameter2 0xa1c //SQ threshold
\r
181 #define rCCK0_TxFilter1 0xa20
\r
182 #define rCCK0_TxFilter2 0xa24
\r
183 #define rCCK0_DebugPort 0xa28 //debug port and Tx filter3
\r
184 #define rCCK0_FalseAlarmReport 0xa2c //0xa2d useless now 0xa30-a4f channel report
\r
185 #define rCCK0_TRSSIReport 0xa50
\r
186 #define rCCK0_RxReport 0xa54 //0xa57
\r
187 #define rCCK0_FACounterLower 0xa5c //0xa5b
\r
188 #define rCCK0_FACounterUpper 0xa58 //0xa5c
\r
193 #define rPdp_AntA 0xb00
\r
194 #define rPdp_AntA_4 0xb04
\r
195 #define rPdp_AntA_8 0xb08
\r
196 #define rPdp_AntA_C 0xb0c
\r
197 #define rPdp_AntA_10 0xb10
\r
198 #define rPdp_AntA_14 0xb14
\r
199 #define rPdp_AntA_18 0xb18
\r
200 #define rPdp_AntA_1C 0xb1c
\r
201 #define rPdp_AntA_20 0xb20
\r
202 #define rPdp_AntA_24 0xb24
\r
204 #define rConfig_Pmpd_AntA 0xb28
\r
205 #define rConfig_ram64x16 0xb2c
\r
207 #define rBndA 0xb30
\r
208 #define rHssiPar 0xb34
\r
210 #define rConfig_AntA 0xb68
\r
211 #define rConfig_AntB 0xb6c
\r
213 #define rPdp_AntB 0xb70
\r
214 #define rPdp_AntB_4 0xb74
\r
215 #define rPdp_AntB_8 0xb78
\r
216 #define rPdp_AntB_C 0xb7c
\r
217 #define rPdp_AntB_10 0xb80
\r
218 #define rPdp_AntB_14 0xb84
\r
219 #define rPdp_AntB_18 0xb88
\r
220 #define rPdp_AntB_1C 0xb8c
\r
221 #define rPdp_AntB_20 0xb90
\r
222 #define rPdp_AntB_24 0xb94
\r
224 #define rConfig_Pmpd_AntB 0xb98
\r
226 #define rBndB 0xba0
\r
229 #define rPm_Rx0_AntA 0xbdc
\r
230 #define rPm_Rx1_AntA 0xbe0
\r
231 #define rPm_Rx2_AntA 0xbe4
\r
232 #define rPm_Rx3_AntA 0xbe8
\r
233 #define rPm_Rx0_AntB 0xbec
\r
234 #define rPm_Rx1_AntB 0xbf0
\r
235 #define rPm_Rx2_AntB 0xbf4
\r
236 #define rPm_Rx3_AntB 0xbf8
\r
241 #define rOFDM0_LSTF 0xc00
\r
243 #define rOFDM0_TRxPathEnable 0xc04
\r
244 #define rOFDM0_TRMuxPar 0xc08
\r
245 #define rOFDM0_TRSWIsolation 0xc0c
\r
247 #define rOFDM0_XARxAFE 0xc10 //RxIQ DC offset, Rx digital filter, DC notch filter
\r
248 #define rOFDM0_XARxIQImbalance 0xc14 //RxIQ imblance matrix
\r
249 #define rOFDM0_XBRxAFE 0xc18
\r
250 #define rOFDM0_XBRxIQImbalance 0xc1c
\r
251 #define rOFDM0_XCRxAFE 0xc20
\r
252 #define rOFDM0_XCRxIQImbalance 0xc24
\r
253 #define rOFDM0_XDRxAFE 0xc28
\r
254 #define rOFDM0_XDRxIQImbalance 0xc2c
\r
256 #define rOFDM0_RxDetector1 0xc30 //PD,BW & SBD // DM tune init gain
\r
257 #define rOFDM0_RxDetector2 0xc34 //SBD & Fame Sync.
\r
258 #define rOFDM0_RxDetector3 0xc38 //Frame Sync.
\r
259 #define rOFDM0_RxDetector4 0xc3c //PD, SBD, Frame Sync & Short-GI
\r
261 #define rOFDM0_RxDSP 0xc40 //Rx Sync Path
\r
262 #define rOFDM0_CFOandDAGC 0xc44 //CFO & DAGC
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263 #define rOFDM0_CCADropThreshold 0xc48 //CCA Drop threshold
\r
264 #define rOFDM0_ECCAThreshold 0xc4c // energy CCA
\r
266 #define rOFDM0_XAAGCCore1 0xc50 // DIG
\r
267 #define rOFDM0_XAAGCCore2 0xc54
\r
268 #define rOFDM0_XBAGCCore1 0xc58
\r
269 #define rOFDM0_XBAGCCore2 0xc5c
\r
270 #define rOFDM0_XCAGCCore1 0xc60
\r
271 #define rOFDM0_XCAGCCore2 0xc64
\r
272 #define rOFDM0_XDAGCCore1 0xc68
\r
273 #define rOFDM0_XDAGCCore2 0xc6c
\r
275 #define rOFDM0_AGCParameter1 0xc70
\r
276 #define rOFDM0_AGCParameter2 0xc74
\r
277 #define rOFDM0_AGCRSSITable 0xc78
\r
278 #define rOFDM0_HTSTFAGC 0xc7c
\r
280 #define rOFDM0_XATxIQImbalance 0xc80 // TX PWR TRACK and DIG
\r
281 #define rOFDM0_XATxAFE 0xc84
\r
282 #define rOFDM0_XBTxIQImbalance 0xc88
\r
283 #define rOFDM0_XBTxAFE 0xc8c
\r
284 #define rOFDM0_XCTxIQImbalance 0xc90
\r
285 #define rOFDM0_XCTxAFE 0xc94
\r
286 #define rOFDM0_XDTxIQImbalance 0xc98
\r
287 #define rOFDM0_XDTxAFE 0xc9c
\r
289 #define rOFDM0_RxIQExtAnta 0xca0
\r
290 #define rOFDM0_TxCoeff1 0xca4
\r
291 #define rOFDM0_TxCoeff2 0xca8
\r
292 #define rOFDM0_TxCoeff3 0xcac
\r
293 #define rOFDM0_TxCoeff4 0xcb0
\r
294 #define rOFDM0_TxCoeff5 0xcb4
\r
295 #define rOFDM0_TxCoeff6 0xcb8
\r
296 #define rOFDM0_RxHPParameter 0xce0
\r
297 #define rOFDM0_TxPseudoNoiseWgt 0xce4
\r
298 #define rOFDM0_FrameSync 0xcf0
\r
299 #define rOFDM0_DFSReport 0xcf4
\r
304 #define rOFDM1_LSTF 0xd00
\r
305 #define rOFDM1_TRxPathEnable 0xd04
\r
307 #define rOFDM1_CFO 0xd08 // No setting now
\r
308 #define rOFDM1_CSI1 0xd10
\r
309 #define rOFDM1_SBD 0xd14
\r
310 #define rOFDM1_CSI2 0xd18
\r
311 #define rOFDM1_CFOTracking 0xd2c
\r
312 #define rOFDM1_TRxMesaure1 0xd34
\r
313 #define rOFDM1_IntfDet 0xd3c
\r
314 #define rOFDM1_PseudoNoiseStateAB 0xd50
\r
315 #define rOFDM1_PseudoNoiseStateCD 0xd54
\r
316 #define rOFDM1_RxPseudoNoiseWgt 0xd58
\r
318 #define rOFDM_PHYCounter1 0xda0 //cca, parity fail
\r
319 #define rOFDM_PHYCounter2 0xda4 //rate illegal, crc8 fail
\r
320 #define rOFDM_PHYCounter3 0xda8 //MCS not support
\r
322 #define rOFDM_ShortCFOAB 0xdac // No setting now
\r
323 #define rOFDM_ShortCFOCD 0xdb0
\r
324 #define rOFDM_LongCFOAB 0xdb4
\r
325 #define rOFDM_LongCFOCD 0xdb8
\r
326 #define rOFDM_TailCFOAB 0xdbc
\r
327 #define rOFDM_TailCFOCD 0xdc0
\r
328 #define rOFDM_PWMeasure1 0xdc4
\r
329 #define rOFDM_PWMeasure2 0xdc8
\r
330 #define rOFDM_BWReport 0xdcc
\r
331 #define rOFDM_AGCReport 0xdd0
\r
332 #define rOFDM_RxSNR 0xdd4
\r
333 #define rOFDM_RxEVMCSI 0xdd8
\r
334 #define rOFDM_SIGReport 0xddc
\r
340 #define rTxAGC_A_Rate18_06 0xe00
\r
341 #define rTxAGC_A_Rate54_24 0xe04
\r
342 #define rTxAGC_A_CCK1_Mcs32 0xe08
\r
343 #define rTxAGC_A_Mcs03_Mcs00 0xe10
\r
344 #define rTxAGC_A_Mcs07_Mcs04 0xe14
\r
345 #define rTxAGC_A_Mcs11_Mcs08 0xe18
\r
346 #define rTxAGC_A_Mcs15_Mcs12 0xe1c
\r
348 #define rTxAGC_B_Rate18_06 0x830
\r
349 #define rTxAGC_B_Rate54_24 0x834
\r
350 #define rTxAGC_B_CCK1_55_Mcs32 0x838
\r
351 #define rTxAGC_B_Mcs03_Mcs00 0x83c
\r
352 #define rTxAGC_B_Mcs07_Mcs04 0x848
\r
353 #define rTxAGC_B_Mcs11_Mcs08 0x84c
\r
354 #define rTxAGC_B_Mcs15_Mcs12 0x868
\r
355 #define rTxAGC_B_CCK11_A_CCK2_11 0x86c
\r
357 #define rFPGA0_IQK 0xe28
\r
358 #define rTx_IQK_Tone_A 0xe30
\r
359 #define rRx_IQK_Tone_A 0xe34
\r
360 #define rTx_IQK_PI_A 0xe38
\r
361 #define rRx_IQK_PI_A 0xe3c
\r
363 #define rTx_IQK 0xe40
\r
364 #define rRx_IQK 0xe44
\r
365 #define rIQK_AGC_Pts 0xe48
\r
366 #define rIQK_AGC_Rsp 0xe4c
\r
367 #define rTx_IQK_Tone_B 0xe50
\r
368 #define rRx_IQK_Tone_B 0xe54
\r
369 #define rTx_IQK_PI_B 0xe58
\r
370 #define rRx_IQK_PI_B 0xe5c
\r
371 #define rIQK_AGC_Cont 0xe60
\r
373 #define rBlue_Tooth 0xe6c
\r
374 #define rRx_Wait_CCA 0xe70
\r
375 #define rTx_CCK_RFON 0xe74
\r
376 #define rTx_CCK_BBON 0xe78
\r
377 #define rTx_OFDM_RFON 0xe7c
\r
378 #define rTx_OFDM_BBON 0xe80
\r
379 #define rTx_To_Rx 0xe84
\r
380 #define rTx_To_Tx 0xe88
\r
381 #define rRx_CCK 0xe8c
\r
383 #define rTx_Power_Before_IQK_A 0xe94
\r
384 #define rTx_Power_After_IQK_A 0xe9c
\r
386 #define rRx_Power_Before_IQK_A 0xea0
\r
387 #define rRx_Power_Before_IQK_A_2 0xea4
\r
388 #define rRx_Power_After_IQK_A 0xea8
\r
389 #define rRx_Power_After_IQK_A_2 0xeac
\r
391 #define rTx_Power_Before_IQK_B 0xeb4
\r
392 #define rTx_Power_After_IQK_B 0xebc
\r
394 #define rRx_Power_Before_IQK_B 0xec0
\r
395 #define rRx_Power_Before_IQK_B_2 0xec4
\r
396 #define rRx_Power_After_IQK_B 0xec8
\r
397 #define rRx_Power_After_IQK_B_2 0xecc
\r
399 #define rRx_OFDM 0xed0
\r
400 #define rRx_Wait_RIFS 0xed4
\r
401 #define rRx_TO_Rx 0xed8
\r
402 #define rStandby 0xedc
\r
403 #define rSleep 0xee0
\r
404 #define rPMPD_ANAEN 0xeec
\r
407 // 7. RF Register 0x00-0x2E (RF 8256)
\r
408 // RF-0222D 0x00-3F
\r
411 #define rZebra1_HSSIEnable 0x0 // Useless now
\r
412 #define rZebra1_TRxEnable1 0x1
\r
413 #define rZebra1_TRxEnable2 0x2
\r
414 #define rZebra1_AGC 0x4
\r
415 #define rZebra1_ChargePump 0x5
\r
416 #define rZebra1_Channel 0x7 // RF channel switch
\r
419 #define rZebra1_TxGain 0x8 // Useless now
\r
420 #define rZebra1_TxLPF 0x9
\r
421 #define rZebra1_RxLPF 0xb
\r
422 #define rZebra1_RxHPFCorner 0xc
\r
425 #define rGlobalCtrl 0 // Useless now
\r
426 #define rRTL8256_TxLPF 19
\r
427 #define rRTL8256_RxLPF 11
\r
430 #define rRTL8258_TxLPF 0x11 // Useless now
\r
431 #define rRTL8258_RxLPF 0x13
\r
432 #define rRTL8258_RSSILPF 0xa
\r
435 // RL6052 Register definition
\r
437 #define RF_AC 0x00 //
\r
439 #define RF_IQADJ_G1 0x01 //
\r
440 #define RF_IQADJ_G2 0x02 //
\r
441 #define RF_BS_PA_APSET_G1_G4 0x03
\r
442 #define RF_BS_PA_APSET_G5_G8 0x04
\r
443 #define RF_POW_TRSW 0x05 //
\r
445 #define RF_GAIN_RX 0x06 //
\r
446 #define RF_GAIN_TX 0x07 //
\r
448 #define RF_TXM_IDAC 0x08 //
\r
449 #define RF_IPA_G 0x09 //
\r
450 #define RF_TXBIAS_G 0x0A
\r
451 #define RF_TXPA_AG 0x0B
\r
452 #define RF_IPA_A 0x0C //
\r
453 #define RF_TXBIAS_A 0x0D
\r
454 #define RF_BS_PA_APSET_G9_G11 0x0E
\r
455 #define RF_BS_IQGEN 0x0F //
\r
457 #define RF_MODE1 0x10 //
\r
458 #define RF_MODE2 0x11 //
\r
460 #define RF_RX_AGC_HP 0x12 //
\r
461 #define RF_TX_AGC 0x13 //
\r
462 #define RF_BIAS 0x14 //
\r
463 #define RF_IPA 0x15 //
\r
464 #define RF_TXBIAS 0x16 //
\r
465 #define RF_POW_ABILITY 0x17 //
\r
466 #define RF_MODE_AG 0x18 //
\r
467 #define rRfChannel 0x18 // RF channel and BW switch
\r
468 #define RF_CHNLBW 0x18 // RF channel and BW switch
\r
469 #define RF_TOP 0x19 //
\r
471 #define RF_RX_G1 0x1A //
\r
472 #define RF_RX_G2 0x1B //
\r
474 #define RF_RX_BB2 0x1C //
\r
475 #define RF_RX_BB1 0x1D //
\r
477 #define RF_RCK1 0x1E //
\r
478 #define RF_RCK2 0x1F //
\r
480 #define RF_TX_G1 0x20 //
\r
481 #define RF_TX_G2 0x21 //
\r
482 #define RF_TX_G3 0x22 //
\r
484 #define RF_TX_BB1 0x23 //
\r
486 #define RF_T_METER 0x42 //
\r
488 #define RF_SYN_G1 0x25 // RF TX Power control
\r
489 #define RF_SYN_G2 0x26 // RF TX Power control
\r
490 #define RF_SYN_G3 0x27 // RF TX Power control
\r
491 #define RF_SYN_G4 0x28 // RF TX Power control
\r
492 #define RF_SYN_G5 0x29 // RF TX Power control
\r
493 #define RF_SYN_G6 0x2A // RF TX Power control
\r
494 #define RF_SYN_G7 0x2B // RF TX Power control
\r
495 #define RF_SYN_G8 0x2C // RF TX Power control
\r
497 #define RF_RCK_OS 0x30 // RF TX PA control
\r
499 #define RF_TXPA_G1 0x31 // RF TX PA control
\r
500 #define RF_TXPA_G2 0x32 // RF TX PA control
\r
501 #define RF_TXPA_G3 0x33 // RF TX PA control
\r
502 #define RF_LOBF_9 0x38
\r
503 #define RF_RXRF_A3 0x3C //
\r
504 #define RF_TRSW 0x3F
\r
506 #define RF_TXRF_A2 0x41
\r
507 #define RF_TXPA_G4 0x46
\r
508 #define RF_TXPA_A4 0x4B
\r
514 #define bBBResetB 0x100 // Useless now?
\r
515 #define bGlobalResetB 0x200
\r
516 #define bOFDMTxStart 0x4
\r
517 #define bCCKTxStart 0x8
\r
518 #define bCRC32Debug 0x100
\r
519 #define bPMACLoopback 0x10
\r
520 #define bTxLSIG 0xffffff
\r
521 #define bOFDMTxRate 0xf
\r
522 #define bOFDMTxReserved 0x10
\r
523 #define bOFDMTxLength 0x1ffe0
\r
524 #define bOFDMTxParity 0x20000
\r
525 #define bTxHTSIG1 0xffffff
\r
526 #define bTxHTMCSRate 0x7f
\r
527 #define bTxHTBW 0x80
\r
528 #define bTxHTLength 0xffff00
\r
529 #define bTxHTSIG2 0xffffff
\r
530 #define bTxHTSmoothing 0x1
\r
531 #define bTxHTSounding 0x2
\r
532 #define bTxHTReserved 0x4
\r
533 #define bTxHTAggreation 0x8
\r
534 #define bTxHTSTBC 0x30
\r
535 #define bTxHTAdvanceCoding 0x40
\r
536 #define bTxHTShortGI 0x80
\r
537 #define bTxHTNumberHT_LTF 0x300
\r
538 #define bTxHTCRC8 0x3fc00
\r
539 #define bCounterReset 0x10000
\r
540 #define bNumOfOFDMTx 0xffff
\r
541 #define bNumOfCCKTx 0xffff0000
\r
542 #define bTxIdleInterval 0xffff
\r
543 #define bOFDMService 0xffff0000
\r
544 #define bTxMACHeader 0xffffffff
\r
545 #define bTxDataInit 0xff
\r
546 #define bTxHTMode 0x100
\r
547 #define bTxDataType 0x30000
\r
548 #define bTxRandomSeed 0xffffffff
\r
549 #define bCCKTxPreamble 0x1
\r
550 #define bCCKTxSFD 0xffff0000
\r
551 #define bCCKTxSIG 0xff
\r
552 #define bCCKTxService 0xff00
\r
553 #define bCCKLengthExt 0x8000
\r
554 #define bCCKTxLength 0xffff0000
\r
555 #define bCCKTxCRC16 0xffff
\r
556 #define bCCKTxStatus 0x1
\r
557 #define bOFDMTxStatus 0x2
\r
559 #define IS_BB_REG_OFFSET_92S(_Offset) ((_Offset >= 0x800) && (_Offset <= 0xfff))
\r
562 #define bRFMOD 0x1 // Reg 0x800 rFPGA0_RFMOD
\r
563 #define bJapanMode 0x2
\r
564 #define bCCKTxSC 0x30
\r
565 #define bCCKEn 0x1000000
\r
566 #define bOFDMEn 0x2000000
\r
568 #define bOFDMRxADCPhase 0x10000 // Useless now
\r
569 #define bOFDMTxDACPhase 0x40000
\r
570 #define bXATxAGC 0x3f
\r
572 #define bAntennaSelect 0x0300
\r
574 #define bXBTxAGC 0xf00 // Reg 80c rFPGA0_TxGainStage
\r
575 #define bXCTxAGC 0xf000
\r
576 #define bXDTxAGC 0xf0000
\r
578 #define bPAStart 0xf0000000 // Useless now
\r
579 #define bTRStart 0x00f00000
\r
580 #define bRFStart 0x0000f000
\r
581 #define bBBStart 0x000000f0
\r
582 #define bBBCCKStart 0x0000000f
\r
583 #define bPAEnd 0xf //Reg0x814
\r
584 #define bTREnd 0x0f000000
\r
585 #define bRFEnd 0x000f0000
\r
586 #define bCCAMask 0x000000f0 //T2R
\r
587 #define bR2RCCAMask 0x00000f00
\r
588 #define bHSSI_R2TDelay 0xf8000000
\r
589 #define bHSSI_T2RDelay 0xf80000
\r
590 #define bContTxHSSI 0x400 //chane gain at continue Tx
\r
591 #define bIGFromCCK 0x200
\r
592 #define bAGCAddress 0x3f
\r
593 #define bRxHPTx 0x7000
\r
594 #define bRxHPT2R 0x38000
\r
595 #define bRxHPCCKIni 0xc0000
\r
596 #define bAGCTxCode 0xc00000
\r
597 #define bAGCRxCode 0x300000
\r
599 #define b3WireDataLength 0x800 // Reg 0x820~84f rFPGA0_XA_HSSIParameter1
\r
600 #define b3WireAddressLength 0x400
\r
602 #define b3WireRFPowerDown 0x1 // Useless now
\r
603 //#define bHWSISelect 0x8
\r
604 #define b5GPAPEPolarity 0x40000000
\r
605 #define b2GPAPEPolarity 0x80000000
\r
606 #define bRFSW_TxDefaultAnt 0x3
\r
607 #define bRFSW_TxOptionAnt 0x30
\r
608 #define bRFSW_RxDefaultAnt 0x300
\r
609 #define bRFSW_RxOptionAnt 0x3000
\r
610 #define bRFSI_3WireData 0x1
\r
611 #define bRFSI_3WireClock 0x2
\r
612 #define bRFSI_3WireLoad 0x4
\r
613 #define bRFSI_3WireRW 0x8
\r
614 #define bRFSI_3Wire 0xf
\r
616 #define bRFSI_RFENV 0x10 // Reg 0x870 rFPGA0_XAB_RFInterfaceSW
\r
618 #define bRFSI_TRSW 0x20 // Useless now
\r
619 #define bRFSI_TRSWB 0x40
\r
620 #define bRFSI_ANTSW 0x100
\r
621 #define bRFSI_ANTSWB 0x200
\r
622 #define bRFSI_PAPE 0x400
\r
623 #define bRFSI_PAPE5G 0x800
\r
624 #define bBandSelect 0x1
\r
625 #define bHTSIG2_GI 0x80
\r
626 #define bHTSIG2_Smoothing 0x01
\r
627 #define bHTSIG2_Sounding 0x02
\r
628 #define bHTSIG2_Aggreaton 0x08
\r
629 #define bHTSIG2_STBC 0x30
\r
630 #define bHTSIG2_AdvCoding 0x40
\r
631 #define bHTSIG2_NumOfHTLTF 0x300
\r
632 #define bHTSIG2_CRC8 0x3fc
\r
633 #define bHTSIG1_MCS 0x7f
\r
634 #define bHTSIG1_BandWidth 0x80
\r
635 #define bHTSIG1_HTLength 0xffff
\r
636 #define bLSIG_Rate 0xf
\r
637 #define bLSIG_Reserved 0x10
\r
638 #define bLSIG_Length 0x1fffe
\r
639 #define bLSIG_Parity 0x20
\r
640 #define bCCKRxPhase 0x4
\r
642 #define bLSSIReadAddress 0x7f800000 // T65 RF
\r
644 #define bLSSIReadEdge 0x80000000 //LSSI "Read" edge signal
\r
646 #define bLSSIReadBackData 0xfffff // T65 RF
\r
648 #define bLSSIReadOKFlag 0x1000 // Useless now
\r
649 #define bCCKSampleRate 0x8 //0: 44MHz, 1:88MHz
\r
650 #define bRegulator0Standby 0x1
\r
651 #define bRegulatorPLLStandby 0x2
\r
652 #define bRegulator1Standby 0x4
\r
653 #define bPLLPowerUp 0x8
\r
654 #define bDPLLPowerUp 0x10
\r
655 #define bDA10PowerUp 0x20
\r
656 #define bAD7PowerUp 0x200
\r
657 #define bDA6PowerUp 0x2000
\r
658 #define bXtalPowerUp 0x4000
\r
659 #define b40MDClkPowerUP 0x8000
\r
660 #define bDA6DebugMode 0x20000
\r
661 #define bDA6Swing 0x380000
\r
663 #define bADClkPhase 0x4000000 // Reg 0x880 rFPGA0_AnalogParameter1 20/40 CCK support switch 40/80 BB MHZ
\r
665 #define b80MClkDelay 0x18000000 // Useless
\r
666 #define bAFEWatchDogEnable 0x20000000
\r
668 #define bXtalCap01 0xc0000000 // Reg 0x884 rFPGA0_AnalogParameter2 Crystal cap
\r
669 #define bXtalCap23 0x3
\r
670 #define bXtalCap92x 0x0f000000
\r
671 #define bXtalCap 0x0f000000
\r
673 #define bIntDifClkEnable 0x400 // Useless
\r
674 #define bExtSigClkEnable 0x800
\r
675 #define bBandgapMbiasPowerUp 0x10000
\r
676 #define bAD11SHGain 0xc0000
\r
677 #define bAD11InputRange 0x700000
\r
678 #define bAD11OPCurrent 0x3800000
\r
679 #define bIPathLoopback 0x4000000
\r
680 #define bQPathLoopback 0x8000000
\r
681 #define bAFELoopback 0x10000000
\r
682 #define bDA10Swing 0x7e0
\r
683 #define bDA10Reverse 0x800
\r
684 #define bDAClkSource 0x1000
\r
685 #define bAD7InputRange 0x6000
\r
686 #define bAD7Gain 0x38000
\r
687 #define bAD7OutputCMMode 0x40000
\r
688 #define bAD7InputCMMode 0x380000
\r
689 #define bAD7Current 0xc00000
\r
690 #define bRegulatorAdjust 0x7000000
\r
691 #define bAD11PowerUpAtTx 0x1
\r
692 #define bDA10PSAtTx 0x10
\r
693 #define bAD11PowerUpAtRx 0x100
\r
694 #define bDA10PSAtRx 0x1000
\r
695 #define bCCKRxAGCFormat 0x200
\r
696 #define bPSDFFTSamplepPoint 0xc000
\r
697 #define bPSDAverageNum 0x3000
\r
698 #define bIQPathControl 0xc00
\r
699 #define bPSDFreq 0x3ff
\r
700 #define bPSDAntennaPath 0x30
\r
701 #define bPSDIQSwitch 0x40
\r
702 #define bPSDRxTrigger 0x400000
\r
703 #define bPSDTxTrigger 0x80000000
\r
704 #define bPSDSineToneScale 0x7f000000
\r
705 #define bPSDReport 0xffff
\r
708 #define bOFDMTxSC 0x30000000 // Useless
\r
709 #define bCCKTxOn 0x1
\r
710 #define bOFDMTxOn 0x2
\r
711 #define bDebugPage 0xfff //reset debug page and also HWord, LWord
\r
712 #define bDebugItem 0xff //reset debug page and LWord
\r
714 #define bAntNonHT 0x100
\r
715 #define bAntHT1 0x1000
\r
716 #define bAntHT2 0x10000
\r
717 #define bAntHT1S1 0x100000
\r
718 #define bAntNonHTS1 0x1000000
\r
721 #define bCCKBBMode 0x3 // Useless
\r
722 #define bCCKTxPowerSaving 0x80
\r
723 #define bCCKRxPowerSaving 0x40
\r
725 #define bCCKSideBand 0x10 // Reg 0xa00 rCCK0_System 20/40 switch
\r
727 #define bCCKScramble 0x8 // Useless
\r
728 #define bCCKAntDiversity 0x8000
\r
729 #define bCCKCarrierRecovery 0x4000
\r
730 #define bCCKTxRate 0x3000
\r
731 #define bCCKDCCancel 0x0800
\r
732 #define bCCKISICancel 0x0400
\r
733 #define bCCKMatchFilter 0x0200
\r
734 #define bCCKEqualizer 0x0100
\r
735 #define bCCKPreambleDetect 0x800000
\r
736 #define bCCKFastFalseCCA 0x400000
\r
737 #define bCCKChEstStart 0x300000
\r
738 #define bCCKCCACount 0x080000
\r
739 #define bCCKcs_lim 0x070000
\r
740 #define bCCKBistMode 0x80000000
\r
741 #define bCCKCCAMask 0x40000000
\r
742 #define bCCKTxDACPhase 0x4
\r
743 #define bCCKRxADCPhase 0x20000000 //r_rx_clk
\r
744 #define bCCKr_cp_mode0 0x0100
\r
745 #define bCCKTxDCOffset 0xf0
\r
746 #define bCCKRxDCOffset 0xf
\r
747 #define bCCKCCAMode 0xc000
\r
748 #define bCCKFalseCS_lim 0x3f00
\r
749 #define bCCKCS_ratio 0xc00000
\r
750 #define bCCKCorgBit_sel 0x300000
\r
751 #define bCCKPD_lim 0x0f0000
\r
752 #define bCCKNewCCA 0x80000000
\r
753 #define bCCKRxHPofIG 0x8000
\r
754 #define bCCKRxIG 0x7f00
\r
755 #define bCCKLNAPolarity 0x800000
\r
756 #define bCCKRx1stGain 0x7f0000
\r
757 #define bCCKRFExtend 0x20000000 //CCK Rx Iinital gain polarity
\r
758 #define bCCKRxAGCSatLevel 0x1f000000
\r
759 #define bCCKRxAGCSatCount 0xe0
\r
760 #define bCCKRxRFSettle 0x1f //AGCsamp_dly
\r
761 #define bCCKFixedRxAGC 0x8000
\r
762 //#define bCCKRxAGCFormat 0x4000 //remove to HSSI register 0x824
\r
763 #define bCCKAntennaPolarity 0x2000
\r
764 #define bCCKTxFilterType 0x0c00
\r
765 #define bCCKRxAGCReportType 0x0300
\r
766 #define bCCKRxDAGCEn 0x80000000
\r
767 #define bCCKRxDAGCPeriod 0x20000000
\r
768 #define bCCKRxDAGCSatLevel 0x1f000000
\r
769 #define bCCKTimingRecovery 0x800000
\r
770 #define bCCKTxC0 0x3f0000
\r
771 #define bCCKTxC1 0x3f000000
\r
772 #define bCCKTxC2 0x3f
\r
773 #define bCCKTxC3 0x3f00
\r
774 #define bCCKTxC4 0x3f0000
\r
775 #define bCCKTxC5 0x3f000000
\r
776 #define bCCKTxC6 0x3f
\r
777 #define bCCKTxC7 0x3f00
\r
778 #define bCCKDebugPort 0xff0000
\r
779 #define bCCKDACDebug 0x0f000000
\r
780 #define bCCKFalseAlarmEnable 0x8000
\r
781 #define bCCKFalseAlarmRead 0x4000
\r
782 #define bCCKTRSSI 0x7f
\r
783 #define bCCKRxAGCReport 0xfe
\r
784 #define bCCKRxReport_AntSel 0x80000000
\r
785 #define bCCKRxReport_MFOff 0x40000000
\r
786 #define bCCKRxRxReport_SQLoss 0x20000000
\r
787 #define bCCKRxReport_Pktloss 0x10000000
\r
788 #define bCCKRxReport_Lockedbit 0x08000000
\r
789 #define bCCKRxReport_RateError 0x04000000
\r
790 #define bCCKRxReport_RxRate 0x03000000
\r
791 #define bCCKRxFACounterLower 0xff
\r
792 #define bCCKRxFACounterUpper 0xff000000
\r
793 #define bCCKRxHPAGCStart 0xe000
\r
794 #define bCCKRxHPAGCFinal 0x1c00
\r
795 #define bCCKRxFalseAlarmEnable 0x8000
\r
796 #define bCCKFACounterFreeze 0x4000
\r
797 #define bCCKTxPathSel 0x10000000
\r
798 #define bCCKDefaultRxPath 0xc000000
\r
799 #define bCCKOptionRxPath 0x3000000
\r
802 #define bNumOfSTF 0x3 // Useless
\r
803 #define bShift_L 0xc0
\r
805 #define bRxPathA 0x1
\r
806 #define bRxPathB 0x2
\r
807 #define bRxPathC 0x4
\r
808 #define bRxPathD 0x8
\r
809 #define bTxPathA 0x1
\r
810 #define bTxPathB 0x2
\r
811 #define bTxPathC 0x4
\r
812 #define bTxPathD 0x8
\r
813 #define bTRSSIFreq 0x200
\r
814 #define bADCBackoff 0x3000
\r
815 #define bDFIRBackoff 0xc000
\r
816 #define bTRSSILatchPhase 0x10000
\r
817 #define bRxIDCOffset 0xff
\r
818 #define bRxQDCOffset 0xff00
\r
819 #define bRxDFIRMode 0x1800000
\r
820 #define bRxDCNFType 0xe000000
\r
821 #define bRXIQImb_A 0x3ff
\r
822 #define bRXIQImb_B 0xfc00
\r
823 #define bRXIQImb_C 0x3f0000
\r
824 #define bRXIQImb_D 0xffc00000
\r
825 #define bDC_dc_Notch 0x60000
\r
826 #define bRxNBINotch 0x1f000000
\r
828 #define bPD_TH_Opt2 0xc000
\r
829 #define bPWED_TH 0x700
\r
830 #define bIfMF_Win_L 0x800
\r
831 #define bPD_Option 0x1000
\r
832 #define bMF_Win_L 0xe000
\r
833 #define bBW_Search_L 0x30000
\r
834 #define bwin_enh_L 0xc0000
\r
835 #define bBW_TH 0x700000
\r
836 #define bED_TH2 0x3800000
\r
837 #define bBW_option 0x4000000
\r
838 #define bRatio_TH 0x18000000
\r
839 #define bWindow_L 0xe0000000
\r
840 #define bSBD_Option 0x1
\r
841 #define bFrame_TH 0x1c
\r
842 #define bFS_Option 0x60
\r
843 #define bDC_Slope_check 0x80
\r
844 #define bFGuard_Counter_DC_L 0xe00
\r
845 #define bFrame_Weight_Short 0x7000
\r
846 #define bSub_Tune 0xe00000
\r
847 #define bFrame_DC_Length 0xe000000
\r
848 #define bSBD_start_offset 0x30000000
\r
849 #define bFrame_TH_2 0x7
\r
850 #define bFrame_GI2_TH 0x38
\r
851 #define bGI2_Sync_en 0x40
\r
852 #define bSarch_Short_Early 0x300
\r
853 #define bSarch_Short_Late 0xc00
\r
854 #define bSarch_GI2_Late 0x70000
\r
855 #define bCFOAntSum 0x1
\r
856 #define bCFOAcc 0x2
\r
857 #define bCFOStartOffset 0xc
\r
858 #define bCFOLookBack 0x70
\r
859 #define bCFOSumWeight 0x80
\r
860 #define bDAGCEnable 0x10000
\r
861 #define bTXIQImb_A 0x3ff
\r
862 #define bTXIQImb_B 0xfc00
\r
863 #define bTXIQImb_C 0x3f0000
\r
864 #define bTXIQImb_D 0xffc00000
\r
865 #define bTxIDCOffset 0xff
\r
866 #define bTxQDCOffset 0xff00
\r
867 #define bTxDFIRMode 0x10000
\r
868 #define bTxPesudoNoiseOn 0x4000000
\r
869 #define bTxPesudoNoise_A 0xff
\r
870 #define bTxPesudoNoise_B 0xff00
\r
871 #define bTxPesudoNoise_C 0xff0000
\r
872 #define bTxPesudoNoise_D 0xff000000
\r
873 #define bCCADropOption 0x20000
\r
874 #define bCCADropThres 0xfff00000
\r
875 #define bEDCCA_H 0xf
\r
876 #define bEDCCA_L 0xf0
\r
877 #define bLambda_ED 0x300
\r
878 #define bRxInitialGain 0x7f
\r
879 #define bRxAntDivEn 0x80
\r
880 #define bRxAGCAddressForLNA 0x7f00
\r
881 #define bRxHighPowerFlow 0x8000
\r
882 #define bRxAGCFreezeThres 0xc0000
\r
883 #define bRxFreezeStep_AGC1 0x300000
\r
884 #define bRxFreezeStep_AGC2 0xc00000
\r
885 #define bRxFreezeStep_AGC3 0x3000000
\r
886 #define bRxFreezeStep_AGC0 0xc000000
\r
887 #define bRxRssi_Cmp_En 0x10000000
\r
888 #define bRxQuickAGCEn 0x20000000
\r
889 #define bRxAGCFreezeThresMode 0x40000000
\r
890 #define bRxOverFlowCheckType 0x80000000
\r
891 #define bRxAGCShift 0x7f
\r
892 #define bTRSW_Tri_Only 0x80
\r
893 #define bPowerThres 0x300
\r
894 #define bRxAGCEn 0x1
\r
895 #define bRxAGCTogetherEn 0x2
\r
896 #define bRxAGCMin 0x4
\r
897 #define bRxHP_Ini 0x7
\r
898 #define bRxHP_TRLNA 0x70
\r
899 #define bRxHP_RSSI 0x700
\r
900 #define bRxHP_BBP1 0x7000
\r
901 #define bRxHP_BBP2 0x70000
\r
902 #define bRxHP_BBP3 0x700000
\r
903 #define bRSSI_H 0x7f0000 //the threshold for high power
\r
904 #define bRSSI_Gen 0x7f000000 //the threshold for ant diversity
\r
905 #define bRxSettle_TRSW 0x7
\r
906 #define bRxSettle_LNA 0x38
\r
907 #define bRxSettle_RSSI 0x1c0
\r
908 #define bRxSettle_BBP 0xe00
\r
909 #define bRxSettle_RxHP 0x7000
\r
910 #define bRxSettle_AntSW_RSSI 0x38000
\r
911 #define bRxSettle_AntSW 0xc0000
\r
912 #define bRxProcessTime_DAGC 0x300000
\r
913 #define bRxSettle_HSSI 0x400000
\r
914 #define bRxProcessTime_BBPPW 0x800000
\r
915 #define bRxAntennaPowerShift 0x3000000
\r
916 #define bRSSITableSelect 0xc000000
\r
917 #define bRxHP_Final 0x7000000
\r
918 #define bRxHTSettle_BBP 0x7
\r
919 #define bRxHTSettle_HSSI 0x8
\r
920 #define bRxHTSettle_RxHP 0x70
\r
921 #define bRxHTSettle_BBPPW 0x80
\r
922 #define bRxHTSettle_Idle 0x300
\r
923 #define bRxHTSettle_Reserved 0x1c00
\r
924 #define bRxHTRxHPEn 0x8000
\r
925 #define bRxHTAGCFreezeThres 0x30000
\r
926 #define bRxHTAGCTogetherEn 0x40000
\r
927 #define bRxHTAGCMin 0x80000
\r
928 #define bRxHTAGCEn 0x100000
\r
929 #define bRxHTDAGCEn 0x200000
\r
930 #define bRxHTRxHP_BBP 0x1c00000
\r
931 #define bRxHTRxHP_Final 0xe0000000
\r
932 #define bRxPWRatioTH 0x3
\r
933 #define bRxPWRatioEn 0x4
\r
934 #define bRxMFHold 0x3800
\r
935 #define bRxPD_Delay_TH1 0x38
\r
936 #define bRxPD_Delay_TH2 0x1c0
\r
937 #define bRxPD_DC_COUNT_MAX 0x600
\r
938 //#define bRxMF_Hold 0x3800
\r
939 #define bRxPD_Delay_TH 0x8000
\r
940 #define bRxProcess_Delay 0xf0000
\r
941 #define bRxSearchrange_GI2_Early 0x700000
\r
942 #define bRxFrame_Guard_Counter_L 0x3800000
\r
943 #define bRxSGI_Guard_L 0xc000000
\r
944 #define bRxSGI_Search_L 0x30000000
\r
945 #define bRxSGI_TH 0xc0000000
\r
946 #define bDFSCnt0 0xff
\r
947 #define bDFSCnt1 0xff00
\r
948 #define bDFSFlag 0xf0000
\r
949 #define bMFWeightSum 0x300000
\r
950 #define bMinIdxTH 0x7f000000
\r
951 #define bDAFormat 0x40000
\r
952 #define bTxChEmuEnable 0x01000000
\r
953 #define bTRSWIsolation_A 0x7f
\r
954 #define bTRSWIsolation_B 0x7f00
\r
955 #define bTRSWIsolation_C 0x7f0000
\r
956 #define bTRSWIsolation_D 0x7f000000
\r
957 #define bExtLNAGain 0x7c00
\r
960 #define bSTBCEn 0x4 // Useless
\r
961 #define bAntennaMapping 0x10
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963 #define bCFOAntSumD 0x200
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964 #define bPHYCounterReset 0x8000000
\r
965 #define bCFOReportGet 0x4000000
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966 #define bOFDMContinueTx 0x10000000
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967 #define bOFDMSingleCarrier 0x20000000
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968 #define bOFDMSingleTone 0x40000000
\r
969 //#define bRxPath1 0x01
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970 //#define bRxPath2 0x02
\r
971 //#define bRxPath3 0x04
\r
972 //#define bRxPath4 0x08
\r
973 //#define bTxPath1 0x10
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974 //#define bTxPath2 0x20
\r
975 #define bHTDetect 0x100
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976 #define bCFOEn 0x10000
\r
977 #define bCFOValue 0xfff00000
\r
978 #define bSigTone_Re 0x3f
\r
979 #define bSigTone_Im 0x7f00
\r
980 #define bCounter_CCA 0xffff
\r
981 #define bCounter_ParityFail 0xffff0000
\r
982 #define bCounter_RateIllegal 0xffff
\r
983 #define bCounter_CRC8Fail 0xffff0000
\r
984 #define bCounter_MCSNoSupport 0xffff
\r
985 #define bCounter_FastSync 0xffff
\r
986 #define bShortCFO 0xfff
\r
987 #define bShortCFOTLength 12 //total
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988 #define bShortCFOFLength 11 //fraction
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989 #define bLongCFO 0x7ff
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990 #define bLongCFOTLength 11
\r
991 #define bLongCFOFLength 11
\r
992 #define bTailCFO 0x1fff
\r
993 #define bTailCFOTLength 13
\r
994 #define bTailCFOFLength 12
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995 #define bmax_en_pwdB 0xffff
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996 #define bCC_power_dB 0xffff0000
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997 #define bnoise_pwdB 0xffff
\r
998 #define bPowerMeasTLength 10
\r
999 #define bPowerMeasFLength 3
\r
1000 #define bRx_HT_BW 0x1
\r
1002 #define bRx_HT 0x8
\r
1003 #define bNB_intf_det_on 0x1
\r
1004 #define bIntf_win_len_cfg 0x30
\r
1005 #define bNB_Intf_TH_cfg 0x1c0
\r
1006 #define bRFGain 0x3f
\r
1007 #define bTableSel 0x40
\r
1008 #define bTRSW 0x80
\r
1009 #define bRxSNR_A 0xff
\r
1010 #define bRxSNR_B 0xff00
\r
1011 #define bRxSNR_C 0xff0000
\r
1012 #define bRxSNR_D 0xff000000
\r
1013 #define bSNREVMTLength 8
\r
1014 #define bSNREVMFLength 1
\r
1015 #define bCSI1st 0xff
\r
1016 #define bCSI2nd 0xff00
\r
1017 #define bRxEVM1st 0xff0000
\r
1018 #define bRxEVM2nd 0xff000000
\r
1019 #define bSIGEVM 0xff
\r
1020 #define bPWDB 0xff00
\r
1021 #define bSGIEN 0x10000
\r
1023 #define bSFactorQAM1 0xf // Useless
\r
1024 #define bSFactorQAM2 0xf0
\r
1025 #define bSFactorQAM3 0xf00
\r
1026 #define bSFactorQAM4 0xf000
\r
1027 #define bSFactorQAM5 0xf0000
\r
1028 #define bSFactorQAM6 0xf0000
\r
1029 #define bSFactorQAM7 0xf00000
\r
1030 #define bSFactorQAM8 0xf000000
\r
1031 #define bSFactorQAM9 0xf0000000
\r
1032 #define bCSIScheme 0x100000
\r
1034 #define bNoiseLvlTopSet 0x3 // Useless
\r
1035 #define bChSmooth 0x4
\r
1036 #define bChSmoothCfg1 0x38
\r
1037 #define bChSmoothCfg2 0x1c0
\r
1038 #define bChSmoothCfg3 0xe00
\r
1039 #define bChSmoothCfg4 0x7000
\r
1040 #define bMRCMode 0x800000
\r
1041 #define bTHEVMCfg 0x7000000
\r
1043 #define bLoopFitType 0x1 // Useless
\r
1044 #define bUpdCFO 0x40
\r
1045 #define bUpdCFOOffData 0x80
\r
1046 #define bAdvUpdCFO 0x100
\r
1047 #define bAdvTimeCtrl 0x800
\r
1048 #define bUpdClko 0x1000
\r
1049 #define bFC 0x6000
\r
1050 #define bTrackingMode 0x8000
\r
1051 #define bPhCmpEnable 0x10000
\r
1052 #define bUpdClkoLTF 0x20000
\r
1053 #define bComChCFO 0x40000
\r
1054 #define bCSIEstiMode 0x80000
\r
1055 #define bAdvUpdEqz 0x100000
\r
1056 #define bUChCfg 0x7000000
\r
1057 #define bUpdEqz 0x8000000
\r
1060 #define bRxPesudoNoiseOn 0x20000000 // Useless
\r
1061 #define bRxPesudoNoise_A 0xff
\r
1062 #define bRxPesudoNoise_B 0xff00
\r
1063 #define bRxPesudoNoise_C 0xff0000
\r
1064 #define bRxPesudoNoise_D 0xff000000
\r
1065 #define bPesudoNoiseState_A 0xffff
\r
1066 #define bPesudoNoiseState_B 0xffff0000
\r
1067 #define bPesudoNoiseState_C 0xffff
\r
1068 #define bPesudoNoiseState_D 0xffff0000
\r
1072 #define bZebra1_HSSIEnable 0x8 // Useless
\r
1073 #define bZebra1_TRxControl 0xc00
\r
1074 #define bZebra1_TRxGainSetting 0x07f
\r
1075 #define bZebra1_RxCorner 0xc00
\r
1076 #define bZebra1_TxChargePump 0x38
\r
1077 #define bZebra1_RxChargePump 0x7
\r
1078 #define bZebra1_ChannelNum 0xf80
\r
1079 #define bZebra1_TxLPFBW 0x400
\r
1080 #define bZebra1_RxLPFBW 0x600
\r
1083 #define bRTL8256RegModeCtrl1 0x100 // Useless
\r
1084 #define bRTL8256RegModeCtrl0 0x40
\r
1085 #define bRTL8256_TxLPFBW 0x18
\r
1086 #define bRTL8256_RxLPFBW 0x600
\r
1089 #define bRTL8258_TxLPFBW 0xc // Useless
\r
1090 #define bRTL8258_RxLPFBW 0xc00
\r
1091 #define bRTL8258_RSSILPFBW 0xc0
\r
1095 // Other Definition
\r
1098 //byte endable for sb_write
\r
1099 #define bByte0 0x1 // Useless
\r
1100 #define bByte1 0x2
\r
1101 #define bByte2 0x4
\r
1102 #define bByte3 0x8
\r
1103 #define bWord0 0x3
\r
1104 #define bWord1 0xc
\r
1105 #define bDWord 0xf
\r
1107 //for PutRegsetting & GetRegSetting BitMask
\r
1108 #define bMaskByte0 0xff // Reg 0xc50 rOFDM0_XAAGCCore~0xC6f
\r
1109 #define bMaskByte1 0xff00
\r
1110 #define bMaskByte2 0xff0000
\r
1111 #define bMaskByte3 0xff000000
\r
1112 #define bMaskHWord 0xffff0000
\r
1113 #define bMaskLWord 0x0000ffff
\r
1114 #define bMaskDWord 0xffffffff
\r
1115 #define bMask12Bits 0xfff
\r
1116 #define bMaskH4Bits 0xf0000000
\r
1117 #define bMaskOFDM_D 0xffc00000
\r
1118 #define bMaskCCK 0x3f3f3f3f
\r
1120 //for PutRFRegsetting & GetRFRegSetting BitMask
\r
1121 //#define bMask12Bits 0xfffff // RF Reg mask bits
\r
1122 //#define bMask20Bits 0xfffff // RF Reg mask bits T65 RF
\r
1123 #define bRFRegOffsetMask 0xfffff
\r
1124 //#define bRFRegOffsetMask 0xfff
\r
1126 //MAC0 will wirte PHY1
\r
1127 #define MAC0_ACCESS_PHY1 0x4000
\r
1128 //MAC1 will wirte PHY0
\r
1129 #define MAC1_ACCESS_PHY0 0x2000
\r
1131 #define bEnable 0x1 // Useless
\r
1132 #define bDisable 0x0
\r
1134 #define LeftAntenna 0x0 // Useless
\r
1135 #define RightAntenna 0x1
\r
1137 #define tCheckTxStatus 500 //500ms // Useless
\r
1138 #define tUpdateRxCounter 100 //100ms
\r
1140 #define rateCCK 0 // Useless
\r
1141 #define rateOFDM 1
\r
1144 //define Register-End
\r
1145 #define bPMAC_End 0x1ff // Useless
\r
1146 #define bFPGAPHY0_End 0x8ff
\r
1147 #define bFPGAPHY1_End 0x9ff
\r
1148 #define bCCKPHY0_End 0xaff
\r
1149 #define bOFDMPHY0_End 0xcff
\r
1150 #define bOFDMPHY1_End 0xdff
\r
1152 //define max debug item in each debug page
\r
1153 //#define bMaxItem_FPGA_PHY0 0x9
\r
1154 //#define bMaxItem_FPGA_PHY1 0x3
\r
1155 //#define bMaxItem_PHY_11B 0x16
\r
1156 //#define bMaxItem_OFDM_PHY0 0x29
\r
1157 //#define bMaxItem_OFDM_PHY1 0x0
\r
1159 #define bPMACControl 0x0 // Useless
\r
1160 #define bWMACControl 0x1
\r
1161 #define bWNICControl 0x2
\r
1163 #define PathA 0x0 // Useless
\r
1168 /*--------------------------Define Parameters-------------------------------*/
\r
1171 #endif //__INC_HAL8192SPHYREG_H
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projects / firefly-linux-kernel-4.4.55.git / blob