drivers/net/wireless/rtl8723au/include/Hal8192DPhyCfg.h

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  *
  19  ******************************************************************************/
  20 /*****************************************************************************
  21  *
  22  * Module:      __INC_HAL8192DPHYCFG_H
  23  *
  24  *
  25  * Note:
  26  *
  27  *
  28  * Export:      Constants, macro, functions(API), global variables(None).
  29  *
  30  * Abbrev:
  31  *
  32  * History:
  33  *              Data            Who             Remark
  34  *      08/07/2007  MHC         1. Porting from 9x series PHYCFG.h.
  35  *                                                      2. Reorganize code architecture.
  36  *
  37  *****************************************************************************/
  38  /* Check to see if the file has been included already.  */
  39 #ifndef __INC_HAL8192DPHYCFG_H
  40 #define __INC_HAL8192DPHYCFG_H
  41
  42
  43 /*--------------------------Define Parameters-------------------------------*/
  44 #define LOOP_LIMIT                              5
  45 #define MAX_STALL_TIME                  50              //us
  46 #define AntennaDiversityValue   0x80    //(Adapter->bSoftwareAntennaDiversity ? 0x00:0x80)
  47 #define MAX_TXPWR_IDX_NMODE_92S 63
  48 #define Reset_Cnt_Limit                 3
  49
  50
  51 #ifdef CONFIG_PCI_HCI
  52 #define SET_RTL8192SE_RF_SLEEP(_pAdapter)                                                       \
  53 {                                                                                                                                       \
  54         u1Byte          u1bTmp;                                                                                         \
  55         u1bTmp = PlatformEFIORead1Byte(_pAdapter, REG_LDOV12D_CTRL);            \
  56         u1bTmp |= BIT0;                                                                                                 \
  57         PlatformEFIOWrite1Byte(_pAdapter, REG_LDOV12D_CTRL, u1bTmp);            \
  58         PlatformEFIOWrite1Byte(_pAdapter, REG_SPS_OCP_CFG, 0x0);                                \
  59         PlatformEFIOWrite1Byte(_pAdapter, TXPAUSE, 0xFF);                               \
  60         PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x57FC);                                \
  61         delay_us(100);                                                                                                  \
  62         PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x77FC);                                \
  63         PlatformEFIOWrite1Byte(_pAdapter, PHY_CCA, 0x0);                                \
  64         delay_us(10);                                                                                                   \
  65         PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x37FC);                                \
  66         delay_us(10);                                                                                                   \
  67         PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x77FC);                                \
  68         delay_us(10);                                                                                                   \
  69         PlatformEFIOWrite2Byte(_pAdapter, CMDR, 0x57FC);                                \
  70 }
  71 #endif
  72
  73
  74 /*--------------------------Define Parameters-------------------------------*/
  75
  76
  77 /*------------------------------Define structure----------------------------*/
  78 typedef enum _SwChnlCmdID{
  79         CmdID_End,
  80         CmdID_SetTxPowerLevel,
  81         CmdID_BBRegWrite10,
  82         CmdID_WritePortUlong,
  83         CmdID_WritePortUshort,
  84         CmdID_WritePortUchar,
  85         CmdID_RF_WriteReg,
  86 }SwChnlCmdID;
  87
  88
  89 /* 1. Switch channel related */
  90 typedef struct _SwChnlCmd{
  91         SwChnlCmdID     CmdID;
  92         u32                     Para1;
  93         u32                     Para2;
  94         u32                     msDelay;
  95 }SwChnlCmd;
  96
  97 typedef enum _HW90_BLOCK{
  98         HW90_BLOCK_MAC = 0,
  99         HW90_BLOCK_PHY0 = 1,
 100         HW90_BLOCK_PHY1 = 2,
 101         HW90_BLOCK_RF = 3,
 102         HW90_BLOCK_MAXIMUM = 4, // Never use this
 103 }HW90_BLOCK_E, *PHW90_BLOCK_E;
 104
 105 //vivi added this for read parameter from header, 20100908
 106 typedef enum _RF_CONTENT{
 107         radioa_txt = 0x1000,
 108         radiob_txt = 0x1001,
 109         radioc_txt = 0x1002,
 110         radiod_txt = 0x1003
 111 } RF_CONTENT;
 112
 113 typedef enum _RF_RADIO_PATH{
 114         RF_PATH_A = 0,                  //Radio Path A
 115         RF_PATH_B = 1,                  //Radio Path B
 116         RF_PATH_C = 2,                  //Radio Path C
 117         RF_PATH_D = 3,                  //Radio Path D
 118         //RF_PATH_MAX                           //Max RF number 90 support
 119 }RF_RADIO_PATH_E, *PRF_RADIO_PATH_E;
 120
 121 #define RF_PATH_MAX                     2
 122
 123
 124 typedef enum _WIRELESS_MODE {
 125         WIRELESS_MODE_UNKNOWN = 0x00,
 126         WIRELESS_MODE_A = 0x01,
 127         WIRELESS_MODE_B = 0x02,
 128         WIRELESS_MODE_G = 0x04,
 129         WIRELESS_MODE_AUTO = 0x08,
 130         WIRELESS_MODE_N_24G = 0x10,
 131         WIRELESS_MODE_N_5G = 0x20
 132 } WIRELESS_MODE;
 133
 134
 135 #if(TX_POWER_FOR_5G_BAND == 1)
 136 #define CHANNEL_MAX_NUMBER              14+24+21        // 14 is the max channel number
 137 #define CHANNEL_GROUP_MAX               3+9     // ch1~3, ch4~9, ch10~14 total three groups
 138 #define MAX_PG_GROUP 13
 139 #else
 140 #define CHANNEL_MAX_NUMBER              14      // 14 is the max channel number
 141 #define CHANNEL_GROUP_MAX               3       // ch1~3, ch4~9, ch10~14 total three groups
 142 #define MAX_PG_GROUP 7
 143 #endif
 144 #define CHANNEL_GROUP_MAX_2G            3
 145 #define CHANNEL_GROUP_IDX_5GL           3
 146 #define CHANNEL_GROUP_IDX_5GM           6
 147 #define CHANNEL_GROUP_IDX_5GH           9
 148 #define CHANNEL_GROUP_MAX_5G            9
 149 #define CHANNEL_MAX_NUMBER_2G           14
 150
 151 #if (RTL8192D_DUAL_MAC_MODE_SWITCH == 1)
 152 typedef enum _BaseBand_Config_Type{
 153         BaseBand_Config_PHY_REG = 0,
 154         BaseBand_Config_AGC_TAB = 1,
 155         BaseBand_Config_AGC_TAB_2G = 2,
 156         BaseBand_Config_AGC_TAB_5G = 3,
 157 }BaseBand_Config_Type, *PBaseBand_Config_Type;
 158 #else
 159 typedef enum _BaseBand_Config_Type{
 160         BaseBand_Config_PHY_REG = 0,                    //Radio Path A
 161         BaseBand_Config_AGC_TAB = 1,                    //Radio Path B
 162 }BaseBand_Config_Type, *PBaseBand_Config_Type;
 163 #endif
 164
 165
 166 typedef enum _MACPHY_MODE_8192D{
 167         SINGLEMAC_SINGLEPHY,    //SMSP
 168         DUALMAC_DUALPHY,                //DMDP
 169         DUALMAC_SINGLEPHY,      //DMSP
 170 }MACPHY_MODE_8192D,*PMACPHY_MODE_8192D;
 171
 172 typedef enum _MACPHY_MODE_CHANGE_ACTION{
 173         DMDP2DMSP = 0,
 174         DMSP2DMDP = 1,
 175         DMDP2SMSP = 2,
 176         SMSP2DMDP = 3,
 177         DMSP2SMSP = 4,
 178         SMSP2DMSP = 5,
 179         MAXACTION
 180 }MACPHY_MODE_CHANGE_ACTION,*PMACPHY_MODE_CHANGE_ACTION;
 181
 182 typedef enum _BAND_TYPE{
 183         BAND_ON_2_4G    = 1,
 184         BAND_ON_5G      = 2,
 185         BAND_ON_BOTH,
 186         BANDMAX
 187 }BAND_TYPE,*PBAND_TYPE;
 188
 189 typedef enum _PHY_Rate_Tx_Power_Offset_Area{
 190         RA_OFFSET_LEGACY_OFDM1,
 191         RA_OFFSET_LEGACY_OFDM2,
 192         RA_OFFSET_HT_OFDM1,
 193         RA_OFFSET_HT_OFDM2,
 194         RA_OFFSET_HT_OFDM3,
 195         RA_OFFSET_HT_OFDM4,
 196         RA_OFFSET_HT_CCK,
 197 }RA_OFFSET_AREA,*PRA_OFFSET_AREA;
 198
 199
 200 /* BB/RF related */
 201 typedef enum _RF_TYPE_8190P{
 202         RF_TYPE_MIN,    // 0
 203         RF_8225=1,                      // 1 11b/g RF for verification only
 204         RF_8256=2,                      // 2 11b/g/n
 205         RF_8258=3,                      // 3 11a/b/g/n RF
 206         RF_6052=4,              // 4 11b/g/n RF
 207         //RF_6052=5,            // 4 11b/g/n RF
 208         // TODO: We sholud remove this psudo PHY RF after we get new RF.
 209         RF_PSEUDO_11N=5,        // 5, It is a temporality RF.
 210 }RF_TYPE_8190P_E,*PRF_TYPE_8190P_E;
 211
 212
 213
 214 typedef struct _BB_REGISTER_DEFINITION{
 215         u32 rfintfs;                    // set software control:
 216                                                         //              0x870~0x877[8 bytes]
 217
 218         u32 rfintfi;                    // readback data:
 219                                                         //              0x8e0~0x8e7[8 bytes]
 220
 221         u32 rfintfo;            // output data:
 222                                                         //              0x860~0x86f [16 bytes]
 223
 224         u32 rfintfe;            // output enable:
 225                                                         //              0x860~0x86f [16 bytes]
 226
 227         u32 rf3wireOffset;      // LSSI data:
 228                                                         //              0x840~0x84f [16 bytes]
 229
 230         u32 rfLSSI_Select;      // BB Band Select:
 231                                                         //              0x878~0x87f [8 bytes]
 232
 233         u32 rfTxGainStage;      // Tx gain stage:
 234                                                         //              0x80c~0x80f [4 bytes]
 235
 236         u32 rfHSSIPara1;        // wire parameter control1 :
 237                                                         //              0x820~0x823,0x828~0x82b, 0x830~0x833, 0x838~0x83b [16 bytes]
 238
 239         u32 rfHSSIPara2;        // wire parameter control2 :
 240                                                         //              0x824~0x827,0x82c~0x82f, 0x834~0x837, 0x83c~0x83f [16 bytes]
 241
 242         u32 rfSwitchControl; //Tx Rx antenna control :
 243                                                         //              0x858~0x85f [16 bytes]
 244
 245         u32 rfAGCControl1;      //AGC parameter control1 :
 246                                                         //              0xc50~0xc53,0xc58~0xc5b, 0xc60~0xc63, 0xc68~0xc6b [16 bytes]
 247
 248         u32 rfAGCControl2;      //AGC parameter control2 :
 249                                                         //              0xc54~0xc57,0xc5c~0xc5f, 0xc64~0xc67, 0xc6c~0xc6f [16 bytes]
 250
 251         u32 rfRxIQImbalance; //OFDM Rx IQ imbalance matrix :
 252                                                         //              0xc14~0xc17,0xc1c~0xc1f, 0xc24~0xc27, 0xc2c~0xc2f [16 bytes]
 253
 254         u32 rfRxAFE;            //Rx IQ DC ofset and Rx digital filter, Rx DC notch filter :
 255                                                         //              0xc10~0xc13,0xc18~0xc1b, 0xc20~0xc23, 0xc28~0xc2b [16 bytes]
 256
 257         u32 rfTxIQImbalance; //OFDM Tx IQ imbalance matrix
 258                                                         //              0xc80~0xc83,0xc88~0xc8b, 0xc90~0xc93, 0xc98~0xc9b [16 bytes]
 259
 260         u32 rfTxAFE;            //Tx IQ DC Offset and Tx DFIR type
 261                                                         //              0xc84~0xc87,0xc8c~0xc8f, 0xc94~0xc97, 0xc9c~0xc9f [16 bytes]
 262
 263         u32 rfLSSIReadBack;     //LSSI RF readback data SI mode
 264                                                                 //              0x8a0~0x8af [16 bytes]
 265
 266         u32 rfLSSIReadBackPi;   //LSSI RF readback data PI mode 0x8b8-8bc for Path A and B
 267
 268 }BB_REGISTER_DEFINITION_T, *PBB_REGISTER_DEFINITION_T;
 269
 270
 271 typedef struct _R_ANTENNA_SELECT_OFDM{
 272         u32                     r_tx_antenna:4;
 273         u32                     r_ant_l:4;
 274         u32                     r_ant_non_ht:4;
 275         u32                     r_ant_ht1:4;
 276         u32                     r_ant_ht2:4;
 277         u32                     r_ant_ht_s1:4;
 278         u32                     r_ant_non_ht_s1:4;
 279         u32                     OFDM_TXSC:2;
 280         u32                     Reserved:2;
 281 }R_ANTENNA_SELECT_OFDM;
 282
 283 typedef struct _R_ANTENNA_SELECT_CCK{
 284         u8                      r_cckrx_enable_2:2;
 285         u8                      r_cckrx_enable:2;
 286         u8                      r_ccktx_enable:4;
 287 }R_ANTENNA_SELECT_CCK;
 288
 289 /*------------------------------Define structure----------------------------*/
 290
 291
 292 /*------------------------Export global variable----------------------------*/
 293 /*------------------------Export global variable----------------------------*/
 294
 295
 296 /*------------------------Export Marco Definition---------------------------*/
 297
 298 /*--------------------------Exported Function prototype---------------------*/
 299 //
 300 // BB and RF register read/write
 301 //
 302 void    rtl8192d_PHY_SetBBReg1Byte(     IN      PADAPTER        Adapter,
 303                                                                 IN      u32             RegAddr,
 304                                                                 IN      u32             BitMask,
 305                                                                 IN      u32             Data    );
 306 u32     rtl8192d_PHY_QueryBBReg(        IN      PADAPTER        Adapter,
 307                                                                 IN      u32             RegAddr,
 308                                                                 IN      u32             BitMask );
 309 void    rtl8192d_PHY_SetBBReg(  IN      PADAPTER        Adapter,
 310                                                                 IN      u32             RegAddr,
 311                                                                 IN      u32             BitMask,
 312                                                                 IN      u32             Data    );
 313 u32     rtl8192d_PHY_QueryRFReg(        IN      PADAPTER                        Adapter,
 314                                                                 IN      RF_RADIO_PATH_E eRFPath,
 315                                                                 IN      u32                             RegAddr,
 316                                                                 IN      u32                             BitMask );
 317 void    rtl8192d_PHY_SetRFReg(  IN      PADAPTER                        Adapter,
 318                                                                 IN      RF_RADIO_PATH_E eRFPath,
 319                                                                 IN      u32                             RegAddr,
 320                                                                 IN      u32                             BitMask,
 321                                                                 IN      u32                             Data    );
 322
 323 //
 324 // Initialization related function
 325 //
 326 /* MAC/BB/RF HAL config */
 327 extern  int     PHY_MACConfig8192D(     IN      PADAPTER        Adapter );
 328 extern  int     PHY_BBConfig8192D(      IN      PADAPTER        Adapter );
 329 extern  int     PHY_RFConfig8192D(      IN      PADAPTER        Adapter );
 330 /* RF config */
 331 int     rtl8192d_PHY_ConfigRFWithParaFile(      IN      PADAPTER        Adapter,
 332                                                                                                 IN      u8*     pFileName,
 333                                                                                                 IN      RF_RADIO_PATH_E eRFPath);
 334 int     rtl8192d_PHY_ConfigRFWithHeaderFile(    IN      PADAPTER                        Adapter,
 335                                                                                                 IN      RF_CONTENT                      Content,
 336                                                                                                 IN      RF_RADIO_PATH_E eRFPath);
 337 /* BB/RF readback check for making sure init OK */
 338 int     rtl8192d_PHY_CheckBBAndRFOK(    IN      PADAPTER                        Adapter,
 339                                                                                 IN      HW90_BLOCK_E            CheckBlock,
 340                                                                                 IN      RF_RADIO_PATH_E eRFPath   );
 341 /* Read initi reg value for tx power setting. */
 342 void    rtl8192d_PHY_GetHWRegOriginalValue(     IN      PADAPTER                Adapter );
 343
 344 //
 345 // RF Power setting
 346 //
 347 //extern        BOOLEAN PHY_SetRFPowerState(IN  PADAPTER                        Adapter,
 348 //                                                                      IN      RT_RF_POWER_STATE       eRFPowerState);
 349
 350 //
 351 // BB TX Power R/W
 352 //
 353 void    PHY_GetTxPowerLevel8192D(       IN      PADAPTER                Adapter,
 354                                                                                         OUT u32*                powerlevel      );
 355 void    PHY_SetTxPowerLevel8192D(       IN      PADAPTER                Adapter,
 356                                                                                         IN      u8                      channel );
 357 BOOLEAN PHY_UpdateTxPowerDbm8192D(      IN      PADAPTER        Adapter,
 358                                                                                         IN      int             powerInDbm      );
 359
 360 //
 361 VOID
 362 PHY_ScanOperationBackup8192D(IN PADAPTER        Adapter,
 363                                                                                 IN      u8              Operation       );
 364
 365 //
 366 // Switch bandwidth for 8192S
 367 //
 368 //void  PHY_SetBWModeCallback8192C(     IN      PRT_TIMER               pTimer  );
 369 void    PHY_SetBWMode8192D(     IN      PADAPTER                        pAdapter,
 370                                                                         IN      HT_CHANNEL_WIDTH        ChnlWidth,
 371                                                                         IN      unsigned char   Offset  );
 372
 373 //
 374 // Set FW CMD IO for 8192S.
 375 //
 376 //extern        BOOLEAN HalSetIO8192C(  IN      PADAPTER                        Adapter,
 377 //                                                                      IN      IO_TYPE                         IOType);
 378
 379 //
 380 // Set A2 entry to fw for 8192S
 381 //
 382 extern  void FillA2Entry8192C(          IN      PADAPTER                        Adapter,
 383                                                                                 IN      u8                              index,
 384                                                                                 IN      u8*                             val);
 385
 386
 387 //
 388 // channel switch related funciton
 389 //
 390 //extern        void    PHY_SwChnlCallback8192C(        IN      PRT_TIMER               pTimer  );
 391 void    PHY_SwChnl8192D(        IN      PADAPTER                pAdapter,
 392                                                                         IN      u8                      channel );
 393                                 // Call after initialization
 394 void    PHY_SwChnlPhy8192D(     IN      PADAPTER                pAdapter,
 395                                                                         IN      u8                      channel );
 396
 397 extern void ChkFwCmdIoDone(     IN      PADAPTER        Adapter);
 398
 399
 400 //
 401 // BB/MAC/RF other monitor API
 402 //
 403 void    PHY_SetMonitorMode8192D(IN      PADAPTER        pAdapter,
 404                                                                                 IN      BOOLEAN         bEnableMonitorMode      );
 405
 406 BOOLEAN PHY_CheckIsLegalRfPath8192D(IN  PADAPTER        pAdapter,
 407                                                                                         IN      u32             eRFPath );
 408
 409
 410 //
 411 // Modify the value of the hw register when beacon interval be changed.
 412 //
 413 void
 414 rtl8192d_PHY_SetBeaconHwReg(    IN      PADAPTER                Adapter,
 415                                         IN      u16                     BeaconInterval  );
 416
 417
 418 extern  VOID
 419 PHY_SwitchEphyParameter(
 420         IN      PADAPTER                        Adapter
 421         );
 422
 423 extern  VOID
 424 PHY_EnableHostClkReq(
 425         IN      PADAPTER                        Adapter
 426         );
 427
 428 BOOLEAN
 429 SetAntennaConfig92C(
 430         IN      PADAPTER        Adapter,
 431         IN      u8              DefaultAnt
 432         );
 433
 434 VOID
 435 PHY_UpdateBBRFConfiguration8192D(
 436         IN PADAPTER Adapter,
 437         IN BOOLEAN bisBandSwitch
 438 );
 439
 440 VOID PHY_ReadMacPhyMode92D(
 441         IN PADAPTER     Adapter,
 442         IN BOOLEAN      AutoloadFail
 443 );
 444
 445 VOID PHY_ConfigMacPhyMode92D(
 446         IN PADAPTER     Adapter
 447 );
 448
 449 VOID PHY_ConfigMacPhyModeInfo92D(
 450         IN PADAPTER     Adapter
 451 );
 452
 453 VOID PHY_ConfigMacCoexist_RFPage92D(
 454         IN PADAPTER     Adapter
 455 );
 456
 457 VOID
 458 rtl8192d_PHY_InitRxSetting(
 459         IN      PADAPTER Adapter
 460 );
 461
 462
 463 VOID
 464 rtl8192d_PHY_SetRFPathSwitch(IN PADAPTER        pAdapter, IN    BOOLEAN         bMain);
 465
 466 VOID
 467 HalChangeCCKStatus8192D(
 468         IN      PADAPTER        Adapter,
 469         IN      BOOLEAN         bCCKDisable
 470 );
 471
 472 VOID
 473 PHY_InitPABias92D(IN    PADAPTER Adapter);
 474
 475 /*--------------------------Exported Function prototype---------------------*/
 476
 477 #define PHY_SetBBReg1Byte(Adapter, RegAddr, BitMask, Data) rtl8192d_PHY_SetBBReg1Byte((Adapter), (RegAddr), (BitMask), (Data))
 478 #define PHY_QueryBBReg(Adapter, RegAddr, BitMask) rtl8192d_PHY_QueryBBReg((Adapter), (RegAddr), (BitMask))
 479 #define PHY_SetBBReg(Adapter, RegAddr, BitMask, Data) rtl8192d_PHY_SetBBReg((Adapter), (RegAddr), (BitMask), (Data))
 480 #define PHY_QueryRFReg(Adapter, eRFPath, RegAddr, BitMask) rtl8192d_PHY_QueryRFReg((Adapter), (eRFPath), (RegAddr), (BitMask))
 481 #define PHY_SetRFReg(Adapter, eRFPath, RegAddr, BitMask, Data) rtl8192d_PHY_SetRFReg((Adapter), (eRFPath), (RegAddr), (BitMask), (Data))
 482
 483 #define PHY_SetMacReg   PHY_SetBBReg
 484 #define PHY_QueryMacReg PHY_QueryBBReg
 485
 486 #endif  // __INC_HAL8192SPHYCFG_H
 487