1 /******************************************************************************
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3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
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5 * This program is free software; you can redistribute it and/or modify it
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6 * under the terms of version 2 of the GNU General Public License as
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7 * published by the Free Software Foundation.
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9 * This program is distributed in the hope that it will be useful, but WITHOUT
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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14 * You should have received a copy of the GNU General Public License along with
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15 * this program; if not, write to the Free Software Foundation, Inc.,
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16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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19 ******************************************************************************/
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20 #define _RTL8723A_PHYCFG_C_
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22 #include <drv_conf.h>
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23 #include <osdep_service.h>
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24 #include <drv_types.h>
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25 #include <rtw_byteorder.h>
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28 #include <rtw_iol.h>
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31 #include <rtl8723a_hal.h>
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34 /*---------------------------Define Local Constant---------------------------*/
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35 /* Channel switch:The size of command tables for switch channel*/
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36 #define MAX_PRECMD_CNT 16
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37 #define MAX_RFDEPENDCMD_CNT 16
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38 #define MAX_POSTCMD_CNT 16
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40 #define MAX_DOZE_WAITING_TIMES_9x 64
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42 /*---------------------------Define Local Constant---------------------------*/
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45 /*------------------------Define global variable-----------------------------*/
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47 /*------------------------Define local variable------------------------------*/
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50 /*--------------------Define export function prototype-----------------------*/
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51 // Please refer to header file
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52 /*--------------------Define export function prototype-----------------------*/
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54 /*----------------------------Function Body----------------------------------*/
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56 // 1. BB register R/W API
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60 * Function: phy_CalculateBitShift
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62 * OverView: Get shifted position of the BitMask
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68 * Return: u4Byte Return the shift bit bit position of the mask
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71 phy_CalculateBitShift(
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77 for(i=0; i<=31; i++)
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79 if ( ((BitMask>>i) & 0x1 ) == 1)
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88 * Function: PHY_QueryBBReg
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90 * OverView: Read "sepcific bits" from BB register
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94 * u4Byte RegAddr, //The target address to be readback
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95 * u4Byte BitMask //The target bit position in the target address
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98 * Return: u4Byte Data //The readback register value
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99 * Note: This function is equal to "GetRegSetting" in PHY programming guide
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102 rtl8192c_PHY_QueryBBReg(
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103 IN PADAPTER Adapter,
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108 u32 ReturnValue = 0, OriginalValue, BitShift;
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109 u16 BBWaitCounter = 0;
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111 #if (DISABLE_BB_RF == 1)
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115 //RT_TRACE(COMP_RF, DBG_TRACE, ("--->PHY_QueryBBReg(): RegAddr(%#lx), BitMask(%#lx)\n", RegAddr, BitMask));
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117 OriginalValue = rtw_read32(Adapter, RegAddr);
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118 BitShift = phy_CalculateBitShift(BitMask);
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119 ReturnValue = (OriginalValue & BitMask) >> BitShift;
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121 //RTPRINT(FPHY, PHY_BBR, ("BBR MASK=0x%lx Addr[0x%lx]=0x%lx\n", BitMask, RegAddr, OriginalValue));
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122 //RT_TRACE(COMP_RF, DBG_TRACE, ("<---PHY_QueryBBReg(): RegAddr(%#lx), BitMask(%#lx), OriginalValue(%#lx)\n", RegAddr, BitMask, OriginalValue));
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124 return (ReturnValue);
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130 * Function: PHY_SetBBReg
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132 * OverView: Write "Specific bits" to BB register (page 8~)
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135 * PADAPTER Adapter,
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136 * u4Byte RegAddr, //The target address to be modified
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137 * u4Byte BitMask //The target bit position in the target address
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139 * u4Byte Data //The new register value in the target bit position
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140 * //of the target address
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144 * Note: This function is equal to "PutRegSetting" in PHY programming guide
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148 rtl8192c_PHY_SetBBReg(
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149 IN PADAPTER Adapter,
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155 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
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156 //u16 BBWaitCounter = 0;
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157 u32 OriginalValue, BitShift;
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159 #if (DISABLE_BB_RF == 1)
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163 //RT_TRACE(COMP_RF, DBG_TRACE, ("--->PHY_SetBBReg(): RegAddr(%#lx), BitMask(%#lx), Data(%#lx)\n", RegAddr, BitMask, Data));
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165 if(BitMask!= bMaskDWord){//if not "double word" write
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166 OriginalValue = rtw_read32(Adapter, RegAddr);
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167 BitShift = phy_CalculateBitShift(BitMask);
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168 Data = ((OriginalValue & (~BitMask)) | ((Data << BitShift) & BitMask));
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171 rtw_write32(Adapter, RegAddr, Data);
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173 //RTPRINT(FPHY, PHY_BBW, ("BBW MASK=0x%lx Addr[0x%lx]=0x%lx\n", BitMask, RegAddr, Data));
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174 //RT_TRACE(COMP_RF, DBG_TRACE, ("<---PHY_SetBBReg(): RegAddr(%#lx), BitMask(%#lx), Data(%#lx)\n", RegAddr, BitMask, Data));
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180 // 2. RF register R/W API
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183 /*-----------------------------------------------------------------------------
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184 * Function: phy_FwRFSerialRead()
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186 * Overview: We support firmware to execute RF-R/W.
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196 * 01/21/2008 MHC Create Version 0.
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198 *---------------------------------------------------------------------------*/
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200 phy_FwRFSerialRead(
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201 IN PADAPTER Adapter,
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202 IN RF_RADIO_PATH_E eRFPath,
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206 //RT_ASSERT(FALSE,("deprecate!\n"));
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209 } /* phy_FwRFSerialRead */
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212 /*-----------------------------------------------------------------------------
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213 * Function: phy_FwRFSerialWrite()
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215 * Overview: We support firmware to execute RF-R/W.
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225 * 01/21/2008 MHC Create Version 0.
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227 *---------------------------------------------------------------------------*/
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229 phy_FwRFSerialWrite(
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230 IN PADAPTER Adapter,
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231 IN RF_RADIO_PATH_E eRFPath,
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235 //RT_ASSERT(FALSE,("deprecate!\n"));
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240 * Function: phy_RFSerialRead
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242 * OverView: Read regster from RF chips
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245 * PADAPTER Adapter,
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246 * RF_RADIO_PATH_E eRFPath, //Radio path of A/B/C/D
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247 * u4Byte Offset, //The target address to be read
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250 * Return: u4Byte reback value
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251 * Note: Threre are three types of serial operations:
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252 * 1. Software serial write
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253 * 2. Hardware LSSI-Low Speed Serial Interface
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254 * 3. Hardware HSSI-High speed
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255 * serial write. Driver need to implement (1) and (2).
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256 * This function is equal to the combination of RF_ReadReg() and RFLSSIRead()
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260 IN PADAPTER Adapter,
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261 IN RF_RADIO_PATH_E eRFPath,
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266 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
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267 BB_REGISTER_DEFINITION_T *pPhyReg = &pHalData->PHYRegDef[eRFPath];
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269 u32 tmplong,tmplong2;
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272 if(pHalData->RFChipID == RF_8225 && Offset > 0x24) //36 valid regs
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274 if(pHalData->RFChipID == RF_8256 && Offset > 0x2D) //45 valid regs
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278 // Make sure RF register offset is correct
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283 // Switch page for 8256 RF IC
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285 NewOffset = Offset;
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287 // 2009/06/17 MH We can not execute IO for power save or other accident mode.
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288 //if(RT_CANNOT_IO(Adapter))
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290 // RTPRINT(FPHY, PHY_RFR, ("phy_RFSerialRead return all one\n"));
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291 // return 0xFFFFFFFF;
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294 // For 92S LSSI Read RFLSSIRead
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295 // For RF A/B write 0x824/82c(does not work in the future)
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296 // We must use 0x824 for RF A and B to execute read trigger
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297 tmplong = PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter2, bMaskDWord);
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298 if(eRFPath == RF_PATH_A)
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299 tmplong2 = tmplong;
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301 tmplong2 = PHY_QueryBBReg(Adapter, pPhyReg->rfHSSIPara2, bMaskDWord);
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303 tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | (NewOffset<<23) | bLSSIReadEdge; //T65 RF
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305 PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2, bMaskDWord, tmplong&(~bLSSIReadEdge));
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306 rtw_udelay_os(10);// PlatformStallExecution(10);
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308 PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, bMaskDWord, tmplong2);
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309 rtw_udelay_os(100);//PlatformStallExecution(100);
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311 PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2, bMaskDWord, tmplong|bLSSIReadEdge);
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312 rtw_udelay_os(10);//PlatformStallExecution(10);
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314 if(eRFPath == RF_PATH_A)
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315 RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter1, BIT8);
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316 else if(eRFPath == RF_PATH_B)
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317 RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XB_HSSIParameter1, BIT8);
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320 { // Read from BBreg8b8, 12 bits for 8190, 20bits for T65 RF
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321 retValue = PHY_QueryBBReg(Adapter, pPhyReg->rfLSSIReadBackPi, bLSSIReadBackData);
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322 //DBG_8192C("Readback from RF-PI : 0x%x\n", retValue);
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325 { //Read from BBreg8a0, 12 bits for 8190, 20 bits for T65 RF
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326 retValue = PHY_QueryBBReg(Adapter, pPhyReg->rfLSSIReadBack, bLSSIReadBackData);
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327 //DBG_8192C("Readback from RF-SI : 0x%x\n", retValue);
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329 //DBG_8192C("RFR-%d Addr[0x%x]=0x%x\n", eRFPath, pPhyReg->rfLSSIReadBack, retValue);
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338 * Function: phy_RFSerialWrite
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340 * OverView: Write data to RF register (page 8~)
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343 * PADAPTER Adapter,
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344 * RF_RADIO_PATH_E eRFPath, //Radio path of A/B/C/D
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345 * u4Byte Offset, //The target address to be read
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346 * u4Byte Data //The new register Data in the target bit position
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347 * //of the target to be read
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351 * Note: Threre are three types of serial operations:
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352 * 1. Software serial write
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353 * 2. Hardware LSSI-Low Speed Serial Interface
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354 * 3. Hardware HSSI-High speed
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355 * serial write. Driver need to implement (1) and (2).
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356 * This function is equal to the combination of RF_ReadReg() and RFLSSIRead()
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358 * Note: For RF8256 only
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359 * The total count of RTL8256(Zebra4) register is around 36 bit it only employs
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360 * 4-bit RF address. RTL8256 uses "register mode control bit" (Reg00[12], Reg00[10])
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361 * to access register address bigger than 0xf. See "Appendix-4 in PHY Configuration
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362 * programming guide" for more details.
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363 * Thus, we define a sub-finction for RTL8526 register address conversion
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364 * ===========================================================
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365 * Register Mode RegCTL[1] RegCTL[0] Note
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366 * (Reg00[12]) (Reg00[10])
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367 * ===========================================================
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368 * Reg_Mode0 0 x Reg 0 ~15(0x0 ~ 0xf)
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369 * ------------------------------------------------------------------
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370 * Reg_Mode1 1 0 Reg 16 ~30(0x1 ~ 0xf)
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371 * ------------------------------------------------------------------
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372 * Reg_Mode2 1 1 Reg 31 ~ 45(0x1 ~ 0xf)
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373 * ------------------------------------------------------------------
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375 * 2008/09/02 MH Add 92S RF definition
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382 IN PADAPTER Adapter,
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383 IN RF_RADIO_PATH_E eRFPath,
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388 u32 DataAndAddr = 0;
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389 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
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390 BB_REGISTER_DEFINITION_T *pPhyReg = &pHalData->PHYRegDef[eRFPath];
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394 //<Roger_TODO> We should check valid regs for RF_6052 case.
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395 if(pHalData->RFChipID == RF_8225 && Offset > 0x24) //36 valid regs
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397 if(pHalData->RFChipID == RF_8256 && Offset > 0x2D) //45 valid regs
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401 // 2009/06/17 MH We can not execute IO for power save or other accident mode.
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402 //if(RT_CANNOT_IO(Adapter))
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404 // RTPRINT(FPHY, PHY_RFW, ("phy_RFSerialWrite stop\n"));
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413 //PHY_RFShadowWrite(Adapter, eRFPath, Offset, Data);
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416 // Switch page for 8256 RF IC
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418 NewOffset = Offset;
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421 // Put write addr in [5:0] and write data in [31:16]
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423 //DataAndAddr = (Data<<16) | (NewOffset&0x3f);
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424 DataAndAddr = ((NewOffset<<20) | (Data&0x000fffff)) & 0x0fffffff; // T65 RF
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429 PHY_SetBBReg(Adapter, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
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430 //RTPRINT(FPHY, PHY_RFW, ("RFW-%d Addr[0x%lx]=0x%lx\n", eRFPath, pPhyReg->rf3wireOffset, DataAndAddr));
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436 * Function: PHY_QueryRFReg
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438 * OverView: Query "Specific bits" to RF register (page 8~)
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441 * PADAPTER Adapter,
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442 * RF_RADIO_PATH_E eRFPath, //Radio path of A/B/C/D
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443 * u4Byte RegAddr, //The target address to be read
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444 * u4Byte BitMask //The target bit position in the target address
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448 * Return: u4Byte Readback value
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449 * Note: This function is equal to "GetRFRegSetting" in PHY programming guide
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452 rtl8192c_PHY_QueryRFReg(
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453 IN PADAPTER Adapter,
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454 IN RF_RADIO_PATH_E eRFPath,
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459 u32 Original_Value, Readback_Value, BitShift;
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460 //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
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461 //u8 RFWaitCounter = 0;
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464 #if (DISABLE_BB_RF == 1)
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468 //RT_TRACE(COMP_RF, DBG_TRACE, ("--->PHY_QueryRFReg(): RegAddr(%#lx), eRFPath(%#x), BitMask(%#lx)\n", RegAddr, eRFPath,BitMask));
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470 #ifdef CONFIG_USB_HCI
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471 //PlatformAcquireMutex(&pHalData->mxRFOperate);
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473 //_enter_critical(&pHalData->rf_lock, &irqL);
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477 Original_Value = phy_RFSerialRead(Adapter, eRFPath, RegAddr);
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479 BitShift = phy_CalculateBitShift(BitMask);
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480 Readback_Value = (Original_Value & BitMask) >> BitShift;
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482 #ifdef CONFIG_USB_HCI
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483 //PlatformReleaseMutex(&pHalData->mxRFOperate);
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485 //_exit_critical(&pHalData->rf_lock, &irqL);
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489 //RTPRINT(FPHY, PHY_RFR, ("RFR-%d MASK=0x%lx Addr[0x%lx]=0x%lx\n", eRFPath, BitMask, RegAddr, Original_Value));//BitMask(%#lx),BitMask,
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490 //RT_TRACE(COMP_RF, DBG_TRACE, ("<---PHY_QueryRFReg(): RegAddr(%#lx), eRFPath(%#x), Original_Value(%#lx)\n",
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491 // RegAddr, eRFPath, Original_Value));
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493 return (Readback_Value);
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497 * Function: PHY_SetRFReg
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499 * OverView: Write "Specific bits" to RF register (page 8~)
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502 * PADAPTER Adapter,
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503 * RF_RADIO_PATH_E eRFPath, //Radio path of A/B/C/D
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504 * u4Byte RegAddr, //The target address to be modified
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505 * u4Byte BitMask //The target bit position in the target address
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507 * u4Byte Data //The new register Data in the target bit position
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508 * //of the target address
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512 * Note: This function is equal to "PutRFRegSetting" in PHY programming guide
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515 rtl8192c_PHY_SetRFReg(
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516 IN PADAPTER Adapter,
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517 IN RF_RADIO_PATH_E eRFPath,
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524 //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
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525 //u1Byte RFWaitCounter = 0;
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526 u32 Original_Value, BitShift;
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529 #if (DISABLE_BB_RF == 1)
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533 //RT_TRACE(COMP_RF, DBG_TRACE, ("--->PHY_SetRFReg(): RegAddr(%#lx), BitMask(%#lx), Data(%#lx), eRFPath(%#x)\n",
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534 // RegAddr, BitMask, Data, eRFPath));
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535 //RTPRINT(FINIT, INIT_RF, ("PHY_SetRFReg(): RegAddr(%#lx), BitMask(%#lx), Data(%#lx), eRFPath(%#x)\n",
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536 // RegAddr, BitMask, Data, eRFPath));
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539 #ifdef CONFIG_USB_HCI
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540 //PlatformAcquireMutex(&pHalData->mxRFOperate);
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542 //_enter_critical(&pHalData->rf_lock, &irqL);
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546 // RF data is 12 bits only
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547 if (BitMask != bRFRegOffsetMask)
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549 Original_Value = phy_RFSerialRead(Adapter, eRFPath, RegAddr);
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550 BitShift = phy_CalculateBitShift(BitMask);
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551 Data = ((Original_Value & (~BitMask)) | (Data<< BitShift));
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554 phy_RFSerialWrite(Adapter, eRFPath, RegAddr, Data);
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557 #ifdef CONFIG_USB_HCI
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558 //PlatformReleaseMutex(&pHalData->mxRFOperate);
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560 //_exit_critical(&pHalData->rf_lock, &irqL);
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563 //PHY_QueryRFReg(Adapter,eRFPath,RegAddr,BitMask);
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564 //RT_TRACE(COMP_RF, DBG_TRACE, ("<---PHY_SetRFReg(): RegAddr(%#lx), BitMask(%#lx), Data(%#lx), eRFPath(%#x)\n",
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565 // RegAddr, BitMask, Data, eRFPath));
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571 // 3. Initial MAC/BB/RF config by reading MAC/BB/RF txt.
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574 /*-----------------------------------------------------------------------------
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575 * Function: phy_ConfigMACWithParaFile()
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577 * Overview: This function read BB parameters from general file format, and do register
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580 * Input: PADAPTER Adapter
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581 * ps1Byte pFileName
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585 * Return: RT_STATUS_SUCCESS: configuration file exist
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587 * Note: The format of MACPHY_REG.txt is different from PHY and RF.
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588 * [Register][Mask][Value]
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589 *---------------------------------------------------------------------------*/
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591 phy_ConfigMACWithParaFile(
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592 IN PADAPTER Adapter,
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596 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
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598 int rtStatus = _SUCCESS;
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603 /*-----------------------------------------------------------------------------
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604 * Function: phy_ConfigMACWithHeaderFile()
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606 * Overview: This function read BB parameters from Header file we gen, and do register
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609 * Input: PADAPTER Adapter
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610 * ps1Byte pFileName
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614 * Return: RT_STATUS_SUCCESS: configuration file exist
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616 * Note: The format of MACPHY_REG.txt is different from PHY and RF.
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617 * [Register][Mask][Value]
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618 *---------------------------------------------------------------------------*/
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619 #ifndef CONFIG_PHY_SETTING_WITH_ODM
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621 phy_ConfigMACWithHeaderFile(
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622 IN PADAPTER Adapter
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626 u32 ArrayLength = 0;
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628 //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
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630 //2008.11.06 Modified by tynli.
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631 //RT_TRACE(COMP_INIT, DBG_LOUD, ("Read Rtl819XMACPHY_Array\n"));
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632 ArrayLength = Rtl8723_MAC_ArrayLength;
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633 ptrArray = (u32*)Rtl8723_MAC_Array;
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635 #ifdef CONFIG_IOL_MAC
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637 struct xmit_frame *xmit_frame;
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638 if((xmit_frame=rtw_IOL_accquire_xmit_frame(Adapter)) == NULL)
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641 for(i = 0 ;i < ArrayLength;i=i+2){ // Add by tynli for 2 column
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642 rtw_IOL_append_WB_cmd(xmit_frame, ptrArray[i], (u8)ptrArray[i+1]);
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645 return rtw_IOL_exec_cmds_sync(Adapter, xmit_frame, 1000,0);
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648 for(i = 0 ;i < ArrayLength;i=i+2){ // Add by tynli for 2 column
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649 rtw_write8(Adapter, ptrArray[i], (u8)ptrArray[i+1]);
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656 #endif//#ifndef CONFIG_PHY_SETTING_WITH_ODM
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658 /*-----------------------------------------------------------------------------
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659 * Function: PHY_MACConfig8192C
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661 * Overview: Condig MAC by header file or parameter file.
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671 * 08/12/2008 MHC Create Version 0.
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673 *---------------------------------------------------------------------------*/
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674 s32 PHY_MACConfig8723A(PADAPTER Adapter)
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676 int rtStatus = _SUCCESS;
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677 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
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679 s8 sz8723MACRegFile[] = RTL8723_PHY_MACREG;
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680 BOOLEAN is92C = IS_92C_SERIAL(pHalData->VersionID);
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683 pszMACRegFile = sz8723MACRegFile;
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688 #ifdef CONFIG_EMBEDDED_FWIMG
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689 #ifdef CONFIG_PHY_SETTING_WITH_ODM
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690 if(HAL_STATUS_FAILURE == ODM_ConfigMACWithHeaderFile(&pHalData->odmpriv))
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693 rtStatus = phy_ConfigMACWithHeaderFile(Adapter);
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694 #endif//#ifdef CONFIG_PHY_SETTING_WITH_ODM
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697 // Not make sure EEPROM, add later
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698 //RT_TRACE(COMP_INIT, DBG_LOUD, ("Read MACREG.txt\n"));
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699 rtStatus = phy_ConfigMACWithParaFile(Adapter, pszMACRegFile);
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700 #endif//CONFIG_EMBEDDED_FWIMG
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702 #ifdef CONFIG_PCI_HCI
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703 //this switching setting cause some 8192cu hw have redownload fw fail issue
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704 //improve 2-stream TX EVM by Jenyu
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706 rtw_write8(Adapter, REG_SPS0_CTRL+3,0x71);
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710 // 2010.07.13 AMPDU aggregation number 9
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711 //rtw_write8(Adapter, REG_MAX_AGGR_NUM, MAX_AGGR_NUM);
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712 rtw_write8(Adapter, REG_MAX_AGGR_NUM, 0x0A); //By tynli. 2010.11.18.
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713 #ifdef CONFIG_USB_HCI
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714 if(is92C && (BOARD_USB_DONGLE == pHalData->BoardType))
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715 rtw_write8(Adapter, 0x40,0x04);
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724 * Function: phy_InitBBRFRegisterDefinition
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726 * OverView: Initialize Register definition offset for Radio Path A/B/C/D
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729 * PADAPTER Adapter,
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733 * Note: The initialization value is constant and it should never be changes
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736 phy_InitBBRFRegisterDefinition(
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737 IN PADAPTER Adapter
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740 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
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742 // RF Interface Sowrtware Control
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743 pHalData->PHYRegDef[RF_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 LSBs if read 32-bit from 0x870
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744 pHalData->PHYRegDef[RF_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872)
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745 pHalData->PHYRegDef[RF_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 LSBs if read 32-bit from 0x874
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746 pHalData->PHYRegDef[RF_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876)
\r
748 // RF Interface Readback Value
\r
749 pHalData->PHYRegDef[RF_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB; // 16 LSBs if read 32-bit from 0x8E0
\r
750 pHalData->PHYRegDef[RF_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB;// 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2)
\r
751 pHalData->PHYRegDef[RF_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB;// 16 LSBs if read 32-bit from 0x8E4
\r
752 pHalData->PHYRegDef[RF_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB;// 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6)
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754 // RF Interface Output (and Enable)
\r
755 pHalData->PHYRegDef[RF_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x860
\r
756 pHalData->PHYRegDef[RF_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x864
\r
758 // RF Interface (Output and) Enable
\r
759 pHalData->PHYRegDef[RF_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862)
\r
760 pHalData->PHYRegDef[RF_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866)
\r
762 //Addr of LSSI. Wirte RF register by driver
\r
763 pHalData->PHYRegDef[RF_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; //LSSI Parameter
\r
764 pHalData->PHYRegDef[RF_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter;
\r
767 pHalData->PHYRegDef[RF_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter; //BB Band Select
\r
768 pHalData->PHYRegDef[RF_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter;
\r
769 pHalData->PHYRegDef[RF_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter;
\r
770 pHalData->PHYRegDef[RF_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter;
\r
772 // Tx AGC Gain Stage (same for all path. Should we remove this?)
\r
773 pHalData->PHYRegDef[RF_PATH_A].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
\r
774 pHalData->PHYRegDef[RF_PATH_B].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
\r
775 pHalData->PHYRegDef[RF_PATH_C].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
\r
776 pHalData->PHYRegDef[RF_PATH_D].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
\r
778 // Tranceiver A~D HSSI Parameter-1
\r
779 pHalData->PHYRegDef[RF_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1; //wire control parameter1
\r
780 pHalData->PHYRegDef[RF_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1; //wire control parameter1
\r
782 // Tranceiver A~D HSSI Parameter-2
\r
783 pHalData->PHYRegDef[RF_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2; //wire control parameter2
\r
784 pHalData->PHYRegDef[RF_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2; //wire control parameter2
\r
786 // RF switch Control
\r
787 pHalData->PHYRegDef[RF_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl; //TR/Ant switch control
\r
788 pHalData->PHYRegDef[RF_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl;
\r
789 pHalData->PHYRegDef[RF_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl;
\r
790 pHalData->PHYRegDef[RF_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl;
\r
793 pHalData->PHYRegDef[RF_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1;
\r
794 pHalData->PHYRegDef[RF_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1;
\r
795 pHalData->PHYRegDef[RF_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1;
\r
796 pHalData->PHYRegDef[RF_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1;
\r
799 pHalData->PHYRegDef[RF_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2;
\r
800 pHalData->PHYRegDef[RF_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2;
\r
801 pHalData->PHYRegDef[RF_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2;
\r
802 pHalData->PHYRegDef[RF_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2;
\r
804 // RX AFE control 1
\r
805 pHalData->PHYRegDef[RF_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance;
\r
806 pHalData->PHYRegDef[RF_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance;
\r
807 pHalData->PHYRegDef[RF_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance;
\r
808 pHalData->PHYRegDef[RF_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance;
\r
810 // RX AFE control 1
\r
811 pHalData->PHYRegDef[RF_PATH_A].rfRxAFE = rOFDM0_XARxAFE;
\r
812 pHalData->PHYRegDef[RF_PATH_B].rfRxAFE = rOFDM0_XBRxAFE;
\r
813 pHalData->PHYRegDef[RF_PATH_C].rfRxAFE = rOFDM0_XCRxAFE;
\r
814 pHalData->PHYRegDef[RF_PATH_D].rfRxAFE = rOFDM0_XDRxAFE;
\r
816 // Tx AFE control 1
\r
817 pHalData->PHYRegDef[RF_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance;
\r
818 pHalData->PHYRegDef[RF_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance;
\r
819 pHalData->PHYRegDef[RF_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance;
\r
820 pHalData->PHYRegDef[RF_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance;
\r
822 // Tx AFE control 2
\r
823 pHalData->PHYRegDef[RF_PATH_A].rfTxAFE = rOFDM0_XATxAFE;
\r
824 pHalData->PHYRegDef[RF_PATH_B].rfTxAFE = rOFDM0_XBTxAFE;
\r
825 pHalData->PHYRegDef[RF_PATH_C].rfTxAFE = rOFDM0_XCTxAFE;
\r
826 pHalData->PHYRegDef[RF_PATH_D].rfTxAFE = rOFDM0_XDTxAFE;
\r
828 // Tranceiver LSSI Readback SI mode
\r
829 pHalData->PHYRegDef[RF_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;
\r
830 pHalData->PHYRegDef[RF_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;
\r
831 pHalData->PHYRegDef[RF_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack;
\r
832 pHalData->PHYRegDef[RF_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack;
\r
834 // Tranceiver LSSI Readback PI mode
\r
835 pHalData->PHYRegDef[RF_PATH_A].rfLSSIReadBackPi = TransceiverA_HSPI_Readback;
\r
836 pHalData->PHYRegDef[RF_PATH_B].rfLSSIReadBackPi = TransceiverB_HSPI_Readback;
\r
837 //pHalData->PHYRegDef[RF_PATH_C].rfLSSIReadBackPi = rFPGA0_XC_LSSIReadBack;
\r
838 //pHalData->PHYRegDef[RF_PATH_D].rfLSSIReadBackPi = rFPGA0_XD_LSSIReadBack;
\r
843 /*-----------------------------------------------------------------------------
\r
844 * Function: phy_ConfigBBWithParaFile()
\r
846 * Overview: This function read BB parameters from general file format, and do register
\r
849 * Input: PADAPTER Adapter
\r
850 * ps1Byte pFileName
\r
854 * Return: RT_STATUS_SUCCESS: configuration file exist
\r
855 * 2008/11/06 MH For 92S we do not support silent reset now. Disable
\r
856 * parameter file compare!!!!!!??
\r
858 *---------------------------------------------------------------------------*/
\r
860 phy_ConfigBBWithParaFile(
\r
861 IN PADAPTER Adapter,
\r
865 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
\r
867 int rtStatus = _SUCCESS;
\r
874 //****************************************
\r
875 // The following is for High Power PA
\r
876 //****************************************
\r
878 phy_ConfigBBExternalPA(
\r
879 IN PADAPTER Adapter
\r
882 #ifdef CONFIG_USB_HCI
\r
883 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
\r
887 if(!pHalData->ExternalPA)
\r
892 // 2010/10/19 MH According to Jenyu/EEChou 's opinion, we need not to execute the
\r
893 // same code as SU. It is already updated in PHY_REG_1T_HP.txt.
\r
895 PHY_SetBBReg(Adapter, 0xee8, BIT28, 1);
\r
896 temp = PHY_QueryBBReg(Adapter, 0x860, bMaskDWord);
\r
897 temp |= (BIT26|BIT21|BIT10|BIT5);
\r
898 PHY_SetBBReg(Adapter, 0x860, bMaskDWord, temp);
\r
899 PHY_SetBBReg(Adapter, 0x870, BIT10, 0);
\r
900 PHY_SetBBReg(Adapter, 0xc80, bMaskDWord, 0x20000080);
\r
901 PHY_SetBBReg(Adapter, 0xc88, bMaskDWord, 0x40000100);
\r
907 /*-----------------------------------------------------------------------------
\r
908 * Function: phy_ConfigBBWithHeaderFile()
\r
910 * Overview: This function read BB parameters from general file format, and do register
\r
913 * Input: PADAPTER Adapter
\r
914 * u1Byte ConfigType 0 => PHY_CONFIG
\r
919 * Return: RT_STATUS_SUCCESS: configuration file exist
\r
921 *---------------------------------------------------------------------------*/
\r
922 #ifndef CONFIG_PHY_SETTING_WITH_ODM
\r
924 phy_ConfigBBWithHeaderFile(
\r
925 IN PADAPTER Adapter,
\r
930 u32* Rtl819XPHY_REGArray_Table;
\r
931 u32* Rtl819XAGCTAB_Array_Table;
\r
932 u16 PHY_REGArrayLen, AGCTAB_ArrayLen;
\r
933 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
\r
934 int ret = _SUCCESS;
\r
937 AGCTAB_ArrayLen = Rtl8723_AGCTAB_1TArrayLength;
\r
938 Rtl819XAGCTAB_Array_Table = (u32*)Rtl8723_AGCTAB_1TArray;
\r
939 PHY_REGArrayLen = Rtl8723_PHY_REG_1TArrayLength;
\r
940 Rtl819XPHY_REGArray_Table = (u32*)Rtl8723_PHY_REG_1TArray;
\r
941 // RT_TRACE(COMP_INIT, DBG_LOUD, (" ===> phy_ConfigBBWithHeaderFile() phy:Rtl8723AGCTAB_1TArray\n"));
\r
942 // RT_TRACE(COMP_INIT, DBG_LOUD, (" ===> phy_ConfigBBWithHeaderFile() agc:Rtl8723PHY_REG_1TArray\n"));
\r
944 if(ConfigType == BaseBand_Config_PHY_REG)
\r
946 #ifdef CONFIG_IOL_BB_PHY_REG
\r
948 struct xmit_frame *xmit_frame;
\r
951 if((xmit_frame=rtw_IOL_accquire_xmit_frame(Adapter)) == NULL) {
\r
956 for(i=0;i<PHY_REGArrayLen;i=i+2)
\r
958 tmp_value=Rtl819XPHY_REGArray_Table[i+1];
\r
960 if (Rtl819XPHY_REGArray_Table[i] == 0xfe)
\r
961 rtw_IOL_append_DELAY_MS_cmd(xmit_frame, 50);
\r
962 else if (Rtl819XPHY_REGArray_Table[i] == 0xfd)
\r
963 rtw_IOL_append_DELAY_MS_cmd(xmit_frame, 5);
\r
964 else if (Rtl819XPHY_REGArray_Table[i] == 0xfc)
\r
965 rtw_IOL_append_DELAY_MS_cmd(xmit_frame, 1);
\r
966 else if (Rtl819XPHY_REGArray_Table[i] == 0xfb)
\r
967 rtw_IOL_append_DELAY_US_cmd(xmit_frame, 50);
\r
968 else if (Rtl819XPHY_REGArray_Table[i] == 0xfa)
\r
969 rtw_IOL_append_DELAY_US_cmd(xmit_frame, 5);
\r
970 else if (Rtl819XPHY_REGArray_Table[i] == 0xf9)
\r
971 rtw_IOL_append_DELAY_US_cmd(xmit_frame, 1);
\r
973 rtw_IOL_append_WD_cmd(xmit_frame, Rtl819XPHY_REGArray_Table[i], tmp_value);
\r
974 //RT_TRACE(COMP_INIT, DBG_TRACE, ("The Rtl819XPHY_REGArray_Table[0] is %lx Rtl819XPHY_REGArray[1] is %lx \n",Rtl819XPHY_REGArray_Table[i], Rtl819XPHY_REGArray_Table[i+1]));
\r
977 ret = rtw_IOL_exec_cmds_sync(Adapter, xmit_frame, 1000,0);
\r
980 for(i=0;i<PHY_REGArrayLen;i=i+2)
\r
982 if (Rtl819XPHY_REGArray_Table[i] == 0xfe){
\r
983 #ifdef CONFIG_LONG_DELAY_ISSUE
\r
989 else if (Rtl819XPHY_REGArray_Table[i] == 0xfd)
\r
991 else if (Rtl819XPHY_REGArray_Table[i] == 0xfc)
\r
993 else if (Rtl819XPHY_REGArray_Table[i] == 0xfb)
\r
995 else if (Rtl819XPHY_REGArray_Table[i] == 0xfa)
\r
997 else if (Rtl819XPHY_REGArray_Table[i] == 0xf9)
\r
1000 PHY_SetBBReg(Adapter, Rtl819XPHY_REGArray_Table[i], bMaskDWord, Rtl819XPHY_REGArray_Table[i+1]);
\r
1002 // Add 1us delay between BB/RF register setting.
\r
1005 //RT_TRACE(COMP_INIT, DBG_TRACE, ("The Rtl819XPHY_REGArray_Table[0] is %lx Rtl819XPHY_REGArray[1] is %lx \n",Rtl819XPHY_REGArray_Table[i], Rtl819XPHY_REGArray_Table[i+1]));
\r
1008 // for External PA
\r
1009 phy_ConfigBBExternalPA(Adapter);
\r
1011 else if(ConfigType == BaseBand_Config_AGC_TAB)
\r
1013 #ifdef CONFIG_IOL_BB_AGC_TAB
\r
1015 struct xmit_frame *xmit_frame;
\r
1017 if((xmit_frame=rtw_IOL_accquire_xmit_frame(Adapter)) == NULL) {
\r
1022 for(i=0;i<AGCTAB_ArrayLen;i=i+2)
\r
1024 rtw_IOL_append_WD_cmd(xmit_frame, Rtl819XAGCTAB_Array_Table[i], Rtl819XAGCTAB_Array_Table[i+1]);
\r
1025 //RT_TRACE(COMP_INIT, DBG_TRACE, ("The Rtl819XAGCTAB_Array_Table[0] is %lx Rtl819XPHY_REGArray[1] is %lx \n",Rtl819XAGCTAB_Array_Table[i], Rtl819XAGCTAB_Array_Table[i+1]));
\r
1028 ret = rtw_IOL_exec_cmds_sync(Adapter, xmit_frame, 1000,0);
\r
1031 for(i=0;i<AGCTAB_ArrayLen;i=i+2)
\r
1033 PHY_SetBBReg(Adapter, Rtl819XAGCTAB_Array_Table[i], bMaskDWord, Rtl819XAGCTAB_Array_Table[i+1]);
\r
1035 // Add 1us delay between BB/RF register setting.
\r
1038 //RT_TRACE(COMP_INIT, DBG_TRACE, ("The Rtl819XAGCTAB_Array_Table[0] is %lx Rtl819XPHY_REGArray[1] is %lx \n",Rtl819XAGCTAB_Array_Table[i], Rtl819XAGCTAB_Array_Table[i+1]));
\r
1049 storePwrIndexDiffRateOffset(
\r
1050 IN PADAPTER Adapter,
\r
1056 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
\r
1058 if(RegAddr == rTxAGC_A_Rate18_06)
\r
1060 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][0] = Data;
\r
1061 //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][0] = 0x%lx\n", pHalData->pwrGroupCnt,
\r
1062 // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][0]));
\r
1064 if(RegAddr == rTxAGC_A_Rate54_24)
\r
1066 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][1] = Data;
\r
1067 //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][1] = 0x%lx\n", pHalData->pwrGroupCnt,
\r
1068 // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][1]));
\r
1070 if(RegAddr == rTxAGC_A_CCK1_Mcs32)
\r
1072 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][6] = Data;
\r
1073 //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][6] = 0x%lx\n", pHalData->pwrGroupCnt,
\r
1074 // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][6]));
\r
1076 if(RegAddr == rTxAGC_B_CCK11_A_CCK2_11 && BitMask == 0xffffff00)
\r
1078 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][7] = Data;
\r
1079 //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][7] = 0x%lx\n", pHalData->pwrGroupCnt,
\r
1080 // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][7]));
\r
1082 if(RegAddr == rTxAGC_A_Mcs03_Mcs00)
\r
1084 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][2] = Data;
\r
1085 //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][2] = 0x%lx\n", pHalData->pwrGroupCnt,
\r
1086 // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][2]));
\r
1088 if(RegAddr == rTxAGC_A_Mcs07_Mcs04)
\r
1090 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][3] = Data;
\r
1091 //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][3] = 0x%lx\n", pHalData->pwrGroupCnt,
\r
1092 // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][3]));
\r
1094 if(RegAddr == rTxAGC_A_Mcs11_Mcs08)
\r
1096 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][4] = Data;
\r
1097 //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][4] = 0x%lx\n", pHalData->pwrGroupCnt,
\r
1098 // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][4]));
\r
1100 if(RegAddr == rTxAGC_A_Mcs15_Mcs12)
\r
1102 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][5] = Data;
\r
1103 //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][5] = 0x%lx\n", pHalData->pwrGroupCnt,
\r
1104 // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][5]));
\r
1106 if(RegAddr == rTxAGC_B_Rate18_06)
\r
1108 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][8] = Data;
\r
1109 //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][8] = 0x%lx\n", pHalData->pwrGroupCnt,
\r
1110 // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][8]));
\r
1112 if(RegAddr == rTxAGC_B_Rate54_24)
\r
1114 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][9] = Data;
\r
1115 //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][9] = 0x%lx\n", pHalData->pwrGroupCnt,
\r
1116 // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][9]));
\r
1118 if(RegAddr == rTxAGC_B_CCK1_55_Mcs32)
\r
1120 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][14] = Data;
\r
1121 //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][14] = 0x%lx\n", pHalData->pwrGroupCnt,
\r
1122 // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][14]));
\r
1124 if(RegAddr == rTxAGC_B_CCK11_A_CCK2_11 && BitMask == 0x000000ff)
\r
1126 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][15] = Data;
\r
1127 //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][15] = 0x%lx\n", pHalData->pwrGroupCnt,
\r
1128 // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][15]));
\r
1130 if(RegAddr == rTxAGC_B_Mcs03_Mcs00)
\r
1132 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][10] = Data;
\r
1133 //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][10] = 0x%lx\n", pHalData->pwrGroupCnt,
\r
1134 // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][10]));
\r
1136 if(RegAddr == rTxAGC_B_Mcs07_Mcs04)
\r
1138 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][11] = Data;
\r
1139 //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][11] = 0x%lx\n", pHalData->pwrGroupCnt,
\r
1140 // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][11]));
\r
1142 if(RegAddr == rTxAGC_B_Mcs11_Mcs08)
\r
1144 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][12] = Data;
\r
1145 //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][12] = 0x%lx\n", pHalData->pwrGroupCnt,
\r
1146 // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][12]));
\r
1148 if(RegAddr == rTxAGC_B_Mcs15_Mcs12)
\r
1150 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][13] = Data;
\r
1151 //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][13] = 0x%lx\n", pHalData->pwrGroupCnt,
\r
1152 // pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][13]));
\r
1153 pHalData->pwrGroupCnt++;
\r
1156 /*-----------------------------------------------------------------------------
\r
1157 * Function: phy_ConfigBBWithPgParaFile
\r
1167 * Revised History:
\r
1169 * 11/06/2008 MHC Create Version 0.
\r
1170 * 2009/07/29 tynli (porting from 92SE branch)2009/03/11 Add copy parameter file to buffer for silent reset
\r
1171 *---------------------------------------------------------------------------*/
\r
1173 phy_ConfigBBWithPgParaFile(
\r
1174 IN PADAPTER Adapter,
\r
1177 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
\r
1179 int rtStatus = _SUCCESS;
\r
1184 } /* phy_ConfigBBWithPgParaFile */
\r
1187 /*-----------------------------------------------------------------------------
\r
1188 * Function: phy_ConfigBBWithPgHeaderFile
\r
1190 * Overview: Config PHY_REG_PG array
\r
1198 * Revised History:
\r
1200 * 11/06/2008 MHC Add later!!!!!!.. Please modify for new files!!!!
\r
1201 * 11/10/2008 tynli Modify to mew files.
\r
1202 *---------------------------------------------------------------------------*/
\r
1204 phy_ConfigBBWithPgHeaderFile(
\r
1205 IN PADAPTER Adapter,
\r
1209 u32* Rtl819XPHY_REGArray_Table_PG;
\r
1210 u16 PHY_REGArrayPGLen;
\r
1211 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
\r
1214 PHY_REGArrayPGLen = Rtl8723_PHY_REG_Array_PGLength;
\r
1215 Rtl819XPHY_REGArray_Table_PG = (u32*)Rtl8723_PHY_REG_Array_PG;
\r
1217 if(ConfigType == BaseBand_Config_PHY_REG)
\r
1219 for(i=0;i<PHY_REGArrayPGLen;i=i+3)
\r
1221 #if 0 //without IO, no delay is neeeded...
\r
1222 if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfe){
\r
1223 #ifdef CONFIG_LONG_DELAY_ISSUE
\r
1224 rtw_msleep_os(50);
\r
1226 rtw_mdelay_os(50);
\r
1229 else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfd)
\r
1231 else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfc)
\r
1233 else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfb)
\r
1234 rtw_udelay_os(50);
\r
1235 else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfa)
\r
1237 else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xf9)
\r
1239 //PHY_SetBBReg(Adapter, Rtl819XPHY_REGArray_Table_PG[i], Rtl819XPHY_REGArray_Table_PG[i+1], Rtl819XPHY_REGArray_Table_PG[i+2]);
\r
1242 storePwrIndexDiffRateOffset(Adapter, Rtl819XPHY_REGArray_Table_PG[i],
\r
1243 Rtl819XPHY_REGArray_Table_PG[i+1],
\r
1244 Rtl819XPHY_REGArray_Table_PG[i+2]);
\r
1245 //RT_TRACE(COMP_SEND, DBG_TRACE, ("The Rtl819XPHY_REGArray_Table_PG[0] is %lx Rtl819XPHY_REGArray_Table_PG[1] is %lx \n",Rtl819XPHY_REGArray_Table_PG[i], Rtl819XPHY_REGArray_Table_PG[i+1]));
\r
1251 //RT_TRACE(COMP_SEND, DBG_LOUD, ("phy_ConfigBBWithPgHeaderFile(): ConfigType != BaseBand_Config_PHY_REG\n"));
\r
1256 } /* phy_ConfigBBWithPgHeaderFile */
\r
1258 #if (MP_DRIVER == 1)
\r
1260 /*-----------------------------------------------------------------------------
\r
1261 * Function: phy_ConfigBBWithMpParaFile()
\r
1263 * Overview: This function read BB parameters from general file format, and do register
\r
1266 * Input: PADAPTER Adapter
\r
1267 * ps1Byte pFileName
\r
1271 * Return: RT_STATUS_SUCCESS: configuration file exist
\r
1272 * 2008/11/06 MH For 92S we do not support silent reset now. Disable
\r
1273 * parameter file compare!!!!!!??
\r
1275 *---------------------------------------------------------------------------*/
\r
1277 phy_ConfigBBWithMpParaFile(
\r
1278 IN PADAPTER Adapter,
\r
1283 int rtStatus = _SUCCESS;
\r
1285 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
\r
1286 s4Byte nLinesRead, ithLine;
\r
1287 RT_STATUS rtStatus = RT_STATUS_SUCCESS;
\r
1289 u4Byte u4bRegOffset, u4bRegMask, u4bRegValue;
\r
1292 if(ADAPTER_TEST_STATUS_FLAG(Adapter, ADAPTER_STATUS_FIRST_INIT))
\r
1294 rtStatus = PlatformReadFile(
\r
1297 (pu1Byte)(pHalData->BufOfLines),
\r
1298 MAX_LINES_HWCONFIG_TXT,
\r
1299 MAX_BYTES_LINE_HWCONFIG_TXT,
\r
1302 if(rtStatus == RT_STATUS_SUCCESS)
\r
1304 PlatformMoveMemory(pHalData->BufOfLines6, pHalData->BufOfLines, nLinesRead*MAX_BYTES_LINE_HWCONFIG_TXT);
\r
1305 pHalData->nLinesRead6 = nLinesRead;
\r
1309 // Temporarily skip PHY_REG_MP.txt if file does not exist.
\r
1310 pHalData->nLinesRead6 = 0;
\r
1311 RT_TRACE(COMP_INIT, DBG_LOUD, ("No matched file \r\n"));
\r
1312 return RT_STATUS_SUCCESS;
\r
1317 PlatformMoveMemory(pHalData->BufOfLines, pHalData->BufOfLines6, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT);
\r
1318 nLinesRead = pHalData->nLinesRead6;
\r
1319 rtStatus = RT_STATUS_SUCCESS;
\r
1323 if(rtStatus == RT_STATUS_SUCCESS)
\r
1325 RT_TRACE(COMP_INIT, DBG_LOUD, ("phy_ConfigBBWithMpParaFile(): read %s ok\n", pFileName));
\r
1327 for(ithLine = 0; ithLine < nLinesRead; ithLine++)
\r
1329 szLine = pHalData->BufOfLines[ithLine];
\r
1331 if(!IsCommentString(szLine))
\r
1333 // Get 1st hex value as register offset.
\r
1334 if(GetHexValueFromString(szLine, &u4bRegOffset, &u4bMove))
\r
1336 if(u4bRegOffset == 0xff)
\r
1340 else if (u4bRegOffset == 0xfe)
\r
1342 else if (u4bRegOffset == 0xfd)
\r
1344 else if (u4bRegOffset == 0xfc)
\r
1346 else if (u4bRegOffset == 0xfb)
\r
1347 PlatformStallExecution(50);
\r
1348 else if (u4bRegOffset == 0xfa)
\r
1349 PlatformStallExecution(5);
\r
1350 else if (u4bRegOffset == 0xf9)
\r
1351 PlatformStallExecution(1);
\r
1353 // Get 2nd hex value as register value.
\r
1354 szLine += u4bMove;
\r
1355 if(GetHexValueFromString(szLine, &u4bRegValue, &u4bMove))
\r
1357 RT_TRACE(COMP_FPGA, DBG_TRACE, ("[ADDR]%03lX=%08lX\n", u4bRegOffset, u4bRegValue));
\r
1358 PHY_SetBBReg(Adapter, u4bRegOffset, bMaskDWord, u4bRegValue);
\r
1360 // Add 1us delay between BB/RF register setting.
\r
1361 PlatformStallExecution(1);
\r
1369 RT_TRACE(COMP_INIT, DBG_LOUD, ("phy_ConfigBBWithMpParaFile(): Failed%s\n", pFileName));
\r
1376 /*-----------------------------------------------------------------------------
\r
1377 * Function: phy_ConfigBBWithMpHeaderFile
\r
1379 * Overview: Config PHY_REG_MP array
\r
1387 * Revised History:
\r
1389 * 02/04/2010 chiyokolin Modify to new files.
\r
1390 *---------------------------------------------------------------------------*/
\r
1392 phy_ConfigBBWithMpHeaderFile(
\r
1393 IN PADAPTER Adapter,
\r
1394 IN u1Byte ConfigType)
\r
1397 u32* Rtl8192CPHY_REGArray_Table_MP;
\r
1398 u16 PHY_REGArrayMPLen;
\r
1399 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
\r
1402 PHY_REGArrayMPLen = Rtl8723_PHY_REG_Array_MPLength;
\r
1403 Rtl8192CPHY_REGArray_Table_MP = (u32*)Rtl8723_PHY_REG_Array_MP;
\r
1405 if(ConfigType == BaseBand_Config_PHY_REG)
\r
1407 for(i=0;i<PHY_REGArrayMPLen;i=i+2)
\r
1409 if (Rtl8192CPHY_REGArray_Table_MP[i] == 0xfe) {
\r
1410 #ifdef CONFIG_LONG_DELAY_ISSUE
\r
1411 rtw_msleep_os(50);
\r
1413 rtw_mdelay_os(50);
\r
1416 else if (Rtl8192CPHY_REGArray_Table_MP[i] == 0xfd)
\r
1418 else if (Rtl8192CPHY_REGArray_Table_MP[i] == 0xfc)
\r
1420 else if (Rtl8192CPHY_REGArray_Table_MP[i] == 0xfb) {
\r
1421 #ifdef CONFIG_LONG_DELAY_ISSUE
\r
1422 rtw_msleep_os(50);
\r
1424 rtw_mdelay_os(50);
\r
1427 else if (Rtl8192CPHY_REGArray_Table_MP[i] == 0xfa)
\r
1429 else if (Rtl8192CPHY_REGArray_Table_MP[i] == 0xf9)
\r
1431 PHY_SetBBReg(Adapter, Rtl8192CPHY_REGArray_Table_MP[i], bMaskDWord, Rtl8192CPHY_REGArray_Table_MP[i+1]);
\r
1433 // Add 1us delay between BB/RF register setting.
\r
1436 // RT_TRACE(COMP_INIT, DBG_TRACE, ("The Rtl8192CPHY_REGArray_Table_MP[%d] is %lx Rtl8192CPHY_REGArray_Table_MP[%d] is %lx \n", i, i+1, Rtl8192CPHY_REGArray_Table_MP[i], Rtl8192CPHY_REGArray_Table_MP[i+1]));
\r
1441 // RT_TRACE(COMP_SEND, DBG_LOUD, ("phy_ConfigBBWithMpHeaderFile(): ConfigType != BaseBand_Config_PHY_REG\n"));
\r
1445 } /* phy_ConfigBBWithMpHeaderFile */
\r
1447 #endif // #if (MP_DRIVER == 1)
\r
1450 phy_BB8192C_Config_1T(
\r
1451 IN PADAPTER Adapter
\r
1456 PHY_SetBBReg(Adapter, rFPGA0_TxInfo, 0x3, 0x1);
\r
1457 PHY_SetBBReg(Adapter, rFPGA1_TxInfo, 0x0303, 0x0101);
\r
1458 PHY_SetBBReg(Adapter, 0xe74, 0x0c000000, 0x1);
\r
1459 PHY_SetBBReg(Adapter, 0xe78, 0x0c000000, 0x1);
\r
1460 PHY_SetBBReg(Adapter, 0xe7c, 0x0c000000, 0x1);
\r
1461 PHY_SetBBReg(Adapter, 0xe80, 0x0c000000, 0x1);
\r
1462 PHY_SetBBReg(Adapter, 0xe88, 0x0c000000, 0x1);
\r
1465 PHY_SetBBReg(Adapter, rFPGA0_TxInfo, 0x3, 0x2);
\r
1466 PHY_SetBBReg(Adapter, rFPGA1_TxInfo, 0x300033, 0x200022);
\r
1468 // 20100519 Joseph: Add for 1T2R config. Suggested by Kevin, Jenyu and Yunan.
\r
1469 PHY_SetBBReg(Adapter, rCCK0_AFESetting, bMaskByte3, 0x45);
\r
1470 PHY_SetBBReg(Adapter, rOFDM0_TRxPathEnable, bMaskByte0, 0x23);
\r
1471 PHY_SetBBReg(Adapter, rOFDM0_AGCParameter1, 0x30, 0x1); // B path first AGC
\r
1473 PHY_SetBBReg(Adapter, 0xe74, 0x0c000000, 0x2);
\r
1474 PHY_SetBBReg(Adapter, 0xe78, 0x0c000000, 0x2);
\r
1475 PHY_SetBBReg(Adapter, 0xe7c, 0x0c000000, 0x2);
\r
1476 PHY_SetBBReg(Adapter, 0xe80, 0x0c000000, 0x2);
\r
1477 PHY_SetBBReg(Adapter, 0xe88, 0x0c000000, 0x2);
\r
1482 // Joseph test: new initialize order!!
\r
1483 // Test only!! This part need to be re-organized.
\r
1484 // Now it is just for 8256.
\r
1486 phy_BB8190_Config_HardCode(
\r
1487 IN PADAPTER Adapter
\r
1490 //RT_ASSERT(FALSE, ("This function is not implement yet!! \n"));
\r
1495 phy_BB8723a_Config_ParaFile(
\r
1496 IN PADAPTER Adapter
\r
1499 EEPROM_EFUSE_PRIV *pEEPROM = GET_EEPROM_EFUSE_PRIV(Adapter);
\r
1500 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
\r
1501 int rtStatus = _SUCCESS;
\r
1503 u8 sz8723BBRegFile[] = RTL8723_PHY_REG;
\r
1504 u8 sz8723AGCTableFile[] = RTL8723_AGC_TAB;
\r
1505 u8 sz8723BBRegPgFile[] = RTL8723_PHY_REG_PG;
\r
1506 u8 sz8723BBRegMpFile[] = RTL8723_PHY_REG_MP;
\r
1508 u8 *pszBBRegFile = NULL, *pszAGCTableFile = NULL, *pszBBRegPgFile = NULL, *pszBBRegMpFile=NULL;
\r
1511 //RT_TRACE(COMP_INIT, DBG_TRACE, ("==>phy_BB8192S_Config_ParaFile\n"));
\r
1513 pszBBRegFile = sz8723BBRegFile ;
\r
1514 pszAGCTableFile = sz8723AGCTableFile;
\r
1515 pszBBRegPgFile = sz8723BBRegPgFile;
\r
1516 pszBBRegMpFile = sz8723BBRegMpFile;
\r
1519 // 1. Read PHY_REG.TXT BB INIT!!
\r
1520 // We will seperate as 88C / 92C according to chip version
\r
1522 #ifdef CONFIG_EMBEDDED_FWIMG
\r
1523 #ifdef CONFIG_PHY_SETTING_WITH_ODM
\r
1524 if(HAL_STATUS_FAILURE ==ODM_ConfigBBWithHeaderFile(&pHalData->odmpriv, CONFIG_BB_PHY_REG))
\r
1527 rtStatus = phy_ConfigBBWithHeaderFile(Adapter, BaseBand_Config_PHY_REG);
\r
1530 // No matter what kind of CHIP we always read PHY_REG.txt. We must copy different
\r
1531 // type of parameter files to phy_reg.txt at first.
\r
1532 rtStatus = phy_ConfigBBWithParaFile(Adapter,pszBBRegFile);
\r
1533 #endif//#ifdef CONFIG_EMBEDDED_FWIMG
\r
1535 if(rtStatus != _SUCCESS){
\r
1536 //RT_TRACE(COMP_INIT, DBG_SERIOUS, ("phy_BB8192S_Config_ParaFile():Write BB Reg Fail!!"));
\r
1537 goto phy_BB8190_Config_ParaFile_Fail;
\r
1540 #if MP_DRIVER == 1
\r
1541 if (Adapter->registrypriv.mp_mode == 1)
\r
1544 // 1.1 Read PHY_REG_MP.TXT BB INIT!!
\r
1545 // We will seperate as 88C / 92C according to chip version
\r
1547 #ifdef CONFIG_EMBEDDED_FWIMG
\r
1548 rtStatus = phy_ConfigBBWithMpHeaderFile(Adapter, BaseBand_Config_PHY_REG);
\r
1550 // No matter what kind of CHIP we always read PHY_REG.txt. We must copy different
\r
1551 // type of parameter files to phy_reg.txt at first.
\r
1552 rtStatus = phy_ConfigBBWithMpParaFile(Adapter, pszBBRegMpFile);
\r
1555 if(rtStatus != _SUCCESS){
\r
1556 // RT_TRACE(COMP_INIT, DBG_SERIOUS, ("phy_BB8192S_Config_ParaFile():Write BB Reg MP Fail!!"));
\r
1557 goto phy_BB8190_Config_ParaFile_Fail;
\r
1560 #endif // #if (MP_DRIVER == 1)
\r
1563 // 20100318 Joseph: Config 2T2R to 1T2R if necessary.
\r
1565 if(pHalData->rf_type == RF_1T2R)
\r
1567 phy_BB8192C_Config_1T(Adapter);
\r
1568 DBG_8192C("phy_BB8723a_Config_ParaFile():Config to 1T!!\n");
\r
1572 // 2. If EEPROM or EFUSE autoload OK, We must config by PHY_REG_PG.txt
\r
1574 if (pEEPROM->bautoload_fail_flag == _FALSE)
\r
1576 pHalData->pwrGroupCnt = 0;
\r
1578 #ifdef CONFIG_EMBEDDED_FWIMG
\r
1579 rtStatus = phy_ConfigBBWithPgHeaderFile(Adapter, BaseBand_Config_PHY_REG);
\r
1581 rtStatus = phy_ConfigBBWithPgParaFile(Adapter, pszBBRegPgFile);
\r
1585 if(rtStatus != _SUCCESS){
\r
1586 //RT_TRACE(COMP_INIT, DBG_SERIOUS, ("phy_BB8192S_Config_ParaFile():BB_PG Reg Fail!!"));
\r
1587 goto phy_BB8190_Config_ParaFile_Fail;
\r
1591 // 3. BB AGC table Initialization
\r
1593 #ifdef CONFIG_EMBEDDED_FWIMG
\r
1594 #ifdef CONFIG_PHY_SETTING_WITH_ODM
\r
1595 if(HAL_STATUS_FAILURE ==ODM_ConfigBBWithHeaderFile(&pHalData->odmpriv, CONFIG_BB_AGC_TAB))
\r
1598 rtStatus = phy_ConfigBBWithHeaderFile(Adapter, BaseBand_Config_AGC_TAB);
\r
1599 #endif//#ifdef CONFIG_PHY_SETTING_WITH_ODM
\r
1601 //RT_TRACE(COMP_INIT, DBG_LOUD, ("phy_BB8192S_Config_ParaFile AGC_TAB.txt\n"));
\r
1602 rtStatus = phy_ConfigBBWithParaFile(Adapter, pszAGCTableFile);
\r
1605 if(rtStatus != _SUCCESS){
\r
1606 //RT_TRACE(COMP_FPGA, DBG_SERIOUS, ("phy_BB8192S_Config_ParaFile():AGC Table Fail\n"));
\r
1607 goto phy_BB8190_Config_ParaFile_Fail;
\r
1610 phy_BB8190_Config_ParaFile_Fail:
\r
1617 PHY_BBConfig8723A(
\r
1618 IN PADAPTER Adapter
\r
1621 int rtStatus = _SUCCESS;
\r
1622 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
\r
1625 u8 value8,CrystalCap;
\r
1627 phy_InitBBRFRegisterDefinition(Adapter);
\r
1629 if(IS_HARDWARE_TYPE_8723A(Adapter))
\r
1631 // Suggested by Scott. tynli_test. 2010.12.30.
\r
1633 TmpU1B = rtw_read8(Adapter, REG_AFE_PLL_CTRL);
\r
1635 rtw_write8(Adapter, REG_AFE_PLL_CTRL, (TmpU1B|BIT1));
\r
1638 //2. 0x29[7:0] = 0xFF
\r
1639 rtw_write8(Adapter, REG_AFE_PLL_CTRL+1, 0xff);
\r
1642 //3. 0x02[1:0] = 2b'11
\r
1643 TmpU1B = rtw_read8(Adapter, REG_SYS_FUNC_EN);
\r
1644 rtw_write8(Adapter, REG_SYS_FUNC_EN, (TmpU1B|FEN_BB_GLB_RSTn|FEN_BBRSTB));
\r
1647 TmpU1B = rtw_read8(Adapter, REG_AFE_XTAL_CTRL+1);
\r
1648 rtw_write8(Adapter, REG_AFE_XTAL_CTRL+1, (TmpU1B&(~BIT6)));
\r
1650 //5. 0x24[20] = 0 //Advised by SD3 Alex Wang. 2011.02.09.
\r
1651 TmpU1B = rtw_read8(Adapter, REG_AFE_XTAL_CTRL+2);
\r
1652 rtw_write8(Adapter, REG_AFE_XTAL_CTRL+2, (TmpU1B&(~BIT4)));
\r
1654 //6. 0x1f[7:0] = 0x07
\r
1655 rtw_write8(Adapter, REG_RF_CTRL, 0x07);
\r
1659 // Enable BB and RF
\r
1660 RegVal = rtw_read16(Adapter, REG_SYS_FUNC_EN);
\r
1661 rtw_write16(Adapter, REG_SYS_FUNC_EN, (u16)(RegVal|BIT13|BIT0|BIT1));
\r
1663 // 20090923 Joseph: Advised by Steven and Jenyu. Power sequence before init RF.
\r
1664 rtw_write8(Adapter, REG_AFE_PLL_CTRL, 0x83);
\r
1665 rtw_write8(Adapter, REG_AFE_PLL_CTRL+1, 0xdb);
\r
1667 rtw_write8(Adapter, REG_RF_CTRL, RF_EN|RF_RSTB|RF_SDMRSTB);
\r
1669 #ifdef CONFIG_USB_HCI
\r
1670 rtw_write8(Adapter, REG_SYS_FUNC_EN, FEN_USBA | FEN_USBD | FEN_BB_GLB_RSTn | FEN_BBRSTB);
\r
1672 rtw_write8(Adapter, REG_SYS_FUNC_EN, FEN_PPLL|FEN_PCIEA|FEN_DIO_PCIE|FEN_BB_GLB_RSTn|FEN_BBRSTB);
\r
1675 // 2009/10/21 by SD1 Jong. Modified by tynli. Not in Documented in V8.1.
\r
1676 #ifdef CONFIG_USB_HCI
\r
1677 //To Fix MAC loopback mode fail. Suggested by SD4 Johnny. 2010.03.23.
\r
1678 rtw_write8(Adapter, REG_LDOHCI12_CTRL, 0x0f);
\r
1679 rtw_write8(Adapter, 0x15, 0xe9);
\r
1682 rtw_write8(Adapter, REG_AFE_XTAL_CTRL+1, 0x80);
\r
1684 #ifdef CONFIG_PCI_HCI
\r
1685 // Force use left antenna by default for 88C.
\r
1686 // if(!IS_92C_SERIAL(pHalData->VersionID) || IS_92C_1T2R(pHalData->VersionID))
\r
1687 if(Adapter->ledpriv.LedStrategy != SW_LED_MODE10)
\r
1689 RegVal = rtw_read32(Adapter, REG_LEDCFG0);
\r
1690 rtw_write32(Adapter, REG_LEDCFG0, RegVal|BIT23);
\r
1696 // Config BB and AGC
\r
1698 rtStatus = phy_BB8723a_Config_ParaFile(Adapter);
\r
1700 #ifdef CONFIG_USB_HCI
\r
1701 if(IS_HARDWARE_TYPE_8192CU(Adapter)&&IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID)
\r
1702 &&(pHalData->BoardType == BOARD_USB_High_PA))
\r
1703 rtw_write8(Adapter, 0xc72, 0x50);
\r
1706 if(IS_HARDWARE_TYPE_8723A(Adapter) && pHalData->EEPROMVersion >= 0x01)
\r
1708 CrystalCap = pHalData->CrystalCap & 0x3F;
\r
1709 PHY_SetBBReg(Adapter, REG_MAC_PHY_CTRL, 0xFFF000, (CrystalCap | (CrystalCap << 6)));
\r
1712 if(IS_HARDWARE_TYPE_8723AE(Adapter))
\r
1713 PHY_SetBBReg(Adapter, REG_LDOA15_CTRL, bMaskDWord, 0x01572505);
\r
1719 PHY_RFConfig8723A(
\r
1720 IN PADAPTER Adapter
\r
1723 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
\r
1724 int rtStatus = _SUCCESS;
\r
1729 rtStatus = PHY_RF6052_Config8723A(Adapter);
\r
1734 /*-----------------------------------------------------------------------------
\r
1735 * Function: PHY_ConfigRFWithParaFile()
\r
1737 * Overview: This function read RF parameters from general file format, and do RF 3-wire
\r
1739 * Input: PADAPTER Adapter
\r
1740 * ps1Byte pFileName
\r
1741 * RF_RADIO_PATH_E eRFPath
\r
1745 * Return: RT_STATUS_SUCCESS: configuration file exist
\r
1747 * Note: Delay may be required for RF configuration
\r
1748 *---------------------------------------------------------------------------*/
\r
1750 rtl8192c_PHY_ConfigRFWithParaFile(
\r
1751 IN PADAPTER Adapter,
\r
1753 RF_RADIO_PATH_E eRFPath
\r
1756 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
\r
1758 int rtStatus = _SUCCESS;
\r
1765 //****************************************
\r
1766 // The following is for High Power PA
\r
1767 //****************************************
\r
1768 #define HighPowerRadioAArrayLen 22
\r
1769 //This is for High power PA
\r
1770 u32 Rtl8192S_HighPower_RadioA_Array[HighPowerRadioAArrayLen] = {
\r
1785 PHY_ConfigRFExternalPA(
\r
1786 IN PADAPTER Adapter,
\r
1787 RF_RADIO_PATH_E eRFPath
\r
1790 int rtStatus = _SUCCESS;
\r
1791 #ifdef CONFIG_USB_HCI
\r
1792 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
\r
1795 if(!pHalData->ExternalPA)
\r
1800 // 2010/10/19 MH According to Jenyu/EEChou 's opinion, we need not to execute the
\r
1801 // same code as SU. It is already updated in radio_a_1T_HP.txt.
\r
1803 //add for SU High Power PA
\r
1804 for(i = 0;i<HighPowerRadioAArrayLen; i=i+2)
\r
1806 RT_TRACE(COMP_INIT, DBG_LOUD, ("External PA, write RF 0x%lx=0x%lx\n", Rtl8192S_HighPower_RadioA_Array[i], Rtl8192S_HighPower_RadioA_Array[i+1]));
\r
1807 PHY_SetRFReg(Adapter, eRFPath, Rtl8192S_HighPower_RadioA_Array[i], bRFRegOffsetMask, Rtl8192S_HighPower_RadioA_Array[i+1]);
\r
1814 //****************************************
\r
1815 /*-----------------------------------------------------------------------------
\r
1816 * Function: PHY_ConfigRFWithHeaderFile()
\r
1818 * Overview: This function read RF parameters from general file format, and do RF 3-wire
\r
1820 * Input: PADAPTER Adapter
\r
1821 * ps1Byte pFileName
\r
1822 * RF_RADIO_PATH_E eRFPath
\r
1826 * Return: RT_STATUS_SUCCESS: configuration file exist
\r
1828 * Note: Delay may be required for RF configuration
\r
1829 *---------------------------------------------------------------------------*/
\r
1830 #ifndef CONFIG_PHY_SETTING_WITH_ODM
\r
1832 rtl8723a_PHY_ConfigRFWithHeaderFile(
\r
1833 IN PADAPTER Adapter,
\r
1834 RF_RADIO_PATH_E eRFPath
\r
1839 int rtStatus = _SUCCESS;
\r
1840 u32* Rtl819XRadioA_Array_Table;
\r
1841 u32* Rtl819XRadioB_Array_Table;
\r
1842 u16 RadioA_ArrayLen,RadioB_ArrayLen;
\r
1843 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
\r
1846 RadioA_ArrayLen = Rtl8723_RadioA_1TArrayLength;
\r
1847 Rtl819XRadioA_Array_Table = (u32*)Rtl8723_RadioA_1TArray;
\r
1848 RadioB_ArrayLen = Rtl8723_RadioB_1TArrayLength;
\r
1849 Rtl819XRadioB_Array_Table = (u32*)Rtl8723_RadioB_1TArray;
\r
1850 // RT_TRACE(COMP_INIT, DBG_LOUD, (" ===> PHY_ConfigRFWithHeaderFile() Radio_A:Rtl8723RadioA_1TArray\n"));
\r
1851 // RT_TRACE(COMP_INIT, DBG_LOUD, (" ===> PHY_ConfigRFWithHeaderFile() Radio_B:Rtl8723RadioB_1TArray\n"));
\r
1856 #ifdef CONFIG_IOL_RF_RF90_PATH_A
\r
1858 struct xmit_frame *xmit_frame;
\r
1859 if((xmit_frame=rtw_IOL_accquire_xmit_frame(Adapter)) == NULL) {
\r
1864 for(i = 0;i<RadioA_ArrayLen; i=i+2)
\r
1866 if(Rtl819XRadioA_Array_Table[i] == 0xfe)
\r
1867 rtw_IOL_append_DELAY_MS_cmd(xmit_frame, 50);
\r
1868 else if (Rtl819XRadioA_Array_Table[i] == 0xfd)
\r
1869 rtw_IOL_append_DELAY_MS_cmd(xmit_frame, 5);
\r
1870 else if (Rtl819XRadioA_Array_Table[i] == 0xfc)
\r
1871 rtw_IOL_append_DELAY_MS_cmd(xmit_frame, 1);
\r
1872 else if (Rtl819XRadioA_Array_Table[i] == 0xfb)
\r
1873 rtw_IOL_append_DELAY_US_cmd(xmit_frame, 50);
\r
1874 else if (Rtl819XRadioA_Array_Table[i] == 0xfa)
\r
1875 rtw_IOL_append_DELAY_US_cmd(xmit_frame, 5);
\r
1876 else if (Rtl819XRadioA_Array_Table[i] == 0xf9)
\r
1877 rtw_IOL_append_DELAY_US_cmd(xmit_frame, 1);
\r
1880 BB_REGISTER_DEFINITION_T *pPhyReg = &pHalData->PHYRegDef[eRFPath];
\r
1881 u32 NewOffset = 0;
\r
1882 u32 DataAndAddr = 0;
\r
1884 NewOffset = Rtl819XRadioA_Array_Table[i] & 0x3f;
\r
1885 DataAndAddr = ((NewOffset<<20) | (Rtl819XRadioA_Array_Table[i+1]&0x000fffff)) & 0x0fffffff; // T65 RF
\r
1886 rtw_IOL_append_WD_cmd(xmit_frame, pPhyReg->rf3wireOffset, DataAndAddr);
\r
1889 rtStatus = rtw_IOL_exec_cmds_sync(Adapter, xmit_frame, 1000,0);
\r
1892 for(i = 0;i<RadioA_ArrayLen; i=i+2)
\r
1894 if(Rtl819XRadioA_Array_Table[i] == 0xfe) {
\r
1895 #ifdef CONFIG_LONG_DELAY_ISSUE
\r
1896 rtw_msleep_os(50);
\r
1898 rtw_mdelay_os(50);
\r
1901 else if (Rtl819XRadioA_Array_Table[i] == 0xfd)
\r
1903 else if (Rtl819XRadioA_Array_Table[i] == 0xfc)
\r
1905 else if (Rtl819XRadioA_Array_Table[i] == 0xfb)
\r
1906 rtw_udelay_os(50);
\r
1907 else if (Rtl819XRadioA_Array_Table[i] == 0xfa)
\r
1909 else if (Rtl819XRadioA_Array_Table[i] == 0xf9)
\r
1913 PHY_SetRFReg(Adapter, eRFPath, Rtl819XRadioA_Array_Table[i], bRFRegOffsetMask, Rtl819XRadioA_Array_Table[i+1]);
\r
1914 // Add 1us delay between BB/RF register setting.
\r
1919 //Add for High Power PA
\r
1920 PHY_ConfigRFExternalPA(Adapter, eRFPath);
\r
1923 #ifdef CONFIG_IOL_RF_RF_PATH_B
\r
1925 struct xmit_frame *xmit_frame;
\r
1926 if((xmit_frame=rtw_IOL_accquire_xmit_frame(Adapter)) == NULL) {
\r
1931 for(i = 0;i<RadioB_ArrayLen; i=i+2)
\r
1933 if(Rtl819XRadioB_Array_Table[i] == 0xfe)
\r
1934 rtw_IOL_append_DELAY_MS_cmd(xmit_frame, 50);
\r
1935 else if (Rtl819XRadioB_Array_Table[i] == 0xfd)
\r
1936 rtw_IOL_append_DELAY_MS_cmd(xmit_frame, 5);
\r
1937 else if (Rtl819XRadioB_Array_Table[i] == 0xfc)
\r
1938 rtw_IOL_append_DELAY_MS_cmd(xmit_frame, 1);
\r
1939 else if (Rtl819XRadioB_Array_Table[i] == 0xfb)
\r
1940 rtw_IOL_append_DELAY_US_cmd(xmit_frame, 50);
\r
1941 else if (Rtl819XRadioB_Array_Table[i] == 0xfa)
\r
1942 rtw_IOL_append_DELAY_US_cmd(xmit_frame, 5);
\r
1943 else if (Rtl819XRadioB_Array_Table[i] == 0xf9)
\r
1944 rtw_IOL_append_DELAY_US_cmd(xmit_frame, 1);
\r
1947 BB_REGISTER_DEFINITION_T *pPhyReg = &pHalData->PHYRegDef[eRFPath];
\r
1948 u32 NewOffset = 0;
\r
1949 u32 DataAndAddr = 0;
\r
1951 NewOffset = Rtl819XRadioB_Array_Table[i] & 0x3f;
\r
1952 DataAndAddr = ((NewOffset<<20) | (Rtl819XRadioB_Array_Table[i+1]&0x000fffff)) & 0x0fffffff; // T65 RF
\r
1953 rtw_IOL_append_WD_cmd(xmit_frame, pPhyReg->rf3wireOffset, DataAndAddr);
\r
1956 rtStatus = rtw_IOL_exec_cmds_sync(Adapter, xmit_frame, 1000,0);
\r
1959 for(i = 0;i<RadioB_ArrayLen; i=i+2)
\r
1961 if(Rtl819XRadioB_Array_Table[i] == 0xfe)
\r
1962 { // Deay specific ms. Only RF configuration require delay.
\r
1963 #if 0//#ifdef CONFIG_USB_HCI
\r
1964 #ifdef CONFIG_LONG_DELAY_ISSUE
\r
1965 rtw_msleep_os(1000);
\r
1967 rtw_mdelay_os(1000);
\r
1970 #ifdef CONFIG_LONG_DELAY_ISSUE
\r
1971 rtw_msleep_os(50);
\r
1973 rtw_mdelay_os(50);
\r
1977 else if (Rtl819XRadioB_Array_Table[i] == 0xfd)
\r
1979 else if (Rtl819XRadioB_Array_Table[i] == 0xfc)
\r
1981 else if (Rtl819XRadioB_Array_Table[i] == 0xfb)
\r
1982 rtw_udelay_os(50);
\r
1983 else if (Rtl819XRadioB_Array_Table[i] == 0xfa)
\r
1985 else if (Rtl819XRadioB_Array_Table[i] == 0xf9)
\r
1989 PHY_SetRFReg(Adapter, eRFPath, Rtl819XRadioB_Array_Table[i], bRFRegOffsetMask, Rtl819XRadioB_Array_Table[i+1]);
\r
1990 // Add 1us delay between BB/RF register setting.
\r
2008 /*-----------------------------------------------------------------------------
\r
2009 * Function: PHY_CheckBBAndRFOK()
\r
2011 * Overview: This function is write register and then readback to make sure whether
\r
2012 * BB[PHY0, PHY1], RF[Patha, path b, path c, path d] is Ok
\r
2014 * Input: PADAPTER Adapter
\r
2015 * HW90_BLOCK_E CheckBlock
\r
2016 * RF_RADIO_PATH_E eRFPath // it is used only when CheckBlock is HW90_BLOCK_RF
\r
2020 * Return: RT_STATUS_SUCCESS: PHY is OK
\r
2022 * Note: This function may be removed in the ASIC
\r
2023 *---------------------------------------------------------------------------*/
\r
2025 PHY_CheckBBAndRFOK(
\r
2026 IN PADAPTER Adapter,
\r
2027 IN HW90_BLOCK_E CheckBlock,
\r
2028 IN RF_RADIO_PATH_E eRFPath
\r
2031 int rtStatus = _SUCCESS;
\r
2033 u32 i, CheckTimes = 4,ulRegRead = 0;
\r
2036 u32 WriteData[] = {0xfffff027, 0xaa55a02f, 0x00000027, 0x55aa502f};
\r
2038 // Initialize register address offset to be checked
\r
2039 WriteAddr[HW90_BLOCK_MAC] = 0x100;
\r
2040 WriteAddr[HW90_BLOCK_PHY0] = 0x900;
\r
2041 WriteAddr[HW90_BLOCK_PHY1] = 0x800;
\r
2042 WriteAddr[HW90_BLOCK_RF] = 0x3;
\r
2044 for(i=0 ; i < CheckTimes ; i++)
\r
2048 // Write Data to register and readback
\r
2050 switch(CheckBlock)
\r
2052 case HW90_BLOCK_MAC:
\r
2053 //RT_ASSERT(FALSE, ("PHY_CheckBBRFOK(): Never Write 0x100 here!"));
\r
2054 //RT_TRACE(COMP_INIT, DBG_LOUD, ("PHY_CheckBBRFOK(): Never Write 0x100 here!\n"));
\r
2057 case HW90_BLOCK_PHY0:
\r
2058 case HW90_BLOCK_PHY1:
\r
2059 rtw_write32(Adapter, WriteAddr[CheckBlock], WriteData[i]);
\r
2060 ulRegRead = rtw_read32(Adapter, WriteAddr[CheckBlock]);
\r
2063 case HW90_BLOCK_RF:
\r
2064 // When initialization, we want the delay function(delay_ms(), delay_us()
\r
2065 // ==> actually we call PlatformStallExecution()) to do NdisStallExecution()
\r
2066 // [busy wait] instead of NdisMSleep(). So we acquire RT_INITIAL_SPINLOCK
\r
2067 // to run at Dispatch level to achive it.
\r
2068 //cosa PlatformAcquireSpinLock(Adapter, RT_INITIAL_SPINLOCK);
\r
2069 WriteData[i] &= 0xfff;
\r
2070 PHY_SetRFReg(Adapter, eRFPath, WriteAddr[HW90_BLOCK_RF], bRFRegOffsetMask, WriteData[i]);
\r
2071 // TODO: we should not delay for such a long time. Ask SD3
\r
2072 rtw_mdelay_os(10);
\r
2073 ulRegRead = PHY_QueryRFReg(Adapter, eRFPath, WriteAddr[HW90_BLOCK_RF], bMaskDWord);
\r
2074 rtw_mdelay_os(10);
\r
2075 //cosa PlatformReleaseSpinLock(Adapter, RT_INITIAL_SPINLOCK);
\r
2085 // Check whether readback data is correct
\r
2087 if(ulRegRead != WriteData[i])
\r
2089 //RT_TRACE(COMP_FPGA, DBG_LOUD, ("ulRegRead: %lx, WriteData: %lx \n", ulRegRead, WriteData[i]));
\r
2100 rtl8192c_PHY_GetHWRegOriginalValue(
\r
2101 IN PADAPTER Adapter
\r
2104 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
\r
2106 // read rx initial gain
\r
2107 pHalData->DefaultInitialGain[0] = (u8)PHY_QueryBBReg(Adapter, rOFDM0_XAAGCCore1, bMaskByte0);
\r
2108 pHalData->DefaultInitialGain[1] = (u8)PHY_QueryBBReg(Adapter, rOFDM0_XBAGCCore1, bMaskByte0);
\r
2109 pHalData->DefaultInitialGain[2] = (u8)PHY_QueryBBReg(Adapter, rOFDM0_XCAGCCore1, bMaskByte0);
\r
2110 pHalData->DefaultInitialGain[3] = (u8)PHY_QueryBBReg(Adapter, rOFDM0_XDAGCCore1, bMaskByte0);
\r
2111 //RT_TRACE(COMP_INIT, DBG_LOUD,
\r
2112 //("Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x) \n",
\r
2113 //pHalData->DefaultInitialGain[0], pHalData->DefaultInitialGain[1],
\r
2114 //pHalData->DefaultInitialGain[2], pHalData->DefaultInitialGain[3]));
\r
2117 pHalData->framesync = (u8)PHY_QueryBBReg(Adapter, rOFDM0_RxDetector3, bMaskByte0);
\r
2118 pHalData->framesyncC34 = PHY_QueryBBReg(Adapter, rOFDM0_RxDetector2, bMaskDWord);
\r
2119 //RT_TRACE(COMP_INIT, DBG_LOUD, ("Default framesync (0x%x) = 0x%x \n",
\r
2120 // rOFDM0_RxDetector3, pHalData->framesync));
\r
2126 // Map dBm into Tx power index according to
\r
2127 // current HW model, for example, RF and PA, and
\r
2128 // current wireless mode.
\r
2129 // By Bruce, 2008-01-29.
\r
2132 phy_DbmToTxPwrIdx(
\r
2133 IN PADAPTER Adapter,
\r
2134 IN WIRELESS_MODE WirelessMode,
\r
2143 // Tested by MP, we found that CCK Index 0 equals to 8dbm, OFDM legacy equals to
\r
2144 // 3dbm, and OFDM HT equals to 0dbm repectively.
\r
2146 // The mapping may be different by different NICs. Do not use this formula for what needs accurate result.
\r
2147 // By Bruce, 2008-01-29.
\r
2149 switch(WirelessMode)
\r
2151 case WIRELESS_MODE_B:
\r
2155 case WIRELESS_MODE_G:
\r
2156 case WIRELESS_MODE_N_24G:
\r
2164 if((PowerInDbm - Offset) > 0)
\r
2166 TxPwrIdx = (u8)((PowerInDbm - Offset) * 2);
\r
2173 // Tx Power Index is too large.
\r
2174 if(TxPwrIdx > MAX_TXPWR_IDX_NMODE_92S)
\r
2175 TxPwrIdx = MAX_TXPWR_IDX_NMODE_92S;
\r
2182 // Map Tx power index into dBm according to
\r
2183 // current HW model, for example, RF and PA, and
\r
2184 // current wireless mode.
\r
2185 // By Bruce, 2008-01-29.
\r
2188 phy_TxPwrIdxToDbm(
\r
2189 IN PADAPTER Adapter,
\r
2190 IN WIRELESS_MODE WirelessMode,
\r
2195 int PwrOutDbm = 0;
\r
2198 // Tested by MP, we found that CCK Index 0 equals to -7dbm, OFDM legacy equals to -8dbm.
\r
2200 // The mapping may be different by different NICs. Do not use this formula for what needs accurate result.
\r
2201 // By Bruce, 2008-01-29.
\r
2203 switch(WirelessMode)
\r
2205 case WIRELESS_MODE_B:
\r
2209 case WIRELESS_MODE_G:
\r
2210 case WIRELESS_MODE_N_24G:
\r
2217 PwrOutDbm = TxPwrIdx / 2 + Offset; // Discard the decimal part.
\r
2223 /*-----------------------------------------------------------------------------
\r
2224 * Function: GetTxPowerLevel8190()
\r
2226 * Overview: This function is export to "common" moudule
\r
2228 * Input: PADAPTER Adapter
\r
2229 * psByte Power Level
\r
2235 *---------------------------------------------------------------------------*/
\r
2237 PHY_GetTxPowerLevel8192C(
\r
2238 IN PADAPTER Adapter,
\r
2239 OUT u32* powerlevel
\r
2242 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
\r
2243 u8 TxPwrLevel = 0;
\r
2247 // Because the Tx power indexes are different, we report the maximum of them to
\r
2248 // meet the CCX TPC request. By Bruce, 2008-01-31.
\r
2252 TxPwrLevel = pHalData->CurrentCckTxPwrIdx;
\r
2253 TxPwrDbm = phy_TxPwrIdxToDbm(Adapter, WIRELESS_MODE_B, TxPwrLevel);
\r
2256 TxPwrLevel = pHalData->CurrentOfdm24GTxPwrIdx + pHalData->LegacyHTTxPowerDiff;
\r
2258 // Compare with Legacy OFDM Tx power.
\r
2259 if(phy_TxPwrIdxToDbm(Adapter, WIRELESS_MODE_G, TxPwrLevel) > TxPwrDbm)
\r
2260 TxPwrDbm = phy_TxPwrIdxToDbm(Adapter, WIRELESS_MODE_G, TxPwrLevel);
\r
2263 TxPwrLevel = pHalData->CurrentOfdm24GTxPwrIdx;
\r
2265 // Compare with HT OFDM Tx power.
\r
2266 if(phy_TxPwrIdxToDbm(Adapter, WIRELESS_MODE_N_24G, TxPwrLevel) > TxPwrDbm)
\r
2267 TxPwrDbm = phy_TxPwrIdxToDbm(Adapter, WIRELESS_MODE_N_24G, TxPwrLevel);
\r
2269 *powerlevel = TxPwrDbm;
\r
2273 static void getTxPowerIndex(
\r
2274 IN PADAPTER Adapter,
\r
2276 IN OUT u8* cckPowerLevel,
\r
2277 IN OUT u8* ofdmPowerLevel
\r
2280 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
\r
2281 u8 index = (channel -1);
\r
2283 cckPowerLevel[RF_PATH_A] = pHalData->TxPwrLevelCck[RF_PATH_A][index]; //RF-A
\r
2284 cckPowerLevel[RF_PATH_B] = pHalData->TxPwrLevelCck[RF_PATH_B][index]; //RF-B
\r
2286 // 2. OFDM for 1S or 2S
\r
2287 if (GET_RF_TYPE(Adapter) == RF_1T2R || GET_RF_TYPE(Adapter) == RF_1T1R)
\r
2289 // Read HT 40 OFDM TX power
\r
2290 ofdmPowerLevel[RF_PATH_A] = pHalData->TxPwrLevelHT40_1S[RF_PATH_A][index];
\r
2291 ofdmPowerLevel[RF_PATH_B] = pHalData->TxPwrLevelHT40_1S[RF_PATH_B][index];
\r
2293 else if (GET_RF_TYPE(Adapter) == RF_2T2R)
\r
2295 // Read HT 40 OFDM TX power
\r
2296 ofdmPowerLevel[RF_PATH_A] = pHalData->TxPwrLevelHT40_2S[RF_PATH_A][index];
\r
2297 ofdmPowerLevel[RF_PATH_B] = pHalData->TxPwrLevelHT40_2S[RF_PATH_B][index];
\r
2299 //RTPRINT(FPHY, PHY_TXPWR, ("Channel-%d, set tx power index !!\n", channel));
\r
2302 static void ccxPowerIndexCheck(
\r
2303 IN PADAPTER Adapter,
\r
2305 IN OUT u8* cckPowerLevel,
\r
2306 IN OUT u8* ofdmPowerLevel
\r
2310 PMGNT_INFO pMgntInfo = &(Adapter->MgntInfo);
\r
2311 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
\r
2312 PRT_CCX_INFO pCcxInfo = GET_CCX_INFO(pMgntInfo);
\r
2315 // CCX 2 S31, AP control of client transmit power:
\r
2316 // 1. We shall not exceed Cell Power Limit as possible as we can.
\r
2317 // 2. Tolerance is +/- 5dB.
\r
2318 // 3. 802.11h Power Contraint takes higher precedence over CCX Cell Power Limit.
\r
2321 // 1. 802.11h power contraint
\r
2323 // 071011, by rcnjko.
\r
2325 if( pMgntInfo->OpMode == RT_OP_MODE_INFRASTRUCTURE &&
\r
2326 pMgntInfo->mAssoc &&
\r
2327 pCcxInfo->bUpdateCcxPwr &&
\r
2328 pCcxInfo->bWithCcxCellPwr &&
\r
2329 channel == pMgntInfo->dot11CurrentChannelNumber)
\r
2331 u1Byte CckCellPwrIdx = phy_DbmToTxPwrIdx(Adapter, WIRELESS_MODE_B, pCcxInfo->CcxCellPwr);
\r
2332 u1Byte LegacyOfdmCellPwrIdx = phy_DbmToTxPwrIdx(Adapter, WIRELESS_MODE_G, pCcxInfo->CcxCellPwr);
\r
2333 u1Byte OfdmCellPwrIdx = phy_DbmToTxPwrIdx(Adapter, WIRELESS_MODE_N_24G, pCcxInfo->CcxCellPwr);
\r
2335 RT_TRACE(COMP_TXAGC, DBG_LOUD,
\r
2336 ("CCX Cell Limit: %d dbm => CCK Tx power index : %d, Legacy OFDM Tx power index : %d, OFDM Tx power index: %d\n",
\r
2337 pCcxInfo->CcxCellPwr, CckCellPwrIdx, LegacyOfdmCellPwrIdx, OfdmCellPwrIdx));
\r
2338 RT_TRACE(COMP_TXAGC, DBG_LOUD,
\r
2339 ("EEPROM channel(%d) => CCK Tx power index: %d, Legacy OFDM Tx power index : %d, OFDM Tx power index: %d\n",
\r
2340 channel, cckPowerLevel[0], ofdmPowerLevel[0] + pHalData->LegacyHTTxPowerDiff, ofdmPowerLevel[0]));
\r
2343 if(cckPowerLevel[0] > CckCellPwrIdx)
\r
2344 cckPowerLevel[0] = CckCellPwrIdx;
\r
2345 // Legacy OFDM, HT OFDM
\r
2346 if(ofdmPowerLevel[0] + pHalData->LegacyHTTxPowerDiff > LegacyOfdmCellPwrIdx)
\r
2348 if((OfdmCellPwrIdx - pHalData->LegacyHTTxPowerDiff) > 0)
\r
2350 ofdmPowerLevel[0] = OfdmCellPwrIdx - pHalData->LegacyHTTxPowerDiff;
\r
2354 ofdmPowerLevel[0] = 0;
\r
2358 RT_TRACE(COMP_TXAGC, DBG_LOUD,
\r
2359 ("Altered CCK Tx power index : %d, Legacy OFDM Tx power index: %d, OFDM Tx power index: %d\n",
\r
2360 cckPowerLevel[0], ofdmPowerLevel[0] + pHalData->LegacyHTTxPowerDiff, ofdmPowerLevel[0]));
\r
2363 pHalData->CurrentCckTxPwrIdx = cckPowerLevel[0];
\r
2364 pHalData->CurrentOfdm24GTxPwrIdx = ofdmPowerLevel[0];
\r
2366 RT_TRACE(COMP_TXAGC, DBG_LOUD,
\r
2367 ("PHY_SetTxPowerLevel8192S(): CCK Tx power index : %d, Legacy OFDM Tx power index: %d, OFDM Tx power index: %d\n",
\r
2368 cckPowerLevel[0], ofdmPowerLevel[0] + pHalData->LegacyHTTxPowerDiff, ofdmPowerLevel[0]));
\r
2371 /*-----------------------------------------------------------------------------
\r
2372 * Function: SetTxPowerLevel8190()
\r
2374 * Overview: This function is export to "HalCommon" moudule
\r
2375 * We must consider RF path later!!!!!!!
\r
2377 * Input: PADAPTER Adapter
\r
2383 * 2008/11/04 MHC We remove EEPROM_93C56.
\r
2384 * We need to move CCX relative code to independet file.
\r
2385 * 2009/01/21 MHC Support new EEPROM format from SD3 requirement.
\r
2387 *---------------------------------------------------------------------------*/
\r
2389 PHY_SetTxPowerLevel8192C(
\r
2390 IN PADAPTER Adapter,
\r
2394 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
\r
2395 u8 cckPowerLevel[2], ofdmPowerLevel[2]; // [0]:RF-A, [1]:RF-B
\r
2397 #if(MP_DRIVER == 1)
\r
2398 if (Adapter->registrypriv.mp_mode == 1)
\r
2402 if(pHalData->bTXPowerDataReadFromEEPORM == _FALSE)
\r
2405 getTxPowerIndex(Adapter, channel, &cckPowerLevel[0], &ofdmPowerLevel[0]);
\r
2406 //RTPRINT(FPHY, PHY_TXPWR, ("Channel-%d, cckPowerLevel (A / B) = 0x%x / 0x%x, ofdmPowerLevel (A / B) = 0x%x / 0x%x\n",
\r
2407 // channel, cckPowerLevel[0], cckPowerLevel[1], ofdmPowerLevel[0], ofdmPowerLevel[1]));
\r
2409 ccxPowerIndexCheck(Adapter, channel, &cckPowerLevel[0], &ofdmPowerLevel[0]);
\r
2411 rtl8192c_PHY_RF6052SetCckTxPower(Adapter, &cckPowerLevel[0]);
\r
2412 rtl8192c_PHY_RF6052SetOFDMTxPower(Adapter, &ofdmPowerLevel[0], channel);
\r
2415 switch(pHalData->rf_chip)
\r
2418 PHY_SetRF8225CckTxPower(Adapter, cckPowerLevel[0]);
\r
2419 PHY_SetRF8225OfdmTxPower(Adapter, ofdmPowerLevel[0]);
\r
2423 PHY_SetRF8256CCKTxPower(Adapter, cckPowerLevel[0]);
\r
2424 PHY_SetRF8256OFDMTxPower(Adapter, ofdmPowerLevel[0]);
\r
2428 PHY_RF6052SetCckTxPower(Adapter, &cckPowerLevel[0]);
\r
2429 PHY_RF6052SetOFDMTxPower(Adapter, &ofdmPowerLevel[0], channel);
\r
2442 // Update transmit power level of all channel supported.
\r
2446 // By Bruce, 2008-02-04.
\r
2449 PHY_UpdateTxPowerDbm8192C(
\r
2450 IN PADAPTER Adapter,
\r
2454 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
\r
2458 // TODO: A mode Tx power.
\r
2459 u8 CckTxPwrIdx = phy_DbmToTxPwrIdx(Adapter, WIRELESS_MODE_B, powerInDbm);
\r
2460 u8 OfdmTxPwrIdx = phy_DbmToTxPwrIdx(Adapter, WIRELESS_MODE_N_24G, powerInDbm);
\r
2462 if(OfdmTxPwrIdx - pHalData->LegacyHTTxPowerDiff > 0)
\r
2463 OfdmTxPwrIdx -= pHalData->LegacyHTTxPowerDiff;
\r
2467 //RT_TRACE(COMP_TXAGC, DBG_LOUD, ("PHY_UpdateTxPowerDbm8192S(): %ld dBm , CckTxPwrIdx = %d, OfdmTxPwrIdx = %d\n", powerInDbm, CckTxPwrIdx, OfdmTxPwrIdx));
\r
2469 for(idx = 0; idx < 14; idx++)
\r
2471 for (rf_path = 0; rf_path < 2; rf_path++)
\r
2473 pHalData->TxPwrLevelCck[rf_path][idx] = CckTxPwrIdx;
\r
2474 pHalData->TxPwrLevelHT40_1S[rf_path][idx] =
\r
2475 pHalData->TxPwrLevelHT40_2S[rf_path][idx] = OfdmTxPwrIdx;
\r
2479 //Adapter->HalFunc.SetTxPowerLevelHandler(Adapter, pHalData->CurrentChannel);//gtest:todo
\r
2487 When beacon interval is changed, the values of the
\r
2488 hw registers should be modified.
\r
2489 By tynli, 2008.10.24.
\r
2495 rtl8192c_PHY_SetBeaconHwReg(
\r
2496 IN PADAPTER Adapter,
\r
2497 IN u16 BeaconInterval
\r
2505 PHY_ScanOperationBackup8192C(
\r
2506 IN PADAPTER Adapter,
\r
2513 if(!Adapter->bDriverStopped)
\r
2517 case SCAN_OPT_BACKUP:
\r
2518 IoType = IO_CMD_PAUSE_DM_BY_SCAN;
\r
2519 rtw_hal_set_hwreg(Adapter,HW_VAR_IO_CMD, (pu1Byte)&IoType);
\r
2523 case SCAN_OPT_RESTORE:
\r
2524 IoType = IO_CMD_RESUME_DM_BY_SCAN;
\r
2525 rtw_hal_set_hwreg(Adapter,HW_VAR_IO_CMD, (pu1Byte)&IoType);
\r
2529 RT_TRACE(COMP_SCAN, DBG_LOUD, ("Unknown Scan Backup Operation. \n"));
\r
2536 /*-----------------------------------------------------------------------------
\r
2537 * Function: PHY_SetBWModeCallback8192C()
\r
2539 * Overview: Timer callback function for SetSetBWMode
\r
2541 * Input: PRT_TIMER pTimer
\r
2547 * Note: (1) We do not take j mode into consideration now
\r
2548 * (2) Will two workitem of "switch channel" and "switch channel bandwidth" run
\r
2550 *---------------------------------------------------------------------------*/
\r
2552 _PHY_SetBWMode92C(
\r
2553 IN PADAPTER Adapter
\r
2556 // PADAPTER Adapter = (PADAPTER)pTimer->Adapter;
\r
2557 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
\r
2563 // Added it for 20/40 mhz switch time evaluation by guangan 070531
\r
2564 //u4Byte NowL, NowH;
\r
2565 //u8Byte BeginTime, EndTime;
\r
2567 /*RT_TRACE(COMP_SCAN, DBG_LOUD, ("==>PHY_SetBWModeCallback8192C() Switch to %s bandwidth\n", \
\r
2568 pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz"))*/
\r
2570 if(pHalData->rf_chip == RF_PSEUDO_11N)
\r
2572 //pHalData->SetBWModeInProgress= _FALSE;
\r
2576 // There is no 40MHz mode in RF_8225.
\r
2577 if(pHalData->rf_chip==RF_8225)
\r
2580 if(Adapter->bDriverStopped)
\r
2583 // Added it for 20/40 mhz switch time evaluation by guangan 070531
\r
2584 //NowL = PlatformEFIORead4Byte(Adapter, TSFR);
\r
2585 //NowH = PlatformEFIORead4Byte(Adapter, TSFR+4);
\r
2586 //BeginTime = ((u8Byte)NowH << 32) + NowL;
\r
2589 //3//<1>Set MAC register
\r
2591 //Adapter->HalFunc.SetBWModeHandler();
\r
2593 regBwOpMode = rtw_read8(Adapter, REG_BWOPMODE);
\r
2594 regRRSR_RSC = rtw_read8(Adapter, REG_RRSR+2);
\r
2595 //regBwOpMode = rtw_hal_get_hwreg(Adapter,HW_VAR_BWMODE,(pu1Byte)®BwOpMode);
\r
2597 switch(pHalData->CurrentChannelBW)
\r
2599 case HT_CHANNEL_WIDTH_20:
\r
2600 regBwOpMode |= BW_OPMODE_20MHZ;
\r
2601 // 2007/02/07 Mark by Emily becasue we have not verify whether this register works
\r
2602 rtw_write8(Adapter, REG_BWOPMODE, regBwOpMode);
\r
2605 case HT_CHANNEL_WIDTH_40:
\r
2606 regBwOpMode &= ~BW_OPMODE_20MHZ;
\r
2607 // 2007/02/07 Mark by Emily becasue we have not verify whether this register works
\r
2608 rtw_write8(Adapter, REG_BWOPMODE, regBwOpMode);
\r
2610 regRRSR_RSC = (regRRSR_RSC&0x90) |(pHalData->nCur40MhzPrimeSC<<5);
\r
2611 rtw_write8(Adapter, REG_RRSR+2, regRRSR_RSC);
\r
2615 /*RT_TRACE(COMP_DBG, DBG_LOUD, ("PHY_SetBWModeCallback8192C():
\r
2616 unknown Bandwidth: %#X\n",pHalData->CurrentChannelBW));*/
\r
2621 //3//<2>Set PHY related register
\r
2623 switch(pHalData->CurrentChannelBW)
\r
2625 /* 20 MHz channel*/
\r
2626 case HT_CHANNEL_WIDTH_20:
\r
2627 PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bRFMOD, 0x0);
\r
2628 PHY_SetBBReg(Adapter, rFPGA1_RFMOD, bRFMOD, 0x0);
\r
2629 PHY_SetBBReg(Adapter, rFPGA0_AnalogParameter2, BIT10, 1);
\r
2634 /* 40 MHz channel*/
\r
2635 case HT_CHANNEL_WIDTH_40:
\r
2636 PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bRFMOD, 0x1);
\r
2637 PHY_SetBBReg(Adapter, rFPGA1_RFMOD, bRFMOD, 0x1);
\r
2639 // Set Control channel to upper or lower. These settings are required only for 40MHz
\r
2640 PHY_SetBBReg(Adapter, rCCK0_System, bCCKSideBand, (pHalData->nCur40MhzPrimeSC>>1));
\r
2641 PHY_SetBBReg(Adapter, rOFDM1_LSTF, 0xC00, pHalData->nCur40MhzPrimeSC);
\r
2642 PHY_SetBBReg(Adapter, rFPGA0_AnalogParameter2, BIT10, 0);
\r
2644 PHY_SetBBReg(Adapter, 0x818, (BIT26|BIT27), (pHalData->nCur40MhzPrimeSC==HAL_PRIME_CHNL_OFFSET_LOWER)?2:1);
\r
2651 /*RT_TRACE(COMP_DBG, DBG_LOUD, ("PHY_SetBWModeCallback8192C(): unknown Bandwidth: %#X\n"\
\r
2652 ,pHalData->CurrentChannelBW));*/
\r
2656 //Skip over setting of J-mode in BB register here. Default value is "None J mode". Emily 20070315
\r
2658 // Added it for 20/40 mhz switch time evaluation by guangan 070531
\r
2659 //NowL = PlatformEFIORead4Byte(Adapter, TSFR);
\r
2660 //NowH = PlatformEFIORead4Byte(Adapter, TSFR+4);
\r
2661 //EndTime = ((u8Byte)NowH << 32) + NowL;
\r
2662 //RT_TRACE(COMP_SCAN, DBG_LOUD, ("SetBWModeCallback8190Pci: time of SetBWMode = %I64d us!\n", (EndTime - BeginTime)));
\r
2664 //3<3>Set RF related register
\r
2665 switch(pHalData->rf_chip)
\r
2668 //PHY_SetRF8225Bandwidth(Adapter, pHalData->CurrentChannelBW);
\r
2672 // Please implement this function in Hal8190PciPhy8256.c
\r
2673 //PHY_SetRF8256Bandwidth(Adapter, pHalData->CurrentChannelBW);
\r
2677 // Please implement this function in Hal8190PciPhy8258.c
\r
2678 // PHY_SetRF8258Bandwidth();
\r
2681 case RF_PSEUDO_11N:
\r
2686 rtl8192c_PHY_RF6052SetBandwidth(Adapter, pHalData->CurrentChannelBW);
\r
2690 //RT_ASSERT(FALSE, ("Unknown RFChipID: %d\n", pHalData->RFChipID));
\r
2694 //pHalData->SetBWModeInProgress= FALSE;
\r
2696 //RT_TRACE(COMP_SCAN, DBG_LOUD, ("<==PHY_SetBWModeCallback8192C() \n" ));
\r
2700 /*-----------------------------------------------------------------------------
\r
2701 * Function: SetBWMode8190Pci()
\r
2703 * Overview: This function is export to "HalCommon" moudule
\r
2705 * Input: PADAPTER Adapter
\r
2706 * HT_CHANNEL_WIDTH Bandwidth //20M or 40M
\r
2712 * Note: We do not take j mode into consideration now
\r
2713 *---------------------------------------------------------------------------*/
\r
2715 PHY_SetBWMode8192C(
\r
2716 IN PADAPTER Adapter,
\r
2717 IN HT_CHANNEL_WIDTH Bandwidth, // 20M or 40M
\r
2718 IN unsigned char Offset // Upper, Lower, or Don't care
\r
2721 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
\r
2722 HT_CHANNEL_WIDTH tmpBW= pHalData->CurrentChannelBW;
\r
2723 // Modified it for 20/40 mhz switch by guangan 070531
\r
2724 //PMGNT_INFO pMgntInfo=&Adapter->MgntInfo;
\r
2728 //if(pHalData->SwChnlInProgress)
\r
2729 // if(pMgntInfo->bScanInProgress)
\r
2731 // RT_TRACE(COMP_SCAN, DBG_LOUD, ("PHY_SetBWMode8192C() %s Exit because bScanInProgress!\n",
\r
2732 // Bandwidth == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz"));
\r
2736 // if(pHalData->SetBWModeInProgress)
\r
2738 // // Modified it for 20/40 mhz switch by guangan 070531
\r
2739 // RT_TRACE(COMP_SCAN, DBG_LOUD, ("PHY_SetBWMode8192C() %s cancel last timer because SetBWModeInProgress!\n",
\r
2740 // Bandwidth == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz"));
\r
2741 // PlatformCancelTimer(Adapter, &pHalData->SetBWModeTimer);
\r
2745 //if(pHalData->SetBWModeInProgress)
\r
2748 //pHalData->SetBWModeInProgress= TRUE;
\r
2750 pHalData->CurrentChannelBW = Bandwidth;
\r
2753 if(Offset==HT_EXTCHNL_OFFSET_LOWER)
\r
2754 pHalData->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER;
\r
2755 else if(Offset==HT_EXTCHNL_OFFSET_UPPER)
\r
2756 pHalData->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER;
\r
2758 pHalData->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
\r
2760 pHalData->nCur40MhzPrimeSC = Offset;
\r
2763 if((!Adapter->bDriverStopped) && (!Adapter->bSurpriseRemoved))
\r
2767 //PlatformSetTimer(Adapter, &(pHalData->SetBWModeTimer), 0);
\r
2769 _PHY_SetBWMode92C(Adapter);
\r
2775 //RT_TRACE(COMP_SCAN, DBG_LOUD, ("PHY_SetBWMode8192C() SetBWModeInProgress FALSE driver sleep or unload\n"));
\r
2776 //pHalData->SetBWModeInProgress= FALSE;
\r
2777 pHalData->CurrentChannelBW = tmpBW;
\r
2783 static void _PHY_SwChnl8192C(PADAPTER Adapter, u8 channel)
\r
2786 u32 param1, param2;
\r
2787 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
\r
2789 if ( Adapter->bNotifyChannelChange )
\r
2791 DBG_871X( "[%s] ch = %d\n", __FUNCTION__, channel );
\r
2794 //s1. pre common command - CmdID_SetTxPowerLevel
\r
2795 PHY_SetTxPowerLevel8192C(Adapter, channel);
\r
2797 //s2. RF dependent command - CmdID_RF_WriteReg, param1=RF_CHNLBW, param2=channel
\r
2798 param1 = RF_CHNLBW;
\r
2800 for(eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
\r
2802 pHalData->RfRegChnlVal[eRFPath] = ((pHalData->RfRegChnlVal[eRFPath] & 0xfffffc00) | param2);
\r
2803 PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)eRFPath, param1, bRFRegOffsetMask, pHalData->RfRegChnlVal[eRFPath]);
\r
2806 if(channel >= 1 && channel <= 9)
\r
2808 //DBG_8192C("phy_SwitchRfSetting8723A REG_AFE_PLL_CTRL 0xF0FFFF83\n");
\r
2809 PHY_SetBBReg(Adapter, REG_AFE_PLL_CTRL, bMaskDWord, 0xF0FFFF83);
\r
2811 else if (channel >= 10 && channel <= 14)
\r
2813 //DBG_8192C("phy_SwitchRfSetting8723A REG_AFE_PLL_CTRL 0xF2FFFF83\n");
\r
2814 PHY_SetBBReg(Adapter, REG_AFE_PLL_CTRL, bMaskDWord, 0xF2FFFF83);
\r
2816 //s3. post common command - CmdID_End, None
\r
2821 PHY_SwChnl8192C( // Call after initialization
\r
2822 IN PADAPTER Adapter,
\r
2826 //PADAPTER Adapter = ADJUST_TO_ADAPTIVE_ADAPTER(pAdapter, _TRUE);
\r
2827 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
\r
2828 u8 tmpchannel = pHalData->CurrentChannel;
\r
2829 BOOLEAN bResult = _TRUE;
\r
2831 if(pHalData->rf_chip == RF_PSEUDO_11N)
\r
2833 //pHalData->SwChnlInProgress=FALSE;
\r
2834 return; //return immediately if it is peudo-phy
\r
2837 //if(pHalData->SwChnlInProgress)
\r
2840 //if(pHalData->SetBWModeInProgress)
\r
2843 //--------------------------------------------
\r
2844 switch(pHalData->CurrentWirelessMode)
\r
2846 case WIRELESS_MODE_A:
\r
2847 case WIRELESS_MODE_N_5G:
\r
2848 //RT_ASSERT((channel>14), ("WIRELESS_MODE_A but channel<=14"));
\r
2851 case WIRELESS_MODE_B:
\r
2852 //RT_ASSERT((channel<=14), ("WIRELESS_MODE_B but channel>14"));
\r
2855 case WIRELESS_MODE_G:
\r
2856 case WIRELESS_MODE_N_24G:
\r
2857 //RT_ASSERT((channel<=14), ("WIRELESS_MODE_G but channel>14"));
\r
2861 //RT_ASSERT(FALSE, ("Invalid WirelessMode(%#x)!!\n", pHalData->CurrentWirelessMode));
\r
2864 //--------------------------------------------
\r
2866 //pHalData->SwChnlInProgress = TRUE;
\r
2870 pHalData->CurrentChannel=channel;
\r
2872 //pHalData->SwChnlStage=0;
\r
2873 //pHalData->SwChnlStep=0;
\r
2875 if((!Adapter->bDriverStopped) && (!Adapter->bSurpriseRemoved))
\r
2879 //PlatformSetTimer(Adapter, &(pHalData->SwChnlTimer), 0);
\r
2881 _PHY_SwChnl8192C(Adapter, channel);
\r
2886 //RT_TRACE(COMP_SCAN, DBG_LOUD, ("PHY_SwChnl8192C SwChnlInProgress TRUE schdule workitem done\n"));
\r
2890 //RT_TRACE(COMP_SCAN, DBG_LOUD, ("PHY_SwChnl8192C SwChnlInProgress FALSE schdule workitem error\n"));
\r
2891 //if(IS_HARDWARE_TYPE_8192SU(Adapter))
\r
2893 // pHalData->SwChnlInProgress = FALSE;
\r
2894 pHalData->CurrentChannel = tmpchannel;
\r
2901 //RT_TRACE(COMP_SCAN, DBG_LOUD, ("PHY_SwChnl8192C SwChnlInProgress FALSE driver sleep or unload\n"));
\r
2902 //if(IS_HARDWARE_TYPE_8192SU(Adapter))
\r
2904 // pHalData->SwChnlInProgress = FALSE;
\r
2905 pHalData->CurrentChannel = tmpchannel;
\r
2912 phy_SwChnlStepByStep(
\r
2913 IN PADAPTER Adapter,
\r
2921 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
\r
2922 PCHANNEL_ACCESS_SETTING pChnlAccessSetting;
\r
2923 SwChnlCmd PreCommonCmd[MAX_PRECMD_CNT];
\r
2924 u4Byte PreCommonCmdCnt;
\r
2925 SwChnlCmd PostCommonCmd[MAX_POSTCMD_CNT];
\r
2926 u4Byte PostCommonCmdCnt;
\r
2927 SwChnlCmd RfDependCmd[MAX_RFDEPENDCMD_CNT];
\r
2928 u4Byte RfDependCmdCnt;
\r
2929 SwChnlCmd *CurrentCmd;
\r
2931 u4Byte RfTXPowerCtrl;
\r
2932 BOOLEAN bAdjRfTXPowerCtrl = _FALSE;
\r
2935 RT_ASSERT((Adapter != NULL), ("Adapter should not be NULL\n"));
\r
2936 #if(MP_DRIVER != 1)
\r
2937 RT_ASSERT(IsLegalChannel(Adapter, channel), ("illegal channel: %d\n", channel));
\r
2939 RT_ASSERT((pHalData != NULL), ("pHalData should not be NULL\n"));
\r
2941 pChnlAccessSetting = &Adapter->MgntInfo.Info8185.ChannelAccessSetting;
\r
2942 RT_ASSERT((pChnlAccessSetting != NULL), ("pChnlAccessSetting should not be NULL\n"));
\r
2944 //for(eRFPath = RF_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
\r
2945 //for(eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
\r
2947 // <1> Fill up pre common command.
\r
2948 PreCommonCmdCnt = 0;
\r
2949 phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT,
\r
2950 CmdID_SetTxPowerLevel, 0, 0, 0);
\r
2951 phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT,
\r
2952 CmdID_End, 0, 0, 0);
\r
2954 // <2> Fill up post common command.
\r
2955 PostCommonCmdCnt = 0;
\r
2957 phy_SetSwChnlCmdArray(PostCommonCmd, PostCommonCmdCnt++, MAX_POSTCMD_CNT,
\r
2958 CmdID_End, 0, 0, 0);
\r
2960 // <3> Fill up RF dependent command.
\r
2961 RfDependCmdCnt = 0;
\r
2962 switch( pHalData->RFChipID )
\r
2965 RT_ASSERT((channel >= 1 && channel <= 14), ("illegal channel for Zebra: %d\n", channel));
\r
2966 // 2008/09/04 MH Change channel.
\r
2967 if(channel==14) channel++;
\r
2968 phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
\r
2969 CmdID_RF_WriteReg, rZebra1_Channel, (0x10+channel-1), 10);
\r
2970 phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
\r
2971 CmdID_End, 0, 0, 0);
\r
2975 // TEST!! This is not the table for 8256!!
\r
2976 RT_ASSERT((channel >= 1 && channel <= 14), ("illegal channel for Zebra: %d\n", channel));
\r
2977 phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
\r
2978 CmdID_RF_WriteReg, rRfChannel, channel, 10);
\r
2979 phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
\r
2980 CmdID_End, 0, 0, 0);
\r
2984 RT_ASSERT((channel >= 1 && channel <= 14), ("illegal channel for Zebra: %d\n", channel));
\r
2985 phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
\r
2986 CmdID_RF_WriteReg, RF_CHNLBW, channel, 10);
\r
2987 phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
\r
2988 CmdID_End, 0, 0, 0);
\r
2995 // For FPGA two MAC verification
\r
2996 case RF_PSEUDO_11N:
\r
2999 RT_ASSERT(FALSE, ("Unknown RFChipID: %d\n", pHalData->RFChipID));
\r
3009 CurrentCmd=&PreCommonCmd[*step];
\r
3012 CurrentCmd=&RfDependCmd[*step];
\r
3015 CurrentCmd=&PostCommonCmd[*step];
\r
3019 if(CurrentCmd->CmdID==CmdID_End)
\r
3033 switch(CurrentCmd->CmdID)
\r
3035 case CmdID_SetTxPowerLevel:
\r
3036 PHY_SetTxPowerLevel8192C(Adapter,channel);
\r
3038 case CmdID_WritePortUlong:
\r
3039 PlatformEFIOWrite4Byte(Adapter, CurrentCmd->Para1, CurrentCmd->Para2);
\r
3041 case CmdID_WritePortUshort:
\r
3042 PlatformEFIOWrite2Byte(Adapter, CurrentCmd->Para1, (u2Byte)CurrentCmd->Para2);
\r
3044 case CmdID_WritePortUchar:
\r
3045 PlatformEFIOWrite1Byte(Adapter, CurrentCmd->Para1, (u1Byte)CurrentCmd->Para2);
\r
3047 case CmdID_RF_WriteReg: // Only modify channel for the register now !!!!!
\r
3048 for(eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
\r
3051 pHalData->RfRegChnlVal[eRFPath] = ((pHalData->RfRegChnlVal[eRFPath] & 0xfffffc00) | CurrentCmd->Para2);
\r
3052 PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, bRFRegOffsetMask, pHalData->RfRegChnlVal[eRFPath]);
\r
3054 PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, bRFRegOffsetMask, (CurrentCmd->Para2));
\r
3062 //cosa }/*for(Number of RF paths)*/
\r
3064 (*delay)=CurrentCmd->msDelay;
\r
3073 phy_SetSwChnlCmdArray(
\r
3074 SwChnlCmd* CmdTable,
\r
3077 SwChnlCmdID CmdID,
\r
3085 if(CmdTable == NULL)
\r
3087 //RT_ASSERT(FALSE, ("phy_SetSwChnlCmdArray(): CmdTable cannot be NULL.\n"));
\r
3090 if(CmdTableIdx >= CmdTableSz)
\r
3092 //RT_ASSERT(FALSE,
\r
3093 // ("phy_SetSwChnlCmdArray(): Access invalid index, please check size of the table, CmdTableIdx:%ld, CmdTableSz:%ld\n",
\r
3094 // CmdTableIdx, CmdTableSz));
\r
3098 pCmd = CmdTable + CmdTableIdx;
\r
3099 pCmd->CmdID = CmdID;
\r
3100 pCmd->Para1 = Para1;
\r
3101 pCmd->Para2 = Para2;
\r
3102 pCmd->msDelay = msDelay;
\r
3109 phy_FinishSwChnlNow( // We should not call this function directly
\r
3110 IN PADAPTER Adapter,
\r
3115 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
\r
3118 while(!phy_SwChnlStepByStep(Adapter,channel,&pHalData->SwChnlStage,&pHalData->SwChnlStep,&delay))
\r
3121 rtw_mdelay_os(delay);
\r
3130 // Switch channel synchronously. Called by SwChnlByDelayHandler.
\r
3132 // Implemented by Bruce, 2008-02-14.
\r
3133 // The following procedure is operted according to SwChanlCallback8190Pci().
\r
3134 // However, this procedure is performed synchronously which should be running under
\r
3138 PHY_SwChnlPhy8192C( // Only called during initialize
\r
3139 IN PADAPTER Adapter,
\r
3143 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(Adapter);
\r
3145 //RT_TRACE(COMP_SCAN | COMP_RM, DBG_LOUD, ("==>PHY_SwChnlPhy8192S(), switch from channel %d to channel %d.\n", pHalData->CurrentChannel, channel));
\r
3148 //if(RT_CANNOT_IO(Adapter))
\r
3151 // Channel Switching is in progress.
\r
3152 //if(pHalData->SwChnlInProgress)
\r
3155 //return immediately if it is peudo-phy
\r
3156 if(pHalData->rf_chip == RF_PSEUDO_11N)
\r
3158 //pHalData->SwChnlInProgress=FALSE;
\r
3162 //pHalData->SwChnlInProgress = TRUE;
\r
3166 pHalData->CurrentChannel=channel;
\r
3168 //pHalData->SwChnlStage = 0;
\r
3169 //pHalData->SwChnlStep = 0;
\r
3171 phy_FinishSwChnlNow(Adapter,channel);
\r
3173 //pHalData->SwChnlInProgress = FALSE;
\r
3179 // Configure H/W functionality to enable/disable Monitor mode.
\r
3180 // Note, because we possibly need to configure BB and RF in this function,
\r
3181 // so caller should in PASSIVE_LEVEL. 080118, by rcnjko.
\r
3184 PHY_SetMonitorMode8192C(
\r
3185 IN PADAPTER pAdapter,
\r
3186 IN BOOLEAN bEnableMonitorMode
\r
3190 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
\r
3191 BOOLEAN bFilterOutNonAssociatedBSSID = FALSE;
\r
3193 //2 Note: we may need to stop antenna diversity.
\r
3194 if(bEnableMonitorMode)
\r
3196 bFilterOutNonAssociatedBSSID = FALSE;
\r
3197 RT_TRACE(COMP_RM, DBG_LOUD, ("PHY_SetMonitorMode8192S(): enable monitor mode\n"));
\r
3199 pHalData->bInMonitorMode = TRUE;
\r
3200 pAdapter->HalFunc.AllowAllDestAddrHandler(pAdapter, TRUE, TRUE);
\r
3201 rtw_hal_set_hwreg(pAdapter, HW_VAR_CHECK_BSSID, (pu1Byte)&bFilterOutNonAssociatedBSSID);
\r
3205 bFilterOutNonAssociatedBSSID = TRUE;
\r
3206 RT_TRACE(COMP_RM, DBG_LOUD, ("PHY_SetMonitorMode8192S(): disable monitor mode\n"));
\r
3208 pAdapter->HalFunc.AllowAllDestAddrHandler(pAdapter, FALSE, TRUE);
\r
3209 pHalData->bInMonitorMode = FALSE;
\r
3210 rtw_hal_set_hwreg(pAdapter, HW_VAR_CHECK_BSSID, (pu1Byte)&bFilterOutNonAssociatedBSSID);
\r
3216 /*-----------------------------------------------------------------------------
\r
3217 * Function: PHYCheckIsLegalRfPath8190Pci()
\r
3219 * Overview: Check different RF type to execute legal judgement. If RF Path is illegal
\r
3220 * We will return false.
\r
3228 * Revised History:
\r
3230 * 11/15/2007 MHC Create Version 0.
\r
3232 *---------------------------------------------------------------------------*/
\r
3234 PHY_CheckIsLegalRfPath8192C(
\r
3235 IN PADAPTER pAdapter,
\r
3238 // HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
\r
3239 BOOLEAN rtValue = _TRUE;
\r
3241 // NOt check RF Path now.!
\r
3243 if (pHalData->RF_Type == RF_1T2R && eRFPath != RF_PATH_A)
\r
3247 if (pHalData->RF_Type == RF_1T2R && eRFPath != RF_PATH_A)
\r
3254 } /* PHY_CheckIsLegalRfPath8192C */
\r
3256 static VOID _PHY_SetRFPathSwitch(
\r
3257 IN PADAPTER pAdapter,
\r
3264 if(!pAdapter->hw_init_completed)
\r
3266 u1bTmp = rtw_read8(pAdapter, REG_LEDCFG2) | BIT7;
\r
3267 rtw_write8(pAdapter, REG_LEDCFG2, u1bTmp);
\r
3268 //PHY_SetBBReg(pAdapter, REG_LEDCFG0, BIT23, 0x01);
\r
3269 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT13, 0x01);
\r
3275 PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6, 0x1); //92C_Path_A
\r
3277 PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6, 0x2); //BT
\r
3283 PHY_SetBBReg(pAdapter, rFPGA0_XA_RFInterfaceOE, 0x300, 0x2); //Main
\r
3285 PHY_SetBBReg(pAdapter, rFPGA0_XA_RFInterfaceOE, 0x300, 0x1); //Aux
\r
3290 //return value TRUE => Main; FALSE => Aux
\r
3292 static BOOLEAN _PHY_QueryRFPathSwitch(
\r
3293 IN PADAPTER pAdapter,
\r
3300 if(!pAdapter->hw_init_completed)
\r
3302 PHY_SetBBReg(pAdapter, REG_LEDCFG0, BIT23, 0x01);
\r
3303 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT13, 0x01);
\r
3308 if(PHY_QueryBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6) == 0x01)
\r
3315 if(PHY_QueryBBReg(pAdapter, rFPGA0_XA_RFInterfaceOE, 0x300) == 0x02)
\r
3324 _PHY_DumpRFReg(IN PADAPTER pAdapter)
\r
3326 u32 rfRegValue,rfRegOffset;
\r
3328 //RTPRINT(FINIT, INIT_RF, ("PHY_DumpRFReg()====>\n"));
\r
3330 for(rfRegOffset = 0x00;rfRegOffset<=0x30;rfRegOffset++){
\r
3331 rfRegValue = PHY_QueryRFReg(pAdapter,RF_PATH_A, rfRegOffset, bMaskDWord);
\r
3332 //RTPRINT(FINIT, INIT_RF, (" 0x%02x = 0x%08x\n",rfRegOffset,rfRegValue));
\r
3334 //RTPRINT(FINIT, INIT_RF, ("<===== PHY_DumpRFReg()\n"));
\r
3338 VOID rtl8192c_PHY_SetRFPathSwitch(
\r
3339 IN PADAPTER pAdapter,
\r
3343 HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);
\r
3349 if(IS_92C_SERIAL( pHalData->VersionID)){
\r
3350 _PHY_SetRFPathSwitch(pAdapter, bMain, _TRUE);
\r
3354 _PHY_SetRFPathSwitch(pAdapter, bMain, _FALSE);
\r
3359 // Move from phycfg.c to gen.c to be code independent later
\r
3361 //-------------------------Move to other DIR later----------------------------*/
\r
3362 #ifdef CONFIG_USB_HCI
\r
3366 // To dump all Tx FIFO LLT related link-list table.
\r
3367 // Added by Roger, 2009.03.10.
\r
3370 DumpBBDbgPort_92CU(
\r
3371 IN PADAPTER Adapter
\r
3375 //RT_TRACE(COMP_SEND, DBG_WARNING, ("\n>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>\n"));
\r
3376 //RT_TRACE(COMP_SEND, DBG_WARNING, ("BaseBand Debug Ports:\n"));
\r
3378 PHY_SetBBReg(Adapter, 0x0908, 0xffff, 0x0000);
\r
3379 //RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xdf4, PHY_QueryBBReg(Adapter, 0x0df4, bMaskDWord)));
\r
3381 PHY_SetBBReg(Adapter, 0x0908, 0xffff, 0x0803);
\r
3382 //RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xdf4, PHY_QueryBBReg(Adapter, 0x0df4, bMaskDWord)));
\r
3384 PHY_SetBBReg(Adapter, 0x0908, 0xffff, 0x0a06);
\r
3385 //RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xdf4, PHY_QueryBBReg(Adapter, 0x0df4, bMaskDWord)));
\r
3387 PHY_SetBBReg(Adapter, 0x0908, 0xffff, 0x0007);
\r
3388 //RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xdf4, PHY_QueryBBReg(Adapter, 0x0df4, bMaskDWord)));
\r
3390 PHY_SetBBReg(Adapter, 0x0908, 0xffff, 0x0100);
\r
3391 PHY_SetBBReg(Adapter, 0x0a28, 0x00ff0000, 0x000f0000);
\r
3392 //RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xdf4, PHY_QueryBBReg(Adapter, 0x0df4, bMaskDWord)));
\r
3394 PHY_SetBBReg(Adapter, 0x0908, 0xffff, 0x0100);
\r
3395 PHY_SetBBReg(Adapter, 0x0a28, 0x00ff0000, 0x00150000);
\r
3396 //RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xdf4, PHY_QueryBBReg(Adapter, 0x0df4, bMaskDWord)));
\r
3398 //RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0x800, PHY_QueryBBReg(Adapter, 0x0800, bMaskDWord)));
\r
3399 //RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0x900, PHY_QueryBBReg(Adapter, 0x0900, bMaskDWord)));
\r
3400 //RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xa00, PHY_QueryBBReg(Adapter, 0x0a00, bMaskDWord)));
\r
3401 //RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xa54, PHY_QueryBBReg(Adapter, 0x0a54, bMaskDWord)));
\r
3402 //RT_TRACE(COMP_SEND, DBG_WARNING, ("Offset[%x]: %x\n", 0xa58, PHY_QueryBBReg(Adapter, 0x0a58, bMaskDWord)));
\r
projects / firefly-linux-kernel-4.4.55.git / blob