drivers/net/wireless/rtl8192du/os_dep/linux/pci_intf.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  *
  19  ******************************************************************************/
  20 #define _HCI_INTF_C_
  21
  22 #include <drv_conf.h>
  23 #include <osdep_service.h>
  24 #include <drv_types.h>
  25 #include <recv_osdep.h>
  26 #include <xmit_osdep.h>
  27 #include <hal_intf.h>
  28 #include <rtw_version.h>
  29
  30 #ifndef CONFIG_PCI_HCI
  31
  32 #error "CONFIG_PCI_HCI shall be on!\n"
  33
  34 #endif
  35
  36 #include <pci_ops.h>
  37 #include <pci_osintf.h>
  38 #include <pci_hal.h>
  39
  40 #if defined (PLATFORM_LINUX) && defined (PLATFORM_WINDOWS)
  41
  42 #error "Shall be Linux or Windows, but not both!\n"
  43
  44 #endif
  45
  46 #ifdef CONFIG_80211N_HT
  47 extern int rtw_ht_enable;
  48 extern int rtw_cbw40_enable;
  49 extern int rtw_ampdu_enable;//for enable tx_ampdu
  50 #endif
  51
  52 #ifdef CONFIG_PM
  53 extern int pm_netdev_open(struct net_device *pnetdev);
  54 static int rtw_suspend(struct pci_dev *pdev, pm_message_t state);
  55 static int rtw_resume(struct pci_dev *pdev);
  56 #endif
  57
  58
  59 static int rtw_drv_init(struct pci_dev *pdev, const struct pci_device_id *pdid);
  60 static void rtw_dev_remove(struct pci_dev *pdev);
  61
  62 static struct specific_device_id specific_device_id_tbl[] = {
  63         {.idVendor=0x0b05, .idProduct=0x1791, .flags=SPEC_DEV_ID_DISABLE_HT},
  64         {.idVendor=0x13D3, .idProduct=0x3311, .flags=SPEC_DEV_ID_DISABLE_HT},
  65         {}
  66 };
  67
  68 struct pci_device_id rtw_pci_id_tbl[] = {
  69 #ifdef CONFIG_RTL8192C
  70         {PCI_DEVICE(PCI_VENDER_ID_REALTEK, 0x8191)},
  71         {PCI_DEVICE(PCI_VENDER_ID_REALTEK, 0x8178)},
  72         {PCI_DEVICE(PCI_VENDER_ID_REALTEK, 0x8177)},
  73         {PCI_DEVICE(PCI_VENDER_ID_REALTEK, 0x8176)},
  74 #endif
  75 #ifdef CONFIG_RTL8192D
  76         {PCI_DEVICE(PCI_VENDER_ID_REALTEK, 0x8193)},
  77         {PCI_DEVICE(PCI_VENDER_ID_REALTEK, 0x002B)},
  78 #endif
  79         {},
  80 };
  81
  82 struct pci_drv_priv {
  83         struct pci_driver rtw_pci_drv;
  84         int drv_registered;
  85 };
  86
  87
  88 static struct pci_drv_priv pci_drvpriv = {
  89         .rtw_pci_drv.name = (char*)DRV_NAME,
  90         .rtw_pci_drv.probe = rtw_drv_init,
  91         .rtw_pci_drv.remove = rtw_dev_remove,
  92         .rtw_pci_drv.id_table = rtw_pci_id_tbl,
  93 #ifdef CONFIG_PM
  94         .rtw_pci_drv.suspend = rtw_suspend,
  95         .rtw_pci_drv.resume = rtw_resume,
  96 #else
  97         .rtw_pci_drv.suspend = NULL,
  98         .rtw_pci_drv.resume = NULL,
  99 #endif
 100 };
 101
 102
 103 MODULE_DEVICE_TABLE(pci, rtw_pci_id_tbl);
 104
 105
 106 static u16 pcibridge_vendors[PCI_BRIDGE_VENDOR_MAX] = {
 107         INTEL_VENDOR_ID,
 108         ATI_VENDOR_ID,
 109         AMD_VENDOR_ID,
 110         SIS_VENDOR_ID
 111 };
 112
 113 static u8 rtw_pci_platform_switch_device_pci_aspm(_adapter *padapter, u8 value)
 114 {
 115         struct dvobj_priv       *pdvobjpriv = adapter_to_dvobj(padapter);
 116         u8      bresult = _SUCCESS;
 117         int     error;
 118
 119         value |= 0x40;
 120
 121         error = pci_write_config_byte(pdvobjpriv->ppcidev, 0x80, value);
 122
 123         if(error != 0)
 124         {
 125                 bresult = _FALSE;
 126                 DBG_871X("rtw_pci_platform_switch_device_pci_aspm error (%d)\n",error);
 127         }
 128
 129         return bresult;
 130 }
 131
 132 //
 133 // When we set 0x01 to enable clk request. Set 0x0 to disable clk req.
 134 //
 135 static u8 rtw_pci_switch_clk_req(_adapter *padapter, u8 value)
 136 {
 137         struct dvobj_priv       *pdvobjpriv = adapter_to_dvobj(padapter);
 138         u8      buffer, bresult = _SUCCESS;
 139         int     error;
 140
 141         buffer = value;
 142
 143         if(!padapter->hw_init_completed)
 144                 return bresult;
 145
 146         error = pci_write_config_byte(pdvobjpriv->ppcidev, 0x81, value);
 147
 148         if(error != 0)
 149         {
 150                 bresult = _FALSE;
 151                 DBG_871X("rtw_pci_switch_clk_req error (%d)\n",error);
 152         }
 153
 154         return bresult;
 155 }
 156
 157 #if 0
 158 //Description:
 159 //Disable RTL8192SE ASPM & Disable Pci Bridge ASPM
 160 void rtw_pci_disable_aspm(_adapter *padapter)
 161 {
 162         struct dvobj_priv       *pdvobjpriv = adapter_to_dvobj(padapter);
 163         struct pwrctrl_priv     *pwrpriv = &padapter->pwrctrlpriv;
 164         struct pci_priv *pcipriv = &(pdvobjpriv->pcipriv);
 165         u32     pcicfg_addrport = 0;
 166         u8      num4bytes;
 167         u8      linkctrl_reg;
 168         u16     pcibridge_linkctrlreg, aspmlevel = 0;
 169
 170         // When there exists anyone's busnum, devnum, and funcnum that are set to 0xff,
 171         // we do not execute any action and return.
 172         // if it is not intel bus then don't enable ASPM.
 173         if ((pcipriv->busnumber == 0xff
 174                 && pcipriv->devnumber == 0xff
 175                 && pcipriv->funcnumber == 0xff)
 176                 || (pcipriv->pcibridge_busnum == 0xff
 177                 && pcipriv->pcibridge_devnum == 0xff
 178                 && pcipriv->pcibridge_funcnum == 0xff))
 179         {
 180                 DBG_871X("PlatformEnableASPM(): Fail to enable ASPM. Cannot find the Bus of PCI(Bridge).\n");
 181                 return;
 182         }
 183
 184         if (pcipriv->pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
 185                 DBG_871X("%s(): Disable ASPM. Recognize the Bus of PCI(Bridge) as UNKNOWN.\n", __func__);
 186         }
 187
 188         if (pwrpriv->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
 189                 RT_CLEAR_PS_LEVEL(pwrpriv, RT_RF_OFF_LEVL_CLK_REQ);
 190                 rtw_pci_switch_clk_req(padapter, 0x0);
 191         }
 192
 193         {
 194                 // Suggested by SD1 for promising device will in L0 state after an I/O.
 195                 u8 tmp_u1b;
 196
 197                 pci_read_config_byte(pdvobjpriv->ppcidev, 0x80, &tmp_u1b);
 198         }
 199
 200         // Retrieve original configuration settings.
 201         linkctrl_reg = pcipriv->linkctrl_reg;
 202         pcibridge_linkctrlreg = pcipriv->pcibridge_linkctrlreg;
 203
 204         // Set corresponding value.
 205         aspmlevel |= BIT(0) | BIT(1);
 206         linkctrl_reg &= ~aspmlevel;
 207         pcibridge_linkctrlreg &= ~(BIT(0) | BIT(1));
 208
 209         rtw_pci_platform_switch_device_pci_aspm(padapter, linkctrl_reg);
 210         rtw_udelay_os(50);
 211
 212         //When there exists anyone's busnum, devnum, and funcnum that are set to 0xff,
 213         // we do not execute any action and return.
 214         if ((pcipriv->busnumber == 0xff &&
 215                 pcipriv->devnumber == 0xff &&
 216                 pcipriv->funcnumber == 0xff) ||
 217                 (pcipriv->pcibridge_busnum == 0xff &&
 218                 pcipriv->pcibridge_devnum == 0xff
 219                 && pcipriv->pcibridge_funcnum == 0xff))
 220         {
 221                 //Do Nothing!!
 222         }
 223         else
 224         {
 225                 //4 //Disable Pci Bridge ASPM
 226                 pcicfg_addrport = (pcipriv->pcibridge_busnum << 16) |
 227                                                 (pcipriv->pcibridge_devnum << 11) |
 228                                                 (pcipriv->pcibridge_funcnum << 8) | (1 << 31);
 229                 num4bytes = (pcipriv->pcibridge_pciehdr_offset + 0x10) / 4;
 230
 231                 // set up address port at 0xCF8 offset field= 0 (dev|vend)
 232                 NdisRawWritePortUlong(PCI_CONF_ADDRESS, pcicfg_addrport + (num4bytes << 2));
 233
 234                 // now grab data port with device|vendor 4 byte dword
 235                 NdisRawWritePortUchar(PCI_CONF_DATA, pcibridge_linkctrlreg);
 236
 237                 DBG_871X("rtw_pci_disable_aspm():PciBridge busnumber[%x], DevNumbe[%x], funcnumber[%x], Write reg[%x] = %x\n",
 238                         pcipriv->pcibridge_busnum, pcipriv->pcibridge_devnum,
 239                         pcipriv->pcibridge_funcnum,
 240                         (pcipriv->pcibridge_pciehdr_offset+0x10), pcibridge_linkctrlreg);
 241
 242                 rtw_udelay_os(50);
 243         }
 244 }
 245
 246 //[ASPM]
 247 //Description:
 248 //              Enable RTL8192SE ASPM & Enable Pci Bridge ASPM for power saving
 249 //              We should follow the sequence to enable RTL8192SE first then enable Pci Bridge ASPM
 250 //              or the system will show bluescreen.
 251 void rtw_pci_enable_aspm(_adapter *padapter)
 252 {
 253         struct dvobj_priv       *pdvobjpriv = adapter_to_dvobj(padapter);
 254         struct pwrctrl_priv     *pwrpriv = &padapter->pwrctrlpriv;
 255         struct pci_priv *pcipriv = &(pdvobjpriv->pcipriv);
 256         u16     aspmlevel = 0;
 257         u32     pcicfg_addrport = 0;
 258         u8      num4bytes;
 259         u8      u_pcibridge_aspmsetting = 0;
 260         u8      u_device_aspmsetting = 0;
 261
 262         // When there exists anyone's busnum, devnum, and funcnum that are set to 0xff,
 263         // we do not execute any action and return.
 264         // if it is not intel bus then don't enable ASPM.
 265
 266         if ((pcipriv->busnumber == 0xff
 267                 && pcipriv->devnumber == 0xff
 268                 && pcipriv->funcnumber == 0xff)
 269                 || (pcipriv->pcibridge_busnum == 0xff
 270                 && pcipriv->pcibridge_devnum == 0xff
 271                 && pcipriv->pcibridge_funcnum == 0xff))
 272         {
 273                 DBG_871X("PlatformEnableASPM(): Fail to enable ASPM. Cannot find the Bus of PCI(Bridge).\n");
 274                 return;
 275         }
 276
 277         //4 Enable Pci Bridge ASPM
 278         pcicfg_addrport = (pcipriv->pcibridge_busnum << 16)
 279                                         | (pcipriv->pcibridge_devnum << 11)
 280                                         | (pcipriv->pcibridge_funcnum << 8) | (1 << 31);
 281         num4bytes = (pcipriv->pcibridge_pciehdr_offset + 0x10) / 4;
 282         // set up address port at 0xCF8 offset field= 0 (dev|vend)
 283         NdisRawWritePortUlong(PCI_CONF_ADDRESS, pcicfg_addrport + (num4bytes << 2));
 284         // now grab data port with device|vendor 4 byte dword
 285
 286         u_pcibridge_aspmsetting = pcipriv->pcibridge_linkctrlreg | pdvobjpriv->const_hostpci_aspm_setting;
 287
 288         if (pcipriv->pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL ||
 289                 pcipriv->pcibridge_vendor == PCI_BRIDGE_VENDOR_SIS)
 290                 u_pcibridge_aspmsetting &= ~BIT(0);
 291
 292         NdisRawWritePortUchar(PCI_CONF_DATA, u_pcibridge_aspmsetting);
 293
 294         DBG_871X("PlatformEnableASPM():PciBridge busnumber[%x], DevNumbe[%x], funcnumber[%x], Write reg[%x] = %x\n",
 295                 pcipriv->pcibridge_busnum,
 296                 pcipriv->pcibridge_devnum,
 297                 pcipriv->pcibridge_funcnum,
 298                 (pcipriv->pcibridge_pciehdr_offset+0x10),
 299                 u_pcibridge_aspmsetting);
 300
 301         rtw_udelay_os(50);
 302
 303         // Get ASPM level (with/without Clock Req)
 304         aspmlevel |= pdvobjpriv->const_devicepci_aspm_setting;
 305         u_device_aspmsetting = pcipriv->linkctrl_reg;
 306         u_device_aspmsetting |= aspmlevel;
 307
 308         rtw_pci_platform_switch_device_pci_aspm(padapter, u_device_aspmsetting);        //(priv->linkctrl_reg | ASPMLevel));
 309
 310         if (pwrpriv->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
 311                 rtw_pci_switch_clk_req(padapter, (pwrpriv->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) ? 1 : 0);
 312                 RT_SET_PS_LEVEL(pwrpriv, RT_RF_OFF_LEVL_CLK_REQ);
 313         }
 314
 315         rtw_udelay_os(50);
 316 }
 317
 318 //
 319 //Description:
 320 //To get link control field by searching from PCIe capability lists.
 321 //
 322 static u8
 323 rtw_get_link_control_field(_adapter *padapter, u8 busnum, u8 devnum,
 324                                 u8 funcnum)
 325 {
 326         struct dvobj_priv       *pdvobjpriv = adapter_to_dvobj(padapter);
 327         struct pci_priv *pcipriv = &(pdvobjpriv->pcipriv);
 328         struct rt_pci_capabilities_header capability_hdr;
 329         u8      capability_offset, num4bytes;
 330         u32     pcicfg_addrport = 0;
 331         u8      linkctrl_reg;
 332         u8      status = _FALSE;
 333
 334         //If busnum, devnum, funcnum are set to 0xff.
 335         if (busnum == 0xff && devnum == 0xff && funcnum == 0xff) {
 336                 DBG_871X("GetLinkControlField(): Fail to find PCIe Capability\n");
 337                 return _FALSE;
 338         }
 339
 340         pcicfg_addrport = (busnum << 16) | (devnum << 11) | (funcnum << 8) | (1 << 31);
 341
 342         //2PCIeCap
 343
 344         // The device supports capability lists. Find the capabilities.
 345         num4bytes = 0x34 / 4;
 346         //get capability_offset
 347         // set up address port at 0xCF8 offset field= 0 (dev|vend)
 348         NdisRawWritePortUlong(PCI_CONF_ADDRESS, pcicfg_addrport + (num4bytes << 2));
 349         // now grab data port with device|vendor 4 byte dword
 350         NdisRawReadPortUchar(PCI_CONF_DATA, &capability_offset);
 351
 352         // Loop through the capabilities in search of the power management capability.
 353         // The list is NULL-terminated, so the last offset will always be zero.
 354
 355         while (capability_offset != 0) {
 356                 // First find the number of 4 Byte.
 357                 num4bytes = capability_offset / 4;
 358
 359                 // Read the header of the capability at  this offset. If the retrieved capability is not
 360                 // the power management capability that we are looking for, follow the link to the
 361                 // next capability and continue looping.
 362
 363                 //4 get capability_hdr
 364                 // set up address port at 0xCF8 offset field= 0 (dev|vend)
 365                 NdisRawWritePortUlong(PCI_CONF_ADDRESS, pcicfg_addrport + (num4bytes << 2));
 366                 // now grab data port with device|vendor 4 byte dword
 367                 NdisRawReadPortUshort(PCI_CONF_DATA, (u16 *) & capability_hdr);
 368
 369                 // Found the PCI express capability
 370                 if (capability_hdr.capability_id == PCI_CAPABILITY_ID_PCI_EXPRESS)
 371                 {
 372                         break;
 373                 }
 374                 else
 375                 {
 376                         // This is some other capability. Keep looking for the PCI express capability.
 377                         capability_offset = capability_hdr.next;
 378                 }
 379         }
 380
 381         if (capability_hdr.capability_id == PCI_CAPABILITY_ID_PCI_EXPRESS)      //
 382         {
 383                 num4bytes = (capability_offset + 0x10) / 4;
 384
 385                 //4 Read  Link Control Register
 386                 // set up address port at 0xCF8 offset field= 0 (dev|vend)
 387                 NdisRawWritePortUlong(PCI_CONF_ADDRESS, pcicfg_addrport + (num4bytes << 2));
 388                 // now grab data port with device|vendor 4 byte dword
 389                 NdisRawReadPortUchar(PCI_CONF_DATA, &linkctrl_reg);
 390
 391                 pcipriv->pcibridge_pciehdr_offset = capability_offset;
 392                 pcipriv->pcibridge_linkctrlreg = linkctrl_reg;
 393
 394                 status = _TRUE;
 395         }
 396         else
 397         {
 398                 // We didn't find a PCIe capability.
 399                 DBG_871X("GetLinkControlField(): Cannot Find PCIe Capability\n");
 400         }
 401
 402         return status;
 403 }
 404
 405 //
 406 //Description:
 407 //To get PCI bus infomation and return busnum, devnum, and funcnum about
 408 //the bus(bridge) which the device binds.
 409 //
 410 static u8
 411 rtw_get_pci_bus_info(_adapter *padapter,
 412                           u16 vendorid,
 413                           u16 deviceid,
 414                           u8 irql, u8 basecode, u8 subclass, u8 filed19val,
 415                           u8 * busnum, u8 * devnum, u8 * funcnum)
 416 {
 417         struct dvobj_priv       *pdvobjpriv = adapter_to_dvobj(padapter);
 418         struct pci_dev  *pdev = pdvobjpriv->ppcidev;
 419         u8      busnum_idx, devicenum_idx, functionnum_idx;
 420         u32     pcicfg_addrport = 0;
 421         u32     dev_venid = 0, classcode, field19, headertype;
 422         u16     venId, devId;
 423         u8      basec, subc, irqline;
 424         u16     regoffset;
 425         u8      b_singlefunc = _FALSE;
 426         u8      b_bridgechk = _FALSE;
 427
 428         *busnum = 0xFF;
 429         *devnum = 0xFF;
 430         *funcnum = 0xFF;
 431
 432         //DBG_871X("==============>vendorid:%x,deviceid:%x,irql:%x\n", vendorid,deviceid,irql);
 433         if ((basecode == PCI_CLASS_BRIDGE_DEV) &&
 434                 (subclass == PCI_SUBCLASS_BR_PCI_TO_PCI)
 435                 && (filed19val == U1DONTCARE))
 436                 b_bridgechk = _TRUE;
 437
 438         // perform a complete pci bus scan operation
 439         for (busnum_idx = 0; busnum_idx < PCI_MAX_BRIDGE_NUMBER; busnum_idx++)  //255
 440         {
 441                 for (devicenum_idx = 0; devicenum_idx < PCI_MAX_DEVICES; devicenum_idx++)       //32
 442                 {
 443                         b_singlefunc = _FALSE;
 444                         for (functionnum_idx = 0; functionnum_idx < PCI_MAX_FUNCTION; functionnum_idx++)        //8
 445                         {
 446                                 //
 447                                 // <Roger_Notes> We have to skip redundant Bus scan to prevent unexpected system hang
 448                                 // if single function is present in this device.
 449                                 // 2009.02.26.
 450                                 //
 451                                 if (functionnum_idx == 0) {
 452                                         //4 get header type (DWORD #3)
 453                                         pcicfg_addrport = (busnum_idx << 16) | (devicenum_idx << 11) | (functionnum_idx << 8) | (1 << 31);
 454                                         NdisRawWritePortUlong(PCI_CONF_ADDRESS, pcicfg_addrport + (3 << 2));
 455                                         NdisRawReadPortUlong(PCI_CONF_DATA, &headertype);
 456                                         headertype = ((headertype >> 16) & 0x0080) >> 7;        // address 0x0e[7].
 457                                         if (headertype == 0)    //Single function
 458                                                 b_singlefunc = _TRUE;
 459                                 }
 460                                 else
 461                                 {//By pass the following scan process.
 462                                         if (b_singlefunc == _TRUE)
 463                                                 break;
 464                                 }
 465
 466                                 // Set access enable control.
 467                                 pcicfg_addrport = (busnum_idx << 16) | (devicenum_idx << 11) | (functionnum_idx << 8) | (1 << 31);
 468
 469                                 //4 // Get vendorid/ deviceid
 470                                 // set up address port at 0xCF8 offset field= 0 (dev|vend)
 471                                 NdisRawWritePortUlong(PCI_CONF_ADDRESS, pcicfg_addrport);
 472                                 // now grab data port with device|vendor 4 byte dword
 473                                 NdisRawReadPortUlong(PCI_CONF_DATA, &dev_venid);
 474
 475                                 // if data port is full of 1s, no device is present
 476                                 // some broken boards return 0 if a slot is empty:
 477                                 if (dev_venid == 0xFFFFFFFF || dev_venid == 0)
 478                                         continue;       //PCI_INVALID_VENDORID
 479
 480                                 // 4 // Get irql
 481                                 regoffset = 0x3C;
 482                                 pcicfg_addrport = (busnum_idx << 16) | (devicenum_idx << 11) | (functionnum_idx << 8) | (1 << 31) | (regoffset & 0xFFFFFFFC);
 483                                 NdisRawWritePortUlong(PCI_CONF_ADDRESS, pcicfg_addrport);
 484                                 NdisRawReadPortUchar((PCI_CONF_DATA +(regoffset & 0x3)), &irqline);
 485
 486                                 venId = (u16) (dev_venid >> 0) & 0xFFFF;
 487                                 devId = (u16) (dev_venid >> 16) & 0xFFFF;
 488
 489                                 // Check Vendor ID
 490                                 if (!b_bridgechk && (venId != vendorid) && (vendorid != U2DONTCARE))
 491                                         continue;
 492
 493                                 // Check Device ID
 494                                 if (!b_bridgechk && (devId != deviceid) && (deviceid != U2DONTCARE))
 495                                         continue;
 496
 497                                 // Check irql
 498                                 if (!b_bridgechk && (irqline != irql) && (irql != U1DONTCARE))
 499                                         continue;
 500
 501                                 //4 get Class Code
 502                                 pcicfg_addrport = (busnum_idx << 16) | (devicenum_idx << 11) | (functionnum_idx << 8) | (1 << 31);
 503                                 NdisRawWritePortUlong(PCI_CONF_ADDRESS, pcicfg_addrport + (2 << 2));
 504                                 NdisRawReadPortUlong(PCI_CONF_DATA, &classcode);
 505                                 classcode = classcode >> 8;
 506
 507                                 basec = (u8) (classcode >> 16) & 0xFF;
 508                                 subc = (u8) (classcode >> 8) & 0xFF;
 509                                 if (b_bridgechk && (venId != vendorid) && (basec == basecode) && (subc == subclass))
 510                                         return _TRUE;
 511
 512                                 // Check Vendor ID
 513                                 if (b_bridgechk && (venId != vendorid) && (vendorid != U2DONTCARE))
 514                                         continue;
 515
 516                                 // Check Device ID
 517                                 if (b_bridgechk && (devId != deviceid) && (deviceid != U2DONTCARE))
 518                                         continue;
 519
 520                                 // Check irql
 521                                 if (b_bridgechk && (irqline != irql) && (irql != U1DONTCARE))
 522                                         continue;
 523
 524                                 //4 get field 0x19 value  (DWORD #6)
 525                                 NdisRawWritePortUlong(PCI_CONF_ADDRESS, pcicfg_addrport + (6 << 2));
 526                                 NdisRawReadPortUlong(PCI_CONF_DATA, &field19);
 527                                 field19 = (field19 >> 8) & 0xFF;
 528
 529                                 //4 Matching Class Code and filed19.
 530                                 if ((basec == basecode) && (subc == subclass) && ((field19 == filed19val) || (filed19val == U1DONTCARE))) {
 531                                         *busnum = busnum_idx;
 532                                         *devnum = devicenum_idx;
 533                                         *funcnum = functionnum_idx;
 534
 535                                         DBG_871X("GetPciBusInfo(): Find Device(%X:%X)  bus=%d dev=%d, func=%d\n",
 536                                                 vendorid, deviceid, busnum_idx, devicenum_idx, functionnum_idx);
 537                                         return _TRUE;
 538                                 }
 539                         }
 540                 }
 541         }
 542
 543         DBG_871X("GetPciBusInfo(): Cannot Find Device(%X:%X:%X)\n", vendorid, deviceid, dev_venid);
 544
 545         return _FALSE;
 546 }
 547
 548 static u8
 549 rtw_get_pci_brideg_info(_adapter *padapter,
 550                              u8 basecode,
 551                              u8 subclass,
 552                              u8 filed19val, u8 * busnum, u8 * devnum,
 553                              u8 * funcnum, u16 * vendorid, u16 * deviceid)
 554 {
 555         u8      busnum_idx, devicenum_idx, functionnum_idx;
 556         u32     pcicfg_addrport = 0;
 557         u32     dev_venid, classcode, field19, headertype;
 558         u16     venId, devId;
 559         u8      basec, subc, irqline;
 560         u16     regoffset;
 561         u8      b_singlefunc = _FALSE;
 562
 563         *busnum = 0xFF;
 564         *devnum = 0xFF;
 565         *funcnum = 0xFF;
 566
 567         // perform a complete pci bus scan operation
 568         for (busnum_idx = 0; busnum_idx < PCI_MAX_BRIDGE_NUMBER; busnum_idx++)  //255
 569         {
 570                 for (devicenum_idx = 0; devicenum_idx < PCI_MAX_DEVICES; devicenum_idx++)       //32
 571                 {
 572                         b_singlefunc = _FALSE;
 573                         for (functionnum_idx = 0; functionnum_idx < PCI_MAX_FUNCTION; functionnum_idx++)        //8
 574                         {
 575                                 //
 576                                 // <Roger_Notes> We have to skip redundant Bus scan to prevent unexpected system hang
 577                                 // if single function is present in this device.
 578                                 // 2009.02.26.
 579                                 //
 580                                 if (functionnum_idx == 0)
 581                                 {
 582                                         //4 get header type (DWORD #3)
 583                                         pcicfg_addrport = (busnum_idx << 16) | (devicenum_idx << 11) | (functionnum_idx << 8) | (1 << 31);
 584                                         //NdisRawWritePortUlong((ULONG_PTR)PCI_CONF_ADDRESS ,  pcicfg_addrport + (3 << 2));
 585                                         //NdisRawReadPortUlong((ULONG_PTR)PCI_CONF_DATA, &headertype);
 586                                         NdisRawWritePortUlong(PCI_CONF_ADDRESS, pcicfg_addrport + (3 << 2));
 587                                         NdisRawReadPortUlong(PCI_CONF_DATA, &headertype);
 588                                         headertype = ((headertype >> 16) & 0x0080) >> 7;        // address 0x0e[7].
 589                                         if (headertype == 0)    //Single function
 590                                                 b_singlefunc = _TRUE;
 591                                 }
 592                                 else
 593                                 {//By pass the following scan process.
 594                                         if (b_singlefunc == _TRUE)
 595                                                 break;
 596                                 }
 597
 598                                 pcicfg_addrport = (busnum_idx << 16) | (devicenum_idx << 11) | (functionnum_idx << 8) | (1 << 31);
 599
 600                                 //4 // Get vendorid/ deviceid
 601                                 // set up address port at 0xCF8 offset field= 0 (dev|vend)
 602                                 NdisRawWritePortUlong(PCI_CONF_ADDRESS, pcicfg_addrport);
 603                                 // now grab data port with device|vendor 4 byte dword
 604                                 NdisRawReadPortUlong(PCI_CONF_DATA, &dev_venid);
 605
 606                                 //4 Get irql
 607                                 regoffset = 0x3C;
 608                                 pcicfg_addrport = (busnum_idx << 16) | (devicenum_idx << 11) | (functionnum_idx << 8) | (1 << 31) | (regoffset & 0xFFFFFFFC);
 609                                 NdisRawWritePortUlong(PCI_CONF_ADDRESS, pcicfg_addrport);
 610                                 NdisRawReadPortUchar((PCI_CONF_DATA + (regoffset & 0x3)), &irqline);
 611
 612                                 venId = (u16) (dev_venid >> 0) & 0xFFFF;
 613                                 devId = (u16) (dev_venid >> 16) & 0xFFFF;
 614
 615                                 //4 get Class Code
 616                                 pcicfg_addrport = (busnum_idx << 16) | (devicenum_idx << 11) | (functionnum_idx << 8) | (1 << 31);
 617                                 NdisRawWritePortUlong(PCI_CONF_ADDRESS, pcicfg_addrport + (2 << 2));
 618                                 NdisRawReadPortUlong(PCI_CONF_DATA, &classcode);
 619                                 classcode = classcode >> 8;
 620
 621                                 basec = (u8) (classcode >> 16) & 0xFF;
 622                                 subc = (u8) (classcode >> 8) & 0xFF;
 623
 624                                 //4 get field 0x19 value  (DWORD #6)
 625                                 NdisRawWritePortUlong(PCI_CONF_ADDRESS, pcicfg_addrport + (6 << 2));
 626                                 NdisRawReadPortUlong(PCI_CONF_DATA, &field19);
 627                                 field19 = (field19 >> 8) & 0xFF;
 628
 629                                 //4 Matching Class Code and filed19.
 630                                 if ((basec == basecode) && (subc == subclass) && ((field19 == filed19val) || (filed19val == U1DONTCARE))) {
 631                                         *busnum = busnum_idx;
 632                                         *devnum = devicenum_idx;
 633                                         *funcnum = functionnum_idx;
 634                                         *vendorid = venId;
 635                                         *deviceid = devId;
 636
 637                                         DBG_871X("GetPciBridegInfo : Find Device(%X:%X)  bus=%d dev=%d, func=%d\n",
 638                                                 venId, devId, busnum_idx, devicenum_idx, functionnum_idx);
 639
 640                                         return _TRUE;
 641                                 }
 642                         }
 643                 }
 644         }
 645
 646         DBG_871X("GetPciBridegInfo(): Cannot Find PciBridge for Device\n");
 647
 648         return _FALSE;
 649 }                               // end of GetPciBridegInfo
 650
 651 //
 652 //Description:
 653 //To find specific bridge information.
 654 //
 655 static void rtw_find_bridge_info(_adapter *padapter)
 656 {
 657         struct dvobj_priv       *pdvobjpriv = adapter_to_dvobj(padapter);
 658         struct pci_priv *pcipriv = &(pdvobjpriv->pcipriv);
 659         u8      pcibridge_busnum = 0xff;
 660         u8      pcibridge_devnum = 0xff;
 661         u8      pcibridge_funcnum = 0xff;
 662         u16     pcibridge_vendorid = 0xff;
 663         u16     pcibridge_deviceid = 0xff;
 664         u8      tmp = 0;
 665
 666         rtw_get_pci_brideg_info(padapter,
 667                                      PCI_CLASS_BRIDGE_DEV,
 668                                      PCI_SUBCLASS_BR_PCI_TO_PCI,
 669                                      pcipriv->busnumber,
 670                                      &pcibridge_busnum,
 671                                      &pcibridge_devnum, &pcibridge_funcnum,
 672                                      &pcibridge_vendorid, &pcibridge_deviceid);
 673
 674         // match the array of vendor id and regonize which chipset is used.
 675         pcipriv->pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN;
 676
 677         for (tmp = 0; tmp < PCI_BRIDGE_VENDOR_MAX; tmp++) {
 678                 if (pcibridge_vendorid == pcibridge_vendors[tmp]) {
 679                         pcipriv->pcibridge_vendor = tmp;
 680                         DBG_871X("Pci Bridge Vendor is found index: %d\n", tmp);
 681                         break;
 682                 }
 683         }
 684         DBG_871X("Pci Bridge Vendor is %x\n", pcibridge_vendors[tmp]);
 685
 686         // Update corresponding PCI bus info.
 687         pcipriv->pcibridge_busnum = pcibridge_busnum;
 688         pcipriv->pcibridge_devnum = pcibridge_devnum;
 689         pcipriv->pcibridge_funcnum = pcibridge_funcnum;
 690         pcipriv->pcibridge_vendorid = pcibridge_vendorid;
 691         pcipriv->pcibridge_deviceid = pcibridge_deviceid;
 692
 693 }
 694
 695 static u8
 696 rtw_get_amd_l1_patch(_adapter *padapter, u8 busnum, u8 devnum,
 697                           u8 funcnum)
 698 {
 699         u8      status = _FALSE;
 700         u8      offset_e0;
 701         unsigned        offset_e4;
 702         u32     pcicfg_addrport = 0;
 703
 704         pcicfg_addrport = (busnum << 16) | (devnum << 11) | (funcnum << 8) | (1 << 31);
 705
 706         NdisRawWritePortUlong(PCI_CONF_ADDRESS, pcicfg_addrport + 0xE0);
 707         NdisRawWritePortUchar(PCI_CONF_DATA, 0xA0);
 708
 709         NdisRawWritePortUlong(PCI_CONF_ADDRESS, pcicfg_addrport + 0xE0);
 710         NdisRawReadPortUchar(PCI_CONF_DATA, &offset_e0);
 711
 712         if (offset_e0 == 0xA0)
 713         {
 714                 NdisRawWritePortUlong(PCI_CONF_ADDRESS, pcicfg_addrport + 0xE4);
 715                 NdisRawReadPortUlong(PCI_CONF_DATA, &offset_e4);
 716                 //DbgPrint("Offset E4 %x\n", offset_e4);
 717                 if (offset_e4 & BIT(23))
 718                         status = _TRUE;
 719         }
 720
 721         return status;
 722 }
 723 #else
 724 /*Disable RTL8192SE ASPM & Disable Pci Bridge ASPM*/
 725 void rtw_pci_disable_aspm(_adapter *padapter)
 726 {
 727         struct dvobj_priv       *pdvobjpriv = adapter_to_dvobj(padapter);
 728         struct pwrctrl_priv     *pwrpriv = &padapter->pwrctrlpriv;
 729         struct pci_dev  *pdev = pdvobjpriv->ppcidev;
 730         struct pci_dev  *bridge_pdev = pdev->bus->self;
 731         struct pci_priv *pcipriv = &(pdvobjpriv->pcipriv);
 732         u8      linkctrl_reg;
 733         u16     pcibridge_linkctrlreg;
 734         u16     aspmlevel = 0;
 735
 736         // We do not diable/enable ASPM by driver, in the future, the BIOS will enable host and NIC ASPM.
 737         // Advertised by SD1 victorh. Added by tynli. 2009.11.23.
 738         if(pdvobjpriv->const_pci_aspm == 0)
 739                 return;
 740
 741         if(!padapter->hw_init_completed)
 742                 return;
 743
 744         if (pcipriv->pcibridge_vendor == PCI_BRIDGE_VENDOR_UNKNOWN) {
 745                 RT_TRACE(_module_hci_intfs_c_, _drv_err_, ("%s(): PCI(Bridge) UNKNOWN.\n", __FUNCTION__));
 746                 return;
 747         }
 748
 749         linkctrl_reg = pcipriv->linkctrl_reg;
 750         pcibridge_linkctrlreg = pcipriv->pcibridge_linkctrlreg;
 751
 752         // Set corresponding value.
 753         aspmlevel |= BIT(0) | BIT(1);
 754         linkctrl_reg &=~aspmlevel;
 755         pcibridge_linkctrlreg &=~aspmlevel;
 756
 757         if (pwrpriv->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
 758                 RT_CLEAR_PS_LEVEL(pwrpriv, RT_RF_OFF_LEVL_CLK_REQ);
 759                 rtw_pci_switch_clk_req(padapter, 0x0);
 760         }
 761
 762         {
 763                 /*for promising device will in L0 state after an I/O.*/
 764                 u8 tmp_u1b;
 765                 pci_read_config_byte(pdev, 0x80, &tmp_u1b);
 766         }
 767
 768         rtw_pci_platform_switch_device_pci_aspm(padapter, linkctrl_reg);
 769         rtw_udelay_os(50);
 770
 771         //When there exists anyone's BusNum, DevNum, and FuncNum that are set to 0xff,
 772         // we do not execute any action and return. Added by tynli.
 773         if( (pcipriv->busnumber == 0xff && pcipriv->devnumber == 0xff && pcipriv->funcnumber == 0xff) ||
 774                 (pcipriv->pcibridge_busnum == 0xff && pcipriv->pcibridge_devnum == 0xff && pcipriv->pcibridge_funcnum == 0xff) )
 775         {
 776                 // Do Nothing!!
 777         }
 778         else
 779         {
 780                 /*Disable Pci Bridge ASPM*/
 781                 //NdisRawWritePortUlong(PCI_CONF_ADDRESS, pcicfg_addrport + (num4bytes << 2));
 782                 //NdisRawWritePortUchar(PCI_CONF_DATA, pcibridge_linkctrlreg);
 783                 pci_write_config_byte(bridge_pdev, pcipriv->pcibridge_pciehdr_offset + 0x10, pcibridge_linkctrlreg);
 784
 785                 DBG_871X("rtw_pci_disable_aspm():PciBridge busnumber[%x], DevNumbe[%x], funcnumber[%x], Write reg[%x] = %x\n",
 786                         pcipriv->pcibridge_busnum, pcipriv->pcibridge_devnum,
 787                         pcipriv->pcibridge_funcnum,
 788                         (pcipriv->pcibridge_pciehdr_offset+0x10), pcibridge_linkctrlreg);
 789
 790                 rtw_udelay_os(50);
 791         }
 792
 793 }
 794
 795 /*Enable RTL8192SE ASPM & Enable Pci Bridge ASPM for
 796 power saving We should follow the sequence to enable
 797 RTL8192SE first then enable Pci Bridge ASPM
 798 or the system will show bluescreen.*/
 799 void rtw_pci_enable_aspm(_adapter *padapter)
 800 {
 801         struct dvobj_priv       *pdvobjpriv = adapter_to_dvobj(padapter);
 802         struct pwrctrl_priv     *pwrpriv = &padapter->pwrctrlpriv;
 803         struct pci_dev  *pdev = pdvobjpriv->ppcidev;
 804         struct pci_dev  *bridge_pdev = pdev->bus->self;
 805         struct pci_priv *pcipriv = &(pdvobjpriv->pcipriv);
 806         u16     aspmlevel = 0;
 807         u8      u_pcibridge_aspmsetting = 0;
 808         u8      u_device_aspmsetting = 0;
 809         u32     u_device_aspmsupportsetting = 0;
 810
 811         // We do not diable/enable ASPM by driver, in the future, the BIOS will enable host and NIC ASPM.
 812         // Advertised by SD1 victorh. Added by tynli. 2009.11.23.
 813         if(pdvobjpriv->const_pci_aspm == 0)
 814                 return;
 815
 816         //When there exists anyone's BusNum, DevNum, and FuncNum that are set to 0xff,
 817         // we do not execute any action and return. Added by tynli.
 818         if( (pcipriv->busnumber == 0xff && pcipriv->devnumber == 0xff && pcipriv->funcnumber == 0xff) ||
 819                 (pcipriv->pcibridge_busnum == 0xff && pcipriv->pcibridge_devnum == 0xff && pcipriv->pcibridge_funcnum == 0xff) )
 820         {
 821                 DBG_871X("rtw_pci_enable_aspm(): Fail to enable ASPM. Cannot find the Bus of PCI(Bridge).\n");
 822                 return;
 823         }
 824
 825 //Get Bridge ASPM Support
 826 //not to enable bridge aspm if bridge does not support
 827 //Added by sherry 20100803
 828         if (IS_HARDWARE_TYPE_8192DE(padapter))
 829         {
 830                 //PciCfgAddrPort = (pcipriv->pcibridge_busnum << 16)|(pcipriv->pcibridge_devnum<< 11)|(pcipriv->pcibridge_funcnum <<  8)|(1 << 31);
 831                 //Num4Bytes = (pcipriv->pcibridge_pciehdr_offset+0x0C)/4;
 832                 //NdisRawWritePortUlong((ULONG_PTR)PCI_CONF_ADDRESS , PciCfgAddrPort+(Num4Bytes << 2));
 833                 //NdisRawReadPortUlong((ULONG_PTR)PCI_CONF_DATA,&uDeviceASPMSupportSetting);
 834                 pci_read_config_dword(bridge_pdev, (pcipriv->pcibridge_pciehdr_offset+0x0C), &u_device_aspmsupportsetting);
 835                 DBG_871X("rtw_pci_enable_aspm(): Bridge ASPM support %x \n",u_device_aspmsupportsetting);
 836                 if(((u_device_aspmsupportsetting & BIT(11)) != BIT(11)) || ((u_device_aspmsupportsetting & BIT(10)) != BIT(10)))
 837                 {
 838                         if(pdvobjpriv->const_devicepci_aspm_setting == 3)
 839                         {
 840                                 DBG_871X("rtw_pci_enable_aspm(): Bridge not support L0S or L1\n");
 841                                 return;
 842                         }
 843                         else if(pdvobjpriv->const_devicepci_aspm_setting == 2)
 844                         {
 845                                 if((u_device_aspmsupportsetting & BIT(11)) != BIT(11))
 846                                 {
 847                                         DBG_871X("rtw_pci_enable_aspm(): Bridge not support L1 \n");
 848                                         return;
 849                                 }
 850                         }
 851                         else if(pdvobjpriv->const_devicepci_aspm_setting == 1)
 852                         {
 853                                 if((u_device_aspmsupportsetting & BIT(10)) != BIT(10))
 854                                 {
 855                                         DBG_871X("rtw_pci_enable_aspm(): Bridge not support L0s \n");
 856                                         return;
 857                                 }
 858
 859                         }
 860                 }
 861                 else
 862                 {
 863                         DBG_871X("rtw_pci_enable_aspm(): Bridge support L0s and L1 \n");
 864                 }
 865         }
 866
 867
 868         /*Enable Pci Bridge ASPM*/
 869         //PciCfgAddrPort = (pcipriv->pcibridge_busnum << 16)|(pcipriv->pcibridge_devnum<< 11) |(pcipriv->pcibridge_funcnum <<  8)|(1 << 31);
 870         //Num4Bytes = (pcipriv->pcibridge_pciehdr_offset+0x10)/4;
 871         // set up address port at 0xCF8 offset field= 0 (dev|vend)
 872         //NdisRawWritePortUlong(PCI_CONF_ADDRESS, PciCfgAddrPort + (Num4Bytes << 2));
 873         // now grab data port with device|vendor 4 byte dword
 874
 875         u_pcibridge_aspmsetting = pcipriv->pcibridge_linkctrlreg;
 876         u_pcibridge_aspmsetting |= pdvobjpriv->const_hostpci_aspm_setting;
 877
 878         if (pcipriv->pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL ||
 879                 pcipriv->pcibridge_vendor == PCI_BRIDGE_VENDOR_SIS )
 880                 u_pcibridge_aspmsetting &= ~BIT(0); // for intel host 42 device 43
 881
 882         //NdisRawWritePortUchar(PCI_CONF_DATA, u_pcibridge_aspmsetting);
 883         pci_write_config_byte(bridge_pdev, (pcipriv->pcibridge_pciehdr_offset+0x10), u_pcibridge_aspmsetting);
 884
 885         DBG_871X("PlatformEnableASPM():PciBridge busnumber[%x], DevNumbe[%x], funcnumber[%x], Write reg[%x] = %x\n",
 886                 pcipriv->pcibridge_busnum, pcipriv->pcibridge_devnum, pcipriv->pcibridge_funcnum,
 887                 (pcipriv->pcibridge_pciehdr_offset+0x10),
 888                 u_pcibridge_aspmsetting);
 889
 890         rtw_udelay_os(50);
 891
 892         /*Get ASPM level (with/without Clock Req)*/
 893         aspmlevel |= pdvobjpriv->const_devicepci_aspm_setting;
 894         u_device_aspmsetting = pcipriv->linkctrl_reg;
 895         u_device_aspmsetting |= aspmlevel; // device 43
 896
 897         rtw_pci_platform_switch_device_pci_aspm(padapter, u_device_aspmsetting);
 898
 899         if (pwrpriv->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) {
 900                 rtw_pci_switch_clk_req(padapter, (pwrpriv->reg_rfps_level & RT_RF_OFF_LEVL_CLK_REQ) ? 1 : 0);
 901                 RT_SET_PS_LEVEL(pwrpriv, RT_RF_OFF_LEVL_CLK_REQ);
 902         }
 903
 904         rtw_udelay_os(50);
 905 }
 906
 907 static u8 rtw_pci_get_amd_l1_patch(struct dvobj_priv *dvobj)
 908 {
 909         struct pci_dev  *pdev = dvobj->ppcidev;
 910         struct pci_dev  *bridge_pdev = pdev->bus->self;
 911         u8      status = _FALSE;
 912         u8      offset_e0;
 913         u32     offset_e4;
 914
 915         //NdisRawWritePortUlong(PCI_CONF_ADDRESS,pcicfg_addrport + 0xE0);
 916         //NdisRawWritePortUchar(PCI_CONF_DATA, 0xA0);
 917         pci_write_config_byte(bridge_pdev, 0xE0, 0xA0);
 918
 919         //NdisRawWritePortUlong(PCI_CONF_ADDRESS,pcicfg_addrport + 0xE0);
 920         //NdisRawReadPortUchar(PCI_CONF_DATA, &offset_e0);
 921         pci_read_config_byte(bridge_pdev, 0xE0, &offset_e0);
 922
 923         if (offset_e0 == 0xA0) {
 924                 //NdisRawWritePortUlong(PCI_CONF_ADDRESS, pcicfg_addrport + 0xE4);
 925                 //NdisRawReadPortUlong(PCI_CONF_DATA, &offset_e4);
 926                 pci_read_config_dword(bridge_pdev, 0xE4, &offset_e4);
 927                 if (offset_e4 & BIT(23))
 928                         status = _TRUE;
 929         }
 930
 931         return status;
 932 }
 933
 934 static void rtw_pci_get_linkcontrol_field(struct dvobj_priv *dvobj)
 935 {
 936         struct pci_priv *pcipriv = &(dvobj->pcipriv);
 937         struct pci_dev  *pdev = dvobj->ppcidev;
 938         struct pci_dev  *bridge_pdev = pdev->bus->self;
 939         u8      capabilityoffset = pcipriv->pcibridge_pciehdr_offset;
 940         u8      linkctrl_reg;
 941
 942         /*Read  Link Control Register*/
 943         pci_read_config_byte(bridge_pdev, capabilityoffset + PCI_EXP_LNKCTL, &linkctrl_reg);
 944
 945         pcipriv->pcibridge_linkctrlreg = linkctrl_reg;
 946 }
 947 #endif
 948
 949 static void rtw_pci_parse_configuration(struct dvobj_priv *dvobj)
 950 {
 951         struct pci_dev  *pdev = dvobj->ppcidev;
 952         struct pci_priv *pcipriv = &(dvobj->pcipriv);
 953         u8 tmp;
 954         int pos;
 955         u8 linkctrl_reg;
 956
 957         //Link Control Register
 958         pos = pci_find_capability(pdev, PCI_CAP_ID_EXP);
 959         pci_read_config_byte(pdev, pos + PCI_EXP_LNKCTL, &linkctrl_reg);
 960         pcipriv->linkctrl_reg = linkctrl_reg;
 961
 962         //DBG_871X("Link Control Register = %x\n", pcipriv->linkctrl_reg);
 963
 964         pci_read_config_byte(pdev, 0x98, &tmp);
 965         tmp |= BIT(4);
 966         pci_write_config_byte(pdev, 0x98, tmp);
 967
 968         //tmp = 0x17;
 969         //pci_write_config_byte(pdev, 0x70f, tmp);
 970 }
 971
 972 //
 973 // Update PCI dependent default settings.
 974 //
 975 static void rtw_pci_update_default_setting(_adapter *padapter)
 976 {
 977         struct dvobj_priv       *pdvobjpriv = adapter_to_dvobj(padapter);
 978         struct pci_priv *pcipriv = &(pdvobjpriv->pcipriv);
 979         struct pwrctrl_priv     *pwrpriv = &padapter->pwrctrlpriv;
 980
 981         //reset pPSC->reg_rfps_level & priv->b_support_aspm
 982         pwrpriv->reg_rfps_level = 0;
 983         pwrpriv->b_support_aspm = 0;
 984
 985         // Dynamic Mechanism,
 986         //rtw_hal_set_def_var(pAdapter, HAL_DEF_INIT_GAIN, &(pDevice->InitGainState));
 987
 988         // Update PCI ASPM setting
 989         pwrpriv->const_amdpci_aspm = pdvobjpriv->const_amdpci_aspm;
 990         switch (pdvobjpriv->const_pci_aspm) {
 991                 case 0:         // No ASPM
 992                         break;
 993
 994                 case 1:         // ASPM dynamically enabled/disable.
 995                         pwrpriv->reg_rfps_level |= RT_RF_LPS_LEVEL_ASPM;
 996                         break;
 997
 998                 case 2:         // ASPM with Clock Req dynamically enabled/disable.
 999                         pwrpriv->reg_rfps_level |= (RT_RF_LPS_LEVEL_ASPM | RT_RF_OFF_LEVL_CLK_REQ);
1000                         break;
1001
1002                 case 3:         // Always enable ASPM and Clock Req from initialization to halt.
1003                         pwrpriv->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM);
1004                         pwrpriv->reg_rfps_level |= (RT_RF_PS_LEVEL_ALWAYS_ASPM | RT_RF_OFF_LEVL_CLK_REQ);
1005                         break;
1006
1007                 case 4:         // Always enable ASPM without Clock Req from initialization to halt.
1008                         pwrpriv->reg_rfps_level &= ~(RT_RF_LPS_LEVEL_ASPM | RT_RF_OFF_LEVL_CLK_REQ);
1009                         pwrpriv->reg_rfps_level |= RT_RF_PS_LEVEL_ALWAYS_ASPM;
1010                         break;
1011         }
1012
1013         pwrpriv->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
1014
1015         // Update Radio OFF setting
1016         switch (pdvobjpriv->const_hwsw_rfoff_d3) {
1017                 case 1:
1018                         if (pwrpriv->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
1019                                 pwrpriv->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
1020                         break;
1021
1022                 case 2:
1023                         if (pwrpriv->reg_rfps_level & RT_RF_LPS_LEVEL_ASPM)
1024                                 pwrpriv->reg_rfps_level |= RT_RF_OFF_LEVL_ASPM;
1025                         pwrpriv->reg_rfps_level |= RT_RF_OFF_LEVL_HALT_NIC;
1026                         break;
1027
1028                 case 3:
1029                         pwrpriv->reg_rfps_level |= RT_RF_OFF_LEVL_PCI_D3;
1030                         break;
1031         }
1032
1033         // Update Rx 2R setting
1034         //pPSC->reg_rfps_level |= ((pDevice->RegLPS2RDisable) ? RT_RF_LPS_DISALBE_2R : 0);
1035
1036         //
1037         // Set HW definition to determine if it supports ASPM.
1038         //
1039         switch (pdvobjpriv->const_support_pciaspm) {
1040                 case 0: // Not support ASPM.
1041                         {
1042                                 u8      b_support_aspm = _FALSE;
1043                                 pwrpriv->b_support_aspm = b_support_aspm;
1044                         }
1045                         break;
1046
1047                 case 1: // Support ASPM.
1048                         {
1049                                 u8      b_support_aspm = _TRUE;
1050                                 u8      b_support_backdoor = _TRUE;
1051
1052                                 pwrpriv->b_support_aspm = b_support_aspm;
1053
1054                                 /*if(pAdapter->MgntInfo.CustomerID == RT_CID_TOSHIBA &&
1055                                         pcipriv->pcibridge_vendor == PCI_BRIDGE_VENDOR_AMD &&
1056                                         !pcipriv->amd_l1_patch)
1057                                         b_support_backdoor = _FALSE;*/
1058
1059                                 pwrpriv->b_support_backdoor = b_support_backdoor;
1060                         }
1061                         break;
1062
1063                 case 2: // Set by Chipset.
1064                         // ASPM value set by chipset.
1065                         if (pcipriv->pcibridge_vendor == PCI_BRIDGE_VENDOR_INTEL) {
1066                                 u8      b_support_aspm = _TRUE;
1067                                 pwrpriv->b_support_aspm = b_support_aspm;
1068                         }
1069                         break;
1070
1071                 default:
1072                         // Do nothing. Set when finding the chipset.
1073                         break;
1074         }
1075 }
1076
1077 static void rtw_pci_initialize_adapter_common(_adapter *padapter)
1078 {
1079         struct pwrctrl_priv     *pwrpriv = &padapter->pwrctrlpriv;
1080
1081         rtw_pci_update_default_setting(padapter);
1082
1083         if (pwrpriv->reg_rfps_level & RT_RF_PS_LEVEL_ALWAYS_ASPM) {
1084                 // Always enable ASPM & Clock Req.
1085                 rtw_pci_enable_aspm(padapter);
1086                 RT_SET_PS_LEVEL(pwrpriv, RT_RF_PS_LEVEL_ALWAYS_ASPM);
1087         }
1088
1089 }
1090
1091 #if (LINUX_VERSION_CODE < KERNEL_VERSION(2,5,0)) || (LINUX_VERSION_CODE > KERNEL_VERSION(2,6,18))
1092 #define rtw_pci_interrupt(x,y,z) rtw_pci_interrupt(x,y)
1093 #endif
1094
1095 static irqreturn_t rtw_pci_interrupt(int irq, void *priv, struct pt_regs *regs)
1096 {
1097         struct dvobj_priv *dvobj = (struct dvobj_priv *)priv;
1098         _adapter *adapter = dvobj->if1;
1099
1100         if (dvobj->irq_enabled == 0) {
1101                 return IRQ_HANDLED;
1102         }
1103
1104         if(rtw_hal_interrupt_handler(adapter) == _FAIL)
1105                 return IRQ_HANDLED;
1106                 //return IRQ_NONE;
1107
1108         return IRQ_HANDLED;
1109 }
1110
1111 #ifdef RTK_DMP_PLATFORM
1112 #define pci_iounmap(x,y) iounmap(y)
1113 #endif
1114
1115 int pci_alloc_irq(struct dvobj_priv *dvobj)
1116 {
1117         int err;
1118         struct pci_dev *pdev = dvobj->ppcidev;
1119
1120 #if defined(IRQF_SHARED)
1121         err = request_irq(pdev->irq, &rtw_pci_interrupt, IRQF_SHARED, DRV_NAME, dvobj);
1122 #else
1123         err = request_irq(pdev->irq, &rtw_pci_interrupt, SA_SHIRQ, DRV_NAME, dvobj);
1124 #endif
1125         if (err) {
1126                 DBG_871X("Error allocating IRQ %d",pdev->irq);
1127         } else {
1128                 dvobj->irq_alloc = 1;
1129                 DBG_871X("Request_irq OK, IRQ %d\n",pdev->irq);
1130         }
1131
1132         return err?_FAIL:_SUCCESS;
1133 }
1134
1135 static struct dvobj_priv *pci_dvobj_init(struct pci_dev *pdev)
1136 {
1137         int err;
1138         u32     status = _FAIL;
1139         struct dvobj_priv *dvobj = NULL;
1140         struct pci_priv *pcipriv = NULL;
1141         struct pci_dev *bridge_pdev = pdev->bus->self;
1142         unsigned long pmem_start, pmem_len, pmem_flags;
1143         u8      tmp;
1144
1145 _func_enter_;
1146
1147         if ((dvobj = devobj_init()) == NULL) {
1148                 goto exit;
1149         }
1150         dvobj->ppcidev = pdev;
1151         pcipriv = &(dvobj->pcipriv);
1152         pci_set_drvdata(pdev, dvobj);
1153
1154         if ( (err = pci_enable_device(pdev)) != 0) {
1155                 DBG_871X(KERN_ERR "%s : Cannot enable new PCI device\n", pci_name(pdev));
1156                 goto free_dvobj;
1157         }
1158
1159 #ifdef CONFIG_64BIT_DMA
1160         if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
1161                 DBG_871X("RTL819xCE: Using 64bit DMA\n");
1162                 if ((err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64))) != 0) {
1163                         DBG_871X(KERN_ERR "Unable to obtain 64bit DMA for consistent allocations\n");
1164                         goto disable_picdev;
1165                 }
1166                 dvobj->bdma64 = _TRUE;
1167         } else
1168 #endif
1169         {
1170                 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) {
1171                         if ((err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32))) != 0) {
1172                                 DBG_871X(KERN_ERR "Unable to obtain 32bit DMA for consistent allocations\n");
1173                                 goto disable_picdev;
1174                         }
1175                 }
1176         }
1177
1178         pci_set_master(pdev);
1179
1180         if ((err = pci_request_regions(pdev, DRV_NAME)) != 0) {
1181                 DBG_871X(KERN_ERR "Can't obtain PCI resources\n");
1182                 goto disable_picdev;
1183         }
1184         //MEM map
1185         pmem_start = pci_resource_start(pdev, 2);
1186         pmem_len = pci_resource_len(pdev, 2);
1187         pmem_flags = pci_resource_flags(pdev, 2);
1188
1189 #ifdef RTK_DMP_PLATFORM
1190         dvobj->pci_mem_start = (unsigned long)ioremap_nocache(pmem_start, pmem_len);
1191 #else
1192         dvobj->pci_mem_start = (unsigned long)pci_iomap(pdev, 2, pmem_len); /* shared mem start */
1193 #endif
1194         if (dvobj->pci_mem_start == 0) {
1195                 DBG_871X(KERN_ERR "Can't map PCI mem\n");
1196                 goto release_regions;
1197         }
1198
1199         DBG_871X("Memory mapped space start: 0x%08lx len:%08lx flags:%08lx, after map:0x%08lx\n",
1200                 pmem_start, pmem_len, pmem_flags, dvobj->pci_mem_start);
1201
1202         // Disable Clk Request */
1203         pci_write_config_byte(pdev, 0x81, 0);
1204         // leave D3 mode */
1205         pci_write_config_byte(pdev, 0x44, 0);
1206         pci_write_config_byte(pdev, 0x04, 0x06);
1207         pci_write_config_byte(pdev, 0x04, 0x07);
1208
1209
1210 #if 1
1211         /*find bus info*/
1212         pcipriv->busnumber = pdev->bus->number;
1213         pcipriv->devnumber = PCI_SLOT(pdev->devfn);
1214         pcipriv->funcnumber = PCI_FUNC(pdev->devfn);
1215
1216         /*find bridge info*/
1217         pcipriv->pcibridge_vendor = PCI_BRIDGE_VENDOR_UNKNOWN;
1218         if(bridge_pdev){
1219                 pcipriv->pcibridge_vendorid = bridge_pdev->vendor;
1220                 for (tmp = 0; tmp < PCI_BRIDGE_VENDOR_MAX; tmp++) {
1221                         if (bridge_pdev->vendor == pcibridge_vendors[tmp]) {
1222                                 pcipriv->pcibridge_vendor = tmp;
1223                                 DBG_871X("Pci Bridge Vendor is found index: %d, %x\n", tmp, pcibridge_vendors[tmp]);
1224                                 break;
1225                         }
1226                 }
1227         }
1228
1229         //if (pcipriv->pcibridge_vendor != PCI_BRIDGE_VENDOR_UNKNOWN) {
1230         if(bridge_pdev){
1231                 pcipriv->pcibridge_busnum = bridge_pdev->bus->number;
1232                 pcipriv->pcibridge_devnum = PCI_SLOT(bridge_pdev->devfn);
1233                 pcipriv->pcibridge_funcnum = PCI_FUNC(bridge_pdev->devfn);
1234
1235 #if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,34))
1236                 pcipriv->pcibridge_pciehdr_offset = pci_find_capability(bridge_pdev, PCI_CAP_ID_EXP);
1237 #else
1238                 pcipriv->pcibridge_pciehdr_offset = bridge_pdev->pcie_cap;
1239 #endif
1240
1241                 rtw_pci_get_linkcontrol_field(dvobj);
1242
1243                 if (pcipriv->pcibridge_vendor == PCI_BRIDGE_VENDOR_AMD) {
1244                         pcipriv->amd_l1_patch = rtw_pci_get_amd_l1_patch(dvobj);
1245                 }
1246         }
1247 #else
1248         //
1249         // Find bridge related info.
1250         //
1251         rtw_get_pci_bus_info(padapter,
1252                                   pdev->vendor,
1253                                   pdev->device,
1254                                   (u8) pdvobjpriv->irqline,
1255                                   0x02, 0x80, U1DONTCARE,
1256                                   &pcipriv->busnumber,
1257                                   &pcipriv->devnumber,
1258                                   &pcipriv->funcnumber);
1259
1260         rtw_find_bridge_info(padapter);
1261
1262         if (pcipriv->pcibridge_vendor != PCI_BRIDGE_VENDOR_UNKNOWN) {
1263                 rtw_get_link_control_field(padapter,
1264                                                 pcipriv->pcibridge_busnum,
1265                                                 pcipriv->pcibridge_devnum,
1266                                                 pcipriv->pcibridge_funcnum);
1267
1268                 if (pcipriv->pcibridge_vendor == PCI_BRIDGE_VENDOR_AMD) {
1269                         pcipriv->amd_l1_patch =
1270                                 rtw_get_amd_l1_patch(padapter,
1271                                                         pcipriv->pcibridge_busnum,
1272                                                         pcipriv->pcibridge_devnum,
1273                                                         pcipriv->pcibridge_funcnum);
1274                 }
1275         }
1276 #endif
1277
1278         //
1279         // Allow the hardware to look at PCI config information.
1280         //
1281         rtw_pci_parse_configuration(dvobj);
1282
1283         DBG_871X("pcidev busnumber:devnumber:funcnumber:"
1284                 "vendor:link_ctl %d:%d:%d:%x:%x\n",
1285                 pcipriv->busnumber,
1286                 pcipriv->devnumber,
1287                 pcipriv->funcnumber,
1288                 pdev->vendor,
1289                 pcipriv->linkctrl_reg);
1290
1291         DBG_871X("pci_bridge busnumber:devnumber:funcnumber:vendor:"
1292                 "pcie_cap:link_ctl_reg: %d:%d:%d:%x:%x:%x:%x\n",
1293                 pcipriv->pcibridge_busnum,
1294                 pcipriv->pcibridge_devnum,
1295                 pcipriv->pcibridge_funcnum,
1296                 pcibridge_vendors[pcipriv->pcibridge_vendor],
1297                 pcipriv->pcibridge_pciehdr_offset,
1298                 pcipriv->pcibridge_linkctrlreg,
1299                 pcipriv->amd_l1_patch);
1300
1301         status = _SUCCESS;
1302
1303 iounmap:
1304         if (status != _SUCCESS && dvobj->pci_mem_start != 0) {
1305                 pci_iounmap(pdev, (void *)dvobj->pci_mem_start);
1306                 dvobj->pci_mem_start = 0;
1307         }
1308 release_regions:
1309         if (status != _SUCCESS)
1310                 pci_release_regions(pdev);
1311 disable_picdev:
1312         if (status != _SUCCESS)
1313                 pci_disable_device(pdev);
1314 free_dvobj:
1315         if (status != _SUCCESS && dvobj) {
1316                 pci_set_drvdata(pdev, NULL);
1317                 devobj_deinit(dvobj);
1318                 dvobj = NULL;
1319         }
1320 exit:
1321 _func_exit_;
1322         return dvobj;
1323 }
1324
1325 static void pci_dvobj_deinit(struct pci_dev *pdev)
1326 {
1327         struct dvobj_priv *dvobj = pci_get_drvdata(pdev);
1328 _func_enter_;
1329
1330         pci_set_drvdata(pdev, NULL);
1331         if (dvobj) {
1332                 if (dvobj->irq_alloc) {
1333                         free_irq(pdev->irq, dvobj);
1334                         dvobj->irq_alloc = 0;
1335                 }
1336
1337                 if (dvobj->pci_mem_start != 0) {
1338                         pci_iounmap(pdev, (void *)dvobj->pci_mem_start);
1339                         dvobj->pci_mem_start = 0;
1340                 }
1341
1342                 devobj_deinit(dvobj);
1343         }
1344
1345         pci_release_regions(pdev);
1346         pci_disable_device(pdev);
1347
1348 _func_exit_;
1349 }
1350
1351 static void decide_chip_type_by_pci_device_id(_adapter *padapter, struct pci_dev *pdev)
1352 {
1353         u16     venderid, deviceid, irqline;
1354         u8      revisionid;
1355         struct dvobj_priv       *pdvobjpriv = adapter_to_dvobj(padapter);
1356
1357
1358         venderid = pdev->vendor;
1359         deviceid = pdev->device;
1360 #if (LINUX_VERSION_CODE < KERNEL_VERSION(2,6,23))
1361         pci_read_config_byte(pdev, PCI_REVISION_ID, &revisionid); // PCI_REVISION_ID 0x08
1362 #else
1363         revisionid = pdev->revision;
1364 #endif
1365         pci_read_config_word(pdev, PCI_INTERRUPT_LINE, &irqline); // PCI_INTERRUPT_LINE 0x3c
1366         pdvobjpriv->irqline = irqline;
1367
1368
1369         //
1370         // Decide hardware type here.
1371         //
1372         if( deviceid == HAL_HW_PCI_8185_DEVICE_ID ||
1373             deviceid == HAL_HW_PCI_8188_DEVICE_ID ||
1374             deviceid == HAL_HW_PCI_8198_DEVICE_ID)
1375         {
1376                 DBG_871X("Adapter (8185/8185B) is found- VendorID/DeviceID=%x/%x\n", venderid, deviceid);
1377                 padapter->HardwareType=HARDWARE_TYPE_RTL8185;
1378         }
1379         else if (deviceid == HAL_HW_PCI_8190_DEVICE_ID ||
1380                 deviceid == HAL_HW_PCI_0045_DEVICE_ID ||
1381                 deviceid == HAL_HW_PCI_0046_DEVICE_ID ||
1382                 deviceid == HAL_HW_PCI_DLINK_DEVICE_ID)
1383         {
1384                 DBG_871X("Adapter(8190 PCI) is found - vendorid/deviceid=%x/%x\n", venderid, deviceid);
1385                 padapter->HardwareType = HARDWARE_TYPE_RTL8190P;
1386         }
1387         else if (deviceid == HAL_HW_PCI_8192_DEVICE_ID ||
1388                 deviceid == HAL_HW_PCI_0044_DEVICE_ID ||
1389                 deviceid == HAL_HW_PCI_0047_DEVICE_ID ||
1390                 deviceid == HAL_HW_PCI_8192SE_DEVICE_ID ||
1391                 deviceid == HAL_HW_PCI_8174_DEVICE_ID ||
1392                 deviceid == HAL_HW_PCI_8173_DEVICE_ID ||
1393                 deviceid == HAL_HW_PCI_8172_DEVICE_ID ||
1394                 deviceid == HAL_HW_PCI_8171_DEVICE_ID)
1395         {
1396                 // 8192e and and 8192se may have the same device ID 8192. However, their Revision
1397                 // ID is different
1398                 // Added for 92DE. We deferentiate it from SVID,SDID.
1399                 if( pdev->subsystem_vendor == 0x10EC && pdev->subsystem_device == 0xE020){
1400                         padapter->HardwareType = HARDWARE_TYPE_RTL8192DE;
1401                         DBG_871X("Adapter(8192DE) is found - VendorID/DeviceID/RID=%X/%X/%X\n", venderid, deviceid, revisionid);
1402                 }else{
1403                         switch (revisionid) {
1404                                 case HAL_HW_PCI_REVISION_ID_8192PCIE:
1405                                         DBG_871X("Adapter(8192 PCI-E) is found - vendorid/deviceid=%x/%x\n", venderid, deviceid);
1406                                         padapter->HardwareType = HARDWARE_TYPE_RTL8192E;
1407                                         break;
1408                                 case HAL_HW_PCI_REVISION_ID_8192SE:
1409                                         DBG_871X("Adapter(8192SE) is found - vendorid/deviceid=%x/%x\n", venderid, deviceid);
1410                                         padapter->HardwareType = HARDWARE_TYPE_RTL8192SE;
1411                                         break;
1412                                 default:
1413                                         DBG_871X("Err: Unknown device - vendorid/deviceid=%x/%x\n", venderid, deviceid);
1414                                         padapter->HardwareType = HARDWARE_TYPE_RTL8192SE;
1415                                         break;
1416                         }
1417                 }
1418         }
1419         else if(deviceid==HAL_HW_PCI_8723E_DEVICE_ID )
1420         {//RTL8723E may have the same device ID with RTL8192CET
1421                 padapter->HardwareType = HARDWARE_TYPE_RTL8723AE;
1422                 DBG_871X("Adapter(8723 PCI-E) is found - VendorID/DeviceID=%x/%x\n", venderid, deviceid);
1423         }
1424         else if (deviceid == HAL_HW_PCI_8192CET_DEVICE_ID ||
1425                 deviceid == HAL_HW_PCI_8192CE_DEVICE_ID ||
1426                 deviceid == HAL_HW_PCI_8191CE_DEVICE_ID ||
1427                 deviceid == HAL_HW_PCI_8188CE_DEVICE_ID)
1428         {
1429                 DBG_871X("Adapter(8192C PCI-E) is found - vendorid/deviceid=%x/%x\n", venderid, deviceid);
1430                 padapter->HardwareType = HARDWARE_TYPE_RTL8192CE;
1431         }
1432         else if (deviceid == HAL_HW_PCI_8192DE_DEVICE_ID ||
1433                 deviceid == HAL_HW_PCI_002B_DEVICE_ID ){
1434                 padapter->HardwareType = HARDWARE_TYPE_RTL8192DE;
1435                 DBG_871X("Adapter(8192DE) is found - VendorID/DeviceID/RID=%X/%X/%X\n", venderid, deviceid, revisionid);
1436         }
1437         else
1438         {
1439                 DBG_871X("Err: Unknown device - vendorid/deviceid=%x/%x\n", venderid, deviceid);
1440                 //padapter->HardwareType = HAL_DEFAULT_HARDWARE_TYPE;
1441         }
1442
1443
1444         padapter->chip_type = NULL_CHIP_TYPE;
1445
1446         //TODO:
1447 #ifdef CONFIG_RTL8192C
1448         padapter->chip_type = RTL8188C_8192C;
1449         padapter->HardwareType = HARDWARE_TYPE_RTL8192CE;
1450 #endif
1451 #ifdef CONFIG_RTL8192D
1452         pdvobjpriv->InterfaceNumber = revisionid;
1453
1454         padapter->chip_type = RTL8192D;
1455         padapter->HardwareType = HARDWARE_TYPE_RTL8192DE;
1456 #endif
1457
1458 }
1459
1460 static void pci_intf_start(_adapter *padapter)
1461 {
1462
1463         RT_TRACE(_module_hci_intfs_c_,_drv_err_,("+pci_intf_start\n"));
1464         DBG_871X("+pci_intf_start\n");
1465
1466 #ifdef CONFIG_PCILED_BLINK
1467         rtw_led_control(padapter, LED_CTL_NO_LINK);
1468 #endif
1469         //Enable hw interrupt
1470         rtw_hal_enable_interrupt(padapter);
1471
1472         RT_TRACE(_module_hci_intfs_c_,_drv_err_,("-pci_intf_start\n"));
1473         DBG_871X("-pci_intf_start\n");
1474 }
1475
1476 static void pci_intf_stop(_adapter *padapter)
1477 {
1478
1479         RT_TRACE(_module_hci_intfs_c_,_drv_err_,("+pci_intf_stop\n"));
1480
1481         //Disable hw interrupt
1482         if(padapter->bSurpriseRemoved == _FALSE)
1483         {
1484                 //device still exists, so driver can do i/o operation
1485                 rtw_hal_disable_interrupt(padapter);
1486                 tasklet_disable(&(padapter->recvpriv.recv_tasklet));
1487                 tasklet_disable(&(padapter->recvpriv.irq_prepare_beacon_tasklet));
1488                 tasklet_disable(&(padapter->xmitpriv.xmit_tasklet));
1489
1490 #ifdef CONFIG_CONCURRENT_MODE
1491                 /*      This function only be called at driver removing. disable buddy_adapter too
1492                         don't disable interrupt of buddy_adapter because it is same as primary.
1493                 */
1494                 if (padapter->pbuddy_adapter){
1495                         tasklet_disable(&(padapter->pbuddy_adapter->recvpriv.recv_tasklet));
1496                         tasklet_disable(&(padapter->pbuddy_adapter->recvpriv.irq_prepare_beacon_tasklet));
1497                         tasklet_disable(&(padapter->pbuddy_adapter->xmitpriv.xmit_tasklet));
1498                 }
1499 #endif
1500                 RT_TRACE(_module_hci_intfs_c_,_drv_err_,("pci_intf_stop: SurpriseRemoved==_FALSE\n"));
1501         }
1502         else
1503         {
1504                 // Clear irq_enabled to prevent handle interrupt function.
1505                 adapter_to_dvobj(padapter)->irq_enabled = 0;
1506         }
1507
1508         RT_TRACE(_module_hci_intfs_c_,_drv_err_,("-pci_intf_stop\n"));
1509
1510 }
1511
1512
1513 static void rtw_dev_unload(_adapter *padapter)
1514 {
1515         struct net_device *pnetdev= (struct net_device*)padapter->pnetdev;
1516
1517         RT_TRACE(_module_hci_intfs_c_,_drv_err_,("+rtw_dev_unload\n"));
1518
1519         if(padapter->bup == _TRUE)
1520         {
1521                 DBG_871X("+rtw_dev_unload\n");
1522
1523                 padapter->bDriverStopped = _TRUE;
1524                 #ifdef CONFIG_XMIT_ACK
1525                 if (padapter->xmitpriv.ack_tx)
1526                         rtw_ack_tx_done(&padapter->xmitpriv, RTW_SCTX_DONE_DRV_STOP);
1527                 #endif
1528
1529                 //s3.
1530                 if(padapter->intf_stop)
1531                 {
1532                         padapter->intf_stop(padapter);
1533                 }
1534
1535                 //s4.
1536                 rtw_stop_drv_threads(padapter);
1537
1538
1539                 //s5.
1540                 if(padapter->bSurpriseRemoved == _FALSE)
1541                 {
1542                         DBG_871X("r871x_dev_unload()->rtl871x_hal_deinit()\n");
1543                         rtw_hal_deinit(padapter);
1544
1545                         padapter->bSurpriseRemoved = _TRUE;
1546                 }
1547
1548                 padapter->bup = _FALSE;
1549
1550         }
1551         else
1552         {
1553                 RT_TRACE(_module_hci_intfs_c_,_drv_err_,("r871x_dev_unload():padapter->bup == _FALSE\n" ));
1554         }
1555
1556         DBG_871X("-rtw_dev_unload\n");
1557
1558         RT_TRACE(_module_hci_intfs_c_,_drv_err_,("-rtw_dev_unload\n"));
1559
1560 }
1561
1562 static void disable_ht_for_spec_devid(const struct pci_device_id *pdid)
1563 {
1564 #ifdef CONFIG_80211N_HT
1565         u16 vid, pid;
1566         u32 flags;
1567         int i;
1568         int num = sizeof(specific_device_id_tbl)/sizeof(struct specific_device_id);
1569
1570         for(i=0; i<num; i++)
1571         {
1572                 vid = specific_device_id_tbl[i].idVendor;
1573                 pid = specific_device_id_tbl[i].idProduct;
1574                 flags = specific_device_id_tbl[i].flags;
1575
1576                 if((pdid->vendor==vid) && (pdid->device==pid) && (flags&SPEC_DEV_ID_DISABLE_HT))
1577                 {
1578                          rtw_ht_enable = 0;
1579                          rtw_cbw40_enable = 0;
1580                          rtw_ampdu_enable = 0;
1581                 }
1582
1583         }
1584 #endif
1585 }
1586
1587 #ifdef CONFIG_PM
1588 static int rtw_suspend(struct pci_dev *pdev, pm_message_t state)
1589 {
1590         _func_enter_;
1591
1592
1593         _func_exit_;
1594         return 0;
1595 }
1596
1597 static int rtw_resume(struct pci_dev *pdev)
1598 {
1599         _func_enter_;
1600
1601
1602         _func_exit_;
1603
1604         return 0;
1605 }
1606 #endif
1607
1608 _adapter *rtw_pci_if1_init(struct dvobj_priv * dvobj, struct pci_dev *pdev,
1609         const struct pci_device_id *pdid)
1610 {
1611         _adapter *padapter = NULL;
1612         struct net_device *pnetdev = NULL;
1613         int status = _FAIL;
1614
1615         if ((padapter = (_adapter *)rtw_zvmalloc(sizeof(*padapter))) == NULL) {
1616                 goto exit;
1617         }
1618         padapter->dvobj = dvobj;
1619         dvobj->if1 = padapter;
1620
1621         padapter->bDriverStopped=_TRUE;
1622
1623         dvobj->padapters[dvobj->iface_nums++] = padapter;
1624         padapter->iface_id = IFACE_ID0;
1625
1626 #if defined(CONFIG_CONCURRENT_MODE) || defined(CONFIG_DUALMAC_CONCURRENT)
1627         //set adapter_type/iface type for primary padapter
1628         padapter->isprimary = _TRUE;
1629         padapter->adapter_type = PRIMARY_ADAPTER;
1630         #ifndef CONFIG_HWPORT_SWAP
1631         padapter->iface_type = IFACE_PORT0;
1632         #else
1633         padapter->iface_type = IFACE_PORT1;
1634         #endif
1635 #endif
1636
1637         //step 1-1., decide the chip_type via vid/pid
1638         padapter->interface_type = RTW_PCIE;
1639         decide_chip_type_by_pci_device_id(padapter, pdev);
1640
1641         if((pnetdev = rtw_init_netdev(padapter)) == NULL) {
1642                 goto free_adapter;
1643         }
1644         if (dvobj->bdma64)
1645                 pnetdev->features |= NETIF_F_HIGHDMA;
1646         pnetdev->irq = pdev->irq;
1647         SET_NETDEV_DEV(pnetdev, dvobj_to_dev(dvobj));
1648         padapter = rtw_netdev_priv(pnetdev);
1649
1650         //step 2. hook HalFunc, allocate HalData
1651         if (padapter->chip_type == RTL8188C_8192C) {
1652                 #ifdef CONFIG_RTL8192C
1653                 rtl8192ce_set_hal_ops(padapter);
1654                 #endif
1655         } else if (padapter->chip_type == RTL8192D) {
1656                 #ifdef CONFIG_RTL8192D
1657                 rtl8192de_set_hal_ops(padapter);
1658                 #endif
1659         } else {
1660                 DBG_871X("Detect NULL_CHIP_TYPE\n");
1661                 goto free_hal_data;
1662         }
1663
1664         //step 3.       initialize the dvobj_priv
1665         padapter->intf_start=&pci_intf_start;
1666         padapter->intf_stop=&pci_intf_stop;
1667
1668
1669         //.2
1670         if ((rtw_init_io_priv(padapter, pci_set_intf_ops)) == _FAIL) {
1671                 RT_TRACE(_module_hci_intfs_c_,_drv_err_,(" \n Can't init io_reqs\n"));
1672                 goto free_hal_data;
1673         }
1674
1675         //.3
1676         rtw_hal_read_chip_version(padapter);
1677
1678         //.4
1679         rtw_hal_chip_configure(padapter);
1680
1681         //step 4. read efuse/eeprom data and get mac_addr
1682         rtw_hal_read_chip_info(padapter);
1683
1684         if (rtw_handle_dualmac(padapter, 1) != _SUCCESS)
1685                 goto free_hal_data;
1686
1687 #ifdef CONFIG_IOCTL_CFG80211
1688         if(rtw_wdev_alloc(padapter, dvobj_to_dev(dvobj)) != 0) {
1689                 goto handle_dualmac;
1690         }
1691 #endif
1692
1693         //step 5.
1694         if (rtw_init_drv_sw(padapter) == _FAIL) {
1695                 RT_TRACE(_module_hci_intfs_c_,_drv_err_,("Initialize driver software resource Failed!\n"));
1696                 goto free_wdev;
1697         }
1698
1699         status = rtw_hal_inirp_init(padapter);
1700         if(status ==_FAIL){
1701                 RT_TRACE(_module_hci_intfs_c_,_drv_err_,("Initialize PCI desc ring Failed!\n"));
1702                 goto free_drv_sw;
1703         }
1704
1705         rtw_macaddr_cfg(padapter->eeprompriv.mac_addr);
1706         rtw_init_wifidirect_addrs(padapter, padapter->eeprompriv.mac_addr, padapter->eeprompriv.mac_addr);
1707
1708
1709         rtw_hal_disable_interrupt(padapter);
1710
1711         //step 6. Init pci related configuration
1712         rtw_pci_initialize_adapter_common(padapter);
1713
1714         DBG_871X("bDriverStopped:%d, bSurpriseRemoved:%d, bup:%d, hw_init_completed:%d\n"
1715                 ,padapter->bDriverStopped
1716                 ,padapter->bSurpriseRemoved
1717                 ,padapter->bup
1718                 ,padapter->hw_init_completed
1719         );
1720
1721         status = _SUCCESS;
1722
1723 inirp_deinit:
1724         if (status != _SUCCESS)
1725                 rtw_hal_inirp_deinit(padapter);
1726 free_drv_sw:
1727         if (status != _SUCCESS)
1728                 rtw_free_drv_sw(padapter);
1729 free_wdev:
1730         if (status != _SUCCESS) {
1731                 #ifdef CONFIG_IOCTL_CFG80211
1732                 rtw_wdev_unregister(padapter->rtw_wdev);
1733                 rtw_wdev_free(padapter->rtw_wdev);
1734                 #endif
1735         }
1736 handle_dualmac:
1737         if (status != _SUCCESS)
1738                 rtw_handle_dualmac(padapter, 0);
1739 free_hal_data:
1740         if (status != _SUCCESS && padapter->HalData)
1741                 rtw_mfree(padapter->HalData, sizeof(*(padapter->HalData)));
1742 free_adapter:
1743         if (status != _SUCCESS) {
1744                 if (pnetdev)
1745                         rtw_free_netdev(pnetdev);
1746                 else if (padapter)
1747                         rtw_vmfree((u8*)padapter, sizeof(*padapter));
1748                 padapter = NULL;
1749         }
1750 exit:
1751         return padapter;
1752 }
1753
1754 static void rtw_pci_if1_deinit(_adapter *if1)
1755 {
1756         struct net_device *pnetdev = if1->pnetdev;
1757         struct mlme_priv *pmlmepriv= &if1->mlmepriv;
1758
1759         //      padapter->intf_stop(padapter);
1760
1761         if(check_fwstate(pmlmepriv, _FW_LINKED))
1762                 rtw_disassoc_cmd(if1, 0, _FALSE);
1763
1764 #ifdef CONFIG_AP_MODE
1765         free_mlme_ap_info(if1);
1766         #ifdef CONFIG_HOSTAPD_MLME
1767         hostapd_mode_unload(if1);
1768         #endif
1769 #endif
1770
1771         rtw_cancel_all_timer(if1);
1772 #ifdef CONFIG_WOWLAN
1773         if1->pwrctrlpriv.wowlan_mode=_FALSE;
1774 #endif //CONFIG_WOWLAN
1775         rtw_dev_unload(if1);
1776
1777         DBG_871X("%s, hw_init_completed=%d\n", __func__, if1->hw_init_completed);
1778
1779         //s6.
1780         rtw_handle_dualmac(if1, 0);
1781
1782 #ifdef CONFIG_IOCTL_CFG80211
1783         if (if1->rtw_wdev)
1784                 rtw_wdev_free(if1->rtw_wdev);
1785 #endif //CONFIG_IOCTL_CFG80211
1786
1787         rtw_hal_inirp_deinit(if1);
1788         rtw_free_drv_sw(if1);
1789
1790         if(pnetdev)
1791                 rtw_free_netdev(pnetdev);
1792
1793 #ifdef CONFIG_PLATFORM_RTD2880B
1794         DBG_871X("wlan link down\n");
1795         rtd2885_wlan_netlink_sendMsg("linkdown", "8712");
1796 #endif
1797 }
1798
1799 /*
1800  * drv_init() - a device potentially for us
1801  *
1802  * notes: drv_init() is called when the bus driver has located a card for us to support.
1803  *        We accept the new device by returning 0.
1804 */
1805 static int rtw_drv_init(struct pci_dev *pdev, const struct pci_device_id *did)
1806 {
1807         int i, err = -ENODEV;
1808
1809         int status;
1810         _adapter *if1 = NULL, *if2 = NULL;
1811         struct dvobj_priv *dvobj;
1812
1813         RT_TRACE(_module_hci_intfs_c_, _drv_err_, ("+rtw_drv_init\n"));
1814
1815         //step 0.
1816         disable_ht_for_spec_devid(did);
1817
1818         /* Initialize dvobj_priv */
1819         if ((dvobj = pci_dvobj_init(pdev)) == NULL) {
1820                 RT_TRACE(_module_hci_intfs_c_, _drv_err_, ("initialize device object priv Failed!\n"));
1821                 goto exit;
1822         }
1823
1824         /* Initialize if1 */
1825         if ((if1 = rtw_pci_if1_init(dvobj, pdev, did)) == NULL) {
1826                 DBG_871X("rtw_pci_if1_init Failed!\n");
1827                 goto free_dvobj;
1828         }
1829
1830         /* Initialize if2 */
1831 #ifdef CONFIG_CONCURRENT_MODE
1832         if((if2 = rtw_drv_if2_init(if1, pci_set_intf_ops)) == NULL) {
1833                 goto free_if1;
1834         }
1835 #endif
1836
1837 #ifdef CONFIG_GLOBAL_UI_PID
1838         if (ui_pid[1]!=0) {
1839                 DBG_871X("ui_pid[1]:%d\n",ui_pid[1]);
1840                 rtw_signal_process(ui_pid[1], SIGUSR2);
1841         }
1842 #endif
1843
1844         //dev_alloc_name && register_netdev
1845         if((status = rtw_drv_register_netdev(if1)) != _SUCCESS) {
1846                 goto free_if1;
1847         }
1848
1849 #ifdef CONFIG_HOSTAPD_MLME
1850         hostapd_mode_init(if1);
1851 #endif
1852
1853 #ifdef CONFIG_PLATFORM_RTD2880B
1854         DBG_871X("wlan link up\n");
1855         rtd2885_wlan_netlink_sendMsg("linkup", "8712");
1856 #endif
1857
1858 #ifdef RTK_DMP_PLATFORM
1859         rtw_proc_init_one(if1->pnetdev);
1860 #endif
1861
1862
1863         /* alloc irq */
1864         if (pci_alloc_irq(dvobj) != _SUCCESS)
1865                 goto free_if2;
1866
1867         RT_TRACE(_module_hci_intfs_c_,_drv_err_,("-871x_drv - drv_init, success!\n"));
1868         //DBG_871X("-871x_drv - drv_init, success!\n");
1869
1870         status = _SUCCESS;
1871
1872 free_if2:
1873         if(status != _SUCCESS && if2) {
1874                 #ifdef CONFIG_CONCURRENT_MODE
1875                 rtw_drv_if2_stop(if2);
1876                 rtw_drv_if2_free(if2);
1877                 #endif
1878         }
1879 free_if1:
1880         if (status != _SUCCESS && if1) {
1881                 rtw_pci_if1_deinit(if1);
1882         }
1883 free_dvobj:
1884         if (status != _SUCCESS)
1885                 pci_dvobj_deinit(pdev);
1886 exit:
1887         return status == _SUCCESS?0:-ENODEV;
1888 }
1889
1890 /*
1891  * dev_remove() - our device is being removed
1892 */
1893 //rmmod module & unplug(SurpriseRemoved) will call r871xu_dev_remove() => how to recognize both
1894 static void rtw_dev_remove(struct pci_dev *pdev)
1895 {
1896         struct dvobj_priv *pdvobjpriv = pci_get_drvdata(pdev);
1897         _adapter *padapter = pdvobjpriv->if1;
1898         struct net_device *pnetdev = padapter->pnetdev;
1899
1900 _func_exit_;
1901
1902         DBG_871X("+rtw_dev_remove\n");
1903
1904         pdvobjpriv->processing_dev_remove = _TRUE;
1905
1906         if (unlikely(!padapter)) {
1907                 return;
1908         }
1909
1910         rtw_unregister_netdevs(pdvobjpriv);
1911
1912         #if 0
1913 #ifdef RTK_DMP_PLATFORM
1914         padapter->bSurpriseRemoved = _FALSE;    // always trate as device exists
1915                                                                                         // this will let the driver to disable it's interrupt
1916 #else
1917         if(pci_drvpriv.drv_registered == _TRUE)
1918         {
1919                 //DBG_871X("r871xu_dev_remove():padapter->bSurpriseRemoved == _TRUE\n");
1920                 padapter->bSurpriseRemoved = _TRUE;
1921         }
1922         /*else
1923         {
1924                 //DBG_871X("r871xu_dev_remove():module removed\n");
1925                 padapter->hw_init_completed = _FALSE;
1926         }*/
1927 #endif
1928         #endif
1929
1930 #if defined(CONFIG_HAS_EARLYSUSPEND) || defined(CONFIG_ANDROID_POWER)
1931         rtw_unregister_early_suspend(&padapter->pwrctrlpriv);
1932 #endif
1933
1934         rtw_pm_set_ips(padapter, IPS_NONE);
1935         rtw_pm_set_lps(padapter, PS_MODE_ACTIVE);
1936
1937         LeaveAllPowerSaveMode(padapter);
1938
1939         rtw_hal_disable_interrupt(padapter);
1940
1941 #ifdef CONFIG_CONCURRENT_MODE
1942         rtw_drv_if2_stop(pdvobjpriv->if2);
1943 #endif //CONFIG_CONCURRENT_MODE
1944
1945         rtw_pci_if1_deinit(padapter);
1946
1947 #ifdef CONFIG_CONCURRENT_MODE
1948         rtw_drv_if2_free(pdvobjpriv->if2);
1949 #endif
1950
1951         pci_dvobj_deinit(pdev);
1952
1953         DBG_871X("-r871xu_dev_remove, done\n");
1954
1955 _func_exit_;
1956         return;
1957 }
1958
1959
1960 static int __init rtw_drv_entry(void)
1961 {
1962         int ret = 0;
1963
1964         RT_TRACE(_module_hci_intfs_c_,_drv_err_,("+rtw_drv_entry\n"));
1965         DBG_871X("rtw driver version=%s\n", DRIVERVERSION);
1966         DBG_871X("Build at: %s %s\n", __DATE__, __TIME__);
1967         pci_drvpriv.drv_registered = _TRUE;
1968
1969         rtw_suspend_lock_init();
1970
1971         ret = pci_register_driver(&pci_drvpriv.rtw_pci_drv);
1972         if (ret) {
1973                 RT_TRACE(_module_hci_intfs_c_, _drv_err_, (": No device found\n"));
1974         }
1975
1976         return ret;
1977 }
1978
1979 static void __exit rtw_drv_halt(void)
1980 {
1981         RT_TRACE(_module_hci_intfs_c_,_drv_err_,("+rtw_drv_halt\n"));
1982         DBG_871X("+rtw_drv_halt\n");
1983
1984         pci_drvpriv.drv_registered = _FALSE;
1985
1986         pci_unregister_driver(&pci_drvpriv.rtw_pci_drv);
1987
1988         rtw_suspend_lock_uninit();
1989         DBG_871X("-rtw_drv_halt\n");
1990
1991         rtw_mstat_dump();
1992 }
1993
1994
1995 module_init(rtw_drv_entry);
1996 module_exit(rtw_drv_halt);
1997