drivers/net/wireless/rtl8192du/include/rtw_pwrctrl.h

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  *
  19  ******************************************************************************/
  20 #ifndef __RTW_PWRCTRL_H_
  21 #define __RTW_PWRCTRL_H_
  22
  23 #include <drv_conf.h>
  24 #include <osdep_service.h>
  25 #include <drv_types.h>
  26
  27 #ifdef CONFIG_HAS_EARLYSUSPEND
  28 #include <linux/earlysuspend.h>
  29 #endif //CONFIG_HAS_EARLYSUSPEND
  30
  31
  32 #define FW_PWR0 0
  33 #define FW_PWR1         1
  34 #define FW_PWR2         2
  35 #define FW_PWR3         3
  36
  37
  38 #define HW_PWR0 7
  39 #define HW_PWR1         6
  40 #define HW_PWR2         2
  41 #define HW_PWR3 0
  42 #define HW_PWR4 8
  43
  44 #define FW_PWRMSK       0x7
  45
  46
  47 #define XMIT_ALIVE      BIT(0)
  48 #define RECV_ALIVE      BIT(1)
  49 #define CMD_ALIVE       BIT(2)
  50 #define EVT_ALIVE       BIT(3)
  51
  52
  53 enum Power_Mgnt
  54 {
  55         PS_MODE_ACTIVE  = 0     ,
  56         PS_MODE_MIN                     ,
  57         PS_MODE_MAX                     ,
  58         PS_MODE_DTIM                    ,
  59         PS_MODE_VOIP                    ,
  60         PS_MODE_UAPSD_WMM       ,
  61         PS_MODE_UAPSD                   ,
  62         PS_MODE_IBSS                    ,
  63         PS_MODE_WWLAN           ,
  64         PM_Radio_Off                    ,
  65         PM_Card_Disable         ,
  66         PS_MODE_NUM
  67 };
  68
  69
  70 /*
  71         BIT[2:0] = HW state
  72         BIT[3] = Protocol PS state,   0: register active state , 1: register sleep state
  73         BIT[4] = sub-state
  74 */
  75
  76 #define PS_DPS                          BIT(0)
  77 #define PS_LCLK                         (PS_DPS)
  78 #define PS_RF_OFF                       BIT(1)
  79 #define PS_ALL_ON                       BIT(2)
  80 #define PS_ST_ACTIVE            BIT(3)
  81
  82 #define PS_ISR_ENABLE           BIT(4)
  83 #define PS_IMR_ENABLE           BIT(5)
  84 #define PS_ACK                          BIT(6)
  85 #define PS_TOGGLE                       BIT(7)
  86
  87 #define PS_STATE_MASK           (0x0F)
  88 #define PS_STATE_HW_MASK        (0x07)
  89 #define PS_SEQ_MASK                     (0xc0)
  90
  91 #define PS_STATE(x)             (PS_STATE_MASK & (x))
  92 #define PS_STATE_HW(x)  (PS_STATE_HW_MASK & (x))
  93 #define PS_SEQ(x)               (PS_SEQ_MASK & (x))
  94
  95 #define PS_STATE_S0             (PS_DPS)
  96 #define PS_STATE_S1             (PS_LCLK)
  97 #define PS_STATE_S2             (PS_RF_OFF)
  98 #define PS_STATE_S3             (PS_ALL_ON)
  99 #define PS_STATE_S4             ((PS_ST_ACTIVE) | (PS_ALL_ON))
 100
 101
 102 #define PS_IS_RF_ON(x)  ((x) & (PS_ALL_ON))
 103 #define PS_IS_ACTIVE(x) ((x) & (PS_ST_ACTIVE))
 104 #define CLR_PS_STATE(x) ((x) = ((x) & (0xF0)))
 105
 106
 107 struct reportpwrstate_parm {
 108         unsigned char mode;
 109         unsigned char state; //the CPWM value
 110         unsigned short rsvd;
 111 };
 112
 113
 114 typedef _sema _pwrlock;
 115
 116
 117 __inline static void _init_pwrlock(_pwrlock *plock)
 118 {
 119         _rtw_init_sema(plock, 1);
 120 }
 121
 122 __inline static void _free_pwrlock(_pwrlock *plock)
 123 {
 124         _rtw_free_sema(plock);
 125 }
 126
 127
 128 __inline static void _enter_pwrlock(_pwrlock *plock)
 129 {
 130         _rtw_down_sema(plock);
 131 }
 132
 133
 134 __inline static void _exit_pwrlock(_pwrlock *plock)
 135 {
 136         _rtw_up_sema(plock);
 137 }
 138
 139 #define LPS_DELAY_TIME  1*HZ // 1 sec
 140
 141 #define EXE_PWR_NONE    0x01
 142 #define EXE_PWR_IPS             0x02
 143 #define EXE_PWR_LPS             0x04
 144
 145 // RF state.
 146 typedef enum _rt_rf_power_state
 147 {
 148         rf_on,          // RF is on after RFSleep or RFOff
 149         rf_sleep,       // 802.11 Power Save mode
 150         rf_off,         // HW/SW Radio OFF or Inactive Power Save
 151         //=====Add the new RF state above this line=====//
 152         rf_max
 153 }rt_rf_power_state;
 154
 155 // RF Off Level for IPS or HW/SW radio off
 156 #define RT_RF_OFF_LEVL_ASPM                     BIT(0)  // PCI ASPM
 157 #define RT_RF_OFF_LEVL_CLK_REQ          BIT(1)  // PCI clock request
 158 #define RT_RF_OFF_LEVL_PCI_D3                   BIT(2)  // PCI D3 mode
 159 #define RT_RF_OFF_LEVL_HALT_NIC         BIT(3)  // NIC halt, re-initialize hw parameters
 160 #define RT_RF_OFF_LEVL_FREE_FW          BIT(4)  // FW free, re-download the FW
 161 #define RT_RF_OFF_LEVL_FW_32K           BIT(5)  // FW in 32k
 162 #define RT_RF_PS_LEVEL_ALWAYS_ASPM      BIT(6)  // Always enable ASPM and Clock Req in initialization.
 163 #define RT_RF_LPS_DISALBE_2R                    BIT(30) // When LPS is on, disable 2R if no packet is received or transmittd.
 164 #define RT_RF_LPS_LEVEL_ASPM                    BIT(31) // LPS with ASPM
 165
 166 #define RT_IN_PS_LEVEL(ppsc, _PS_FLAG)          ((ppsc->cur_ps_level & _PS_FLAG) ? _TRUE : _FALSE)
 167 #define RT_CLEAR_PS_LEVEL(ppsc, _PS_FLAG)       (ppsc->cur_ps_level &= (~(_PS_FLAG)))
 168 #define RT_SET_PS_LEVEL(ppsc, _PS_FLAG)         (ppsc->cur_ps_level |= _PS_FLAG)
 169
 170
 171 enum _PS_BBRegBackup_ {
 172         PSBBREG_RF0 = 0,
 173         PSBBREG_RF1,
 174         PSBBREG_RF2,
 175         PSBBREG_AFE0,
 176         PSBBREG_TOTALCNT
 177 };
 178
 179 enum { // for ips_mode
 180         IPS_NONE=0,
 181         IPS_NORMAL,
 182         IPS_LEVEL_2,
 183 };
 184
 185 struct pwrctrl_priv
 186 {
 187         _pwrlock        lock;
 188         volatile u8 rpwm; // requested power state for fw
 189         volatile u8 cpwm; // fw current power state. updated when 1. read from HCPWM 2. driver lowers power level
 190         volatile u8 tog; // toggling
 191         volatile u8 cpwm_tog; // toggling
 192         u8      pwr_mode;
 193         u8      smart_ps;
 194         u32 alives;
 195
 196         u8      b_hw_radio_off;
 197         u8      reg_rfoff;
 198         u8      reg_pdnmode; //powerdown mode
 199         u32     rfoff_reason;
 200
 201         //RF OFF Level
 202         u32     cur_ps_level;
 203         u32     reg_rfps_level;
 204
 205
 206
 207 #ifdef CONFIG_PCI_HCI
 208         //just for PCIE ASPM
 209         u8      b_support_aspm; // If it supports ASPM, Offset[560h] = 0x40, otherwise Offset[560h] = 0x00.
 210         u8      b_support_backdoor;
 211
 212         //just for PCIE ASPM
 213         u8      const_amdpci_aspm;
 214 #endif
 215
 216         uint    ips_enter_cnts;
 217         uint    ips_leave_cnts;
 218
 219         u8      ips_mode;
 220         u8      ips_mode_req; // used to accept the mode setting request, will update to ipsmode later
 221         uint bips_processing;
 222         u32 ips_deny_time; /* will deny IPS when system time is smaller than this */
 223         u8 ps_processing; /* temporarily used to mark whether in rtw_ps_processor */
 224
 225         u8      bLeisurePs;
 226         u8      LpsIdleCount;
 227         u8      power_mgnt;
 228         u8      bFwCurrentInPSMode;
 229         u32     DelayLPSLastTimeStamp;
 230
 231         s32             pnp_current_pwr_state;
 232         u8              pnp_bstop_trx;
 233
 234
 235         u8              bInternalAutoSuspend;
 236         u8              bInSuspend;
 237         u8              bSupportRemoteWakeup;
 238 #ifdef CONFIG_WOWLAN
 239         u8              wowlan_mode;
 240         u8              wowlan_pattern;
 241         u8              wowlan_magic;
 242         u8              wowlan_unicast;
 243         u8              wowlan_pattern_idx;
 244         u32             wowlan_pattern_context[8][5];
 245 #endif // CONFIG_WOWLAN
 246         _timer  pwr_state_check_timer;
 247         int             pwr_state_check_interval;
 248         u8              pwr_state_check_cnts;
 249
 250         int             ps_flag;
 251
 252         rt_rf_power_state       rf_pwrstate;//cur power state
 253         //rt_rf_power_state     current_rfpwrstate;
 254         rt_rf_power_state       change_rfpwrstate;
 255
 256         u8              bHWPowerdown;//if support hw power down
 257         u8              bHWPwrPindetect;
 258         u8              bkeepfwalive;
 259         u8              brfoffbyhw;
 260         unsigned long PS_BBRegBackup[PSBBREG_TOTALCNT];
 261
 262         #ifdef CONFIG_RESUME_IN_WORKQUEUE
 263         struct workqueue_struct *rtw_workqueue;
 264         _workitem resume_work;
 265         #endif
 266
 267         #ifdef CONFIG_HAS_EARLYSUSPEND
 268         struct early_suspend early_suspend;
 269         u8 do_late_resume;
 270         #endif //CONFIG_HAS_EARLYSUSPEND
 271
 272         #ifdef CONFIG_ANDROID_POWER
 273         android_early_suspend_t early_suspend;
 274         u8 do_late_resume;
 275         #endif
 276
 277 };
 278
 279 #define rtw_get_ips_mode_req(pwrctrlpriv) \
 280         (pwrctrlpriv)->ips_mode_req
 281
 282 #define rtw_ips_mode_req(pwrctrlpriv, ips_mode) \
 283         (pwrctrlpriv)->ips_mode_req = (ips_mode)
 284
 285 #define RTW_PWR_STATE_CHK_INTERVAL 2000
 286
 287 #define _rtw_set_pwr_state_check_timer(pwrctrlpriv, ms) \
 288         do { \
 289                 /*DBG_871X("%s _rtw_set_pwr_state_check_timer(%p, %d)\n", __FUNCTION__, (pwrctrlpriv), (ms));*/ \
 290                 _set_timer(&(pwrctrlpriv)->pwr_state_check_timer, (ms)); \
 291         } while(0)
 292
 293 #define rtw_set_pwr_state_check_timer(pwrctrlpriv) \
 294         _rtw_set_pwr_state_check_timer((pwrctrlpriv), (pwrctrlpriv)->pwr_state_check_interval)
 295
 296 extern void rtw_init_pwrctrl_priv(_adapter *adapter);
 297 extern void rtw_free_pwrctrl_priv(_adapter * adapter);
 298
 299 #ifdef CONFIG_LPS_LCLK
 300 extern s32 rtw_register_tx_alive(PADAPTER padapter);
 301 extern void rtw_unregister_tx_alive(PADAPTER padapter);
 302 extern s32 rtw_register_rx_alive(PADAPTER padapter);
 303 extern void rtw_unregister_rx_alive(PADAPTER padapter);
 304 extern s32 rtw_register_cmd_alive(PADAPTER padapter);
 305 extern void rtw_unregister_cmd_alive(PADAPTER padapter);
 306 extern s32 rtw_register_evt_alive(PADAPTER padapter);
 307 extern void rtw_unregister_evt_alive(PADAPTER padapter);
 308 extern void cpwm_int_hdl(PADAPTER padapter, struct reportpwrstate_parm *preportpwrstate);
 309 #endif
 310
 311 extern void rtw_set_ps_mode(_adapter * padapter, u8 ps_mode, u8 smart_ps);
 312 extern void rtw_set_rpwm(_adapter * padapter, u8 val8);
 313 extern void LeaveAllPowerSaveMode(PADAPTER Adapter);
 314 #ifdef CONFIG_IPS
 315 void _ips_enter(_adapter * padapter);
 316 void ips_enter(_adapter * padapter);
 317 int _ips_leave(_adapter * padapter);
 318 int ips_leave(_adapter * padapter);
 319 #endif
 320
 321 void rtw_ps_processor(_adapter*padapter);
 322
 323 #ifdef CONFIG_AUTOSUSPEND
 324 int autoresume_enter(_adapter* padapter);
 325 #endif
 326 #ifdef SUPPORT_HW_RFOFF_DETECTED
 327 rt_rf_power_state RfOnOffDetect(IN      PADAPTER pAdapter );
 328 #endif
 329
 330
 331 #ifdef CONFIG_LPS
 332 void LPS_Enter(PADAPTER padapter);
 333 void LPS_Leave(PADAPTER padapter);
 334 #endif
 335
 336 #ifdef CONFIG_RESUME_IN_WORKQUEUE
 337 void rtw_resume_in_workqueue(struct pwrctrl_priv *pwrpriv);
 338 #endif //CONFIG_RESUME_IN_WORKQUEUE
 339
 340 #if defined(CONFIG_HAS_EARLYSUSPEND ) || defined(CONFIG_ANDROID_POWER)
 341 bool rtw_is_earlysuspend_registered(struct pwrctrl_priv *pwrpriv);
 342 bool rtw_is_do_late_resume(struct pwrctrl_priv *pwrpriv);
 343 void rtw_set_do_late_resume(struct pwrctrl_priv *pwrpriv, bool enable);
 344 void rtw_register_early_suspend(struct pwrctrl_priv *pwrpriv);
 345 void rtw_unregister_early_suspend(struct pwrctrl_priv *pwrpriv);
 346 #else
 347 #define rtw_is_earlysuspend_registered(pwrpriv) _FALSE
 348 #define rtw_is_do_late_resume(pwrpriv) _FALSE
 349 #define rtw_set_do_late_resume(pwrpriv, enable) do {} while (0)
 350 #define rtw_register_early_suspend(pwrpriv) do {} while (0)
 351 #define rtw_unregister_early_suspend(pwrpriv) do {} while (0)
 352 #endif /* CONFIG_HAS_EARLYSUSPEND || CONFIG_ANDROID_POWER */
 353
 354 u8 rtw_interface_ps_func(_adapter *padapter,HAL_INTF_PS_FUNC efunc_id,u8* val);
 355 void rtw_set_ips_deny(_adapter *padapter, u32 ms);
 356 int _rtw_pwr_wakeup(_adapter *padapter, u32 ips_deffer_ms, const char *caller);
 357 #define rtw_pwr_wakeup(adapter) _rtw_pwr_wakeup(adapter, RTW_PWR_STATE_CHK_INTERVAL, __FUNCTION__)
 358 #define rtw_pwr_wakeup_ex(adapter, ips_deffer_ms) _rtw_pwr_wakeup(adapter, ips_deffer_ms, __FUNCTION__)
 359 int rtw_pm_set_ips(_adapter *padapter, u8 mode);
 360 int rtw_pm_set_lps(_adapter *padapter, u8 mode);
 361
 362 #endif  //__RTL871X_PWRCTRL_H_