1 /******************************************************************************
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
19 ******************************************************************************/
20 #ifndef __HALPWRSEQCMD_H__
21 #define __HALPWRSEQCMD_H__
23 #include <drv_types.h>
25 /*---------------------------------------------*/
26 //3 The value of cmd: 4 bits
27 /*---------------------------------------------*/
28 #define PWR_CMD_READ 0x00
29 // offset: the read register offset
30 // msk: the mask of the read value
31 // value: N/A, left by 0
32 // note: dirver shall implement this function by read & msk
34 #define PWR_CMD_WRITE 0x01
35 // offset: the read register offset
36 // msk: the mask of the write bits
38 // note: driver shall implement this cmd by read & msk after write
40 #define PWR_CMD_POLLING 0x02
41 // offset: the read register offset
42 // msk: the mask of the polled value
43 // value: the value to be polled, masked by the msd field.
44 // note: driver shall implement this cmd by
46 // if( (Read(offset) & msk) == (value & msk) )
48 // } while(not timeout);
50 #define PWR_CMD_DELAY 0x03
51 // offset: the value to delay
53 // value: the unit of delay, 0: us, 1: ms
55 #define PWR_CMD_END 0x04
60 /*---------------------------------------------*/
61 //3 The value of base: 4 bits
62 /*---------------------------------------------*/
63 // define the base address of each block
64 #define PWR_BASEADDR_MAC 0x00
65 #define PWR_BASEADDR_USB 0x01
66 #define PWR_BASEADDR_PCIE 0x02
67 #define PWR_BASEADDR_SDIO 0x03
69 /*---------------------------------------------*/
70 //3 The value of interface_msk: 4 bits
71 /*---------------------------------------------*/
72 #define PWR_INTF_SDIO_MSK BIT(0)
73 #define PWR_INTF_USB_MSK BIT(1)
74 #define PWR_INTF_PCI_MSK BIT(2)
75 #define PWR_INTF_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3))
77 /*---------------------------------------------*/
78 //3 The value of fab_msk: 4 bits
79 /*---------------------------------------------*/
80 #define PWR_FAB_TSMC_MSK BIT(0)
81 #define PWR_FAB_UMC_MSK BIT(1)
82 #define PWR_FAB_ALL_MSK (BIT(0)|BIT(1)|BIT(2)|BIT(3))
84 /*---------------------------------------------*/
85 //3 The value of cut_msk: 8 bits
86 /*---------------------------------------------*/
87 #define PWR_CUT_TESTCHIP_MSK BIT(0)
88 #define PWR_CUT_A_MSK BIT(1)
89 #define PWR_CUT_B_MSK BIT(2)
90 #define PWR_CUT_C_MSK BIT(3)
91 #define PWR_CUT_D_MSK BIT(4)
92 #define PWR_CUT_E_MSK BIT(5)
93 #define PWR_CUT_F_MSK BIT(6)
94 #define PWR_CUT_G_MSK BIT(7)
95 #define PWR_CUT_ALL_MSK 0xFF
98 typedef enum _PWRSEQ_CMD_DELAY_UNIT_
104 typedef struct _WL_PWR_CFG_
114 } WLAN_PWR_CFG, *PWLAN_PWR_CFG;
117 #define GET_PWR_CFG_OFFSET(__PWR_CMD) __PWR_CMD.offset
118 #define GET_PWR_CFG_CUT_MASK(__PWR_CMD) __PWR_CMD.cut_msk
119 #define GET_PWR_CFG_FAB_MASK(__PWR_CMD) __PWR_CMD.fab_msk
120 #define GET_PWR_CFG_INTF_MASK(__PWR_CMD) __PWR_CMD.interface_msk
121 #define GET_PWR_CFG_BASE(__PWR_CMD) __PWR_CMD.base
122 #define GET_PWR_CFG_CMD(__PWR_CMD) __PWR_CMD.cmd
123 #define GET_PWR_CFG_MASK(__PWR_CMD) __PWR_CMD.msk
124 #define GET_PWR_CFG_VALUE(__PWR_CMD) __PWR_CMD.value
127 //================================================================================
128 // Prototype of protected function.
129 //================================================================================
130 u8 HalPwrSeqCmdParsing(
135 WLAN_PWR_CFG PwrCfgCmd[]);