drivers/net/wireless/rtl8192du/hal/dm.c

   1 /******************************************************************************\r
   2  *\r
   3  * Copyright(c) 2007 - 2013 Realtek Corporation. All rights reserved.\r
   4  *                                        \r
   5  * This program is free software; you can redistribute it and/or modify it\r
   6  * under the terms of version 2 of the GNU General Public License as\r
   7  * published by the Free Software Foundation.\r
   8  *\r
   9  * This program is distributed in the hope that it will be useful, but WITHOUT\r
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
  12  * more details.\r
  13  *\r
  14  * You should have received a copy of the GNU General Public License along with\r
  15  * this program; if not, write to the Free Software Foundation, Inc.,\r
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA\r
  17  *\r
  18  *\r
  19  ******************************************************************************/\r
  20 \r
  21 #include <drv_conf.h>\r
  22 #include <osdep_service.h>\r
  23 #include <drv_types.h>\r
  24 \r
  25 #ifdef CONFIG_RTL8192C\r
  26 #include <rtl8192c_hal.h>\r
  27 #endif\r
  28 \r
  29 #ifdef CONFIG_RTL8192D\r
  30 #include <rtl8192d_hal.h>\r
  31 #endif\r
  32 \r
  33 bool rtw_adapter_linked(_adapter *adapter)\r
  34 {\r
  35         bool linked = _FALSE;\r
  36         struct mlme_priv        *mlmepriv = &adapter->mlmepriv;\r
  37 \r
  38         if(     (check_fwstate(mlmepriv, WIFI_AP_STATE) == _TRUE) ||\r
  39                 (check_fwstate(mlmepriv, WIFI_ADHOC_STATE|WIFI_ADHOC_MASTER_STATE) == _TRUE))\r
  40         {                               \r
  41                 if(adapter->stapriv.asoc_sta_count > 2)\r
  42                         linked = _TRUE;\r
  43         }\r
  44         else{//Station mode\r
  45                 if(check_fwstate(mlmepriv, _FW_LINKED)== _TRUE)\r
  46                         linked = _TRUE;\r
  47         }\r
  48 \r
  49         return linked;\r
  50 }\r
  51 \r
  52 bool dm_linked(_adapter *adapter)\r
  53 {\r
  54         bool linked;\r
  55 \r
  56         if ((linked = rtw_adapter_linked(adapter)))\r
  57                 goto exit;\r
  58 \r
  59 #ifdef CONFIG_CONCURRENT_MODE\r
  60         if ((adapter =  adapter->pbuddy_adapter) == NULL)\r
  61                 goto exit;\r
  62         linked = rtw_adapter_linked(adapter);\r
  63 #endif\r
  64 \r
  65 exit:\r
  66         return linked;\r
  67 }\r
  68 \r
  69 #if 0\r
  70 void dm_enable_EDCCA(_adapter *adapter)\r
  71 {\r
  72         // Enable EDCCA. The value is suggested by SD3 Wilson.\r
  73 \r
  74         //\r
  75         // Revised for ASUS 11b/g performance issues, suggested by BB Neil, 2012.04.13.\r
  76         //\r
  77         /*if((pDM_Odm->SupportICType == ODM_RTL8723A)&&(IS_WIRELESS_MODE_G(pAdapter)))\r
  78         {\r
  79                 rtw_write8(adapter,rOFDM0_ECCAThreshold,0x00);\r
  80                 rtw_write8(adapter,rOFDM0_ECCAThreshold+2,0xFD);\r
  81                 \r
  82         }       \r
  83         else*/\r
  84         {\r
  85                 rtw_write8(adapter,rOFDM0_ECCAThreshold,0x03);\r
  86                 rtw_write8(adapter,rOFDM0_ECCAThreshold+2,0x00);\r
  87         }\r
  88 }\r
  89 \r
  90 void dm_disable_EDCCA(_adapter *adapter)\r
  91 {       \r
  92         // Disable EDCCA..\r
  93         rtw_write8(adapter, rOFDM0_ECCAThreshold, 0x7f);\r
  94         rtw_write8(adapter, rOFDM0_ECCAThreshold+2, 0x7f);\r
  95 }\r
  96 \r
  97 //\r
  98 // Description: According to initial gain value to determine to enable or disable EDCCA.\r
  99 //\r
 100 // Suggested by SD3 Wilson. Added by tynli. 2011.11.25.\r
 101 //\r
 102 void dm_dynamic_EDCCA(_adapter *pAdapter)\r
 103 {\r
 104         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);\r
 105         struct dm_priv *dmpriv = &pHalData->dmpriv;\r
 106         u8 RegC50, RegC58;\r
 107         \r
 108         RegC50 = (u8)PHY_QueryBBReg(pAdapter, rOFDM0_XAAGCCore1, bMaskByte0);\r
 109         RegC58 = (u8)PHY_QueryBBReg(pAdapter, rOFDM0_XBAGCCore1, bMaskByte0);\r
 110 \r
 111 \r
 112         if((RegC50 > 0x28 && RegC58 > 0x28)\r
 113                 /*|| ((pDM_Odm->SupportICType == ODM_RTL8723A && IS_WIRELESS_MODE_G(pAdapter) && RegC50>0x26))\r
 114                 || (pDM_Odm->SupportICType == ODM_RTL8188E && RegC50 > 0x28)*/\r
 115         )\r
 116         {\r
 117                 if(!dmpriv->bPreEdccaEnable)\r
 118                 {\r
 119                         dm_enable_EDCCA(pAdapter);\r
 120                         dmpriv->bPreEdccaEnable = _TRUE;\r
 121                 }\r
 122                 \r
 123         }\r
 124         else if((RegC50 < 0x25 && RegC58 < 0x25)\r
 125                 /*|| (pDM_Odm->SupportICType == ODM_RTL8188E && RegC50 < 0x25)*/\r
 126         )\r
 127         {\r
 128                 if(dmpriv->bPreEdccaEnable)\r
 129                 {\r
 130                         dm_disable_EDCCA(pAdapter);\r
 131                         dmpriv->bPreEdccaEnable = _FALSE;\r
 132                 }\r
 133         }\r
 134 }\r
 135 #endif\r
 136 \r
 137 #define DM_ADAPTIVITY_VER "ADAPTIVITY_V001"\r
 138 \r
 139 int dm_adaptivity_get_parm_str(_adapter *pAdapter, char *buf, int len)\r
 140 {\r
 141 #ifdef CONFIG_DM_ADAPTIVITY\r
 142         HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);\r
 143         struct dm_priv *dmpriv = &pHalData->dmpriv;\r
 144 \r
 145         return snprintf(buf, len, DM_ADAPTIVITY_VER"\n"\r
 146                 "TH_L2H_ini\tTH_EDCCA_HL_diff\tIGI_Base\tForceEDCCA\tAdapEn_RSSI\tIGI_LowerBound\n"\r
 147                 "0x%02x\t%d\t0x%02x\t%d\t%u\t%u\n",\r
 148                 (u8)dmpriv->TH_L2H_ini,\r
 149                 dmpriv->TH_EDCCA_HL_diff,\r
 150                 dmpriv->IGI_Base,\r
 151                 dmpriv->ForceEDCCA,\r
 152                 dmpriv->AdapEn_RSSI,\r
 153                 dmpriv->IGI_LowerBound\r
 154         );\r
 155 #endif /* CONFIG_DM_ADAPTIVITY */\r
 156         return 0;\r
 157 }\r
 158 \r
 159 void dm_adaptivity_set_parm(_adapter *pAdapter, s8 TH_L2H_ini, s8 TH_EDCCA_HL_diff,\r
 160         s8 IGI_Base, bool ForceEDCCA, u8 AdapEn_RSSI, u8 IGI_LowerBound)\r
 161 {\r
 162 #ifdef CONFIG_DM_ADAPTIVITY\r
 163         HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);\r
 164         struct dm_priv *dmpriv = &pHalData->dmpriv;\r
 165 \r
 166         dmpriv->TH_L2H_ini = TH_L2H_ini;\r
 167         dmpriv->TH_EDCCA_HL_diff = TH_EDCCA_HL_diff;\r
 168         dmpriv->IGI_Base = IGI_Base;\r
 169         dmpriv->ForceEDCCA = ForceEDCCA;\r
 170         dmpriv->AdapEn_RSSI = AdapEn_RSSI;\r
 171         dmpriv->IGI_LowerBound = IGI_LowerBound;\r
 172 \r
 173 #endif /* CONFIG_DM_ADAPTIVITY */\r
 174 }\r
 175 \r
 176 void dm_adaptivity_init(_adapter *pAdapter)\r
 177 {\r
 178 #ifdef CONFIG_DM_ADAPTIVITY\r
 179         HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);\r
 180         struct dm_priv *dmpriv = &pHalData->dmpriv;\r
 181 \r
 182         /*\r
 183         if(pDM_Odm->SupportICType == ODM_RTL8723B)\r
 184         {\r
 185                 pDM_Odm->TH_L2H_ini = 0xf8; // -8\r
 186         }\r
 187         if((pDM_Odm->SupportICType == ODM_RTL8192E)&&(pDM_Odm->SupportInterface == ODM_ITRF_PCIE))\r
 188         {\r
 189                 pDM_Odm->TH_L2H_ini = 0xf0; // -16\r
 190         }\r
 191         else */\r
 192         {\r
 193                 dmpriv->TH_L2H_ini = 0xf9; // -7\r
 194         }\r
 195 \r
 196         dmpriv->TH_EDCCA_HL_diff = 7;\r
 197         dmpriv->IGI_Base = 0x32;\r
 198         dmpriv->IGI_target = 0x1c;\r
 199         dmpriv->ForceEDCCA = 0;\r
 200         dmpriv->AdapEn_RSSI = 20;\r
 201         dmpriv->IGI_LowerBound = 0;\r
 202 \r
 203         //Reg524[11]=0 is easily to transmit packets during adaptivity test\r
 204         PHY_SetBBReg(pAdapter, 0x524, BIT11, 1); // stop counting if EDCCA is asserted\r
 205 \r
 206 #endif /* CONFIG_DM_ADAPTIVITY */\r
 207 }\r
 208 \r
 209 void dm_adaptivity(_adapter *pAdapter)\r
 210 {\r
 211 #ifdef CONFIG_DM_ADAPTIVITY\r
 212         s8 TH_L2H_dmc, TH_H2L_dmc;\r
 213         s8 TH_L2H, TH_H2L, Diff, IGI_target;\r
 214         u32 value32;\r
 215         BOOLEAN EDCCA_State;\r
 216 \r
 217         HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);\r
 218         struct dm_priv *dmpriv = &pHalData->dmpriv;\r
 219         DIG_T *pDigTable = &dmpriv->DM_DigTable;\r
 220         u8 IGI = pDigTable->CurIGValue;\r
 221         u8 RSSI_Min = pDigTable->Rssi_val_min;\r
 222         HT_CHANNEL_WIDTH BandWidth = pHalData->CurrentChannelBW;\r
 223 \r
 224         if (!(dmpriv->DMFlag & DYNAMIC_FUNC_ADAPTIVITY))\r
 225         {\r
 226                 LOG_LEVEL(_drv_info_, "Go to odm_DynamicEDCCA() \n");\r
 227                 // Add by Neil Chen to enable edcca to MP Platform \r
 228                 // Adjust EDCCA.\r
 229                 /*if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES)\r
 230                         dm_dynamic_EDCCA(pAdapter);\r
 231                 */\r
 232                 return;\r
 233         }\r
 234         LOG_LEVEL(_drv_info_, "odm_Adaptivity() =====> \n");\r
 235 \r
 236         LOG_LEVEL(_drv_info_, "ForceEDCCA=%d, IGI_Base=0x%x, TH_L2H_ini = %d, TH_EDCCA_HL_diff = %d, AdapEn_RSSI = %d\n", \r
 237                 dmpriv->ForceEDCCA, dmpriv->IGI_Base, dmpriv->TH_L2H_ini, dmpriv->TH_EDCCA_HL_diff, dmpriv->AdapEn_RSSI);\r
 238 \r
 239         /*if(pDM_Odm->SupportICType & ODM_IC_11AC_SERIES)\r
 240                 PHY_SetBBReg(0x800, BIT10, 0); //ADC_mask enable\r
 241         */\r
 242         \r
 243         if(!dm_linked(pAdapter) || pHalData->CurrentChannel > 149) /* Band4 doesn't need adaptivity */\r
 244         {\r
 245                 /*if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES)*/\r
 246                 {\r
 247                         PHY_SetBBReg(pAdapter,rOFDM0_ECCAThreshold, bMaskByte0, 0x7f);\r
 248                         PHY_SetBBReg(pAdapter,rOFDM0_ECCAThreshold, bMaskByte2, 0x7f);\r
 249                 }\r
 250                 /*else\r
 251                 {\r
 252                         ODM_SetBBReg(pDM_Odm, rFPGA0_XB_LSSIReadBack, 0xFFFF, (0x7f<<8) | 0x7f);\r
 253                 }*/\r
 254                 return;\r
 255         }\r
 256 \r
 257         if(!dmpriv->ForceEDCCA)\r
 258         {\r
 259                 if(RSSI_Min > dmpriv->AdapEn_RSSI)\r
 260                         EDCCA_State = 1;\r
 261                 else if(RSSI_Min < (dmpriv->AdapEn_RSSI - 5))\r
 262                         EDCCA_State = 0;\r
 263         }\r
 264         else\r
 265                 EDCCA_State = 1;\r
 266         //if((pDM_Odm->SupportICType & ODM_IC_11AC_SERIES) && (*pDM_Odm->pBandType == BAND_ON_5G))\r
 267                 //IGI_target = pDM_Odm->IGI_Base;\r
 268         //else\r
 269         {\r
 270 \r
 271                 if(BandWidth == HT_CHANNEL_WIDTH_20) //CHANNEL_WIDTH_20\r
 272                         IGI_target = dmpriv->IGI_Base;\r
 273                 else if(BandWidth == HT_CHANNEL_WIDTH_40)\r
 274                         IGI_target = dmpriv->IGI_Base + 2;\r
 275                 /*else if(*pDM_Odm->pBandWidth == ODM_BW80M)\r
 276                         IGI_target = pDM_Odm->IGI_Base + 6;*/\r
 277                 else\r
 278                         IGI_target = dmpriv->IGI_Base;\r
 279         }\r
 280 \r
 281         dmpriv->IGI_target = (u8)IGI_target;\r
 282 \r
 283         LOG_LEVEL(_drv_info_, "BandWidth=%s, IGI_target=0x%x, EDCCA_State=%d\n",\r
 284                 (BandWidth==HT_CHANNEL_WIDTH_40)?"40M":"20M", IGI_target, EDCCA_State);\r
 285 \r
 286         if(EDCCA_State == 1)\r
 287         {\r
 288                 Diff = IGI_target -(s8)IGI;\r
 289                 TH_L2H_dmc = dmpriv->TH_L2H_ini + Diff;\r
 290                 if(TH_L2H_dmc > 10)     TH_L2H_dmc = 10;\r
 291                 TH_H2L_dmc = TH_L2H_dmc - dmpriv->TH_EDCCA_HL_diff;\r
 292         }\r
 293         else\r
 294         {\r
 295                 TH_L2H_dmc = 0x7f;\r
 296                 TH_H2L_dmc = 0x7f;\r
 297         }\r
 298 \r
 299         LOG_LEVEL(_drv_info_, "IGI=0x%x, TH_L2H_dmc = %d, TH_H2L_dmc = %d\n", \r
 300                 IGI, TH_L2H_dmc, TH_H2L_dmc);\r
 301 \r
 302         /*if(pDM_Odm->SupportICType & ODM_IC_11N_SERIES)*/\r
 303         {\r
 304                 PHY_SetBBReg(pAdapter,rOFDM0_ECCAThreshold, bMaskByte0, (u8)TH_L2H_dmc);\r
 305                 PHY_SetBBReg(pAdapter,rOFDM0_ECCAThreshold, bMaskByte2, (u8)TH_H2L_dmc);\r
 306         }\r
 307         /*else\r
 308                 PHY_SetBBReg(pAdapter, rFPGA0_XB_LSSIReadBack, 0xFFFF, ((u8)TH_H2L_dmc<<8) | (u8)TH_L2H_dmc);*/\r
 309 \r
 310 skip_dm:\r
 311         return;\r
 312 #endif /* CONFIG_DM_ADAPTIVITY */\r
 313 }\r
 314 \r