drivers/net/wireless/rtl8192cu/hal/rtl8192c/rtl8192c_phycfg.c

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  *
  19  ******************************************************************************/
  20 /******************************************************************************
  21
  22  Module:        rtl8192c_phycfg.c
  23
  24  Note:          Merge 92SE/SU PHY config as below
  25                         1. BB register R/W API
  26                         2. RF register R/W API
  27                         3. Initial BB/RF/MAC config by reading BB/MAC/RF txt.
  28                         3. Power setting API
  29                         4. Channel switch API
  30                         5. Initial gain switch API.
  31                         6. Other BB/MAC/RF API.
  32
  33  Function:      PHY: Extern function, phy: local function
  34
  35  Export:        PHY_FunctionName
  36
  37  Abbrev:        NONE
  38
  39  History:
  40         Data            Who             Remark
  41         08/08/2008  MHC         1. Port from 9x series phycfg.c
  42                                                 2. Reorganize code arch and ad description.
  43                                                 3. Collect similar function.
  44                                                 4. Seperate extern/local API.
  45         08/12/2008      MHC             We must merge or move USB PHY relative function later.
  46         10/07/2008      MHC             Add IQ calibration for PHY.(Only 1T2R mode now!!!)
  47         11/06/2008      MHC             Add TX Power index PG file to config in 0xExx register
  48                                                 area to map with EEPROM/EFUSE tx pwr index.
  49
  50 ******************************************************************************/
  51 #define _HAL_8192C_PHYCFG_C_
  52
  53 #include <drv_conf.h>
  54 #include <osdep_service.h>
  55 #include <drv_types.h>
  56 #include <rtw_byteorder.h>
  57
  58 #ifdef CONFIG_IOL
  59 #include <rtw_iol.h>
  60 #endif
  61
  62 #include <rtl8192c_hal.h>
  63
  64
  65 /*---------------------------Define Local Constant---------------------------*/
  66 /* Channel switch:The size of command tables for switch channel*/
  67 #define MAX_PRECMD_CNT 16
  68 #define MAX_RFDEPENDCMD_CNT 16
  69 #define MAX_POSTCMD_CNT 16
  70
  71 #define MAX_DOZE_WAITING_TIMES_9x 64
  72
  73 /*---------------------------Define Local Constant---------------------------*/
  74
  75
  76 /*------------------------Define global variable-----------------------------*/
  77
  78 /*------------------------Define local variable------------------------------*/
  79
  80
  81 /*--------------------Define export function prototype-----------------------*/
  82 // Please refer to header file
  83 /*--------------------Define export function prototype-----------------------*/
  84
  85 /*----------------------------Function Body----------------------------------*/
  86 //
  87 // 1. BB register R/W API
  88 //
  89
  90 /**
  91 * Function:     phy_CalculateBitShift
  92 *
  93 * OverView:     Get shifted position of the BitMask
  94 *
  95 * Input:
  96 *                       u4Byte          BitMask,
  97 *
  98 * Output:       none
  99 * Return:               u4Byte          Return the shift bit bit position of the mask
 100 */
 101 static  u32
 102 phy_CalculateBitShift(
 103         u32 BitMask
 104         )
 105 {
 106         u32 i;
 107
 108         for(i=0; i<=31; i++)
 109         {
 110                 if ( ((BitMask>>i) &  0x1 ) == 1)
 111                         break;
 112         }
 113
 114         return (i);
 115 }
 116
 117
 118 /**
 119 * Function:     PHY_QueryBBReg
 120 *
 121 * OverView:     Read "sepcific bits" from BB register
 122 *
 123 * Input:
 124 *                       PADAPTER                Adapter,
 125 *                       u4Byte                  RegAddr,                //The target address to be readback
 126 *                       u4Byte                  BitMask         //The target bit position in the target address
 127 *                                                                               //to be readback
 128 * Output:       None
 129 * Return:               u4Byte                  Data                    //The readback register value
 130 * Note:         This function is equal to "GetRegSetting" in PHY programming guide
 131 */
 132 u32
 133 rtl8192c_PHY_QueryBBReg(
 134         IN      PADAPTER        Adapter,
 135         IN      u32             RegAddr,
 136         IN      u32             BitMask
 137         )
 138 {
 139         u32     ReturnValue = 0, OriginalValue, BitShift;
 140         u16     BBWaitCounter = 0;
 141
 142 #if (DISABLE_BB_RF == 1)
 143         return 0;
 144 #endif
 145
 146         //RT_TRACE(COMP_RF, DBG_TRACE, ("--->PHY_QueryBBReg(): RegAddr(%#lx), BitMask(%#lx)\n", RegAddr, BitMask));
 147
 148         OriginalValue = rtw_read32(Adapter, RegAddr);
 149         BitShift = phy_CalculateBitShift(BitMask);
 150         ReturnValue = (OriginalValue & BitMask) >> BitShift;
 151
 152         //RTPRINT(FPHY, PHY_BBR, ("BBR MASK=0x%lx Addr[0x%lx]=0x%lx\n", BitMask, RegAddr, OriginalValue));
 153         //RT_TRACE(COMP_RF, DBG_TRACE, ("<---PHY_QueryBBReg(): RegAddr(%#lx), BitMask(%#lx), OriginalValue(%#lx)\n", RegAddr, BitMask, OriginalValue));
 154
 155         return (ReturnValue);
 156
 157 }
 158
 159
 160 /**
 161 * Function:     PHY_SetBBReg
 162 *
 163 * OverView:     Write "Specific bits" to BB register (page 8~)
 164 *
 165 * Input:
 166 *                       PADAPTER                Adapter,
 167 *                       u4Byte                  RegAddr,                //The target address to be modified
 168 *                       u4Byte                  BitMask         //The target bit position in the target address
 169 *                                                                               //to be modified
 170 *                       u4Byte                  Data                    //The new register value in the target bit position
 171 *                                                                               //of the target address
 172 *
 173 * Output:       None
 174 * Return:               None
 175 * Note:         This function is equal to "PutRegSetting" in PHY programming guide
 176 */
 177
 178 VOID
 179 rtl8192c_PHY_SetBBReg(
 180         IN      PADAPTER        Adapter,
 181         IN      u32             RegAddr,
 182         IN      u32             BitMask,
 183         IN      u32             Data
 184         )
 185 {
 186         HAL_DATA_TYPE   *pHalData               = GET_HAL_DATA(Adapter);
 187         //u16                   BBWaitCounter   = 0;
 188         u32                     OriginalValue, BitShift;
 189
 190 #if (DISABLE_BB_RF == 1)
 191         return;
 192 #endif
 193
 194         //RT_TRACE(COMP_RF, DBG_TRACE, ("--->PHY_SetBBReg(): RegAddr(%#lx), BitMask(%#lx), Data(%#lx)\n", RegAddr, BitMask, Data));
 195
 196         if(BitMask!= bMaskDWord){//if not "double word" write
 197                 OriginalValue = rtw_read32(Adapter, RegAddr);
 198                 BitShift = phy_CalculateBitShift(BitMask);
 199                 Data = ((OriginalValue & (~BitMask)) | ((Data << BitShift) & BitMask));
 200         }
 201
 202         rtw_write32(Adapter, RegAddr, Data);
 203
 204         //RTPRINT(FPHY, PHY_BBW, ("BBW MASK=0x%lx Addr[0x%lx]=0x%lx\n", BitMask, RegAddr, Data));
 205         //RT_TRACE(COMP_RF, DBG_TRACE, ("<---PHY_SetBBReg(): RegAddr(%#lx), BitMask(%#lx), Data(%#lx)\n", RegAddr, BitMask, Data));
 206
 207 }
 208
 209
 210 //
 211 // 2. RF register R/W API
 212 //
 213
 214 /*-----------------------------------------------------------------------------
 215  * Function:    phy_FwRFSerialRead()
 216  *
 217  * Overview:    We support firmware to execute RF-R/W.
 218  *
 219  * Input:               NONE
 220  *
 221  * Output:              NONE
 222  *
 223  * Return:              NONE
 224  *
 225  * Revised History:
 226  *      When            Who             Remark
 227  *      01/21/2008      MHC             Create Version 0.
 228  *
 229  *---------------------------------------------------------------------------*/
 230 static  u32
 231 phy_FwRFSerialRead(
 232         IN      PADAPTER                        Adapter,
 233         IN      RF_RADIO_PATH_E eRFPath,
 234         IN      u32                             Offset  )
 235 {
 236         u32             retValue = 0;
 237         //RT_ASSERT(FALSE,("deprecate!\n"));
 238         return  (retValue);
 239
 240 }       /* phy_FwRFSerialRead */
 241
 242
 243 /*-----------------------------------------------------------------------------
 244  * Function:    phy_FwRFSerialWrite()
 245  *
 246  * Overview:    We support firmware to execute RF-R/W.
 247  *
 248  * Input:               NONE
 249  *
 250  * Output:              NONE
 251  *
 252  * Return:              NONE
 253  *
 254  * Revised History:
 255  *      When            Who             Remark
 256  *      01/21/2008      MHC             Create Version 0.
 257  *
 258  *---------------------------------------------------------------------------*/
 259 static  VOID
 260 phy_FwRFSerialWrite(
 261         IN      PADAPTER                        Adapter,
 262         IN      RF_RADIO_PATH_E eRFPath,
 263         IN      u32                             Offset,
 264         IN      u32                             Data    )
 265 {
 266         //RT_ASSERT(FALSE,("deprecate!\n"));
 267 }
 268
 269
 270 /**
 271 * Function:     phy_RFSerialRead
 272 *
 273 * OverView:     Read regster from RF chips
 274 *
 275 * Input:
 276 *                       PADAPTER                Adapter,
 277 *                       RF_RADIO_PATH_E eRFPath,        //Radio path of A/B/C/D
 278 *                       u4Byte                  Offset,         //The target address to be read
 279 *
 280 * Output:       None
 281 * Return:               u4Byte                  reback value
 282 * Note:         Threre are three types of serial operations:
 283 *                       1. Software serial write
 284 *                       2. Hardware LSSI-Low Speed Serial Interface
 285 *                       3. Hardware HSSI-High speed
 286 *                       serial write. Driver need to implement (1) and (2).
 287 *                       This function is equal to the combination of RF_ReadReg() and  RFLSSIRead()
 288 */
 289 static  u32
 290 phy_RFSerialRead(
 291         IN      PADAPTER                        Adapter,
 292         IN      RF_RADIO_PATH_E eRFPath,
 293         IN      u32                             Offset
 294         )
 295 {
 296         u32                                             retValue = 0;
 297         HAL_DATA_TYPE                           *pHalData = GET_HAL_DATA(Adapter);
 298         BB_REGISTER_DEFINITION_T        *pPhyReg = &pHalData->PHYRegDef[eRFPath];
 299         u32                                             NewOffset;
 300         u32                                             tmplong,tmplong2;
 301         u8                                      RfPiEnable=0;
 302 #if 0
 303         if(pHalData->RFChipID == RF_8225 && Offset > 0x24) //36 valid regs
 304                 return  retValue;
 305         if(pHalData->RFChipID == RF_8256 && Offset > 0x2D) //45 valid regs
 306                 return  retValue;
 307 #endif
 308         //
 309         // Make sure RF register offset is correct
 310         //
 311         Offset &= 0x3f;
 312
 313         //
 314         // Switch page for 8256 RF IC
 315         //
 316         NewOffset = Offset;
 317
 318         // 2009/06/17 MH We can not execute IO for power save or other accident mode.
 319         //if(RT_CANNOT_IO(Adapter))
 320         //{
 321         //      RTPRINT(FPHY, PHY_RFR, ("phy_RFSerialRead return all one\n"));
 322         //      return  0xFFFFFFFF;
 323         //}
 324
 325         // For 92S LSSI Read RFLSSIRead
 326         // For RF A/B write 0x824/82c(does not work in the future)
 327         // We must use 0x824 for RF A and B to execute read trigger
 328         tmplong = PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter2, bMaskDWord);
 329         if(eRFPath == RF_PATH_A)
 330                 tmplong2 = tmplong;
 331         else
 332                 tmplong2 = PHY_QueryBBReg(Adapter, pPhyReg->rfHSSIPara2, bMaskDWord);
 333
 334         tmplong2 = (tmplong2 & (~bLSSIReadAddress)) | (NewOffset<<23) | bLSSIReadEdge;  //T65 RF
 335
 336         PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2, bMaskDWord, tmplong&(~bLSSIReadEdge));
 337         rtw_udelay_os(10);// PlatformStallExecution(10);
 338
 339         PHY_SetBBReg(Adapter, pPhyReg->rfHSSIPara2, bMaskDWord, tmplong2);
 340         rtw_udelay_os(100);//PlatformStallExecution(100);
 341
 342         PHY_SetBBReg(Adapter, rFPGA0_XA_HSSIParameter2, bMaskDWord, tmplong|bLSSIReadEdge);
 343         rtw_udelay_os(10);//PlatformStallExecution(10);
 344
 345         if(eRFPath == RF_PATH_A)
 346                 RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter1, BIT8);
 347         else if(eRFPath == RF_PATH_B)
 348                 RfPiEnable = (u8)PHY_QueryBBReg(Adapter, rFPGA0_XB_HSSIParameter1, BIT8);
 349
 350         if(RfPiEnable)
 351         {       // Read from BBreg8b8, 12 bits for 8190, 20bits for T65 RF
 352                 retValue = PHY_QueryBBReg(Adapter, pPhyReg->rfLSSIReadBackPi, bLSSIReadBackData);
 353                 //DBG_8192C("Readback from RF-PI : 0x%x\n", retValue);
 354         }
 355         else
 356         {       //Read from BBreg8a0, 12 bits for 8190, 20 bits for T65 RF
 357                 retValue = PHY_QueryBBReg(Adapter, pPhyReg->rfLSSIReadBack, bLSSIReadBackData);
 358                 //DBG_8192C("Readback from RF-SI : 0x%x\n", retValue);
 359         }
 360         //DBG_8192C("RFR-%d Addr[0x%x]=0x%x\n", eRFPath, pPhyReg->rfLSSIReadBack, retValue);
 361
 362         return retValue;
 363
 364 }
 365
 366
 367
 368 /**
 369 * Function:     phy_RFSerialWrite
 370 *
 371 * OverView:     Write data to RF register (page 8~)
 372 *
 373 * Input:
 374 *                       PADAPTER                Adapter,
 375 *                       RF_RADIO_PATH_E eRFPath,        //Radio path of A/B/C/D
 376 *                       u4Byte                  Offset,         //The target address to be read
 377 *                       u4Byte                  Data                    //The new register Data in the target bit position
 378 *                                                                               //of the target to be read
 379 *
 380 * Output:       None
 381 * Return:               None
 382 * Note:         Threre are three types of serial operations:
 383 *                       1. Software serial write
 384 *                       2. Hardware LSSI-Low Speed Serial Interface
 385 *                       3. Hardware HSSI-High speed
 386 *                       serial write. Driver need to implement (1) and (2).
 387 *                       This function is equal to the combination of RF_ReadReg() and  RFLSSIRead()
 388  *
 389  * Note:                  For RF8256 only
 390  *                       The total count of RTL8256(Zebra4) register is around 36 bit it only employs
 391  *                       4-bit RF address. RTL8256 uses "register mode control bit" (Reg00[12], Reg00[10])
 392  *                       to access register address bigger than 0xf. See "Appendix-4 in PHY Configuration
 393  *                       programming guide" for more details.
 394  *                       Thus, we define a sub-finction for RTL8526 register address conversion
 395  *                     ===========================================================
 396  *                       Register Mode          RegCTL[1]               RegCTL[0]               Note
 397  *                                                              (Reg00[12])             (Reg00[10])
 398  *                     ===========================================================
 399  *                       Reg_Mode0                              0                               x                       Reg 0 ~15(0x0 ~ 0xf)
 400  *                     ------------------------------------------------------------------
 401  *                       Reg_Mode1                              1                               0                       Reg 16 ~30(0x1 ~ 0xf)
 402  *                     ------------------------------------------------------------------
 403  *                       Reg_Mode2                              1                               1                       Reg 31 ~ 45(0x1 ~ 0xf)
 404  *                     ------------------------------------------------------------------
 405  *
 406  *      2008/09/02      MH      Add 92S RF definition
 407  *
 408  *
 409  *
 410 */
 411 static  VOID
 412 phy_RFSerialWrite(
 413         IN      PADAPTER                        Adapter,
 414         IN      RF_RADIO_PATH_E eRFPath,
 415         IN      u32                             Offset,
 416         IN      u32                             Data
 417         )
 418 {
 419         u32                                             DataAndAddr = 0;
 420         HAL_DATA_TYPE                           *pHalData = GET_HAL_DATA(Adapter);
 421         BB_REGISTER_DEFINITION_T        *pPhyReg = &pHalData->PHYRegDef[eRFPath];
 422         u32                                             NewOffset;
 423
 424 #if 0
 425         //<Roger_TODO> We should check valid regs for RF_6052 case.
 426         if(pHalData->RFChipID == RF_8225 && Offset > 0x24) //36 valid regs
 427                 return;
 428         if(pHalData->RFChipID == RF_8256 && Offset > 0x2D) //45 valid regs
 429                 return;
 430 #endif
 431
 432         // 2009/06/17 MH We can not execute IO for power save or other accident mode.
 433         //if(RT_CANNOT_IO(Adapter))
 434         //{
 435         //      RTPRINT(FPHY, PHY_RFW, ("phy_RFSerialWrite stop\n"));
 436         //      return;
 437         //}
 438
 439         Offset &= 0x3f;
 440
 441         //
 442         // Shadow Update
 443         //
 444         //PHY_RFShadowWrite(Adapter, eRFPath, Offset, Data);
 445
 446         //
 447         // Switch page for 8256 RF IC
 448         //
 449         NewOffset = Offset;
 450
 451         //
 452         // Put write addr in [5:0]  and write data in [31:16]
 453         //
 454         //DataAndAddr = (Data<<16) | (NewOffset&0x3f);
 455         DataAndAddr = ((NewOffset<<20) | (Data&0x000fffff)) & 0x0fffffff;       // T65 RF
 456
 457         //
 458         // Write Operation
 459         //
 460         PHY_SetBBReg(Adapter, pPhyReg->rf3wireOffset, bMaskDWord, DataAndAddr);
 461         //RTPRINT(FPHY, PHY_RFW, ("RFW-%d Addr[0x%lx]=0x%lx\n", eRFPath, pPhyReg->rf3wireOffset, DataAndAddr));
 462
 463 }
 464
 465
 466 /**
 467 * Function:     PHY_QueryRFReg
 468 *
 469 * OverView:     Query "Specific bits" to RF register (page 8~)
 470 *
 471 * Input:
 472 *                       PADAPTER                Adapter,
 473 *                       RF_RADIO_PATH_E eRFPath,        //Radio path of A/B/C/D
 474 *                       u4Byte                  RegAddr,                //The target address to be read
 475 *                       u4Byte                  BitMask         //The target bit position in the target address
 476 *                                                                               //to be read
 477 *
 478 * Output:       None
 479 * Return:               u4Byte                  Readback value
 480 * Note:         This function is equal to "GetRFRegSetting" in PHY programming guide
 481 */
 482 u32
 483 rtl8192c_PHY_QueryRFReg(
 484         IN      PADAPTER                        Adapter,
 485         IN      RF_RADIO_PATH_E eRFPath,
 486         IN      u32                             RegAddr,
 487         IN      u32                             BitMask
 488         )
 489 {
 490         u32 Original_Value, Readback_Value, BitShift;
 491         //HAL_DATA_TYPE         *pHalData = GET_HAL_DATA(Adapter);
 492         //u8    RFWaitCounter = 0;
 493         //_irqL irqL;
 494
 495 #if (DISABLE_BB_RF == 1)
 496         return 0;
 497 #endif
 498
 499         //RT_TRACE(COMP_RF, DBG_TRACE, ("--->PHY_QueryRFReg(): RegAddr(%#lx), eRFPath(%#x), BitMask(%#lx)\n", RegAddr, eRFPath,BitMask));
 500
 501 #ifdef CONFIG_USB_HCI
 502         //PlatformAcquireMutex(&pHalData->mxRFOperate);
 503 #else
 504         //_enter_critical(&pHalData->rf_lock, &irqL);
 505 #endif
 506
 507
 508         Original_Value = phy_RFSerialRead(Adapter, eRFPath, RegAddr);
 509
 510         BitShift =  phy_CalculateBitShift(BitMask);
 511         Readback_Value = (Original_Value & BitMask) >> BitShift;
 512
 513 #ifdef CONFIG_USB_HCI
 514         //PlatformReleaseMutex(&pHalData->mxRFOperate);
 515 #else
 516         //_exit_critical(&pHalData->rf_lock, &irqL);
 517 #endif
 518
 519
 520         //RTPRINT(FPHY, PHY_RFR, ("RFR-%d MASK=0x%lx Addr[0x%lx]=0x%lx\n", eRFPath, BitMask, RegAddr, Original_Value));//BitMask(%#lx),BitMask,
 521         //RT_TRACE(COMP_RF, DBG_TRACE, ("<---PHY_QueryRFReg(): RegAddr(%#lx), eRFPath(%#x),  Original_Value(%#lx)\n",
 522         //                              RegAddr, eRFPath, Original_Value));
 523
 524         return (Readback_Value);
 525 }
 526
 527 /**
 528 * Function:     PHY_SetRFReg
 529 *
 530 * OverView:     Write "Specific bits" to RF register (page 8~)
 531 *
 532 * Input:
 533 *                       PADAPTER                Adapter,
 534 *                       RF_RADIO_PATH_E eRFPath,        //Radio path of A/B/C/D
 535 *                       u4Byte                  RegAddr,                //The target address to be modified
 536 *                       u4Byte                  BitMask         //The target bit position in the target address
 537 *                                                                               //to be modified
 538 *                       u4Byte                  Data                    //The new register Data in the target bit position
 539 *                                                                               //of the target address
 540 *
 541 * Output:       None
 542 * Return:               None
 543 * Note:         This function is equal to "PutRFRegSetting" in PHY programming guide
 544 */
 545 VOID
 546 rtl8192c_PHY_SetRFReg(
 547         IN      PADAPTER                        Adapter,
 548         IN      RF_RADIO_PATH_E eRFPath,
 549         IN      u32                             RegAddr,
 550         IN      u32                             BitMask,
 551         IN      u32                             Data
 552         )
 553 {
 554
 555         //HAL_DATA_TYPE *pHalData               = GET_HAL_DATA(Adapter);
 556         //u1Byte                        RFWaitCounter   = 0;
 557         u32             Original_Value, BitShift;
 558         //_irqL irqL;
 559
 560 #if (DISABLE_BB_RF == 1)
 561         return;
 562 #endif
 563
 564         //RT_TRACE(COMP_RF, DBG_TRACE, ("--->PHY_SetRFReg(): RegAddr(%#lx), BitMask(%#lx), Data(%#lx), eRFPath(%#x)\n",
 565         //      RegAddr, BitMask, Data, eRFPath));
 566         //RTPRINT(FINIT, INIT_RF, ("PHY_SetRFReg(): RegAddr(%#lx), BitMask(%#lx), Data(%#lx), eRFPath(%#x)\n",
 567         //      RegAddr, BitMask, Data, eRFPath));
 568
 569
 570 #ifdef CONFIG_USB_HCI
 571         //PlatformAcquireMutex(&pHalData->mxRFOperate);
 572 #else
 573         //_enter_critical(&pHalData->rf_lock, &irqL);
 574 #endif
 575
 576
 577         // RF data is 12 bits only
 578         if (BitMask != bRFRegOffsetMask)
 579         {
 580                 Original_Value = phy_RFSerialRead(Adapter, eRFPath, RegAddr);
 581                 BitShift =  phy_CalculateBitShift(BitMask);
 582                 Data = ((Original_Value & (~BitMask)) | (Data<< BitShift));
 583         }
 584
 585         phy_RFSerialWrite(Adapter, eRFPath, RegAddr, Data);
 586
 587
 588
 589 #ifdef CONFIG_USB_HCI
 590         //PlatformReleaseMutex(&pHalData->mxRFOperate);
 591 #else
 592         //_exit_critical(&pHalData->rf_lock, &irqL);
 593 #endif
 594
 595         //PHY_QueryRFReg(Adapter,eRFPath,RegAddr,BitMask);
 596         //RT_TRACE(COMP_RF, DBG_TRACE, ("<---PHY_SetRFReg(): RegAddr(%#lx), BitMask(%#lx), Data(%#lx), eRFPath(%#x)\n",
 597         //              RegAddr, BitMask, Data, eRFPath));
 598
 599 }
 600
 601
 602 //
 603 // 3. Initial MAC/BB/RF config by reading MAC/BB/RF txt.
 604 //
 605
 606 /*-----------------------------------------------------------------------------
 607  * Function:    phy_ConfigMACWithParaFile()
 608  *
 609  * Overview:    This function read BB parameters from general file format, and do register
 610  *                        Read/Write
 611  *
 612  * Input:       PADAPTER                Adapter
 613  *                      ps1Byte                         pFileName
 614  *
 615  * Output:      NONE
 616  *
 617  * Return:      RT_STATUS_SUCCESS: configuration file exist
 618  *
 619  * Note:                The format of MACPHY_REG.txt is different from PHY and RF.
 620  *                      [Register][Mask][Value]
 621  *---------------------------------------------------------------------------*/
 622 static  int
 623 phy_ConfigMACWithParaFile(
 624         IN      PADAPTER                Adapter,
 625         IN      u8*                     pFileName
 626 )
 627 {
 628         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
 629
 630         int             rtStatus = _SUCCESS;
 631
 632         return rtStatus;
 633 }
 634
 635 /*-----------------------------------------------------------------------------
 636  * Function:    phy_ConfigMACWithHeaderFile()
 637  *
 638  * Overview:    This function read BB parameters from Header file we gen, and do register
 639  *                        Read/Write
 640  *
 641  * Input:       PADAPTER                Adapter
 642  *                      ps1Byte                         pFileName
 643  *
 644  * Output:      NONE
 645  *
 646  * Return:      RT_STATUS_SUCCESS: configuration file exist
 647  *
 648  * Note:                The format of MACPHY_REG.txt is different from PHY and RF.
 649  *                      [Register][Mask][Value]
 650  *---------------------------------------------------------------------------*/
 651 static  int
 652 phy_ConfigMACWithHeaderFile(
 653         IN      PADAPTER                Adapter
 654 )
 655 {
 656         u32                                     i = 0;
 657         u32                                     ArrayLength = 0;
 658         u32*                            ptrArray;
 659         //HAL_DATA_TYPE                 *pHalData = GET_HAL_DATA(Adapter);
 660
 661         //2008.11.06 Modified by tynli.
 662         //RT_TRACE(COMP_INIT, DBG_LOUD, ("Read Rtl819XMACPHY_Array\n"));
 663         ArrayLength = MAC_2T_ArrayLength;
 664         ptrArray = Rtl819XMAC_Array;
 665
 666 #ifdef CONFIG_IOL_MAC
 667         if(rtw_IOL_applied(Adapter))
 668         {
 669                 struct xmit_frame       *xmit_frame;
 670                 if((xmit_frame=rtw_IOL_accquire_xmit_frame(Adapter)) == NULL)
 671                         return _FAIL;
 672
 673                 for(i = 0 ;i < ArrayLength;i=i+2){ // Add by tynli for 2 column
 674                         rtw_IOL_append_WB_cmd(xmit_frame, ptrArray[i], (u8)ptrArray[i+1]);
 675                 }
 676
 677                 return rtw_IOL_exec_cmds_sync(Adapter, xmit_frame, 1000);
 678         }
 679         else
 680 #endif
 681         {
 682                 for(i = 0 ;i < ArrayLength;i=i+2){ // Add by tynli for 2 column
 683                         rtw_write8(Adapter, ptrArray[i], (u8)ptrArray[i+1]);
 684                 }
 685         }
 686
 687         return _SUCCESS;
 688
 689 }
 690
 691
 692 /*-----------------------------------------------------------------------------
 693  * Function:    PHY_MACConfig8192C
 694  *
 695  * Overview:    Condig MAC by header file or parameter file.
 696  *
 697  * Input:       NONE
 698  *
 699  * Output:      NONE
 700  *
 701  * Return:      NONE
 702  *
 703  * Revised History:
 704  *  When                Who             Remark
 705  *  08/12/2008  MHC             Create Version 0.
 706  *
 707  *---------------------------------------------------------------------------*/
 708 int
 709 PHY_MACConfig8192C(
 710         IN      PADAPTER        Adapter
 711         )
 712 {
 713         int             rtStatus = _SUCCESS;
 714         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
 715         s8                      *pszMACRegFile;
 716         s8                      sz88CMACRegFile[] = RTL8188C_PHY_MACREG;
 717         s8                      sz92CMACRegFile[] = RTL8192C_PHY_MACREG;
 718         BOOLEAN         is92C = IS_92C_SERIAL(pHalData->VersionID);
 719
 720         if(is92C)
 721                 pszMACRegFile = sz92CMACRegFile;
 722         else
 723                 pszMACRegFile = sz88CMACRegFile;
 724
 725         //
 726         // Config MAC
 727         //
 728 #ifdef CONFIG_EMBEDDED_FWIMG
 729         rtStatus = phy_ConfigMACWithHeaderFile(Adapter);
 730 #else
 731
 732         // Not make sure EEPROM, add later
 733         //RT_TRACE(COMP_INIT, DBG_LOUD, ("Read MACREG.txt\n"));
 734         rtStatus = phy_ConfigMACWithParaFile(Adapter, pszMACRegFile);
 735 #endif
 736
 737 #ifdef CONFIG_PCI_HCI
 738         //this switching setting cause some 8192cu hw have redownload fw fail issue
 739         //improve 2-stream TX EVM by Jenyu
 740         if(is92C)
 741                 rtw_write8(Adapter, REG_SPS0_CTRL+3,0x71);
 742 #endif
 743
 744
 745         // 2010.07.13 AMPDU aggregation number 9
 746         //rtw_write16(Adapter, REG_MAX_AGGR_NUM, MAX_AGGR_NUM);
 747         rtw_write8(Adapter, REG_MAX_AGGR_NUM, 0x0A); //By tynli. 2010.11.18.
 748 #ifdef CONFIG_USB_HCI
 749         if(is92C && (BOARD_USB_DONGLE == pHalData->BoardType))
 750                 rtw_write8(Adapter, 0x40,0x04);
 751 #endif
 752
 753         return rtStatus;
 754
 755 }
 756
 757
 758 /**
 759 * Function:     phy_InitBBRFRegisterDefinition
 760 *
 761 * OverView:     Initialize Register definition offset for Radio Path A/B/C/D
 762 *
 763 * Input:
 764 *                       PADAPTER                Adapter,
 765 *
 766 * Output:       None
 767 * Return:               None
 768 * Note:         The initialization value is constant and it should never be changes
 769 */
 770 static  VOID
 771 phy_InitBBRFRegisterDefinition(
 772         IN      PADAPTER                Adapter
 773 )
 774 {
 775         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(Adapter);
 776
 777         // RF Interface Sowrtware Control
 778         pHalData->PHYRegDef[RF_PATH_A].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 LSBs if read 32-bit from 0x870
 779         pHalData->PHYRegDef[RF_PATH_B].rfintfs = rFPGA0_XAB_RFInterfaceSW; // 16 MSBs if read 32-bit from 0x870 (16-bit for 0x872)
 780         pHalData->PHYRegDef[RF_PATH_C].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 LSBs if read 32-bit from 0x874
 781         pHalData->PHYRegDef[RF_PATH_D].rfintfs = rFPGA0_XCD_RFInterfaceSW;// 16 MSBs if read 32-bit from 0x874 (16-bit for 0x876)
 782
 783         // RF Interface Readback Value
 784         pHalData->PHYRegDef[RF_PATH_A].rfintfi = rFPGA0_XAB_RFInterfaceRB; // 16 LSBs if read 32-bit from 0x8E0
 785         pHalData->PHYRegDef[RF_PATH_B].rfintfi = rFPGA0_XAB_RFInterfaceRB;// 16 MSBs if read 32-bit from 0x8E0 (16-bit for 0x8E2)
 786         pHalData->PHYRegDef[RF_PATH_C].rfintfi = rFPGA0_XCD_RFInterfaceRB;// 16 LSBs if read 32-bit from 0x8E4
 787         pHalData->PHYRegDef[RF_PATH_D].rfintfi = rFPGA0_XCD_RFInterfaceRB;// 16 MSBs if read 32-bit from 0x8E4 (16-bit for 0x8E6)
 788
 789         // RF Interface Output (and Enable)
 790         pHalData->PHYRegDef[RF_PATH_A].rfintfo = rFPGA0_XA_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x860
 791         pHalData->PHYRegDef[RF_PATH_B].rfintfo = rFPGA0_XB_RFInterfaceOE; // 16 LSBs if read 32-bit from 0x864
 792
 793         // RF Interface (Output and)  Enable
 794         pHalData->PHYRegDef[RF_PATH_A].rfintfe = rFPGA0_XA_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x860 (16-bit for 0x862)
 795         pHalData->PHYRegDef[RF_PATH_B].rfintfe = rFPGA0_XB_RFInterfaceOE; // 16 MSBs if read 32-bit from 0x864 (16-bit for 0x866)
 796
 797         //Addr of LSSI. Wirte RF register by driver
 798         pHalData->PHYRegDef[RF_PATH_A].rf3wireOffset = rFPGA0_XA_LSSIParameter; //LSSI Parameter
 799         pHalData->PHYRegDef[RF_PATH_B].rf3wireOffset = rFPGA0_XB_LSSIParameter;
 800
 801         // RF parameter
 802         pHalData->PHYRegDef[RF_PATH_A].rfLSSI_Select = rFPGA0_XAB_RFParameter;  //BB Band Select
 803         pHalData->PHYRegDef[RF_PATH_B].rfLSSI_Select = rFPGA0_XAB_RFParameter;
 804         pHalData->PHYRegDef[RF_PATH_C].rfLSSI_Select = rFPGA0_XCD_RFParameter;
 805         pHalData->PHYRegDef[RF_PATH_D].rfLSSI_Select = rFPGA0_XCD_RFParameter;
 806
 807         // Tx AGC Gain Stage (same for all path. Should we remove this?)
 808         pHalData->PHYRegDef[RF_PATH_A].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
 809         pHalData->PHYRegDef[RF_PATH_B].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
 810         pHalData->PHYRegDef[RF_PATH_C].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
 811         pHalData->PHYRegDef[RF_PATH_D].rfTxGainStage = rFPGA0_TxGainStage; //Tx gain stage
 812
 813         // Tranceiver A~D HSSI Parameter-1
 814         pHalData->PHYRegDef[RF_PATH_A].rfHSSIPara1 = rFPGA0_XA_HSSIParameter1;  //wire control parameter1
 815         pHalData->PHYRegDef[RF_PATH_B].rfHSSIPara1 = rFPGA0_XB_HSSIParameter1;  //wire control parameter1
 816
 817         // Tranceiver A~D HSSI Parameter-2
 818         pHalData->PHYRegDef[RF_PATH_A].rfHSSIPara2 = rFPGA0_XA_HSSIParameter2;  //wire control parameter2
 819         pHalData->PHYRegDef[RF_PATH_B].rfHSSIPara2 = rFPGA0_XB_HSSIParameter2;  //wire control parameter2
 820
 821         // RF switch Control
 822         pHalData->PHYRegDef[RF_PATH_A].rfSwitchControl = rFPGA0_XAB_SwitchControl; //TR/Ant switch control
 823         pHalData->PHYRegDef[RF_PATH_B].rfSwitchControl = rFPGA0_XAB_SwitchControl;
 824         pHalData->PHYRegDef[RF_PATH_C].rfSwitchControl = rFPGA0_XCD_SwitchControl;
 825         pHalData->PHYRegDef[RF_PATH_D].rfSwitchControl = rFPGA0_XCD_SwitchControl;
 826
 827         // AGC control 1
 828         pHalData->PHYRegDef[RF_PATH_A].rfAGCControl1 = rOFDM0_XAAGCCore1;
 829         pHalData->PHYRegDef[RF_PATH_B].rfAGCControl1 = rOFDM0_XBAGCCore1;
 830         pHalData->PHYRegDef[RF_PATH_C].rfAGCControl1 = rOFDM0_XCAGCCore1;
 831         pHalData->PHYRegDef[RF_PATH_D].rfAGCControl1 = rOFDM0_XDAGCCore1;
 832
 833         // AGC control 2
 834         pHalData->PHYRegDef[RF_PATH_A].rfAGCControl2 = rOFDM0_XAAGCCore2;
 835         pHalData->PHYRegDef[RF_PATH_B].rfAGCControl2 = rOFDM0_XBAGCCore2;
 836         pHalData->PHYRegDef[RF_PATH_C].rfAGCControl2 = rOFDM0_XCAGCCore2;
 837         pHalData->PHYRegDef[RF_PATH_D].rfAGCControl2 = rOFDM0_XDAGCCore2;
 838
 839         // RX AFE control 1
 840         pHalData->PHYRegDef[RF_PATH_A].rfRxIQImbalance = rOFDM0_XARxIQImbalance;
 841         pHalData->PHYRegDef[RF_PATH_B].rfRxIQImbalance = rOFDM0_XBRxIQImbalance;
 842         pHalData->PHYRegDef[RF_PATH_C].rfRxIQImbalance = rOFDM0_XCRxIQImbalance;
 843         pHalData->PHYRegDef[RF_PATH_D].rfRxIQImbalance = rOFDM0_XDRxIQImbalance;
 844
 845         // RX AFE control 1
 846         pHalData->PHYRegDef[RF_PATH_A].rfRxAFE = rOFDM0_XARxAFE;
 847         pHalData->PHYRegDef[RF_PATH_B].rfRxAFE = rOFDM0_XBRxAFE;
 848         pHalData->PHYRegDef[RF_PATH_C].rfRxAFE = rOFDM0_XCRxAFE;
 849         pHalData->PHYRegDef[RF_PATH_D].rfRxAFE = rOFDM0_XDRxAFE;
 850
 851         // Tx AFE control 1
 852         pHalData->PHYRegDef[RF_PATH_A].rfTxIQImbalance = rOFDM0_XATxIQImbalance;
 853         pHalData->PHYRegDef[RF_PATH_B].rfTxIQImbalance = rOFDM0_XBTxIQImbalance;
 854         pHalData->PHYRegDef[RF_PATH_C].rfTxIQImbalance = rOFDM0_XCTxIQImbalance;
 855         pHalData->PHYRegDef[RF_PATH_D].rfTxIQImbalance = rOFDM0_XDTxIQImbalance;
 856
 857         // Tx AFE control 2
 858         pHalData->PHYRegDef[RF_PATH_A].rfTxAFE = rOFDM0_XATxAFE;
 859         pHalData->PHYRegDef[RF_PATH_B].rfTxAFE = rOFDM0_XBTxAFE;
 860         pHalData->PHYRegDef[RF_PATH_C].rfTxAFE = rOFDM0_XCTxAFE;
 861         pHalData->PHYRegDef[RF_PATH_D].rfTxAFE = rOFDM0_XDTxAFE;
 862
 863         // Tranceiver LSSI Readback SI mode
 864         pHalData->PHYRegDef[RF_PATH_A].rfLSSIReadBack = rFPGA0_XA_LSSIReadBack;
 865         pHalData->PHYRegDef[RF_PATH_B].rfLSSIReadBack = rFPGA0_XB_LSSIReadBack;
 866         pHalData->PHYRegDef[RF_PATH_C].rfLSSIReadBack = rFPGA0_XC_LSSIReadBack;
 867         pHalData->PHYRegDef[RF_PATH_D].rfLSSIReadBack = rFPGA0_XD_LSSIReadBack;
 868
 869         // Tranceiver LSSI Readback PI mode
 870         pHalData->PHYRegDef[RF_PATH_A].rfLSSIReadBackPi = TransceiverA_HSPI_Readback;
 871         pHalData->PHYRegDef[RF_PATH_B].rfLSSIReadBackPi = TransceiverB_HSPI_Readback;
 872         //pHalData->PHYRegDef[RF_PATH_C].rfLSSIReadBackPi = rFPGA0_XC_LSSIReadBack;
 873         //pHalData->PHYRegDef[RF_PATH_D].rfLSSIReadBackPi = rFPGA0_XD_LSSIReadBack;
 874
 875 }
 876
 877
 878 /*-----------------------------------------------------------------------------
 879  * Function:    phy_ConfigBBWithParaFile()
 880  *
 881  * Overview:    This function read BB parameters from general file format, and do register
 882  *                        Read/Write
 883  *
 884  * Input:       PADAPTER                Adapter
 885  *                      ps1Byte                         pFileName
 886  *
 887  * Output:      NONE
 888  *
 889  * Return:      RT_STATUS_SUCCESS: configuration file exist
 890  *      2008/11/06      MH      For 92S we do not support silent reset now. Disable
 891  *                                      parameter file compare!!!!!!??
 892  *
 893  *---------------------------------------------------------------------------*/
 894 static  int
 895 phy_ConfigBBWithParaFile(
 896         IN      PADAPTER                Adapter,
 897         IN      u8*                     pFileName
 898 )
 899 {
 900         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
 901
 902         int             rtStatus = _SUCCESS;
 903
 904         return rtStatus;
 905 }
 906
 907
 908
 909 //****************************************
 910 // The following is for High Power PA
 911 //****************************************
 912 VOID
 913 phy_ConfigBBExternalPA(
 914         IN      PADAPTER                        Adapter
 915 )
 916 {
 917 #ifdef CONFIG_USB_HCI
 918         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
 919         u16 i=0;
 920         u32 temp=0;
 921
 922         if(!pHalData->ExternalPA)
 923         {
 924                 return;
 925         }
 926
 927         // 2010/10/19 MH According to Jenyu/EEChou 's opinion, we need not to execute the
 928         // same code as SU. It is already updated in PHY_REG_1T_HP.txt.
 929 #if 0
 930         PHY_SetBBReg(Adapter, 0xee8, BIT28, 1);
 931         temp = PHY_QueryBBReg(Adapter, 0x860, bMaskDWord);
 932         temp |= (BIT26|BIT21|BIT10|BIT5);
 933         PHY_SetBBReg(Adapter, 0x860, bMaskDWord, temp);
 934         PHY_SetBBReg(Adapter, 0x870, BIT10, 0);
 935         PHY_SetBBReg(Adapter, 0xc80, bMaskDWord, 0x20000080);
 936         PHY_SetBBReg(Adapter, 0xc88, bMaskDWord, 0x40000100);
 937 #endif
 938
 939 #endif
 940 }
 941
 942 /*-----------------------------------------------------------------------------
 943  * Function:    phy_ConfigBBWithHeaderFile()
 944  *
 945  * Overview:    This function read BB parameters from general file format, and do register
 946  *                        Read/Write
 947  *
 948  * Input:       PADAPTER                Adapter
 949  *                      u1Byte                  ConfigType     0 => PHY_CONFIG
 950  *                                                                               1 =>AGC_TAB
 951  *
 952  * Output:      NONE
 953  *
 954  * Return:      RT_STATUS_SUCCESS: configuration file exist
 955  *
 956  *---------------------------------------------------------------------------*/
 957 static  int
 958 phy_ConfigBBWithHeaderFile(
 959         IN      PADAPTER                Adapter,
 960         IN      u8                      ConfigType
 961 )
 962 {
 963         int i;
 964         u32*    Rtl819XPHY_REGArray_Table;
 965         u32*    Rtl819XAGCTAB_Array_Table;
 966         u16     PHY_REGArrayLen, AGCTAB_ArrayLen;
 967         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
 968         int ret = _SUCCESS;
 969
 970         //
 971         // 2009.11.24. Modified by tynli.
 972         //
 973         if(IS_92C_SERIAL(pHalData->VersionID))
 974         {
 975                 AGCTAB_ArrayLen = AGCTAB_2TArrayLength;
 976                 Rtl819XAGCTAB_Array_Table = Rtl819XAGCTAB_2TArray;
 977                 PHY_REGArrayLen = PHY_REG_2TArrayLength;
 978                 Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_2TArray;
 979 #ifdef CONFIG_USB_HCI
 980                 if(pHalData->BoardType == BOARD_MINICARD )
 981                 {
 982                         PHY_REGArrayLen = PHY_REG_2T_mCardArrayLength;
 983                         Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_2T_mCardArray;
 984                 }
 985 #endif
 986         }
 987         else
 988         {
 989                 AGCTAB_ArrayLen = AGCTAB_1TArrayLength;
 990                 Rtl819XAGCTAB_Array_Table = Rtl819XAGCTAB_1TArray;
 991                 PHY_REGArrayLen = PHY_REG_1TArrayLength;
 992                 Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_1TArray;
 993 #ifdef CONFIG_USB_HCI
 994                 if(pHalData->BoardType == BOARD_MINICARD )
 995                 {
 996                         PHY_REGArrayLen = PHY_REG_1T_mCardArrayLength;
 997                         Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_1T_mCardArray;
 998                 }
 999                 else if(pHalData->BoardType == BOARD_USB_High_PA)
1000                 {
1001                         AGCTAB_ArrayLen = AGCTAB_1T_HPArrayLength;
1002                         Rtl819XAGCTAB_Array_Table = Rtl819XAGCTAB_1T_HPArray;
1003                         PHY_REGArrayLen = PHY_REG_1T_HPArrayLength;
1004                         Rtl819XPHY_REGArray_Table = Rtl819XPHY_REG_1T_HPArray;
1005                 }
1006 #endif
1007         }
1008
1009         if(ConfigType == BaseBand_Config_PHY_REG)
1010         {
1011                 #ifdef CONFIG_IOL_BB_PHY_REG
1012                 if(rtw_IOL_applied(Adapter))
1013                 {
1014                         struct xmit_frame       *xmit_frame;
1015                         u32 tmp_value;
1016
1017                         if((xmit_frame=rtw_IOL_accquire_xmit_frame(Adapter)) == NULL) {
1018                                 ret = _FAIL;
1019                                 goto exit;
1020                         }
1021
1022                         for(i=0;i<PHY_REGArrayLen;i=i+2)
1023                         {
1024                                 tmp_value=Rtl819XPHY_REGArray_Table[i+1];
1025
1026                                 if (Rtl819XPHY_REGArray_Table[i] == 0xfe)
1027                                         rtw_IOL_append_DELAY_MS_cmd(xmit_frame, 50);
1028                                 else if (Rtl819XPHY_REGArray_Table[i] == 0xfd)
1029                                         rtw_IOL_append_DELAY_MS_cmd(xmit_frame, 5);
1030                                 else if (Rtl819XPHY_REGArray_Table[i] == 0xfc)
1031                                         rtw_IOL_append_DELAY_MS_cmd(xmit_frame, 1);
1032                                 else if (Rtl819XPHY_REGArray_Table[i] == 0xfb)
1033                                         rtw_IOL_append_DELAY_US_cmd(xmit_frame, 50);
1034                                 else if (Rtl819XPHY_REGArray_Table[i] == 0xfa)
1035                                         rtw_IOL_append_DELAY_US_cmd(xmit_frame, 5);
1036                                 else if (Rtl819XPHY_REGArray_Table[i] == 0xf9)
1037                                         rtw_IOL_append_DELAY_US_cmd(xmit_frame, 1);
1038
1039                                 rtw_IOL_append_WD_cmd(xmit_frame, Rtl819XPHY_REGArray_Table[i], tmp_value);
1040                                 //RT_TRACE(COMP_INIT, DBG_TRACE, ("The Rtl819XPHY_REGArray_Table[0] is %lx Rtl819XPHY_REGArray[1] is %lx \n",Rtl819XPHY_REGArray_Table[i], Rtl819XPHY_REGArray_Table[i+1]));
1041                         }
1042
1043                         ret = rtw_IOL_exec_cmds_sync(Adapter, xmit_frame, 1000);
1044                 }
1045                 else
1046                 #endif
1047                 {
1048                         for(i=0;i<PHY_REGArrayLen;i=i+2)
1049                         {
1050                                 if (Rtl819XPHY_REGArray_Table[i] == 0xfe){
1051                                         #ifdef CONFIG_LONG_DELAY_ISSUE
1052                                         rtw_msleep_os(50);
1053                                         #else
1054                                         rtw_mdelay_os(50);
1055                                         #endif
1056                                 }
1057                                 else if (Rtl819XPHY_REGArray_Table[i] == 0xfd)
1058                                         rtw_mdelay_os(5);
1059                                 else if (Rtl819XPHY_REGArray_Table[i] == 0xfc)
1060                                         rtw_mdelay_os(1);
1061                                 else if (Rtl819XPHY_REGArray_Table[i] == 0xfb)
1062                                         rtw_udelay_os(50);
1063                                 else if (Rtl819XPHY_REGArray_Table[i] == 0xfa)
1064                                         rtw_udelay_os(5);
1065                                 else if (Rtl819XPHY_REGArray_Table[i] == 0xf9)
1066                                         rtw_udelay_os(1);
1067
1068                                 PHY_SetBBReg(Adapter, Rtl819XPHY_REGArray_Table[i], bMaskDWord, Rtl819XPHY_REGArray_Table[i+1]);
1069
1070                                 // Add 1us delay between BB/RF register setting.
1071                                 rtw_udelay_os(1);
1072
1073                                 //RT_TRACE(COMP_INIT, DBG_TRACE, ("The Rtl819XPHY_REGArray_Table[0] is %lx Rtl819XPHY_REGArray[1] is %lx \n",Rtl819XPHY_REGArray_Table[i], Rtl819XPHY_REGArray_Table[i+1]));
1074                         }
1075                 }
1076
1077                 // for External PA
1078                 phy_ConfigBBExternalPA(Adapter);
1079         }
1080         else if(ConfigType == BaseBand_Config_AGC_TAB)
1081         {
1082                 #ifdef CONFIG_IOL_BB_AGC_TAB
1083                 if(rtw_IOL_applied(Adapter))
1084                 {
1085                         struct xmit_frame       *xmit_frame;
1086
1087                         if((xmit_frame=rtw_IOL_accquire_xmit_frame(Adapter)) == NULL) {
1088                                 ret = _FAIL;
1089                                 goto exit;
1090                         }
1091
1092                         for(i=0;i<AGCTAB_ArrayLen;i=i+2)
1093                         {
1094                                 rtw_IOL_append_WD_cmd(xmit_frame, Rtl819XAGCTAB_Array_Table[i], Rtl819XAGCTAB_Array_Table[i+1]);
1095                                 //RT_TRACE(COMP_INIT, DBG_TRACE, ("The Rtl819XAGCTAB_Array_Table[0] is %lx Rtl819XPHY_REGArray[1] is %lx \n",Rtl819XAGCTAB_Array_Table[i], Rtl819XAGCTAB_Array_Table[i+1]));
1096                         }
1097
1098                         ret = rtw_IOL_exec_cmds_sync(Adapter, xmit_frame, 1000);
1099                 }
1100                 else
1101                 #endif
1102                 {
1103                         for(i=0;i<AGCTAB_ArrayLen;i=i+2)
1104                         {
1105                                 PHY_SetBBReg(Adapter, Rtl819XAGCTAB_Array_Table[i], bMaskDWord, Rtl819XAGCTAB_Array_Table[i+1]);
1106
1107                                 // Add 1us delay between BB/RF register setting.
1108                                 rtw_udelay_os(1);
1109
1110                                 //RT_TRACE(COMP_INIT, DBG_TRACE, ("The Rtl819XAGCTAB_Array_Table[0] is %lx Rtl819XPHY_REGArray[1] is %lx \n",Rtl819XAGCTAB_Array_Table[i], Rtl819XAGCTAB_Array_Table[i+1]));
1111                         }
1112                 }
1113         }
1114
1115 exit:
1116         return ret;
1117
1118 }
1119
1120
1121 VOID
1122 storePwrIndexDiffRateOffset(
1123         IN      PADAPTER        Adapter,
1124         IN      u32             RegAddr,
1125         IN      u32             BitMask,
1126         IN      u32             Data
1127         )
1128 {
1129         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
1130
1131         if(RegAddr == rTxAGC_A_Rate18_06)
1132         {
1133                 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][0] = Data;
1134                 //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][0] = 0x%lx\n", pHalData->pwrGroupCnt,
1135                 //      pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][0]));
1136         }
1137         if(RegAddr == rTxAGC_A_Rate54_24)
1138         {
1139                 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][1] = Data;
1140                 //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][1] = 0x%lx\n", pHalData->pwrGroupCnt,
1141                 //      pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][1]));
1142         }
1143         if(RegAddr == rTxAGC_A_CCK1_Mcs32)
1144         {
1145                 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][6] = Data;
1146                 //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][6] = 0x%lx\n", pHalData->pwrGroupCnt,
1147                 //      pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][6]));
1148         }
1149         if(RegAddr == rTxAGC_B_CCK11_A_CCK2_11 && BitMask == 0xffffff00)
1150         {
1151                 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][7] = Data;
1152                 //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][7] = 0x%lx\n", pHalData->pwrGroupCnt,
1153                 //      pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][7]));
1154         }
1155         if(RegAddr == rTxAGC_A_Mcs03_Mcs00)
1156         {
1157                 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][2] = Data;
1158                 //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][2] = 0x%lx\n", pHalData->pwrGroupCnt,
1159                 //      pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][2]));
1160         }
1161         if(RegAddr == rTxAGC_A_Mcs07_Mcs04)
1162         {
1163                 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][3] = Data;
1164                 //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][3] = 0x%lx\n", pHalData->pwrGroupCnt,
1165                 //      pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][3]));
1166         }
1167         if(RegAddr == rTxAGC_A_Mcs11_Mcs08)
1168         {
1169                 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][4] = Data;
1170                 //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][4] = 0x%lx\n", pHalData->pwrGroupCnt,
1171                 //      pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][4]));
1172         }
1173         if(RegAddr == rTxAGC_A_Mcs15_Mcs12)
1174         {
1175                 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][5] = Data;
1176                 //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][5] = 0x%lx\n", pHalData->pwrGroupCnt,
1177                 //      pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][5]));
1178         }
1179         if(RegAddr == rTxAGC_B_Rate18_06)
1180         {
1181                 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][8] = Data;
1182                 //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][8] = 0x%lx\n", pHalData->pwrGroupCnt,
1183                 //      pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][8]));
1184         }
1185         if(RegAddr == rTxAGC_B_Rate54_24)
1186         {
1187                 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][9] = Data;
1188                 //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][9] = 0x%lx\n", pHalData->pwrGroupCnt,
1189                 //      pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][9]));
1190         }
1191         if(RegAddr == rTxAGC_B_CCK1_55_Mcs32)
1192         {
1193                 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][14] = Data;
1194                 //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][14] = 0x%lx\n", pHalData->pwrGroupCnt,
1195                 //      pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][14]));
1196         }
1197         if(RegAddr == rTxAGC_B_CCK11_A_CCK2_11 && BitMask == 0x000000ff)
1198         {
1199                 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][15] = Data;
1200                 //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][15] = 0x%lx\n", pHalData->pwrGroupCnt,
1201                 //      pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][15]));
1202         }
1203         if(RegAddr == rTxAGC_B_Mcs03_Mcs00)
1204         {
1205                 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][10] = Data;
1206                 //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][10] = 0x%lx\n", pHalData->pwrGroupCnt,
1207                 //      pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][10]));
1208         }
1209         if(RegAddr == rTxAGC_B_Mcs07_Mcs04)
1210         {
1211                 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][11] = Data;
1212                 //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][11] = 0x%lx\n", pHalData->pwrGroupCnt,
1213                 //      pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][11]));
1214         }
1215         if(RegAddr == rTxAGC_B_Mcs11_Mcs08)
1216         {
1217                 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][12] = Data;
1218                 //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][12] = 0x%lx\n", pHalData->pwrGroupCnt,
1219                 //      pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][12]));
1220         }
1221         if(RegAddr == rTxAGC_B_Mcs15_Mcs12)
1222         {
1223                 pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][13] = Data;
1224                 //RT_TRACE(COMP_INIT, DBG_TRACE, ("MCSTxPowerLevelOriginalOffset[%d][13] = 0x%lx\n", pHalData->pwrGroupCnt,
1225                 //      pHalData->MCSTxPowerLevelOriginalOffset[pHalData->pwrGroupCnt][13]));
1226                 pHalData->pwrGroupCnt++;
1227         }
1228 }
1229 /*-----------------------------------------------------------------------------
1230  * Function:    phy_ConfigBBWithPgParaFile
1231  *
1232  * Overview:
1233  *
1234  * Input:       NONE
1235  *
1236  * Output:      NONE
1237  *
1238  * Return:      NONE
1239  *
1240  * Revised History:
1241  * When                 Who             Remark
1242  * 11/06/2008   MHC             Create Version 0.
1243  * 2009/07/29   tynli           (porting from 92SE branch)2009/03/11 Add copy parameter file to buffer for silent reset
1244  *---------------------------------------------------------------------------*/
1245 static  int
1246 phy_ConfigBBWithPgParaFile(
1247         IN      PADAPTER                Adapter,
1248         IN      u8*                     pFileName)
1249 {
1250         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
1251
1252         int             rtStatus = _SUCCESS;
1253
1254
1255         return rtStatus;
1256
1257 }       /* phy_ConfigBBWithPgParaFile */
1258
1259
1260 /*-----------------------------------------------------------------------------
1261  * Function:    phy_ConfigBBWithPgHeaderFile
1262  *
1263  * Overview:    Config PHY_REG_PG array
1264  *
1265  * Input:       NONE
1266  *
1267  * Output:      NONE
1268  *
1269  * Return:      NONE
1270  *
1271  * Revised History:
1272  * When                 Who             Remark
1273  * 11/06/2008   MHC             Add later!!!!!!.. Please modify for new files!!!!
1274  * 11/10/2008   tynli           Modify to mew files.
1275  *---------------------------------------------------------------------------*/
1276 static  int
1277 phy_ConfigBBWithPgHeaderFile(
1278         IN      PADAPTER                Adapter,
1279         IN      u8                      ConfigType)
1280 {
1281         int i;
1282         u32*    Rtl819XPHY_REGArray_Table_PG;
1283         u16     PHY_REGArrayPGLen;
1284         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
1285
1286         // Default: pHalData->RF_Type = RF_2T2R.
1287         PHY_REGArrayPGLen = PHY_REG_Array_PGLength;
1288         Rtl819XPHY_REGArray_Table_PG = Rtl819XPHY_REG_Array_PG;
1289
1290 #ifdef CONFIG_USB_HCI
1291 // 2010/10/19 Chiyoko According to Alex/Willson opinion, VAU/dongle can share the same PHY_REG_PG.txt
1292 /*
1293         if(pHalData->BoardType == BOARD_MINICARD )
1294         {
1295                 PHY_REGArrayPGLen = PHY_REG_Array_PG_mCardLength;
1296                 Rtl819XPHY_REGArray_Table_PG = Rtl819XPHY_REG_Array_PG_mCard;
1297         }
1298         else */if(pHalData->BoardType ==BOARD_USB_High_PA )
1299         {
1300                 PHY_REGArrayPGLen = PHY_REG_Array_PG_HPLength;
1301                 Rtl819XPHY_REGArray_Table_PG = Rtl819XPHY_REG_Array_PG_HP;
1302         }
1303 #endif
1304
1305         if(ConfigType == BaseBand_Config_PHY_REG)
1306         {
1307                 for(i=0;i<PHY_REGArrayPGLen;i=i+3)
1308                 {
1309                         #if 0 //without IO, no delay is neeeded...
1310                         if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfe){
1311                                 #ifdef CONFIG_LONG_DELAY_ISSUE
1312                                 rtw_msleep_os(50);
1313                                 #else
1314                                 rtw_mdelay_os(50);
1315                                 #endif
1316                         }
1317                         else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfd)
1318                                 rtw_mdelay_os(5);
1319                         else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfc)
1320                                 rtw_mdelay_os(1);
1321                         else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfb)
1322                                 rtw_udelay_os(50);
1323                         else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xfa)
1324                                 rtw_udelay_os(5);
1325                         else if (Rtl819XPHY_REGArray_Table_PG[i] == 0xf9)
1326                                 rtw_udelay_os(1);
1327                         //PHY_SetBBReg(Adapter, Rtl819XPHY_REGArray_Table_PG[i], Rtl819XPHY_REGArray_Table_PG[i+1], Rtl819XPHY_REGArray_Table_PG[i+2]);
1328                         #endif
1329
1330                         storePwrIndexDiffRateOffset(Adapter, Rtl819XPHY_REGArray_Table_PG[i],
1331                                 Rtl819XPHY_REGArray_Table_PG[i+1],
1332                                 Rtl819XPHY_REGArray_Table_PG[i+2]);
1333                         //RT_TRACE(COMP_SEND, DBG_TRACE, ("The Rtl819XPHY_REGArray_Table_PG[0] is %lx Rtl819XPHY_REGArray_Table_PG[1] is %lx \n",Rtl819XPHY_REGArray_Table_PG[i], Rtl819XPHY_REGArray_Table_PG[i+1]));
1334                 }
1335         }
1336         else
1337         {
1338
1339                 //RT_TRACE(COMP_SEND, DBG_LOUD, ("phy_ConfigBBWithPgHeaderFile(): ConfigType != BaseBand_Config_PHY_REG\n"));
1340         }
1341
1342         return _SUCCESS;
1343
1344 }       /* phy_ConfigBBWithPgHeaderFile */
1345
1346 #if (MP_DRIVER == 1)
1347
1348 /*-----------------------------------------------------------------------------
1349  * Function:    phy_ConfigBBWithMpParaFile()
1350  *
1351  * Overview:    This function read BB parameters from general file format, and do register
1352  *                        Read/Write
1353  *
1354  * Input:       PADAPTER                Adapter
1355  *                      ps1Byte                         pFileName
1356  *
1357  * Output:      NONE
1358  *
1359  * Return:      RT_STATUS_SUCCESS: configuration file exist
1360  *      2008/11/06      MH      For 92S we do not support silent reset now. Disable
1361  *                                      parameter file compare!!!!!!??
1362  *
1363  *---------------------------------------------------------------------------*/
1364 static  int
1365 phy_ConfigBBWithMpParaFile(
1366         IN      PADAPTER                Adapter,
1367         IN      u8*                     pFileName
1368 )
1369 {
1370 #if 1
1371         int             rtStatus = _SUCCESS;
1372 #else
1373         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
1374         s4Byte                  nLinesRead, ithLine;
1375         RT_STATUS               rtStatus = RT_STATUS_SUCCESS;
1376         ps1Byte                 szLine;
1377         u4Byte                  u4bRegOffset, u4bRegMask, u4bRegValue;
1378         u4Byte                  u4bMove;
1379
1380         if(ADAPTER_TEST_STATUS_FLAG(Adapter, ADAPTER_STATUS_FIRST_INIT))
1381         {
1382                 rtStatus = PlatformReadFile(
1383                                         Adapter,
1384                                         pFileName,
1385                                         (pu1Byte)(pHalData->BufOfLines),
1386                                         MAX_LINES_HWCONFIG_TXT,
1387                                         MAX_BYTES_LINE_HWCONFIG_TXT,
1388                                         &nLinesRead
1389                                         );
1390                 if(rtStatus == RT_STATUS_SUCCESS)
1391                 {
1392                         PlatformMoveMemory(pHalData->BufOfLines6, pHalData->BufOfLines, nLinesRead*MAX_BYTES_LINE_HWCONFIG_TXT);
1393                         pHalData->nLinesRead6 = nLinesRead;
1394                 }
1395                 else
1396                 {
1397                         // Temporarily skip PHY_REG_MP.txt if file does not exist.
1398                         pHalData->nLinesRead6 = 0;
1399                         RT_TRACE(COMP_INIT, DBG_LOUD, ("No matched file \r\n"));
1400                         return RT_STATUS_SUCCESS;
1401                 }
1402         }
1403         else
1404         {
1405                 PlatformMoveMemory(pHalData->BufOfLines, pHalData->BufOfLines6, MAX_LINES_HWCONFIG_TXT*MAX_BYTES_LINE_HWCONFIG_TXT);
1406                 nLinesRead = pHalData->nLinesRead6;
1407                 rtStatus = RT_STATUS_SUCCESS;
1408         }
1409
1410
1411         if(rtStatus == RT_STATUS_SUCCESS)
1412         {
1413                 RT_TRACE(COMP_INIT, DBG_LOUD, ("phy_ConfigBBWithMpParaFile(): read %s ok\n", pFileName));
1414
1415                 for(ithLine = 0; ithLine < nLinesRead; ithLine++)
1416                 {
1417                         szLine = pHalData->BufOfLines[ithLine];
1418
1419                         if(!IsCommentString(szLine))
1420                         {
1421                                 // Get 1st hex value as register offset.
1422                                 if(GetHexValueFromString(szLine, &u4bRegOffset, &u4bMove))
1423                                 {
1424                                         if(u4bRegOffset == 0xff)
1425                                         { // Ending.
1426                                                 break;
1427                                         }
1428                                         else if (u4bRegOffset == 0xfe)
1429                                                 delay_ms(50);
1430                                         else if (u4bRegOffset == 0xfd)
1431                                                 delay_ms(5);
1432                                         else if (u4bRegOffset == 0xfc)
1433                                                 delay_ms(1);
1434                                         else if (u4bRegOffset == 0xfb)
1435                                                 PlatformStallExecution(50);
1436                                         else if (u4bRegOffset == 0xfa)
1437                                                 PlatformStallExecution(5);
1438                                         else if (u4bRegOffset == 0xf9)
1439                                                 PlatformStallExecution(1);
1440
1441                                         // Get 2nd hex value as register value.
1442                                         szLine += u4bMove;
1443                                         if(GetHexValueFromString(szLine, &u4bRegValue, &u4bMove))
1444                                         {
1445                                                 RT_TRACE(COMP_FPGA, DBG_TRACE, ("[ADDR]%03lX=%08lX\n", u4bRegOffset, u4bRegValue));
1446                                                 PHY_SetBBReg(Adapter, u4bRegOffset, bMaskDWord, u4bRegValue);
1447
1448                                                 // Add 1us delay between BB/RF register setting.
1449                                                 PlatformStallExecution(1);
1450                                         }
1451                                 }
1452                         }
1453                 }
1454         }
1455         else
1456         {
1457                 RT_TRACE(COMP_INIT, DBG_LOUD, ("phy_ConfigBBWithMpParaFile(): Failed%s\n", pFileName));
1458         }
1459 #endif
1460
1461         return rtStatus;
1462 }
1463
1464 /*-----------------------------------------------------------------------------
1465  * Function:    phy_ConfigBBWithMpHeaderFile
1466  *
1467  * Overview:    Config PHY_REG_MP array
1468  *
1469  * Input:       NONE
1470  *
1471  * Output:      NONE
1472  *
1473  * Return:      NONE
1474  *
1475  * Revised History:
1476  * When                 Who             Remark
1477  * 02/04/2010   chiyokolin              Modify to new files.
1478  *---------------------------------------------------------------------------*/
1479 static int
1480 phy_ConfigBBWithMpHeaderFile(
1481         IN      PADAPTER                Adapter,
1482         IN      u1Byte                  ConfigType)
1483 {
1484         int i;
1485         u32*    Rtl8192CPHY_REGArray_Table_MP;
1486         u16     PHY_REGArrayMPLen;
1487         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
1488
1489         PHY_REGArrayMPLen = PHY_REG_Array_MPLength;
1490         Rtl8192CPHY_REGArray_Table_MP = Rtl819XPHY_REG_Array_MP;
1491
1492         if(ConfigType == BaseBand_Config_PHY_REG)
1493         {
1494                 for(i=0;i<PHY_REGArrayMPLen;i=i+2)
1495                 {
1496                         if (Rtl8192CPHY_REGArray_Table_MP[i] == 0xfe) {
1497                                 #ifdef CONFIG_LONG_DELAY_ISSUE
1498                                 rtw_msleep_os(50);
1499                                 #else
1500                                 rtw_mdelay_os(50);
1501                                 #endif
1502                         }
1503                         else if (Rtl8192CPHY_REGArray_Table_MP[i] == 0xfd)
1504                                 rtw_mdelay_os(5);
1505                         else if (Rtl8192CPHY_REGArray_Table_MP[i] == 0xfc)
1506                                 rtw_mdelay_os(1);
1507                         else if (Rtl8192CPHY_REGArray_Table_MP[i] == 0xfb) {
1508                                 #ifdef CONFIG_LONG_DELAY_ISSUE
1509                                 rtw_msleep_os(50);
1510                                 #else
1511                                 rtw_mdelay_os(50);
1512                                 #endif
1513                         }
1514                         else if (Rtl8192CPHY_REGArray_Table_MP[i] == 0xfa)
1515                                 rtw_mdelay_os(5);
1516                         else if (Rtl8192CPHY_REGArray_Table_MP[i] == 0xf9)
1517                                 rtw_mdelay_os(1);
1518                         PHY_SetBBReg(Adapter, Rtl8192CPHY_REGArray_Table_MP[i], bMaskDWord, Rtl8192CPHY_REGArray_Table_MP[i+1]);
1519
1520                         // Add 1us delay between BB/RF register setting.
1521                         rtw_mdelay_os(1);
1522
1523 //                      RT_TRACE(COMP_INIT, DBG_TRACE, ("The Rtl8192CPHY_REGArray_Table_MP[%d] is %lx Rtl8192CPHY_REGArray_Table_MP[%d] is %lx \n", i, i+1, Rtl8192CPHY_REGArray_Table_MP[i], Rtl8192CPHY_REGArray_Table_MP[i+1]));
1524                 }
1525         }
1526         else
1527         {
1528 //              RT_TRACE(COMP_SEND, DBG_LOUD, ("phy_ConfigBBWithMpHeaderFile(): ConfigType != BaseBand_Config_PHY_REG\n"));
1529         }
1530
1531         return _SUCCESS;
1532 }       /* phy_ConfigBBWithMpHeaderFile */
1533
1534 #endif  // #if (MP_DRIVER == 1)
1535
1536 static VOID
1537 phy_BB8192C_Config_1T(
1538         IN PADAPTER Adapter
1539         )
1540 {
1541 #if 0
1542         //for path - A
1543         PHY_SetBBReg(Adapter, rFPGA0_TxInfo, 0x3, 0x1);
1544         PHY_SetBBReg(Adapter, rFPGA1_TxInfo, 0x0303, 0x0101);
1545         PHY_SetBBReg(Adapter, 0xe74, 0x0c000000, 0x1);
1546         PHY_SetBBReg(Adapter, 0xe78, 0x0c000000, 0x1);
1547         PHY_SetBBReg(Adapter, 0xe7c, 0x0c000000, 0x1);
1548         PHY_SetBBReg(Adapter, 0xe80, 0x0c000000, 0x1);
1549         PHY_SetBBReg(Adapter, 0xe88, 0x0c000000, 0x1);
1550 #endif
1551         //for path - B
1552         PHY_SetBBReg(Adapter, rFPGA0_TxInfo, 0x3, 0x2);
1553         PHY_SetBBReg(Adapter, rFPGA1_TxInfo, 0x300033, 0x200022);
1554
1555         // 20100519 Joseph: Add for 1T2R config. Suggested by Kevin, Jenyu and Yunan.
1556         PHY_SetBBReg(Adapter, rCCK0_AFESetting, bMaskByte3, 0x45);
1557         PHY_SetBBReg(Adapter, rOFDM0_TRxPathEnable, bMaskByte0, 0x23);
1558         PHY_SetBBReg(Adapter, rOFDM0_AGCParameter1, 0x30, 0x1); // B path first AGC
1559
1560         PHY_SetBBReg(Adapter, 0xe74, 0x0c000000, 0x2);
1561         PHY_SetBBReg(Adapter, 0xe78, 0x0c000000, 0x2);
1562         PHY_SetBBReg(Adapter, 0xe7c, 0x0c000000, 0x2);
1563         PHY_SetBBReg(Adapter, 0xe80, 0x0c000000, 0x2);
1564         PHY_SetBBReg(Adapter, 0xe88, 0x0c000000, 0x2);
1565
1566
1567 }
1568
1569 // Joseph test: new initialize order!!
1570 // Test only!! This part need to be re-organized.
1571 // Now it is just for 8256.
1572 static  int
1573 phy_BB8190_Config_HardCode(
1574         IN      PADAPTER        Adapter
1575         )
1576 {
1577         //RT_ASSERT(FALSE, ("This function is not implement yet!! \n"));
1578         return _SUCCESS;
1579 }
1580
1581 static  int
1582 phy_BB8192C_Config_ParaFile(
1583         IN      PADAPTER        Adapter
1584         )
1585 {
1586         EEPROM_EFUSE_PRIV       *pEEPROM = GET_EEPROM_EFUSE_PRIV(Adapter);
1587         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(Adapter);
1588         int                     rtStatus = _SUCCESS;
1589
1590         u8                              szBBRegPgFile[] = RTL819X_PHY_REG_PG;
1591
1592         u8                              sz88CBBRegFile[] = RTL8188C_PHY_REG;
1593         u8                              sz88CAGCTableFile[] = RTL8188C_AGC_TAB;
1594
1595         u8                              sz92CBBRegFile[] = RTL8192C_PHY_REG;
1596         u8                              sz92CAGCTableFile[] = RTL8192C_AGC_TAB;
1597
1598         u8                              *pszBBRegFile, *pszAGCTableFile, *pszBBRegMpFile;
1599
1600         //RT_TRACE(COMP_INIT, DBG_TRACE, ("==>phy_BB8192S_Config_ParaFile\n"));
1601
1602         if(IS_92C_SERIAL(pHalData->VersionID)){
1603                 pszBBRegFile=(u8*)&sz92CBBRegFile ;
1604                 pszAGCTableFile =(u8*)&sz92CAGCTableFile;
1605         }
1606         else{
1607                 pszBBRegFile=(u8*)&sz88CBBRegFile ;
1608                 pszAGCTableFile =(u8*)&sz88CAGCTableFile;
1609         }
1610
1611         //
1612         // 1. Read PHY_REG.TXT BB INIT!!
1613         // We will seperate as 88C / 92C according to chip version
1614         //
1615 #ifdef CONFIG_EMBEDDED_FWIMG
1616         rtStatus = phy_ConfigBBWithHeaderFile(Adapter, BaseBand_Config_PHY_REG);
1617 #else
1618         // No matter what kind of CHIP we always read PHY_REG.txt. We must copy different
1619         // type of parameter files to phy_reg.txt at first.
1620         rtStatus = phy_ConfigBBWithParaFile(Adapter,pszBBRegFile);
1621 #endif
1622
1623         if(rtStatus != _SUCCESS){
1624                 //RT_TRACE(COMP_INIT, DBG_SERIOUS, ("phy_BB8192S_Config_ParaFile():Write BB Reg Fail!!"));
1625                 goto phy_BB8190_Config_ParaFile_Fail;
1626         }
1627
1628 #if MP_DRIVER == 1
1629         //
1630         // 1.1 Read PHY_REG_MP.TXT BB INIT!!
1631         // We will seperate as 88C / 92C according to chip version
1632         //
1633 #ifdef CONFIG_EMBEDDED_FWIMG
1634         rtStatus = phy_ConfigBBWithMpHeaderFile(Adapter, BaseBand_Config_PHY_REG);
1635 #else
1636         // No matter what kind of CHIP we always read PHY_REG.txt. We must copy different
1637         // type of parameter files to phy_reg.txt at first.
1638         rtStatus = phy_ConfigBBWithMpParaFile(Adapter, pszBBRegMpFile);
1639 #endif
1640
1641         if(rtStatus != _SUCCESS){
1642 //              RT_TRACE(COMP_INIT, DBG_SERIOUS, ("phy_BB8192S_Config_ParaFile():Write BB Reg MP Fail!!"));
1643                 goto phy_BB8190_Config_ParaFile_Fail;
1644         }
1645 #endif  // #if (MP_DRIVER == 1)
1646
1647         //
1648         // 20100318 Joseph: Config 2T2R to 1T2R if necessary.
1649         //
1650         if(pHalData->rf_type == RF_1T2R)
1651         {
1652                 phy_BB8192C_Config_1T(Adapter);
1653                 DBG_8192C("phy_BB8192C_Config_ParaFile():Config to 1T!!\n");
1654         }
1655
1656         //
1657         // 2. If EEPROM or EFUSE autoload OK, We must config by PHY_REG_PG.txt
1658         //
1659         if (pEEPROM->bautoload_fail_flag == _FALSE)
1660         {
1661                 pHalData->pwrGroupCnt = 0;
1662
1663 #ifdef CONFIG_EMBEDDED_FWIMG
1664                 rtStatus = phy_ConfigBBWithPgHeaderFile(Adapter, BaseBand_Config_PHY_REG);
1665 #else
1666                 rtStatus = phy_ConfigBBWithPgParaFile(Adapter, (u8*)&szBBRegPgFile);
1667 #endif
1668         }
1669
1670         if(rtStatus != _SUCCESS){
1671                 //RT_TRACE(COMP_INIT, DBG_SERIOUS, ("phy_BB8192S_Config_ParaFile():BB_PG Reg Fail!!"));
1672                 goto phy_BB8190_Config_ParaFile_Fail;
1673         }
1674
1675         //
1676         // 3. BB AGC table Initialization
1677         //
1678 #ifdef CONFIG_EMBEDDED_FWIMG
1679         rtStatus = phy_ConfigBBWithHeaderFile(Adapter, BaseBand_Config_AGC_TAB);
1680 #else
1681         //RT_TRACE(COMP_INIT, DBG_LOUD, ("phy_BB8192S_Config_ParaFile AGC_TAB.txt\n"));
1682         rtStatus = phy_ConfigBBWithParaFile(Adapter, pszAGCTableFile);
1683 #endif
1684
1685         if(rtStatus != _SUCCESS){
1686                 //RT_TRACE(COMP_FPGA, DBG_SERIOUS, ("phy_BB8192S_Config_ParaFile():AGC Table Fail\n"));
1687                 goto phy_BB8190_Config_ParaFile_Fail;
1688         }
1689
1690         // Check if the CCK HighPower is turned ON.
1691         // This is used to calculate PWDB.
1692         pHalData->bCckHighPower = (BOOLEAN)(PHY_QueryBBReg(Adapter, rFPGA0_XA_HSSIParameter2, 0x200));
1693
1694 phy_BB8190_Config_ParaFile_Fail:
1695
1696         return rtStatus;
1697 }
1698
1699
1700 int
1701 PHY_BBConfig8192C(
1702         IN      PADAPTER        Adapter
1703         )
1704 {
1705         int     rtStatus = _SUCCESS;
1706         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
1707         u32     RegVal;
1708         u8      TmpU1B=0;
1709         u8      value8;
1710
1711         phy_InitBBRFRegisterDefinition(Adapter);
1712
1713         if(IS_HARDWARE_TYPE_8723A(Adapter))
1714         {
1715                 // Suggested by Scott. tynli_test. 2010.12.30.
1716                 //1. 0x28[1] = 1
1717                 TmpU1B = rtw_read8(Adapter, REG_AFE_PLL_CTRL);
1718                 rtw_udelay_os(2);
1719                 rtw_write8(Adapter, REG_AFE_PLL_CTRL, (TmpU1B|BIT1));
1720                 rtw_udelay_os(2);
1721
1722                 //2. 0x29[7:0] = 0xFF
1723                 rtw_write8(Adapter, REG_AFE_PLL_CTRL+1, 0xff);
1724                 rtw_udelay_os(2);
1725
1726                 //3. 0x02[1:0] = 2b'11
1727                 TmpU1B = rtw_read8(Adapter, REG_SYS_FUNC_EN);
1728                 rtw_write8(Adapter, REG_SYS_FUNC_EN, (TmpU1B|FEN_BB_GLB_RSTn|FEN_BBRSTB));
1729
1730                 //undo clock gated
1731                 rtw_write32(Adapter, rFPGA0_XCD_RFParameter, rtw_read32(Adapter, rFPGA0_XCD_RFParameter)&(~BIT31));
1732
1733                 //4. 0x25[6] = 0
1734                 TmpU1B = rtw_read8(Adapter, REG_AFE_XTAL_CTRL+1);
1735                 rtw_write8(Adapter, REG_AFE_XTAL_CTRL+1, (TmpU1B&(~BIT6)));
1736
1737                 //5. 0x24[20] = 0       //Advised by SD3 Alex Wang. 2011.02.09.
1738                 TmpU1B = rtw_read8(Adapter, REG_AFE_XTAL_CTRL+2);
1739                 rtw_write8(Adapter, REG_AFE_XTAL_CTRL+2, (TmpU1B&(~BIT4)));
1740
1741                 //6. 0x1f[7:0] = 0x07
1742                 rtw_write8(Adapter, REG_RF_CTRL, 0x07);
1743         }
1744         else
1745         {
1746                 // Enable BB and RF
1747                 RegVal = rtw_read16(Adapter, REG_SYS_FUNC_EN);
1748                 rtw_write16(Adapter, REG_SYS_FUNC_EN, (u16)(RegVal|BIT13|BIT0|BIT1));
1749
1750                 // 20090923 Joseph: Advised by Steven and Jenyu. Power sequence before init RF.
1751                 rtw_write8(Adapter, REG_AFE_PLL_CTRL, 0x83);
1752                 rtw_write8(Adapter, REG_AFE_PLL_CTRL+1, 0xdb);
1753
1754                 rtw_write8(Adapter, REG_RF_CTRL, RF_EN|RF_RSTB|RF_SDMRSTB);
1755
1756 #ifdef CONFIG_USB_HCI
1757                 rtw_write8(Adapter, REG_SYS_FUNC_EN, FEN_USBA | FEN_USBD | FEN_BB_GLB_RSTn | FEN_BBRSTB);
1758 #else
1759                 rtw_write8(Adapter, REG_SYS_FUNC_EN, FEN_PPLL|FEN_PCIEA|FEN_DIO_PCIE|FEN_BB_GLB_RSTn|FEN_BBRSTB);
1760 #endif
1761
1762                 //undo clock gated
1763                 rtw_write32(Adapter, rFPGA0_XCD_RFParameter, rtw_read32(Adapter, rFPGA0_XCD_RFParameter)&(~BIT31));
1764
1765                 // 2009/10/21 by SD1 Jong. Modified by tynli. Not in Documented in V8.1.
1766 #ifdef CONFIG_USB_HCI
1767                 //To Fix MAC loopback mode fail. Suggested by SD4 Johnny. 2010.03.23.
1768                 rtw_write8(Adapter, REG_LDOHCI12_CTRL, 0x0f);
1769                 rtw_write8(Adapter, 0x15, 0xe9);
1770 #endif
1771
1772                 rtw_write8(Adapter, REG_AFE_XTAL_CTRL+1, 0x80);
1773
1774 #ifdef CONFIG_PCI_HCI
1775                 // Force use left antenna by default for 88C.
1776         //      if(!IS_92C_SERIAL(pHalData->VersionID) || IS_92C_1T2R(pHalData->VersionID))
1777                 if(Adapter->ledpriv.LedStrategy != SW_LED_MODE10)
1778                 {
1779                         RegVal = rtw_read32(Adapter, REG_LEDCFG0);
1780                         rtw_write32(Adapter, REG_LEDCFG0, RegVal|BIT23);
1781                 }
1782 #endif
1783         }
1784
1785         //
1786         // Config BB and AGC
1787         //
1788         rtStatus = phy_BB8192C_Config_ParaFile(Adapter);
1789 #if 0
1790         switch(Adapter->MgntInfo.bRegHwParaFile)
1791         {
1792                 case 0:
1793                         phy_BB8190_Config_HardCode(Adapter);
1794                         break;
1795
1796                 case 1:
1797                         rtStatus = phy_BB8192C_Config_ParaFile(Adapter);
1798                         break;
1799
1800                 case 2:
1801                         // Partial Modify.
1802                         phy_BB8190_Config_HardCode(Adapter);
1803                         phy_BB8192C_Config_ParaFile(Adapter);
1804                         break;
1805
1806                 default:
1807                         phy_BB8190_Config_HardCode(Adapter);
1808                         break;
1809         }
1810 #endif
1811 #ifdef CONFIG_USB_HCI
1812         if(IS_HARDWARE_TYPE_8192CU(Adapter)&&IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID)
1813                 &&(pHalData->BoardType == BOARD_USB_High_PA))
1814                         rtw_write8(Adapter, 0xc72, 0x50);
1815 #endif
1816
1817         return rtStatus;
1818 }
1819
1820
1821 int
1822 PHY_RFConfig8192C(
1823         IN      PADAPTER        Adapter
1824         )
1825 {
1826         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
1827         int             rtStatus = _SUCCESS;
1828
1829         //
1830         // RF config
1831         //
1832         rtStatus = PHY_RF6052_Config8192C(Adapter);
1833 #if 0
1834         switch(pHalData->rf_chip)
1835         {
1836                 case RF_6052:
1837                         rtStatus = PHY_RF6052_Config(Adapter);
1838                         break;
1839                 case RF_8225:
1840                         rtStatus = PHY_RF8225_Config(Adapter);
1841                         break;
1842                 case RF_8256:
1843                         rtStatus = PHY_RF8256_Config(Adapter);
1844                         break;
1845                 case RF_8258:
1846                         break;
1847                 case RF_PSEUDO_11N:
1848                         rtStatus = PHY_RF8225_Config(Adapter);
1849                         break;
1850                 default: //for MacOs Warning: "RF_TYPE_MIN" not handled in switch
1851                         break;
1852         }
1853 #endif
1854         return rtStatus;
1855 }
1856
1857
1858 /*-----------------------------------------------------------------------------
1859  * Function:    PHY_ConfigRFWithParaFile()
1860  *
1861  * Overview:    This function read RF parameters from general file format, and do RF 3-wire
1862  *
1863  * Input:       PADAPTER                        Adapter
1864  *                      ps1Byte                                 pFileName
1865  *                      RF_RADIO_PATH_E eRFPath
1866  *
1867  * Output:      NONE
1868  *
1869  * Return:      RT_STATUS_SUCCESS: configuration file exist
1870  *
1871  * Note:                Delay may be required for RF configuration
1872  *---------------------------------------------------------------------------*/
1873 int
1874 rtl8192c_PHY_ConfigRFWithParaFile(
1875         IN      PADAPTER                        Adapter,
1876         IN      u8*                             pFileName,
1877         RF_RADIO_PATH_E         eRFPath
1878 )
1879 {
1880         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
1881
1882         int     rtStatus = _SUCCESS;
1883
1884
1885         return rtStatus;
1886
1887 }
1888
1889 //****************************************
1890 // The following is for High Power PA
1891 //****************************************
1892 #define HighPowerRadioAArrayLen 22
1893 //This is for High power PA
1894 u32 Rtl8192S_HighPower_RadioA_Array[HighPowerRadioAArrayLen] = {
1895 0x013,0x00029ea4,
1896 0x013,0x00025e74,
1897 0x013,0x00020ea4,
1898 0x013,0x0001ced0,
1899 0x013,0x00019f40,
1900 0x013,0x00014e70,
1901 0x013,0x000106a0,
1902 0x013,0x0000c670,
1903 0x013,0x000082a0,
1904 0x013,0x00004270,
1905 0x013,0x00000240,
1906 };
1907
1908 int
1909 PHY_ConfigRFExternalPA(
1910         IN      PADAPTER                        Adapter,
1911         RF_RADIO_PATH_E         eRFPath
1912 )
1913 {
1914         int     rtStatus = _SUCCESS;
1915 #ifdef CONFIG_USB_HCI
1916         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
1917         u16 i=0;
1918
1919         if(!pHalData->ExternalPA)
1920         {
1921                 return rtStatus;
1922         }
1923
1924         // 2010/10/19 MH According to Jenyu/EEChou 's opinion, we need not to execute the
1925         // same code as SU. It is already updated in radio_a_1T_HP.txt.
1926 #if 0
1927         //add for SU High Power PA
1928         for(i = 0;i<HighPowerRadioAArrayLen; i=i+2)
1929         {
1930                 RT_TRACE(COMP_INIT, DBG_LOUD, ("External PA, write RF 0x%lx=0x%lx\n", Rtl8192S_HighPower_RadioA_Array[i], Rtl8192S_HighPower_RadioA_Array[i+1]));
1931                 PHY_SetRFReg(Adapter, eRFPath, Rtl8192S_HighPower_RadioA_Array[i], bRFRegOffsetMask, Rtl8192S_HighPower_RadioA_Array[i+1]);
1932         }
1933 #endif
1934
1935 #endif
1936         return rtStatus;
1937 }
1938 //****************************************
1939 /*-----------------------------------------------------------------------------
1940  * Function:    PHY_ConfigRFWithHeaderFile()
1941  *
1942  * Overview:    This function read RF parameters from general file format, and do RF 3-wire
1943  *
1944  * Input:       PADAPTER                        Adapter
1945  *                      ps1Byte                                 pFileName
1946  *                      RF_RADIO_PATH_E eRFPath
1947  *
1948  * Output:      NONE
1949  *
1950  * Return:      RT_STATUS_SUCCESS: configuration file exist
1951  *
1952  * Note:                Delay may be required for RF configuration
1953  *---------------------------------------------------------------------------*/
1954 int
1955 rtl8192c_PHY_ConfigRFWithHeaderFile(
1956         IN      PADAPTER                        Adapter,
1957         RF_RADIO_PATH_E         eRFPath
1958 )
1959 {
1960
1961         int                     i;
1962         int                     rtStatus = _SUCCESS;
1963         u32*            Rtl819XRadioA_Array_Table;
1964         u32*            Rtl819XRadioB_Array_Table;
1965         u16             RadioA_ArrayLen,RadioB_ArrayLen;
1966         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
1967
1968         //
1969         // 2009.11.24. Modified by tynli.
1970         //
1971         if(IS_92C_SERIAL(pHalData->VersionID))
1972         {
1973                 RadioA_ArrayLen = RadioA_2TArrayLength;
1974                 Rtl819XRadioA_Array_Table = Rtl819XRadioA_2TArray;
1975                 RadioB_ArrayLen = RadioB_2TArrayLength;
1976                 Rtl819XRadioB_Array_Table = Rtl819XRadioB_2TArray;
1977         }
1978         else
1979         {
1980                 RadioA_ArrayLen = RadioA_1TArrayLength;
1981                 Rtl819XRadioA_Array_Table = Rtl819XRadioA_1TArray;
1982                 RadioB_ArrayLen = RadioB_1TArrayLength;
1983                 Rtl819XRadioB_Array_Table = Rtl819XRadioB_1TArray;
1984 #ifdef CONFIG_USB_HCI
1985                 if( BOARD_MINICARD == pHalData->BoardType )
1986                 {
1987                         RadioA_ArrayLen = RadioA_1T_mCardArrayLength;
1988                         Rtl819XRadioA_Array_Table = Rtl819XRadioA_1T_mCardArray;
1989                         RadioB_ArrayLen = RadioB_1T_mCardArrayLength;
1990                         Rtl819XRadioB_Array_Table = Rtl819XRadioB_1T_mCardArray;
1991                 }
1992                 else if( BOARD_USB_High_PA == pHalData->BoardType )
1993                 {
1994                         RadioA_ArrayLen = RadioA_1T_HPArrayLength;
1995                         Rtl819XRadioA_Array_Table = Rtl819XRadioA_1T_HPArray;
1996                 }
1997 #endif
1998         }
1999
2000         switch(eRFPath){
2001                 case RF_PATH_A:
2002                         #ifdef CONFIG_IOL_RF_RF90_PATH_A
2003                         if(rtw_IOL_applied(Adapter))
2004                         {
2005                                 struct xmit_frame       *xmit_frame;
2006                                 if((xmit_frame=rtw_IOL_accquire_xmit_frame(Adapter)) == NULL) {
2007                                         rtStatus = _FAIL;
2008                                         goto exit;
2009                                 }
2010
2011                                 for(i = 0;i<RadioA_ArrayLen; i=i+2)
2012                                 {
2013                                         if(Rtl819XRadioA_Array_Table[i] == 0xfe)
2014                                                 rtw_IOL_append_DELAY_MS_cmd(xmit_frame, 50);
2015                                         else if (Rtl819XRadioA_Array_Table[i] == 0xfd)
2016                                                 rtw_IOL_append_DELAY_MS_cmd(xmit_frame, 5);
2017                                         else if (Rtl819XRadioA_Array_Table[i] == 0xfc)
2018                                                 rtw_IOL_append_DELAY_MS_cmd(xmit_frame, 1);
2019                                         else if (Rtl819XRadioA_Array_Table[i] == 0xfb)
2020                                                 rtw_IOL_append_DELAY_US_cmd(xmit_frame, 50);
2021                                         else if (Rtl819XRadioA_Array_Table[i] == 0xfa)
2022                                                 rtw_IOL_append_DELAY_US_cmd(xmit_frame, 5);
2023                                         else if (Rtl819XRadioA_Array_Table[i] == 0xf9)
2024                                                 rtw_IOL_append_DELAY_US_cmd(xmit_frame, 1);
2025                                         else
2026                                         {
2027                                                 BB_REGISTER_DEFINITION_T        *pPhyReg = &pHalData->PHYRegDef[eRFPath];
2028                                                 u32     NewOffset = 0;
2029                                                 u32     DataAndAddr = 0;
2030
2031                                                 NewOffset = Rtl819XRadioA_Array_Table[i] & 0x3f;
2032                                                 DataAndAddr = ((NewOffset<<20) | (Rtl819XRadioA_Array_Table[i+1]&0x000fffff)) & 0x0fffffff;     // T65 RF
2033                                                 rtw_IOL_append_WD_cmd(xmit_frame, pPhyReg->rf3wireOffset, DataAndAddr);
2034                                         }
2035                                 }
2036                                 rtStatus = rtw_IOL_exec_cmds_sync(Adapter, xmit_frame, 1000);
2037                         }
2038                         else
2039                         #endif
2040                         {
2041                                 for(i = 0;i<RadioA_ArrayLen; i=i+2)
2042                                 {
2043                                         if(Rtl819XRadioA_Array_Table[i] == 0xfe) {
2044                                                 #ifdef CONFIG_LONG_DELAY_ISSUE
2045                                                 rtw_msleep_os(50);
2046                                                 #else
2047                                                 rtw_mdelay_os(50);
2048                                                 #endif
2049                                         }
2050                                         else if (Rtl819XRadioA_Array_Table[i] == 0xfd)
2051                                                 rtw_mdelay_os(5);
2052                                         else if (Rtl819XRadioA_Array_Table[i] == 0xfc)
2053                                                 rtw_mdelay_os(1);
2054                                         else if (Rtl819XRadioA_Array_Table[i] == 0xfb)
2055                                                 rtw_udelay_os(50);
2056                                         else if (Rtl819XRadioA_Array_Table[i] == 0xfa)
2057                                                 rtw_udelay_os(5);
2058                                         else if (Rtl819XRadioA_Array_Table[i] == 0xf9)
2059                                                 rtw_udelay_os(1);
2060                                         else
2061                                         {
2062                                                 PHY_SetRFReg(Adapter, eRFPath, Rtl819XRadioA_Array_Table[i], bRFRegOffsetMask, Rtl819XRadioA_Array_Table[i+1]);
2063                                                 // Add 1us delay between BB/RF register setting.
2064                                                 rtw_udelay_os(1);
2065                                         }
2066                                 }
2067                         }
2068
2069                         //Add for High Power PA
2070                         PHY_ConfigRFExternalPA(Adapter, eRFPath);
2071                         break;
2072                 case RF_PATH_B:
2073                         #ifdef CONFIG_IOL_RF_RF90_PATH_B
2074                         if(rtw_IOL_applied(Adapter))
2075                         {
2076                                 struct xmit_frame       *xmit_frame;
2077                                 if((xmit_frame=rtw_IOL_accquire_xmit_frame(Adapter)) == NULL) {
2078                                         rtStatus = _FAIL;
2079                                         goto exit;
2080                                 }
2081
2082                                 for(i = 0;i<RadioB_ArrayLen; i=i+2)
2083                                 {
2084                                         if(Rtl819XRadioB_Array_Table[i] == 0xfe)
2085                                                 rtw_IOL_append_DELAY_MS_cmd(xmit_frame, 50);
2086                                         else if (Rtl819XRadioB_Array_Table[i] == 0xfd)
2087                                                 rtw_IOL_append_DELAY_MS_cmd(xmit_frame, 5);
2088                                         else if (Rtl819XRadioB_Array_Table[i] == 0xfc)
2089                                                 rtw_IOL_append_DELAY_MS_cmd(xmit_frame, 1);
2090                                         else if (Rtl819XRadioB_Array_Table[i] == 0xfb)
2091                                                 rtw_IOL_append_DELAY_US_cmd(xmit_frame, 50);
2092                                         else if (Rtl819XRadioB_Array_Table[i] == 0xfa)
2093                                                 rtw_IOL_append_DELAY_US_cmd(xmit_frame, 5);
2094                                         else if (Rtl819XRadioB_Array_Table[i] == 0xf9)
2095                                                 rtw_IOL_append_DELAY_US_cmd(xmit_frame, 1);
2096                                         else
2097                                         {
2098                                                 BB_REGISTER_DEFINITION_T        *pPhyReg = &pHalData->PHYRegDef[eRFPath];
2099                                                 u32     NewOffset = 0;
2100                                                 u32     DataAndAddr = 0;
2101
2102                                                 NewOffset = Rtl819XRadioB_Array_Table[i] & 0x3f;
2103                                                 DataAndAddr = ((NewOffset<<20) | (Rtl819XRadioB_Array_Table[i+1]&0x000fffff)) & 0x0fffffff;     // T65 RF
2104                                                 rtw_IOL_append_WD_cmd(xmit_frame, pPhyReg->rf3wireOffset, DataAndAddr);
2105                                         }
2106                                 }
2107                                 rtStatus = rtw_IOL_exec_cmds_sync(Adapter, xmit_frame, 1000);
2108                         }
2109                         else
2110                         #endif
2111                         {
2112                                 for(i = 0;i<RadioB_ArrayLen; i=i+2)
2113                                 {
2114                                         if(Rtl819XRadioB_Array_Table[i] == 0xfe)
2115                                         { // Deay specific ms. Only RF configuration require delay.
2116 #if 0//#ifdef CONFIG_USB_HCI
2117                                                 #ifdef CONFIG_LONG_DELAY_ISSUE
2118                                                 rtw_msleep_os(1000);
2119                                                 #else
2120                                                 rtw_mdelay_os(1000);
2121                                                 #endif
2122 #else
2123                                                 #ifdef CONFIG_LONG_DELAY_ISSUE
2124                                                 rtw_msleep_os(50);
2125                                                 #else
2126                                                 rtw_mdelay_os(50);
2127                                                 #endif
2128 #endif
2129                                         }
2130                                         else if (Rtl819XRadioB_Array_Table[i] == 0xfd)
2131                                                 rtw_mdelay_os(5);
2132                                         else if (Rtl819XRadioB_Array_Table[i] == 0xfc)
2133                                                 rtw_mdelay_os(1);
2134                                         else if (Rtl819XRadioB_Array_Table[i] == 0xfb)
2135                                                 rtw_udelay_os(50);
2136                                         else if (Rtl819XRadioB_Array_Table[i] == 0xfa)
2137                                                 rtw_udelay_os(5);
2138                                         else if (Rtl819XRadioB_Array_Table[i] == 0xf9)
2139                                                 rtw_udelay_os(1);
2140                                         else
2141                                         {
2142                                                 PHY_SetRFReg(Adapter, eRFPath, Rtl819XRadioB_Array_Table[i], bRFRegOffsetMask, Rtl819XRadioB_Array_Table[i+1]);
2143                                                 // Add 1us delay between BB/RF register setting.
2144                                                 rtw_udelay_os(1);
2145                                         }
2146                                 }
2147                         }
2148
2149                         break;
2150                 case RF_PATH_C:
2151                         break;
2152                 case RF_PATH_D:
2153                         break;
2154         }
2155
2156 exit:
2157         return rtStatus;
2158
2159 }
2160
2161
2162 /*-----------------------------------------------------------------------------
2163  * Function:    PHY_CheckBBAndRFOK()
2164  *
2165  * Overview:    This function is write register and then readback to make sure whether
2166  *                        BB[PHY0, PHY1], RF[Patha, path b, path c, path d] is Ok
2167  *
2168  * Input:       PADAPTER                        Adapter
2169  *                      HW90_BLOCK_E            CheckBlock
2170  *                      RF_RADIO_PATH_E eRFPath         // it is used only when CheckBlock is HW90_BLOCK_RF
2171  *
2172  * Output:      NONE
2173  *
2174  * Return:      RT_STATUS_SUCCESS: PHY is OK
2175  *
2176  * Note:                This function may be removed in the ASIC
2177  *---------------------------------------------------------------------------*/
2178 int
2179 PHY_CheckBBAndRFOK(
2180         IN      PADAPTER                        Adapter,
2181         IN      HW90_BLOCK_E            CheckBlock,
2182         IN      RF_RADIO_PATH_E eRFPath
2183         )
2184 {
2185         int                     rtStatus = _SUCCESS;
2186
2187         u32                             i, CheckTimes = 4,ulRegRead = 0;
2188
2189         u32                             WriteAddr[4];
2190         u32                             WriteData[] = {0xfffff027, 0xaa55a02f, 0x00000027, 0x55aa502f};
2191
2192         // Initialize register address offset to be checked
2193         WriteAddr[HW90_BLOCK_MAC] = 0x100;
2194         WriteAddr[HW90_BLOCK_PHY0] = 0x900;
2195         WriteAddr[HW90_BLOCK_PHY1] = 0x800;
2196         WriteAddr[HW90_BLOCK_RF] = 0x3;
2197
2198         for(i=0 ; i < CheckTimes ; i++)
2199         {
2200
2201                 //
2202                 // Write Data to register and readback
2203                 //
2204                 switch(CheckBlock)
2205                 {
2206                 case HW90_BLOCK_MAC:
2207                         //RT_ASSERT(FALSE, ("PHY_CheckBBRFOK(): Never Write 0x100 here!"));
2208                         //RT_TRACE(COMP_INIT, DBG_LOUD, ("PHY_CheckBBRFOK(): Never Write 0x100 here!\n"));
2209                         break;
2210
2211                 case HW90_BLOCK_PHY0:
2212                 case HW90_BLOCK_PHY1:
2213                         rtw_write32(Adapter, WriteAddr[CheckBlock], WriteData[i]);
2214                         ulRegRead = rtw_read32(Adapter, WriteAddr[CheckBlock]);
2215                         break;
2216
2217                 case HW90_BLOCK_RF:
2218                         // When initialization, we want the delay function(delay_ms(), delay_us()
2219                         // ==> actually we call PlatformStallExecution()) to do NdisStallExecution()
2220                         // [busy wait] instead of NdisMSleep(). So we acquire RT_INITIAL_SPINLOCK
2221                         // to run at Dispatch level to achive it.
2222                         //cosa PlatformAcquireSpinLock(Adapter, RT_INITIAL_SPINLOCK);
2223                         WriteData[i] &= 0xfff;
2224                         PHY_SetRFReg(Adapter, eRFPath, WriteAddr[HW90_BLOCK_RF], bRFRegOffsetMask, WriteData[i]);
2225                         // TODO: we should not delay for such a long time. Ask SD3
2226                         rtw_mdelay_os(10);
2227                         ulRegRead = PHY_QueryRFReg(Adapter, eRFPath, WriteAddr[HW90_BLOCK_RF], bMaskDWord);
2228                         rtw_mdelay_os(10);
2229                         //cosa PlatformReleaseSpinLock(Adapter, RT_INITIAL_SPINLOCK);
2230                         break;
2231
2232                 default:
2233                         rtStatus = _FAIL;
2234                         break;
2235                 }
2236
2237
2238                 //
2239                 // Check whether readback data is correct
2240                 //
2241                 if(ulRegRead != WriteData[i])
2242                 {
2243                         //RT_TRACE(COMP_FPGA, DBG_LOUD, ("ulRegRead: %lx, WriteData: %lx \n", ulRegRead, WriteData[i]));
2244                         rtStatus = _FAIL;
2245                         break;
2246                 }
2247         }
2248
2249         return rtStatus;
2250 }
2251
2252
2253 VOID
2254 rtl8192c_PHY_GetHWRegOriginalValue(
2255         IN      PADAPTER                Adapter
2256         )
2257 {
2258         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
2259
2260         // read rx initial gain
2261         pHalData->DefaultInitialGain[0] = (u8)PHY_QueryBBReg(Adapter, rOFDM0_XAAGCCore1, bMaskByte0);
2262         pHalData->DefaultInitialGain[1] = (u8)PHY_QueryBBReg(Adapter, rOFDM0_XBAGCCore1, bMaskByte0);
2263         pHalData->DefaultInitialGain[2] = (u8)PHY_QueryBBReg(Adapter, rOFDM0_XCAGCCore1, bMaskByte0);
2264         pHalData->DefaultInitialGain[3] = (u8)PHY_QueryBBReg(Adapter, rOFDM0_XDAGCCore1, bMaskByte0);
2265         //RT_TRACE(COMP_INIT, DBG_LOUD,
2266         //("Default initial gain (c50=0x%x, c58=0x%x, c60=0x%x, c68=0x%x) \n",
2267         //pHalData->DefaultInitialGain[0], pHalData->DefaultInitialGain[1],
2268         //pHalData->DefaultInitialGain[2], pHalData->DefaultInitialGain[3]));
2269
2270         // read framesync
2271         pHalData->framesync = (u8)PHY_QueryBBReg(Adapter, rOFDM0_RxDetector3, bMaskByte0);
2272         pHalData->framesyncC34 = PHY_QueryBBReg(Adapter, rOFDM0_RxDetector2, bMaskDWord);
2273         //RT_TRACE(COMP_INIT, DBG_LOUD, ("Default framesync (0x%x) = 0x%x \n",
2274         //      rOFDM0_RxDetector3, pHalData->framesync));
2275 }
2276
2277
2278 //
2279 //      Description:
2280 //              Map dBm into Tx power index according to
2281 //              current HW model, for example, RF and PA, and
2282 //              current wireless mode.
2283 //      By Bruce, 2008-01-29.
2284 //
2285 static  u8
2286 phy_DbmToTxPwrIdx(
2287         IN      PADAPTER                Adapter,
2288         IN      WIRELESS_MODE   WirelessMode,
2289         IN      int                     PowerInDbm
2290         )
2291 {
2292         u8                              TxPwrIdx = 0;
2293         int                             Offset = 0;
2294
2295
2296         //
2297         // Tested by MP, we found that CCK Index 0 equals to 8dbm, OFDM legacy equals to
2298         // 3dbm, and OFDM HT equals to 0dbm repectively.
2299         // Note:
2300         //      The mapping may be different by different NICs. Do not use this formula for what needs accurate result.
2301         // By Bruce, 2008-01-29.
2302         //
2303         switch(WirelessMode)
2304         {
2305         case WIRELESS_MODE_B:
2306                 Offset = -7;
2307                 break;
2308
2309         case WIRELESS_MODE_G:
2310         case WIRELESS_MODE_N_24G:
2311                 Offset = -8;
2312                 break;
2313         default:
2314                 Offset = -8;
2315                 break;
2316         }
2317
2318         if((PowerInDbm - Offset) > 0)
2319         {
2320                 TxPwrIdx = (u8)((PowerInDbm - Offset) * 2);
2321         }
2322         else
2323         {
2324                 TxPwrIdx = 0;
2325         }
2326
2327         // Tx Power Index is too large.
2328         if(TxPwrIdx > MAX_TXPWR_IDX_NMODE_92S)
2329                 TxPwrIdx = MAX_TXPWR_IDX_NMODE_92S;
2330
2331         return TxPwrIdx;
2332 }
2333
2334 //
2335 //      Description:
2336 //              Map Tx power index into dBm according to
2337 //              current HW model, for example, RF and PA, and
2338 //              current wireless mode.
2339 //      By Bruce, 2008-01-29.
2340 //
2341 int
2342 phy_TxPwrIdxToDbm(
2343         IN      PADAPTER                Adapter,
2344         IN      WIRELESS_MODE   WirelessMode,
2345         IN      u8                      TxPwrIdx
2346         )
2347 {
2348         int                             Offset = 0;
2349         int                             PwrOutDbm = 0;
2350
2351         //
2352         // Tested by MP, we found that CCK Index 0 equals to -7dbm, OFDM legacy equals to -8dbm.
2353         // Note:
2354         //      The mapping may be different by different NICs. Do not use this formula for what needs accurate result.
2355         // By Bruce, 2008-01-29.
2356         //
2357         switch(WirelessMode)
2358         {
2359         case WIRELESS_MODE_B:
2360                 Offset = -7;
2361                 break;
2362
2363         case WIRELESS_MODE_G:
2364         case WIRELESS_MODE_N_24G:
2365                 Offset = -8;
2366         default:
2367                 Offset = -8;
2368                 break;
2369         }
2370
2371         PwrOutDbm = TxPwrIdx / 2 + Offset; // Discard the decimal part.
2372
2373         return PwrOutDbm;
2374 }
2375
2376
2377 /*-----------------------------------------------------------------------------
2378  * Function:    GetTxPowerLevel8190()
2379  *
2380  * Overview:    This function is export to "common" moudule
2381  *
2382  * Input:       PADAPTER                Adapter
2383  *                      psByte                  Power Level
2384  *
2385  * Output:      NONE
2386  *
2387  * Return:      NONE
2388  *
2389  *---------------------------------------------------------------------------*/
2390 VOID
2391 PHY_GetTxPowerLevel8192C(
2392         IN      PADAPTER                Adapter,
2393         OUT u32*                powerlevel
2394         )
2395 {
2396         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
2397         u8                      TxPwrLevel = 0;
2398         int                     TxPwrDbm;
2399
2400         //
2401         // Because the Tx power indexes are different, we report the maximum of them to
2402         // meet the CCX TPC request. By Bruce, 2008-01-31.
2403         //
2404
2405         // CCK
2406         TxPwrLevel = pHalData->CurrentCckTxPwrIdx;
2407         TxPwrDbm = phy_TxPwrIdxToDbm(Adapter, WIRELESS_MODE_B, TxPwrLevel);
2408
2409         // Legacy OFDM
2410         TxPwrLevel = pHalData->CurrentOfdm24GTxPwrIdx + pHalData->LegacyHTTxPowerDiff;
2411
2412         // Compare with Legacy OFDM Tx power.
2413         if(phy_TxPwrIdxToDbm(Adapter, WIRELESS_MODE_G, TxPwrLevel) > TxPwrDbm)
2414                 TxPwrDbm = phy_TxPwrIdxToDbm(Adapter, WIRELESS_MODE_G, TxPwrLevel);
2415
2416         // HT OFDM
2417         TxPwrLevel = pHalData->CurrentOfdm24GTxPwrIdx;
2418
2419         // Compare with HT OFDM Tx power.
2420         if(phy_TxPwrIdxToDbm(Adapter, WIRELESS_MODE_N_24G, TxPwrLevel) > TxPwrDbm)
2421                 TxPwrDbm = phy_TxPwrIdxToDbm(Adapter, WIRELESS_MODE_N_24G, TxPwrLevel);
2422
2423         *powerlevel = TxPwrDbm;
2424 }
2425
2426
2427 static void getTxPowerIndex(
2428         IN      PADAPTER                Adapter,
2429         IN      u8                      channel,
2430         IN OUT u8*              cckPowerLevel,
2431         IN OUT u8*              ofdmPowerLevel
2432         )
2433 {
2434         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(Adapter);
2435         u8                              index = (channel -1);
2436         // 1. CCK
2437         cckPowerLevel[RF_PATH_A] = pHalData->TxPwrLevelCck[RF_PATH_A][index];   //RF-A
2438         cckPowerLevel[RF_PATH_B] = pHalData->TxPwrLevelCck[RF_PATH_B][index];   //RF-B
2439
2440         // 2. OFDM for 1S or 2S
2441         if (GET_RF_TYPE(Adapter) == RF_1T2R || GET_RF_TYPE(Adapter) == RF_1T1R)
2442         {
2443                 // Read HT 40 OFDM TX power
2444                 ofdmPowerLevel[RF_PATH_A] = pHalData->TxPwrLevelHT40_1S[RF_PATH_A][index];
2445                 ofdmPowerLevel[RF_PATH_B] = pHalData->TxPwrLevelHT40_1S[RF_PATH_B][index];
2446         }
2447         else if (GET_RF_TYPE(Adapter) == RF_2T2R)
2448         {
2449                 // Read HT 40 OFDM TX power
2450                 ofdmPowerLevel[RF_PATH_A] = pHalData->TxPwrLevelHT40_2S[RF_PATH_A][index];
2451                 ofdmPowerLevel[RF_PATH_B] = pHalData->TxPwrLevelHT40_2S[RF_PATH_B][index];
2452         }
2453         //RTPRINT(FPHY, PHY_TXPWR, ("Channel-%d, set tx power index !!\n", channel));
2454 }
2455
2456 static void ccxPowerIndexCheck(
2457         IN      PADAPTER                Adapter,
2458         IN      u8                      channel,
2459         IN OUT u8*              cckPowerLevel,
2460         IN OUT u8*              ofdmPowerLevel
2461         )
2462 {
2463 #if 0
2464         PMGNT_INFO                      pMgntInfo = &(Adapter->MgntInfo);
2465         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(Adapter);
2466         PRT_CCX_INFO            pCcxInfo = GET_CCX_INFO(pMgntInfo);
2467
2468         //
2469         // CCX 2 S31, AP control of client transmit power:
2470         // 1. We shall not exceed Cell Power Limit as possible as we can.
2471         // 2. Tolerance is +/- 5dB.
2472         // 3. 802.11h Power Contraint takes higher precedence over CCX Cell Power Limit.
2473         //
2474         // TODO:
2475         // 1. 802.11h power contraint
2476         //
2477         // 071011, by rcnjko.
2478         //
2479         if(     pMgntInfo->OpMode == RT_OP_MODE_INFRASTRUCTURE &&
2480                 pMgntInfo->mAssoc &&
2481                 pCcxInfo->bUpdateCcxPwr &&
2482                 pCcxInfo->bWithCcxCellPwr &&
2483                 channel == pMgntInfo->dot11CurrentChannelNumber)
2484         {
2485                 u1Byte  CckCellPwrIdx = phy_DbmToTxPwrIdx(Adapter, WIRELESS_MODE_B, pCcxInfo->CcxCellPwr);
2486                 u1Byte  LegacyOfdmCellPwrIdx = phy_DbmToTxPwrIdx(Adapter, WIRELESS_MODE_G, pCcxInfo->CcxCellPwr);
2487                 u1Byte  OfdmCellPwrIdx = phy_DbmToTxPwrIdx(Adapter, WIRELESS_MODE_N_24G, pCcxInfo->CcxCellPwr);
2488
2489                 RT_TRACE(COMP_TXAGC, DBG_LOUD,
2490                 ("CCX Cell Limit: %d dbm => CCK Tx power index : %d, Legacy OFDM Tx power index : %d, OFDM Tx power index: %d\n",
2491                 pCcxInfo->CcxCellPwr, CckCellPwrIdx, LegacyOfdmCellPwrIdx, OfdmCellPwrIdx));
2492                 RT_TRACE(COMP_TXAGC, DBG_LOUD,
2493                 ("EEPROM channel(%d) => CCK Tx power index: %d, Legacy OFDM Tx power index : %d, OFDM Tx power index: %d\n",
2494                 channel, cckPowerLevel[0], ofdmPowerLevel[0] + pHalData->LegacyHTTxPowerDiff, ofdmPowerLevel[0]));
2495
2496                 // CCK
2497                 if(cckPowerLevel[0] > CckCellPwrIdx)
2498                         cckPowerLevel[0] = CckCellPwrIdx;
2499                 // Legacy OFDM, HT OFDM
2500                 if(ofdmPowerLevel[0] + pHalData->LegacyHTTxPowerDiff > LegacyOfdmCellPwrIdx)
2501                 {
2502                         if((OfdmCellPwrIdx - pHalData->LegacyHTTxPowerDiff) > 0)
2503                         {
2504                                 ofdmPowerLevel[0] = OfdmCellPwrIdx - pHalData->LegacyHTTxPowerDiff;
2505                         }
2506                         else
2507                         {
2508                                 ofdmPowerLevel[0] = 0;
2509                         }
2510                 }
2511
2512                 RT_TRACE(COMP_TXAGC, DBG_LOUD,
2513                 ("Altered CCK Tx power index : %d, Legacy OFDM Tx power index: %d, OFDM Tx power index: %d\n",
2514                 cckPowerLevel[0], ofdmPowerLevel[0] + pHalData->LegacyHTTxPowerDiff, ofdmPowerLevel[0]));
2515         }
2516
2517         pHalData->CurrentCckTxPwrIdx = cckPowerLevel[0];
2518         pHalData->CurrentOfdm24GTxPwrIdx = ofdmPowerLevel[0];
2519
2520         RT_TRACE(COMP_TXAGC, DBG_LOUD,
2521                 ("PHY_SetTxPowerLevel8192S(): CCK Tx power index : %d, Legacy OFDM Tx power index: %d, OFDM Tx power index: %d\n",
2522                 cckPowerLevel[0], ofdmPowerLevel[0] + pHalData->LegacyHTTxPowerDiff, ofdmPowerLevel[0]));
2523 #endif
2524 }
2525 /*-----------------------------------------------------------------------------
2526  * Function:    SetTxPowerLevel8190()
2527  *
2528  * Overview:    This function is export to "HalCommon" moudule
2529  *                      We must consider RF path later!!!!!!!
2530  *
2531  * Input:       PADAPTER                Adapter
2532  *                      u1Byte          channel
2533  *
2534  * Output:      NONE
2535  *
2536  * Return:      NONE
2537  *      2008/11/04      MHC             We remove EEPROM_93C56.
2538  *                                              We need to move CCX relative code to independet file.
2539  *      2009/01/21      MHC             Support new EEPROM format from SD3 requirement.
2540  *
2541  *---------------------------------------------------------------------------*/
2542 VOID
2543 PHY_SetTxPowerLevel8192C(
2544         IN      PADAPTER                Adapter,
2545         IN      u8                      channel
2546         )
2547 {
2548         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(Adapter);
2549         u8      cckPowerLevel[2], ofdmPowerLevel[2];    // [0]:RF-A, [1]:RF-B
2550
2551 #if(MP_DRIVER == 1)
2552         return;
2553 #endif
2554
2555         if(pHalData->bTXPowerDataReadFromEEPORM == _FALSE)
2556                 return;
2557
2558         getTxPowerIndex(Adapter, channel, &cckPowerLevel[0], &ofdmPowerLevel[0]);
2559         //RTPRINT(FPHY, PHY_TXPWR, ("Channel-%d, cckPowerLevel (A / B) = 0x%x / 0x%x,   ofdmPowerLevel (A / B) = 0x%x / 0x%x\n",
2560         //      channel, cckPowerLevel[0], cckPowerLevel[1], ofdmPowerLevel[0], ofdmPowerLevel[1]));
2561
2562         ccxPowerIndexCheck(Adapter, channel, &cckPowerLevel[0], &ofdmPowerLevel[0]);
2563
2564         rtl8192c_PHY_RF6052SetCckTxPower(Adapter, &cckPowerLevel[0]);
2565         rtl8192c_PHY_RF6052SetOFDMTxPower(Adapter, &ofdmPowerLevel[0], channel);
2566
2567 #if 0
2568         switch(pHalData->rf_chip)
2569         {
2570                 case RF_8225:
2571                         PHY_SetRF8225CckTxPower(Adapter, cckPowerLevel[0]);
2572                         PHY_SetRF8225OfdmTxPower(Adapter, ofdmPowerLevel[0]);
2573                 break;
2574
2575                 case RF_8256:
2576                         PHY_SetRF8256CCKTxPower(Adapter, cckPowerLevel[0]);
2577                         PHY_SetRF8256OFDMTxPower(Adapter, ofdmPowerLevel[0]);
2578                         break;
2579
2580                 case RF_6052:
2581                         PHY_RF6052SetCckTxPower(Adapter, &cckPowerLevel[0]);
2582                         PHY_RF6052SetOFDMTxPower(Adapter, &ofdmPowerLevel[0], channel);
2583                         break;
2584
2585                 case RF_8258:
2586                         break;
2587         }
2588 #endif
2589
2590 }
2591
2592
2593 //
2594 //      Description:
2595 //              Update transmit power level of all channel supported.
2596 //
2597 //      TODO:
2598 //              A mode.
2599 //      By Bruce, 2008-02-04.
2600 //
2601 BOOLEAN
2602 PHY_UpdateTxPowerDbm8192C(
2603         IN      PADAPTER        Adapter,
2604         IN      int             powerInDbm
2605         )
2606 {
2607         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
2608         u8                              idx;
2609         u8                      rf_path;
2610
2611         // TODO: A mode Tx power.
2612         u8      CckTxPwrIdx = phy_DbmToTxPwrIdx(Adapter, WIRELESS_MODE_B, powerInDbm);
2613         u8      OfdmTxPwrIdx = phy_DbmToTxPwrIdx(Adapter, WIRELESS_MODE_N_24G, powerInDbm);
2614
2615         if(OfdmTxPwrIdx - pHalData->LegacyHTTxPowerDiff > 0)
2616                 OfdmTxPwrIdx -= pHalData->LegacyHTTxPowerDiff;
2617         else
2618                 OfdmTxPwrIdx = 0;
2619
2620         //RT_TRACE(COMP_TXAGC, DBG_LOUD, ("PHY_UpdateTxPowerDbm8192S(): %ld dBm , CckTxPwrIdx = %d, OfdmTxPwrIdx = %d\n", powerInDbm, CckTxPwrIdx, OfdmTxPwrIdx));
2621
2622         for(idx = 0; idx < 14; idx++)
2623         {
2624                 for (rf_path = 0; rf_path < 2; rf_path++)
2625                 {
2626                         pHalData->TxPwrLevelCck[rf_path][idx] = CckTxPwrIdx;
2627                         pHalData->TxPwrLevelHT40_1S[rf_path][idx] =
2628                         pHalData->TxPwrLevelHT40_2S[rf_path][idx] = OfdmTxPwrIdx;
2629                 }
2630         }
2631
2632         //Adapter->HalFunc.SetTxPowerLevelHandler(Adapter, pHalData->CurrentChannel);//gtest:todo
2633
2634         return _TRUE;
2635 }
2636
2637
2638 /*
2639         Description:
2640                 When beacon interval is changed, the values of the
2641                 hw registers should be modified.
2642         By tynli, 2008.10.24.
2643
2644 */
2645
2646
2647 void
2648 rtl8192c_PHY_SetBeaconHwReg(
2649         IN      PADAPTER                Adapter,
2650         IN      u16                     BeaconInterval
2651         )
2652 {
2653
2654 }
2655
2656
2657 VOID
2658 PHY_ScanOperationBackup8192C(
2659         IN      PADAPTER        Adapter,
2660         IN      u8              Operation
2661         )
2662 {
2663 #if 0
2664         IO_TYPE IoType;
2665
2666         if(!Adapter->bDriverStopped)
2667         {
2668                 switch(Operation)
2669                 {
2670                         case SCAN_OPT_BACKUP:
2671                                 IoType = IO_CMD_PAUSE_DM_BY_SCAN;
2672                                 rtw_hal_set_hwreg(Adapter,HW_VAR_IO_CMD,  (pu1Byte)&IoType);
2673
2674                                 break;
2675
2676                         case SCAN_OPT_RESTORE:
2677                                 IoType = IO_CMD_RESUME_DM_BY_SCAN;
2678                                 rtw_hal_set_hwreg(Adapter,HW_VAR_IO_CMD,  (pu1Byte)&IoType);
2679                                 break;
2680
2681                         default:
2682                                 RT_TRACE(COMP_SCAN, DBG_LOUD, ("Unknown Scan Backup Operation. \n"));
2683                                 break;
2684                 }
2685         }
2686 #endif
2687 }
2688
2689 /*-----------------------------------------------------------------------------
2690  * Function:    PHY_SetBWModeCallback8192C()
2691  *
2692  * Overview:    Timer callback function for SetSetBWMode
2693  *
2694  * Input:               PRT_TIMER               pTimer
2695  *
2696  * Output:      NONE
2697  *
2698  * Return:      NONE
2699  *
2700  * Note:                (1) We do not take j mode into consideration now
2701  *                      (2) Will two workitem of "switch channel" and "switch channel bandwidth" run
2702  *                           concurrently?
2703  *---------------------------------------------------------------------------*/
2704 static VOID
2705 _PHY_SetBWMode92C(
2706         IN      PADAPTER        Adapter
2707 )
2708 {
2709 //      PADAPTER                        Adapter = (PADAPTER)pTimer->Adapter;
2710         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(Adapter);
2711         u8                              regBwOpMode;
2712         u8                              regRRSR_RSC;
2713
2714         //return;
2715
2716         // Added it for 20/40 mhz switch time evaluation by guangan 070531
2717         //u4Byte                                NowL, NowH;
2718         //u8Byte                                BeginTime, EndTime;
2719
2720         /*RT_TRACE(COMP_SCAN, DBG_LOUD, ("==>PHY_SetBWModeCallback8192C()  Switch to %s bandwidth\n", \
2721                                         pHalData->CurrentChannelBW == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz"))*/
2722
2723         if(pHalData->rf_chip == RF_PSEUDO_11N)
2724         {
2725                 //pHalData->SetBWModeInProgress= _FALSE;
2726                 return;
2727         }
2728
2729         // There is no 40MHz mode in RF_8225.
2730         if(pHalData->rf_chip==RF_8225)
2731                 return;
2732
2733         if(Adapter->bDriverStopped)
2734                 return;
2735
2736         // Added it for 20/40 mhz switch time evaluation by guangan 070531
2737         //NowL = PlatformEFIORead4Byte(Adapter, TSFR);
2738         //NowH = PlatformEFIORead4Byte(Adapter, TSFR+4);
2739         //BeginTime = ((u8Byte)NowH << 32) + NowL;
2740
2741         //3//
2742         //3//<1>Set MAC register
2743         //3//
2744         //Adapter->HalFunc.SetBWModeHandler();
2745
2746         regBwOpMode = rtw_read8(Adapter, REG_BWOPMODE);
2747         regRRSR_RSC = rtw_read8(Adapter, REG_RRSR+2);
2748         //regBwOpMode = rtw_hal_get_hwreg(Adapter,HW_VAR_BWMODE,(pu1Byte)&regBwOpMode);
2749
2750         switch(pHalData->CurrentChannelBW)
2751         {
2752                 case HT_CHANNEL_WIDTH_20:
2753                         regBwOpMode |= BW_OPMODE_20MHZ;
2754                            // 2007/02/07 Mark by Emily becasue we have not verify whether this register works
2755                         rtw_write8(Adapter, REG_BWOPMODE, regBwOpMode);
2756                         break;
2757
2758                 case HT_CHANNEL_WIDTH_40:
2759                         regBwOpMode &= ~BW_OPMODE_20MHZ;
2760                                 // 2007/02/07 Mark by Emily becasue we have not verify whether this register works
2761                         rtw_write8(Adapter, REG_BWOPMODE, regBwOpMode);
2762
2763                         regRRSR_RSC = (regRRSR_RSC&0x90) |(pHalData->nCur40MhzPrimeSC<<5);
2764                         rtw_write8(Adapter, REG_RRSR+2, regRRSR_RSC);
2765                         break;
2766
2767                 default:
2768                         /*RT_TRACE(COMP_DBG, DBG_LOUD, ("PHY_SetBWModeCallback8192C():
2769                                                 unknown Bandwidth: %#X\n",pHalData->CurrentChannelBW));*/
2770                         break;
2771         }
2772
2773         //3//
2774         //3//<2>Set PHY related register
2775         //3//
2776         switch(pHalData->CurrentChannelBW)
2777         {
2778                 /* 20 MHz channel*/
2779                 case HT_CHANNEL_WIDTH_20:
2780                         PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bRFMOD, 0x0);
2781                         PHY_SetBBReg(Adapter, rFPGA1_RFMOD, bRFMOD, 0x0);
2782                         PHY_SetBBReg(Adapter, rFPGA0_AnalogParameter2, BIT10, 1);
2783
2784                         break;
2785
2786
2787                 /* 40 MHz channel*/
2788                 case HT_CHANNEL_WIDTH_40:
2789                         PHY_SetBBReg(Adapter, rFPGA0_RFMOD, bRFMOD, 0x1);
2790                         PHY_SetBBReg(Adapter, rFPGA1_RFMOD, bRFMOD, 0x1);
2791
2792                         // Set Control channel to upper or lower. These settings are required only for 40MHz
2793                         PHY_SetBBReg(Adapter, rCCK0_System, bCCKSideBand, (pHalData->nCur40MhzPrimeSC>>1));
2794                         PHY_SetBBReg(Adapter, rOFDM1_LSTF, 0xC00, pHalData->nCur40MhzPrimeSC);
2795                         PHY_SetBBReg(Adapter, rFPGA0_AnalogParameter2, BIT10, 0);
2796
2797                         PHY_SetBBReg(Adapter, 0x818, (BIT26|BIT27), (pHalData->nCur40MhzPrimeSC==HAL_PRIME_CHNL_OFFSET_LOWER)?2:1);
2798
2799                         break;
2800
2801
2802
2803                 default:
2804                         /*RT_TRACE(COMP_DBG, DBG_LOUD, ("PHY_SetBWModeCallback8192C(): unknown Bandwidth: %#X\n"\
2805                                                 ,pHalData->CurrentChannelBW));*/
2806                         break;
2807
2808         }
2809         //Skip over setting of J-mode in BB register here. Default value is "None J mode". Emily 20070315
2810
2811         // Added it for 20/40 mhz switch time evaluation by guangan 070531
2812         //NowL = PlatformEFIORead4Byte(Adapter, TSFR);
2813         //NowH = PlatformEFIORead4Byte(Adapter, TSFR+4);
2814         //EndTime = ((u8Byte)NowH << 32) + NowL;
2815         //RT_TRACE(COMP_SCAN, DBG_LOUD, ("SetBWModeCallback8190Pci: time of SetBWMode = %I64d us!\n", (EndTime - BeginTime)));
2816
2817         //3<3>Set RF related register
2818         switch(pHalData->rf_chip)
2819         {
2820                 case RF_8225:
2821                         //PHY_SetRF8225Bandwidth(Adapter, pHalData->CurrentChannelBW);
2822                         break;
2823
2824                 case RF_8256:
2825                         // Please implement this function in Hal8190PciPhy8256.c
2826                         //PHY_SetRF8256Bandwidth(Adapter, pHalData->CurrentChannelBW);
2827                         break;
2828
2829                 case RF_8258:
2830                         // Please implement this function in Hal8190PciPhy8258.c
2831                         // PHY_SetRF8258Bandwidth();
2832                         break;
2833
2834                 case RF_PSEUDO_11N:
2835                         // Do Nothing
2836                         break;
2837
2838                 case RF_6052:
2839                         rtl8192c_PHY_RF6052SetBandwidth(Adapter, pHalData->CurrentChannelBW);
2840                         break;
2841
2842                 default:
2843                         //RT_ASSERT(FALSE, ("Unknown RFChipID: %d\n", pHalData->RFChipID));
2844                         break;
2845         }
2846
2847         //pHalData->SetBWModeInProgress= FALSE;
2848
2849         //RT_TRACE(COMP_SCAN, DBG_LOUD, ("<==PHY_SetBWModeCallback8192C() \n" ));
2850 }
2851
2852
2853  /*-----------------------------------------------------------------------------
2854  * Function:   SetBWMode8190Pci()
2855  *
2856  * Overview:  This function is export to "HalCommon" moudule
2857  *
2858  * Input:               PADAPTER                        Adapter
2859  *                      HT_CHANNEL_WIDTH        Bandwidth       //20M or 40M
2860  *
2861  * Output:      NONE
2862  *
2863  * Return:      NONE
2864  *
2865  * Note:                We do not take j mode into consideration now
2866  *---------------------------------------------------------------------------*/
2867 VOID
2868 PHY_SetBWMode8192C(
2869         IN      PADAPTER                                        Adapter,
2870         IN      HT_CHANNEL_WIDTH        Bandwidth,      // 20M or 40M
2871         IN      unsigned char   Offset          // Upper, Lower, or Don't care
2872 )
2873 {
2874         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
2875         HT_CHANNEL_WIDTH        tmpBW= pHalData->CurrentChannelBW;
2876         // Modified it for 20/40 mhz switch by guangan 070531
2877         //PMGNT_INFO    pMgntInfo=&Adapter->MgntInfo;
2878
2879         //return;
2880
2881         //if(pHalData->SwChnlInProgress)
2882 //      if(pMgntInfo->bScanInProgress)
2883 //      {
2884 //              RT_TRACE(COMP_SCAN, DBG_LOUD, ("PHY_SetBWMode8192C() %s Exit because bScanInProgress!\n",
2885 //                                      Bandwidth == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz"));
2886 //              return;
2887 //      }
2888
2889 //      if(pHalData->SetBWModeInProgress)
2890 //      {
2891 //              // Modified it for 20/40 mhz switch by guangan 070531
2892 //              RT_TRACE(COMP_SCAN, DBG_LOUD, ("PHY_SetBWMode8192C() %s cancel last timer because SetBWModeInProgress!\n",
2893 //                                      Bandwidth == HT_CHANNEL_WIDTH_20?"20MHz":"40MHz"));
2894 //              PlatformCancelTimer(Adapter, &pHalData->SetBWModeTimer);
2895 //              //return;
2896 //      }
2897
2898         //if(pHalData->SetBWModeInProgress)
2899         //      return;
2900
2901         //pHalData->SetBWModeInProgress= TRUE;
2902
2903         pHalData->CurrentChannelBW = Bandwidth;
2904
2905 #if 0
2906         if(Offset==HT_EXTCHNL_OFFSET_LOWER)
2907                 pHalData->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_UPPER;
2908         else if(Offset==HT_EXTCHNL_OFFSET_UPPER)
2909                 pHalData->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_LOWER;
2910         else
2911                 pHalData->nCur40MhzPrimeSC = HAL_PRIME_CHNL_OFFSET_DONT_CARE;
2912 #else
2913         pHalData->nCur40MhzPrimeSC = Offset;
2914 #endif
2915
2916         if((!Adapter->bDriverStopped) && (!Adapter->bSurpriseRemoved))
2917         {
2918 #ifdef USE_WORKITEM
2919                 //PlatformScheduleWorkItem(&(pHalData->SetBWModeWorkItem));
2920 #else
2921         #if 0
2922                 //PlatformSetTimer(Adapter, &(pHalData->SetBWModeTimer), 0);
2923         #else
2924                 _PHY_SetBWMode92C(Adapter);
2925         #endif
2926 #endif
2927         }
2928         else
2929         {
2930                 //RT_TRACE(COMP_SCAN, DBG_LOUD, ("PHY_SetBWMode8192C() SetBWModeInProgress FALSE driver sleep or unload\n"));
2931                 //pHalData->SetBWModeInProgress= FALSE;
2932                 pHalData->CurrentChannelBW = tmpBW;
2933         }
2934
2935 }
2936
2937
2938 static void _PHY_SwChnl8192C(PADAPTER Adapter, u8 channel)
2939 {
2940         u8 eRFPath;
2941         u32 param1, param2;
2942         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
2943
2944         if ( Adapter->bNotifyChannelChange )
2945         {
2946                 DBG_871X( "[%s] ch = %d\n", __FUNCTION__, channel );
2947         }
2948
2949         //s1. pre common command - CmdID_SetTxPowerLevel
2950         PHY_SetTxPowerLevel8192C(Adapter, channel);
2951
2952         //s2. RF dependent command - CmdID_RF_WriteReg, param1=RF_CHNLBW, param2=channel
2953         param1 = RF_CHNLBW;
2954         param2 = channel;
2955         for(eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
2956         {
2957                 pHalData->RfRegChnlVal[eRFPath] = ((pHalData->RfRegChnlVal[eRFPath] & 0xfffffc00) | param2);
2958                 PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)eRFPath, param1, bRFRegOffsetMask, pHalData->RfRegChnlVal[eRFPath]);
2959         }
2960
2961
2962         //s3. post common command - CmdID_End, None
2963
2964 }
2965
2966 VOID
2967 PHY_SwChnl8192C(        // Call after initialization
2968         IN      PADAPTER        Adapter,
2969         IN      u8              channel
2970         )
2971 {
2972         //PADAPTER Adapter =  ADJUST_TO_ADAPTIVE_ADAPTER(pAdapter, _TRUE);
2973         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
2974         u8      tmpchannel = pHalData->CurrentChannel;
2975         BOOLEAN  bResult = _TRUE;
2976
2977         if(pHalData->rf_chip == RF_PSEUDO_11N)
2978         {
2979                 //pHalData->SwChnlInProgress=FALSE;
2980                 return;                                                                 //return immediately if it is peudo-phy
2981         }
2982
2983         //if(pHalData->SwChnlInProgress)
2984         //      return;
2985
2986         //if(pHalData->SetBWModeInProgress)
2987         //      return;
2988
2989         //--------------------------------------------
2990         switch(pHalData->CurrentWirelessMode)
2991         {
2992                 case WIRELESS_MODE_A:
2993                 case WIRELESS_MODE_N_5G:
2994                         //RT_ASSERT((channel>14), ("WIRELESS_MODE_A but channel<=14"));
2995                         break;
2996
2997                 case WIRELESS_MODE_B:
2998                         //RT_ASSERT((channel<=14), ("WIRELESS_MODE_B but channel>14"));
2999                         break;
3000
3001                 case WIRELESS_MODE_G:
3002                 case WIRELESS_MODE_N_24G:
3003                         //RT_ASSERT((channel<=14), ("WIRELESS_MODE_G but channel>14"));
3004                         break;
3005
3006                 default:
3007                         //RT_ASSERT(FALSE, ("Invalid WirelessMode(%#x)!!\n", pHalData->CurrentWirelessMode));
3008                         break;
3009         }
3010         //--------------------------------------------
3011
3012         //pHalData->SwChnlInProgress = TRUE;
3013         if(channel == 0)
3014                 channel = 1;
3015
3016         pHalData->CurrentChannel=channel;
3017
3018         //pHalData->SwChnlStage=0;
3019         //pHalData->SwChnlStep=0;
3020
3021         if((!Adapter->bDriverStopped) && (!Adapter->bSurpriseRemoved))
3022         {
3023 #ifdef USE_WORKITEM
3024                 //bResult = PlatformScheduleWorkItem(&(pHalData->SwChnlWorkItem));
3025 #else
3026                 #if 0
3027                 //PlatformSetTimer(Adapter, &(pHalData->SwChnlTimer), 0);
3028                 #else
3029                 _PHY_SwChnl8192C(Adapter, channel);
3030                 #endif
3031 #endif
3032                 if(bResult)
3033                 {
3034                         //RT_TRACE(COMP_SCAN, DBG_LOUD, ("PHY_SwChnl8192C SwChnlInProgress TRUE schdule workitem done\n"));
3035                 }
3036                 else
3037                 {
3038                         //RT_TRACE(COMP_SCAN, DBG_LOUD, ("PHY_SwChnl8192C SwChnlInProgress FALSE schdule workitem error\n"));
3039                         //if(IS_HARDWARE_TYPE_8192SU(Adapter))
3040                         //{
3041                         //      pHalData->SwChnlInProgress = FALSE;
3042                                 pHalData->CurrentChannel = tmpchannel;
3043                         //}
3044                 }
3045
3046         }
3047         else
3048         {
3049                 //RT_TRACE(COMP_SCAN, DBG_LOUD, ("PHY_SwChnl8192C SwChnlInProgress FALSE driver sleep or unload\n"));
3050                 //if(IS_HARDWARE_TYPE_8192SU(Adapter))
3051                 //{
3052                 //      pHalData->SwChnlInProgress = FALSE;
3053                         pHalData->CurrentChannel = tmpchannel;
3054                 //}
3055         }
3056 }
3057
3058
3059 static  BOOLEAN
3060 phy_SwChnlStepByStep(
3061         IN      PADAPTER        Adapter,
3062         IN      u8              channel,
3063         IN      u8              *stage,
3064         IN      u8              *step,
3065         OUT u32         *delay
3066         )
3067 {
3068 #if 0
3069         HAL_DATA_TYPE                   *pHalData = GET_HAL_DATA(Adapter);
3070         PCHANNEL_ACCESS_SETTING pChnlAccessSetting;
3071         SwChnlCmd                               PreCommonCmd[MAX_PRECMD_CNT];
3072         u4Byte                                  PreCommonCmdCnt;
3073         SwChnlCmd                               PostCommonCmd[MAX_POSTCMD_CNT];
3074         u4Byte                                  PostCommonCmdCnt;
3075         SwChnlCmd                               RfDependCmd[MAX_RFDEPENDCMD_CNT];
3076         u4Byte                                  RfDependCmdCnt;
3077         SwChnlCmd                               *CurrentCmd;
3078         u1Byte                                  eRFPath;
3079         u4Byte                                  RfTXPowerCtrl;
3080         BOOLEAN                                 bAdjRfTXPowerCtrl = _FALSE;
3081
3082
3083         RT_ASSERT((Adapter != NULL), ("Adapter should not be NULL\n"));
3084 #if(MP_DRIVER != 1)
3085         RT_ASSERT(IsLegalChannel(Adapter, channel), ("illegal channel: %d\n", channel));
3086 #endif
3087         RT_ASSERT((pHalData != NULL), ("pHalData should not be NULL\n"));
3088
3089         pChnlAccessSetting = &Adapter->MgntInfo.Info8185.ChannelAccessSetting;
3090         RT_ASSERT((pChnlAccessSetting != NULL), ("pChnlAccessSetting should not be NULL\n"));
3091
3092         //for(eRFPath = RF_PATH_A; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
3093         //for(eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
3094         //{
3095                 // <1> Fill up pre common command.
3096         PreCommonCmdCnt = 0;
3097         phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT,
3098                                 CmdID_SetTxPowerLevel, 0, 0, 0);
3099         phy_SetSwChnlCmdArray(PreCommonCmd, PreCommonCmdCnt++, MAX_PRECMD_CNT,
3100                                 CmdID_End, 0, 0, 0);
3101
3102                 // <2> Fill up post common command.
3103         PostCommonCmdCnt = 0;
3104
3105         phy_SetSwChnlCmdArray(PostCommonCmd, PostCommonCmdCnt++, MAX_POSTCMD_CNT,
3106                                 CmdID_End, 0, 0, 0);
3107
3108                 // <3> Fill up RF dependent command.
3109         RfDependCmdCnt = 0;
3110         switch( pHalData->RFChipID )
3111         {
3112                 case RF_8225:
3113                 RT_ASSERT((channel >= 1 && channel <= 14), ("illegal channel for Zebra: %d\n", channel));
3114                 // 2008/09/04 MH Change channel.
3115                 if(channel==14) channel++;
3116                 phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
3117                         CmdID_RF_WriteReg, rZebra1_Channel, (0x10+channel-1), 10);
3118                 phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
3119                 CmdID_End, 0, 0, 0);
3120                 break;
3121
3122         case RF_8256:
3123                 // TEST!! This is not the table for 8256!!
3124                 RT_ASSERT((channel >= 1 && channel <= 14), ("illegal channel for Zebra: %d\n", channel));
3125                 phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
3126                         CmdID_RF_WriteReg, rRfChannel, channel, 10);
3127                 phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
3128                 CmdID_End, 0, 0, 0);
3129                 break;
3130
3131         case RF_6052:
3132                 RT_ASSERT((channel >= 1 && channel <= 14), ("illegal channel for Zebra: %d\n", channel));
3133                 phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
3134                         CmdID_RF_WriteReg, RF_CHNLBW, channel, 10);
3135                 phy_SetSwChnlCmdArray(RfDependCmd, RfDependCmdCnt++, MAX_RFDEPENDCMD_CNT,
3136                 CmdID_End, 0, 0, 0);
3137
3138                 break;
3139
3140         case RF_8258:
3141                 break;
3142
3143         // For FPGA two MAC verification
3144         case RF_PSEUDO_11N:
3145                 return TRUE;
3146         default:
3147                 RT_ASSERT(FALSE, ("Unknown RFChipID: %d\n", pHalData->RFChipID));
3148                 return FALSE;
3149                 break;
3150         }
3151
3152
3153         do{
3154                 switch(*stage)
3155                 {
3156                 case 0:
3157                         CurrentCmd=&PreCommonCmd[*step];
3158                         break;
3159                 case 1:
3160                         CurrentCmd=&RfDependCmd[*step];
3161                         break;
3162                 case 2:
3163                         CurrentCmd=&PostCommonCmd[*step];
3164                         break;
3165                 }
3166
3167                 if(CurrentCmd->CmdID==CmdID_End)
3168                 {
3169                         if((*stage)==2)
3170                         {
3171                                 return TRUE;
3172                         }
3173                         else
3174                         {
3175                                 (*stage)++;
3176                                 (*step)=0;
3177                                 continue;
3178                         }
3179                 }
3180
3181                 switch(CurrentCmd->CmdID)
3182                 {
3183                 case CmdID_SetTxPowerLevel:
3184                         PHY_SetTxPowerLevel8192C(Adapter,channel);
3185                         break;
3186                 case CmdID_WritePortUlong:
3187                         PlatformEFIOWrite4Byte(Adapter, CurrentCmd->Para1, CurrentCmd->Para2);
3188                         break;
3189                 case CmdID_WritePortUshort:
3190                         PlatformEFIOWrite2Byte(Adapter, CurrentCmd->Para1, (u2Byte)CurrentCmd->Para2);
3191                         break;
3192                 case CmdID_WritePortUchar:
3193                         PlatformEFIOWrite1Byte(Adapter, CurrentCmd->Para1, (u1Byte)CurrentCmd->Para2);
3194                         break;
3195                 case CmdID_RF_WriteReg: // Only modify channel for the register now !!!!!
3196                         for(eRFPath = 0; eRFPath <pHalData->NumTotalRFPath; eRFPath++)
3197                         {
3198 #if 1
3199                                 pHalData->RfRegChnlVal[eRFPath] = ((pHalData->RfRegChnlVal[eRFPath] & 0xfffffc00) | CurrentCmd->Para2);
3200                                 PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, bRFRegOffsetMask, pHalData->RfRegChnlVal[eRFPath]);
3201 #else
3202                                 PHY_SetRFReg(Adapter, (RF_RADIO_PATH_E)eRFPath, CurrentCmd->Para1, bRFRegOffsetMask, (CurrentCmd->Para2));
3203 #endif
3204                         }
3205                         break;
3206                 }
3207
3208                 break;
3209         }while(TRUE);
3210         //cosa }/*for(Number of RF paths)*/
3211
3212         (*delay)=CurrentCmd->msDelay;
3213         (*step)++;
3214         return FALSE;
3215 #endif
3216         return _TRUE;
3217 }
3218
3219
3220 static  BOOLEAN
3221 phy_SetSwChnlCmdArray(
3222         SwChnlCmd*              CmdTable,
3223         u32                     CmdTableIdx,
3224         u32                     CmdTableSz,
3225         SwChnlCmdID             CmdID,
3226         u32                     Para1,
3227         u32                     Para2,
3228         u32                     msDelay
3229         )
3230 {
3231         SwChnlCmd* pCmd;
3232
3233         if(CmdTable == NULL)
3234         {
3235                 //RT_ASSERT(FALSE, ("phy_SetSwChnlCmdArray(): CmdTable cannot be NULL.\n"));
3236                 return _FALSE;
3237         }
3238         if(CmdTableIdx >= CmdTableSz)
3239         {
3240                 //RT_ASSERT(FALSE,
3241                 //              ("phy_SetSwChnlCmdArray(): Access invalid index, please check size of the table, CmdTableIdx:%ld, CmdTableSz:%ld\n",
3242                 //              CmdTableIdx, CmdTableSz));
3243                 return _FALSE;
3244         }
3245
3246         pCmd = CmdTable + CmdTableIdx;
3247         pCmd->CmdID = CmdID;
3248         pCmd->Para1 = Para1;
3249         pCmd->Para2 = Para2;
3250         pCmd->msDelay = msDelay;
3251
3252         return _TRUE;
3253 }
3254
3255
3256 static  void
3257 phy_FinishSwChnlNow(    // We should not call this function directly
3258                 IN      PADAPTER        Adapter,
3259                 IN      u8              channel
3260                 )
3261 {
3262 #if 0
3263         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
3264         u32                     delay;
3265
3266         while(!phy_SwChnlStepByStep(Adapter,channel,&pHalData->SwChnlStage,&pHalData->SwChnlStep,&delay))
3267         {
3268                 if(delay>0)
3269                         rtw_mdelay_os(delay);
3270         }
3271 #endif
3272 }
3273
3274
3275
3276 //
3277 // Description:
3278 //      Switch channel synchronously. Called by SwChnlByDelayHandler.
3279 //
3280 // Implemented by Bruce, 2008-02-14.
3281 // The following procedure is operted according to SwChanlCallback8190Pci().
3282 // However, this procedure is performed synchronously  which should be running under
3283 // passive level.
3284 //
3285 VOID
3286 PHY_SwChnlPhy8192C(     // Only called during initialize
3287         IN      PADAPTER        Adapter,
3288         IN      u8              channel
3289         )
3290 {
3291         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);
3292
3293         //RT_TRACE(COMP_SCAN | COMP_RM, DBG_LOUD, ("==>PHY_SwChnlPhy8192S(), switch from channel %d to channel %d.\n", pHalData->CurrentChannel, channel));
3294
3295         // Cannot IO.
3296         //if(RT_CANNOT_IO(Adapter))
3297         //      return;
3298
3299         // Channel Switching is in progress.
3300         //if(pHalData->SwChnlInProgress)
3301         //      return;
3302
3303         //return immediately if it is peudo-phy
3304         if(pHalData->rf_chip == RF_PSEUDO_11N)
3305         {
3306                 //pHalData->SwChnlInProgress=FALSE;
3307                 return;
3308         }
3309
3310         //pHalData->SwChnlInProgress = TRUE;
3311         if( channel == 0)
3312                 channel = 1;
3313
3314         pHalData->CurrentChannel=channel;
3315
3316         //pHalData->SwChnlStage = 0;
3317         //pHalData->SwChnlStep = 0;
3318
3319         phy_FinishSwChnlNow(Adapter,channel);
3320
3321         //pHalData->SwChnlInProgress = FALSE;
3322 }
3323
3324
3325 //
3326 //      Description:
3327 //              Configure H/W functionality to enable/disable Monitor mode.
3328 //              Note, because we possibly need to configure BB and RF in this function,
3329 //              so caller should in PASSIVE_LEVEL. 080118, by rcnjko.
3330 //
3331 VOID
3332 PHY_SetMonitorMode8192C(
3333         IN      PADAPTER                        pAdapter,
3334         IN      BOOLEAN                         bEnableMonitorMode
3335         )
3336 {
3337 #if 0
3338         HAL_DATA_TYPE           *pHalData       = GET_HAL_DATA(pAdapter);
3339         BOOLEAN                         bFilterOutNonAssociatedBSSID = FALSE;
3340
3341         //2 Note: we may need to stop antenna diversity.
3342         if(bEnableMonitorMode)
3343         {
3344                 bFilterOutNonAssociatedBSSID = FALSE;
3345                 RT_TRACE(COMP_RM, DBG_LOUD, ("PHY_SetMonitorMode8192S(): enable monitor mode\n"));
3346
3347                 pHalData->bInMonitorMode = TRUE;
3348                 pAdapter->HalFunc.AllowAllDestAddrHandler(pAdapter, TRUE, TRUE);
3349                 rtw_hal_set_hwreg(pAdapter, HW_VAR_CHECK_BSSID, (pu1Byte)&bFilterOutNonAssociatedBSSID);
3350         }
3351         else
3352         {
3353                 bFilterOutNonAssociatedBSSID = TRUE;
3354                 RT_TRACE(COMP_RM, DBG_LOUD, ("PHY_SetMonitorMode8192S(): disable monitor mode\n"));
3355
3356                 pAdapter->HalFunc.AllowAllDestAddrHandler(pAdapter, FALSE, TRUE);
3357                 pHalData->bInMonitorMode = FALSE;
3358                 rtw_hal_set_hwreg(pAdapter, HW_VAR_CHECK_BSSID, (pu1Byte)&bFilterOutNonAssociatedBSSID);
3359         }
3360 #endif
3361 }
3362
3363
3364 /*-----------------------------------------------------------------------------
3365  * Function:    PHYCheckIsLegalRfPath8190Pci()
3366  *
3367  * Overview:    Check different RF type to execute legal judgement. If RF Path is illegal
3368  *                      We will return false.
3369  *
3370  * Input:               NONE
3371  *
3372  * Output:              NONE
3373  *
3374  * Return:              NONE
3375  *
3376  * Revised History:
3377  *      When            Who             Remark
3378  *      11/15/2007      MHC             Create Version 0.
3379  *
3380  *---------------------------------------------------------------------------*/
3381 BOOLEAN
3382 PHY_CheckIsLegalRfPath8192C(
3383         IN      PADAPTER        pAdapter,
3384         IN      u32     eRFPath)
3385 {
3386 //      HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);
3387         BOOLEAN                         rtValue = _TRUE;
3388
3389         // NOt check RF Path now.!
3390 #if 0
3391         if (pHalData->RF_Type == RF_1T2R && eRFPath != RF_PATH_A)
3392         {
3393                 rtValue = FALSE;
3394         }
3395         if (pHalData->RF_Type == RF_1T2R && eRFPath != RF_PATH_A)
3396         {
3397
3398         }
3399 #endif
3400         return  rtValue;
3401
3402 }       /* PHY_CheckIsLegalRfPath8192C */
3403
3404 //-------------------------------------------------------------------------
3405 //
3406 //      IQK
3407 //
3408 //-------------------------------------------------------------------------
3409 #define MAX_TOLERANCE           5
3410 #define IQK_DELAY_TIME          1       //ms
3411
3412 static u8                       //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK
3413 _PHY_PathA_IQK(
3414         IN      PADAPTER        pAdapter,
3415         IN      BOOLEAN         configPathB
3416         )
3417 {
3418         u32 regEAC, regE94, regE9C, regEA4;
3419         u8 result = 0x00;
3420         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);
3421
3422         //RTPRINT(FINIT, INIT_IQK, ("Path A IQK!\n"));
3423
3424         //path-A IQK setting
3425         //RTPRINT(FINIT, INIT_IQK, ("Path-A IQK setting!\n"));
3426         PHY_SetBBReg(pAdapter, rTx_IQK_Tone_A, bMaskDWord, 0x10008c1f);
3427         PHY_SetBBReg(pAdapter, rRx_IQK_Tone_A, bMaskDWord, 0x10008c1f);
3428         PHY_SetBBReg(pAdapter, rTx_IQK_PI_A, bMaskDWord, 0x82140102);
3429
3430         PHY_SetBBReg(pAdapter, rRx_IQK_PI_A, bMaskDWord, configPathB ? 0x28160202 :
3431                 IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID)?0x28160202:0x28160502);
3432
3433         //path-B IQK setting
3434         if(configPathB)
3435         {
3436                 PHY_SetBBReg(pAdapter, rTx_IQK_Tone_B, bMaskDWord, 0x10008c22);
3437                 PHY_SetBBReg(pAdapter, rRx_IQK_Tone_B, bMaskDWord, 0x10008c22);
3438                 PHY_SetBBReg(pAdapter, rTx_IQK_PI_B, bMaskDWord, 0x82140102);
3439                 PHY_SetBBReg(pAdapter, rRx_IQK_PI_B, bMaskDWord, 0x28160202);
3440         }
3441
3442         //LO calibration setting
3443         //RTPRINT(FINIT, INIT_IQK, ("LO calibration setting!\n"));
3444         PHY_SetBBReg(pAdapter, rIQK_AGC_Rsp, bMaskDWord, 0x001028d1);
3445
3446         //One shot, path A LOK & IQK
3447         //RTPRINT(FINIT, INIT_IQK, ("One shot, path A LOK & IQK!\n"));
3448         PHY_SetBBReg(pAdapter, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);
3449         PHY_SetBBReg(pAdapter, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);
3450
3451         // delay x ms
3452         //RTPRINT(FINIT, INIT_IQK, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME));
3453         rtw_udelay_os(IQK_DELAY_TIME*1000);//PlatformStallExecution(IQK_DELAY_TIME*1000);
3454
3455         // Check failed
3456         regEAC = PHY_QueryBBReg(pAdapter, rRx_Power_After_IQK_A_2, bMaskDWord);
3457         //RTPRINT(FINIT, INIT_IQK, ("0xeac = 0x%x\n", regEAC));
3458         regE94 = PHY_QueryBBReg(pAdapter, rTx_Power_Before_IQK_A, bMaskDWord);
3459         //RTPRINT(FINIT, INIT_IQK, ("0xe94 = 0x%x\n", regE94));
3460         regE9C= PHY_QueryBBReg(pAdapter, rTx_Power_After_IQK_A, bMaskDWord);
3461         //RTPRINT(FINIT, INIT_IQK, ("0xe9c = 0x%x\n", regE9C));
3462         regEA4= PHY_QueryBBReg(pAdapter, rRx_Power_Before_IQK_A_2, bMaskDWord);
3463         //RTPRINT(FINIT, INIT_IQK, ("0xea4 = 0x%x\n", regEA4));
3464
3465         if(!(regEAC & BIT28) &&
3466                 (((regE94 & 0x03FF0000)>>16) != 0x142) &&
3467                 (((regE9C & 0x03FF0000)>>16) != 0x42) )
3468                 result |= 0x01;
3469         else                                                    //if Tx not OK, ignore Rx
3470                 return result;
3471
3472         if(!(regEAC & BIT27) &&         //if Tx is OK, check whether Rx is OK
3473                 (((regEA4 & 0x03FF0000)>>16) != 0x132) &&
3474                 (((regEAC & 0x03FF0000)>>16) != 0x36))
3475                 result |= 0x02;
3476         else
3477                 DBG_8192C("Path A Rx IQK fail!!\n");
3478
3479         return result;
3480
3481
3482 }
3483
3484 static u8                               //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK
3485 _PHY_PathB_IQK(
3486         IN      PADAPTER        pAdapter
3487         )
3488 {
3489         u32 regEAC, regEB4, regEBC, regEC4, regECC;
3490         u8      result = 0x00;
3491         //RTPRINT(FINIT, INIT_IQK, ("Path B IQK!\n"));
3492
3493         //One shot, path B LOK & IQK
3494         //RTPRINT(FINIT, INIT_IQK, ("One shot, path A LOK & IQK!\n"));
3495         PHY_SetBBReg(pAdapter, rIQK_AGC_Cont, bMaskDWord, 0x00000002);
3496         PHY_SetBBReg(pAdapter, rIQK_AGC_Cont, bMaskDWord, 0x00000000);
3497
3498         // delay x ms
3499         //RTPRINT(FINIT, INIT_IQK, ("Delay %d ms for One shot, path B LOK & IQK.\n", IQK_DELAY_TIME));
3500         rtw_udelay_os(IQK_DELAY_TIME*1000);//PlatformStallExecution(IQK_DELAY_TIME*1000);
3501
3502         // Check failed
3503         regEAC = PHY_QueryBBReg(pAdapter, rRx_Power_After_IQK_A_2, bMaskDWord);
3504         //RTPRINT(FINIT, INIT_IQK, ("0xeac = 0x%x\n", regEAC));
3505         regEB4 = PHY_QueryBBReg(pAdapter, rTx_Power_Before_IQK_B, bMaskDWord);
3506         //RTPRINT(FINIT, INIT_IQK, ("0xeb4 = 0x%x\n", regEB4));
3507         regEBC= PHY_QueryBBReg(pAdapter, rTx_Power_After_IQK_B, bMaskDWord);
3508         //RTPRINT(FINIT, INIT_IQK, ("0xebc = 0x%x\n", regEBC));
3509         regEC4= PHY_QueryBBReg(pAdapter, rRx_Power_Before_IQK_B_2, bMaskDWord);
3510         //RTPRINT(FINIT, INIT_IQK, ("0xec4 = 0x%x\n", regEC4));
3511         regECC= PHY_QueryBBReg(pAdapter, rRx_Power_After_IQK_B_2, bMaskDWord);
3512         //RTPRINT(FINIT, INIT_IQK, ("0xecc = 0x%x\n", regECC));
3513
3514         if(!(regEAC & BIT31) &&
3515                 (((regEB4 & 0x03FF0000)>>16) != 0x142) &&
3516                 (((regEBC & 0x03FF0000)>>16) != 0x42))
3517                 result |= 0x01;
3518         else
3519                 return result;
3520
3521         if(!(regEAC & BIT30) &&
3522                 (((regEC4 & 0x03FF0000)>>16) != 0x132) &&
3523                 (((regECC & 0x03FF0000)>>16) != 0x36))
3524                 result |= 0x02;
3525         else
3526                 DBG_8192C("Path B Rx IQK fail!!\n");
3527
3528
3529         return result;
3530
3531 }
3532
3533 static VOID
3534 _PHY_PathAFillIQKMatrix(
3535         IN      PADAPTER        pAdapter,
3536         IN      BOOLEAN         bIQKOK,
3537         IN      int                     result[][8],
3538         IN      u8                      final_candidate,
3539         IN      BOOLEAN         bTxOnly
3540         )
3541 {
3542         u32     Oldval_0, X, TX0_A, reg;
3543         s32     Y, TX0_C;
3544
3545         DBG_8192C("Path A IQ Calibration %s !\n",(bIQKOK)?"Success":"Failed");
3546
3547         if(final_candidate == 0xFF)
3548                 return;
3549         else if(bIQKOK)
3550         {
3551                 Oldval_0 = (PHY_QueryBBReg(pAdapter, rOFDM0_XATxIQImbalance, bMaskDWord) >> 22) & 0x3FF;
3552
3553                 X = result[final_candidate][0];
3554                 if ((X & 0x00000200) != 0)
3555                         X = X | 0xFFFFFC00;
3556                 TX0_A = (X * Oldval_0) >> 8;
3557                 //RTPRINT(FINIT, INIT_IQK, ("X = 0x%lx, TX0_A = 0x%lx, Oldval_0 0x%lx\n", X, TX0_A, Oldval_0));
3558                 PHY_SetBBReg(pAdapter, rOFDM0_XATxIQImbalance, 0x3FF, TX0_A);
3559                 PHY_SetBBReg(pAdapter, rOFDM0_ECCAThreshold, BIT(31), ((X* Oldval_0>>7) & 0x1));
3560
3561                 Y = result[final_candidate][1];
3562                 if ((Y & 0x00000200) != 0)
3563                         Y = Y | 0xFFFFFC00;
3564                 TX0_C = (Y * Oldval_0) >> 8;
3565                 //RTPRINT(FINIT, INIT_IQK, ("Y = 0x%lx, TX = 0x%lx\n", Y, TX0_C));
3566                 PHY_SetBBReg(pAdapter, rOFDM0_XCTxAFE, 0xF0000000, ((TX0_C&0x3C0)>>6));
3567                 PHY_SetBBReg(pAdapter, rOFDM0_XATxIQImbalance, 0x003F0000, (TX0_C&0x3F));
3568                 PHY_SetBBReg(pAdapter, rOFDM0_ECCAThreshold, BIT(29), ((Y* Oldval_0>>7) & 0x1));
3569
3570                 if(bTxOnly)
3571                 {
3572                         DBG_8192C("_PHY_PathAFillIQKMatrix only Tx OK\n");
3573                         return;
3574                 }
3575
3576                 reg = result[final_candidate][2];
3577                 PHY_SetBBReg(pAdapter, rOFDM0_XARxIQImbalance, 0x3FF, reg);
3578
3579                 reg = result[final_candidate][3] & 0x3F;
3580                 PHY_SetBBReg(pAdapter, rOFDM0_XARxIQImbalance, 0xFC00, reg);
3581
3582                 reg = (result[final_candidate][3] >> 6) & 0xF;
3583                 PHY_SetBBReg(pAdapter, rOFDM0_RxIQExtAnta, 0xF0000000, reg);
3584         }
3585 }
3586
3587 static VOID
3588 _PHY_PathBFillIQKMatrix(
3589         IN      PADAPTER        pAdapter,
3590         IN      BOOLEAN         bIQKOK,
3591         IN      int                     result[][8],
3592         IN      u8                      final_candidate,
3593         IN      BOOLEAN         bTxOnly                 //do Tx only
3594         )
3595 {
3596         u32     Oldval_1, X, TX1_A, reg;
3597         s32     Y, TX1_C;
3598
3599         DBG_8192C("Path B IQ Calibration %s !\n",(bIQKOK)?"Success":"Failed");
3600
3601         if(final_candidate == 0xFF)
3602                 return;
3603         else if(bIQKOK)
3604         {
3605                 Oldval_1 = (PHY_QueryBBReg(pAdapter, rOFDM0_XBTxIQImbalance, bMaskDWord) >> 22) & 0x3FF;
3606
3607                 X = result[final_candidate][4];
3608                 if ((X & 0x00000200) != 0)
3609                         X = X | 0xFFFFFC00;
3610                 TX1_A = (X * Oldval_1) >> 8;
3611                 //RTPRINT(FINIT, INIT_IQK, ("X = 0x%lx, TX1_A = 0x%lx\n", X, TX1_A));
3612                 PHY_SetBBReg(pAdapter, rOFDM0_XBTxIQImbalance, 0x3FF, TX1_A);
3613                 PHY_SetBBReg(pAdapter, rOFDM0_ECCAThreshold, BIT(27), ((X* Oldval_1>>7) & 0x1));
3614
3615                 Y = result[final_candidate][5];
3616                 if ((Y & 0x00000200) != 0)
3617                         Y = Y | 0xFFFFFC00;
3618                 TX1_C = (Y * Oldval_1) >> 8;
3619                 //RTPRINT(FINIT, INIT_IQK, ("Y = 0x%lx, TX1_C = 0x%lx\n", Y, TX1_C));
3620                 PHY_SetBBReg(pAdapter, rOFDM0_XDTxAFE, 0xF0000000, ((TX1_C&0x3C0)>>6));
3621                 PHY_SetBBReg(pAdapter, rOFDM0_XBTxIQImbalance, 0x003F0000, (TX1_C&0x3F));
3622                 PHY_SetBBReg(pAdapter, rOFDM0_ECCAThreshold, BIT(25), ((Y* Oldval_1>>7) & 0x1));
3623
3624                 if(bTxOnly)
3625                         return;
3626
3627                 reg = result[final_candidate][6];
3628                 PHY_SetBBReg(pAdapter, rOFDM0_XBRxIQImbalance, 0x3FF, reg);
3629
3630                 reg = result[final_candidate][7] & 0x3F;
3631                 PHY_SetBBReg(pAdapter, rOFDM0_XBRxIQImbalance, 0xFC00, reg);
3632
3633                 reg = (result[final_candidate][7] >> 6) & 0xF;
3634                 PHY_SetBBReg(pAdapter, rOFDM0_AGCRSSITable, 0x0000F000, reg);
3635         }
3636 }
3637
3638 static VOID
3639 _PHY_SaveADDARegisters(
3640         IN      PADAPTER        pAdapter,
3641         IN      u32*            ADDAReg,
3642         IN      u32*            ADDABackup,
3643         IN      u32                     RegisterNum
3644         )
3645 {
3646         u32     i;
3647
3648         //RTPRINT(FINIT, INIT_IQK, ("Save ADDA parameters.\n"));
3649         for( i = 0 ; i < RegisterNum ; i++){
3650                 ADDABackup[i] = PHY_QueryBBReg(pAdapter, ADDAReg[i], bMaskDWord);
3651         }
3652 }
3653
3654 static VOID
3655 _PHY_SaveMACRegisters(
3656         IN      PADAPTER        pAdapter,
3657         IN      u32*            MACReg,
3658         IN      u32*            MACBackup
3659         )
3660 {
3661         u32     i;
3662
3663         //RTPRINT(FINIT, INIT_IQK, ("Save MAC parameters.\n"));
3664         for( i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++){
3665                 MACBackup[i] =rtw_read8(pAdapter, MACReg[i]);
3666         }
3667         MACBackup[i] = rtw_read32(pAdapter, MACReg[i]);
3668
3669 }
3670
3671 static VOID
3672 _PHY_ReloadADDARegisters(
3673         IN      PADAPTER        pAdapter,
3674         IN      u32*            ADDAReg,
3675         IN      u32*            ADDABackup,
3676         IN      u32                     RegiesterNum
3677         )
3678 {
3679         u32     i;
3680
3681         //RTPRINT(FINIT, INIT_IQK, ("Reload ADDA power saving parameters !\n"));
3682         for(i = 0 ; i < RegiesterNum ; i++){
3683                 PHY_SetBBReg(pAdapter, ADDAReg[i], bMaskDWord, ADDABackup[i]);
3684         }
3685 }
3686
3687 static VOID
3688 _PHY_ReloadMACRegisters(
3689         IN      PADAPTER        pAdapter,
3690         IN      u32*            MACReg,
3691         IN      u32*            MACBackup
3692         )
3693 {
3694         u32     i;
3695
3696         //RTPRINT(FINIT, INIT_IQK, ("Reload MAC parameters !\n"));
3697         for(i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++){
3698                 rtw_write8(pAdapter, MACReg[i], (u8)MACBackup[i]);
3699         }
3700         rtw_write32(pAdapter, MACReg[i], MACBackup[i]);
3701 }
3702
3703 static VOID
3704 _PHY_PathADDAOn(
3705         IN      PADAPTER        pAdapter,
3706         IN      u32*            ADDAReg,
3707         IN      BOOLEAN         isPathAOn,
3708         IN      BOOLEAN         is2T
3709         )
3710 {
3711         u32     pathOn;
3712         u32     i;
3713
3714         //RTPRINT(FINIT, INIT_IQK, ("ADDA ON.\n"));
3715
3716         pathOn = isPathAOn ? 0x04db25a4 : 0x0b1b25a4;
3717         if(_FALSE == is2T){
3718                 pathOn = 0x0bdb25a0;
3719                 PHY_SetBBReg(pAdapter, ADDAReg[0], bMaskDWord, 0x0b1b25a0);
3720         }
3721         else{
3722                 PHY_SetBBReg(pAdapter, ADDAReg[0], bMaskDWord, pathOn);
3723         }
3724
3725         for( i = 1 ; i < IQK_ADDA_REG_NUM ; i++){
3726                 PHY_SetBBReg(pAdapter, ADDAReg[i], bMaskDWord, pathOn);
3727         }
3728
3729 }
3730
3731 static VOID
3732 _PHY_MACSettingCalibration(
3733         IN      PADAPTER        pAdapter,
3734         IN      u32*            MACReg,
3735         IN      u32*            MACBackup
3736         )
3737 {
3738         u32     i = 0;
3739
3740         //RTPRINT(FINIT, INIT_IQK, ("MAC settings for Calibration.\n"));
3741
3742         rtw_write8(pAdapter, MACReg[i], 0x3F);
3743
3744         for(i = 1 ; i < (IQK_MAC_REG_NUM - 1); i++){
3745                 rtw_write8(pAdapter, MACReg[i], (u8)(MACBackup[i]&(~BIT3)));
3746         }
3747         rtw_write8(pAdapter, MACReg[i], (u8)(MACBackup[i]&(~BIT5)));
3748
3749 }
3750
3751 static VOID
3752 _PHY_PathAStandBy(
3753         IN      PADAPTER        pAdapter
3754         )
3755 {
3756         //RTPRINT(FINIT, INIT_IQK, ("Path-A standby mode!\n"));
3757
3758         PHY_SetBBReg(pAdapter, rFPGA0_IQK, bMaskDWord, 0x0);
3759         PHY_SetBBReg(pAdapter, 0x840, bMaskDWord, 0x00010000);
3760         PHY_SetBBReg(pAdapter, rFPGA0_IQK, bMaskDWord, 0x80800000);
3761 }
3762
3763 static VOID
3764 _PHY_PIModeSwitch(
3765         IN      PADAPTER        pAdapter,
3766         IN      BOOLEAN         PIMode
3767         )
3768 {
3769         u32     mode;
3770
3771         //RTPRINT(FINIT, INIT_IQK, ("BB Switch to %s mode!\n", (PIMode ? "PI" : "SI")));
3772
3773         mode = PIMode ? 0x01000100 : 0x01000000;
3774         PHY_SetBBReg(pAdapter, 0x820, bMaskDWord, mode);
3775         PHY_SetBBReg(pAdapter, 0x828, bMaskDWord, mode);
3776 }
3777
3778 /*
3779 return _FALSE => do IQK again
3780 */
3781 static BOOLEAN
3782 _PHY_SimularityCompare(
3783         IN      PADAPTER        pAdapter,
3784         IN      int             result[][8],
3785         IN      u8               c1,
3786         IN      u8               c2
3787         )
3788 {
3789         u32             i, j, diff, SimularityBitMap, bound = 0;
3790         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);
3791         u8              final_candidate[2] = {0xFF, 0xFF};      //for path A and path B
3792         BOOLEAN         bResult = _TRUE, is2T = IS_92C_SERIAL( pHalData->VersionID);
3793
3794         if(is2T)
3795                 bound = 8;
3796         else
3797                 bound = 4;
3798
3799         SimularityBitMap = 0;
3800
3801         for( i = 0; i < bound; i++ )
3802         {
3803                 diff = (result[c1][i] > result[c2][i]) ? (result[c1][i] - result[c2][i]) : (result[c2][i] - result[c1][i]);
3804                 if (diff > MAX_TOLERANCE)
3805                 {
3806                         if((i == 2 || i == 6) && !SimularityBitMap)
3807                         {
3808                                 if(result[c1][i]+result[c1][i+1] == 0)
3809                                         final_candidate[(i/4)] = c2;
3810                                 else if (result[c2][i]+result[c2][i+1] == 0)
3811                                         final_candidate[(i/4)] = c1;
3812                                 else
3813                                         SimularityBitMap = SimularityBitMap|(1<<i);
3814                         }
3815                         else
3816                                 SimularityBitMap = SimularityBitMap|(1<<i);
3817                 }
3818         }
3819
3820         if ( SimularityBitMap == 0)
3821         {
3822                 for( i = 0; i < (bound/4); i++ )
3823                 {
3824                         if(final_candidate[i] != 0xFF)
3825                         {
3826                                 for( j = i*4; j < (i+1)*4-2; j++)
3827                                         result[3][j] = result[final_candidate[i]][j];
3828                                 bResult = _FALSE;
3829                         }
3830                 }
3831                 return bResult;
3832         }
3833         else if (!(SimularityBitMap & 0x0F))                    //path A OK
3834         {
3835                 for(i = 0; i < 4; i++)
3836                         result[3][i] = result[c1][i];
3837                 return _FALSE;
3838         }
3839         else if (!(SimularityBitMap & 0xF0) && is2T)    //path B OK
3840         {
3841                 for(i = 4; i < 8; i++)
3842                         result[3][i] = result[c1][i];
3843                 return _FALSE;
3844         }
3845         else
3846                 return _FALSE;
3847
3848 }
3849
3850 static VOID
3851 _PHY_IQCalibrate(
3852         IN      PADAPTER        pAdapter,
3853         IN      int             result[][8],
3854         IN      u8              t,
3855         IN      BOOLEAN         is2T
3856         )
3857 {
3858         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);
3859         struct dm_priv  *pdmpriv = &pHalData->dmpriv;
3860         u32                     i;
3861         u8                      PathAOK, PathBOK;
3862         u32                     ADDA_REG[IQK_ADDA_REG_NUM] = {
3863                                                 rFPGA0_XCD_SwitchControl,       rBlue_Tooth,
3864                                                 rRx_Wait_CCA,           rTx_CCK_RFON,
3865                                                 rTx_CCK_BBON,   rTx_OFDM_RFON,
3866                                                 rTx_OFDM_BBON,  rTx_To_Rx,
3867                                                 rTx_To_Tx,              rRx_CCK,
3868                                                 rRx_OFDM,               rRx_Wait_RIFS,
3869                                                 rRx_TO_Rx,              rStandby,
3870                                                 rSleep,                         rPMPD_ANAEN };
3871
3872         u32                     IQK_MAC_REG[IQK_MAC_REG_NUM] = {
3873                                                 REG_TXPAUSE,            REG_BCN_CTRL,
3874                                                 REG_BCN_CTRL_1, REG_GPIO_MUXCFG};
3875
3876         u32                     IQK_BB_REG_92C[IQK_BB_REG_NUM] = {
3877                                                         rOFDM0_TRxPathEnable,           rOFDM0_TRMuxPar,
3878                                                         rFPGA0_XCD_RFInterfaceSW,       rConfig_AntA,   rConfig_AntB,
3879                                                         rFPGA0_XAB_RFInterfaceSW,       rFPGA0_XA_RFInterfaceOE,
3880                                                         rFPGA0_XB_RFInterfaceOE,        rFPGA0_RFMOD
3881                                                         };
3882
3883 #if MP_DRIVER
3884         const u32       retryCount = 9;
3885 #else
3886         const u32       retryCount = 2;
3887 #endif
3888
3889         // Note: IQ calibration must be performed after loading
3890         //              PHY_REG.txt , and radio_a, radio_b.txt
3891
3892         u32 bbvalue;
3893
3894         if(t==0)
3895         {
3896                 bbvalue = PHY_QueryBBReg(pAdapter, rFPGA0_RFMOD, bMaskDWord);
3897                 //RTPRINT(FINIT, INIT_IQK, ("PHY_IQCalibrate()==>0x%08lx\n",bbvalue));
3898
3899                 //RTPRINT(FINIT, INIT_IQK, ("IQ Calibration for %s\n", (is2T ? "2T2R" : "1T1R")));
3900
3901                 // Save ADDA parameters, turn Path A ADDA on
3902                 _PHY_SaveADDARegisters(pAdapter, ADDA_REG, pdmpriv->ADDA_backup,IQK_ADDA_REG_NUM);
3903                 _PHY_SaveMACRegisters(pAdapter, IQK_MAC_REG, pdmpriv->IQK_MAC_backup);
3904                 _PHY_SaveADDARegisters(pAdapter, IQK_BB_REG_92C, pdmpriv->IQK_BB_backup, IQK_BB_REG_NUM);
3905         }
3906         _PHY_PathADDAOn(pAdapter, ADDA_REG, _TRUE, is2T);
3907
3908         if(t==0)
3909         {
3910                 pdmpriv->bRfPiEnable = (u8)PHY_QueryBBReg(pAdapter, rFPGA0_XA_HSSIParameter1, BIT(8));
3911         }
3912
3913         if(!pdmpriv->bRfPiEnable){
3914                 // Switch BB to PI mode to do IQ Calibration.
3915                 _PHY_PIModeSwitch(pAdapter, _TRUE);
3916         }
3917
3918         PHY_SetBBReg(pAdapter, rFPGA0_RFMOD, BIT24, 0x00);
3919         PHY_SetBBReg(pAdapter, rOFDM0_TRxPathEnable, bMaskDWord, 0x03a05600);
3920         PHY_SetBBReg(pAdapter, rOFDM0_TRMuxPar, bMaskDWord, 0x000800e4);
3921         PHY_SetBBReg(pAdapter, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22204000);
3922         PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT10, 0x01);
3923         PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFInterfaceSW, BIT26, 0x01);
3924         PHY_SetBBReg(pAdapter, rFPGA0_XA_RFInterfaceOE, BIT10, 0x00);
3925         PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT10, 0x00);
3926
3927         if(is2T)
3928         {
3929                 PHY_SetBBReg(pAdapter, rFPGA0_XA_LSSIParameter, bMaskDWord, 0x00010000);
3930                 PHY_SetBBReg(pAdapter, rFPGA0_XB_LSSIParameter, bMaskDWord, 0x00010000);
3931         }
3932
3933         //MAC settings
3934         _PHY_MACSettingCalibration(pAdapter, IQK_MAC_REG, pdmpriv->IQK_MAC_backup);
3935
3936         //Page B init
3937         PHY_SetBBReg(pAdapter, rConfig_AntA, bMaskDWord, 0x00080000);
3938
3939         if(is2T)
3940         {
3941                 PHY_SetBBReg(pAdapter, rConfig_AntB, bMaskDWord, 0x00080000);
3942         }
3943
3944         // IQ calibration setting
3945         //RTPRINT(FINIT, INIT_IQK, ("IQK setting!\n"));
3946         PHY_SetBBReg(pAdapter, rFPGA0_IQK, bMaskDWord, 0x80800000);
3947         PHY_SetBBReg(pAdapter, rTx_IQK, bMaskDWord, 0x01007c00);
3948         PHY_SetBBReg(pAdapter, rRx_IQK, bMaskDWord, 0x01004800);
3949
3950         for(i = 0 ; i < retryCount ; i++){
3951                 PathAOK = _PHY_PathA_IQK(pAdapter, is2T);
3952                 if(PathAOK == 0x03){
3953                                 DBG_8192C("Path A IQK Success!!\n");
3954                                 result[t][0] = (PHY_QueryBBReg(pAdapter, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16;
3955                                 result[t][1] = (PHY_QueryBBReg(pAdapter, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16;
3956                                 result[t][2] = (PHY_QueryBBReg(pAdapter, rRx_Power_Before_IQK_A_2, bMaskDWord)&0x3FF0000)>>16;
3957                                 result[t][3] = (PHY_QueryBBReg(pAdapter, rRx_Power_After_IQK_A_2, bMaskDWord)&0x3FF0000)>>16;
3958                         break;
3959                 }
3960                 else if (i == (retryCount-1) && PathAOK == 0x01)        //Tx IQK OK
3961                 {
3962                         DBG_8192C("Path A IQK Only  Tx Success!!\n");
3963
3964                         result[t][0] = (PHY_QueryBBReg(pAdapter, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16;
3965                         result[t][1] = (PHY_QueryBBReg(pAdapter, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16;
3966                 }
3967         }
3968
3969         if(0x00 == PathAOK){
3970                 DBG_8192C("Path A IQK failed!!\n");
3971         }
3972
3973         if(is2T){
3974                 _PHY_PathAStandBy(pAdapter);
3975
3976                 // Turn Path B ADDA on
3977                 _PHY_PathADDAOn(pAdapter, ADDA_REG, _FALSE, is2T);
3978
3979                 for(i = 0 ; i < retryCount ; i++){
3980                         PathBOK = _PHY_PathB_IQK(pAdapter);
3981                         if(PathBOK == 0x03){
3982                                 DBG_8192C("Path B IQK Success!!\n");
3983                                 result[t][4] = (PHY_QueryBBReg(pAdapter, rTx_Power_Before_IQK_B, bMaskDWord)&0x3FF0000)>>16;
3984                                 result[t][5] = (PHY_QueryBBReg(pAdapter, rTx_Power_After_IQK_B, bMaskDWord)&0x3FF0000)>>16;
3985                                 result[t][6] = (PHY_QueryBBReg(pAdapter, rRx_Power_Before_IQK_B_2, bMaskDWord)&0x3FF0000)>>16;
3986                                 result[t][7] = (PHY_QueryBBReg(pAdapter, rRx_Power_After_IQK_B_2, bMaskDWord)&0x3FF0000)>>16;
3987                                 break;
3988                         }
3989                         else if (i == (retryCount - 1) && PathBOK == 0x01)      //Tx IQK OK
3990                         {
3991                                 DBG_8192C("Path B Only Tx IQK Success!!\n");
3992                                 result[t][4] = (PHY_QueryBBReg(pAdapter, rTx_Power_Before_IQK_B, bMaskDWord)&0x3FF0000)>>16;
3993                                 result[t][5] = (PHY_QueryBBReg(pAdapter, rTx_Power_After_IQK_B, bMaskDWord)&0x3FF0000)>>16;
3994                         }
3995                 }
3996
3997                 if(0x00 == PathBOK){
3998                         DBG_8192C("Path B IQK failed!!\n");
3999                 }
4000         }
4001
4002         //Back to BB mode, load original value
4003         //RTPRINT(FINIT, INIT_IQK, ("IQK:Back to BB mode, load original value!\n"));
4004         PHY_SetBBReg(pAdapter, rFPGA0_IQK, bMaskDWord, 0);
4005
4006         if(t!=0)
4007         {
4008                 if(!pdmpriv->bRfPiEnable){
4009                         // Switch back BB to SI mode after finish IQ Calibration.
4010                         _PHY_PIModeSwitch(pAdapter, _FALSE);
4011                 }
4012
4013                 // Reload ADDA power saving parameters
4014                 _PHY_ReloadADDARegisters(pAdapter, ADDA_REG, pdmpriv->ADDA_backup, IQK_ADDA_REG_NUM);
4015
4016                 // Reload MAC parameters
4017                 _PHY_ReloadMACRegisters(pAdapter, IQK_MAC_REG, pdmpriv->IQK_MAC_backup);
4018
4019                 // Reload BB parameters
4020                 _PHY_ReloadADDARegisters(pAdapter, IQK_BB_REG_92C, pdmpriv->IQK_BB_backup, IQK_BB_REG_NUM);
4021
4022                 // Restore RX initial gain
4023                 PHY_SetBBReg(pAdapter, rFPGA0_XA_LSSIParameter, bMaskDWord, 0x00032ed3);
4024                 if(is2T){
4025                         PHY_SetBBReg(pAdapter, rFPGA0_XB_LSSIParameter, bMaskDWord, 0x00032ed3);
4026                 }
4027
4028                 //load 0xe30 IQC default value
4029                 PHY_SetBBReg(pAdapter, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00);
4030                 PHY_SetBBReg(pAdapter, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00);
4031
4032         }
4033         //RTPRINT(FINIT, INIT_IQK, ("_PHY_IQCalibrate() <==\n"));
4034
4035 }
4036
4037
4038 static VOID
4039 _PHY_LCCalibrate(
4040         IN      PADAPTER        pAdapter,
4041         IN      BOOLEAN         is2T
4042         )
4043 {
4044         u8      tmpReg;
4045         u32     RF_Amode = 0, RF_Bmode = 0, LC_Cal;
4046
4047         //Check continuous TX and Packet TX
4048         tmpReg = rtw_read8(pAdapter, 0xd03);
4049
4050         if((tmpReg&0x70) != 0)                  //Deal with contisuous TX case
4051                 rtw_write8(pAdapter, 0xd03, tmpReg&0x8F);       //disable all continuous TX
4052         else                                                    // Deal with Packet TX case
4053                 rtw_write8(pAdapter, REG_TXPAUSE, 0xFF);                        // block all queues
4054
4055         if((tmpReg&0x70) != 0)
4056         {
4057                 //1. Read original RF mode
4058                 //Path-A
4059                 RF_Amode = PHY_QueryRFReg(pAdapter, RF_PATH_A, RF_AC, bMask12Bits);
4060
4061                 //Path-B
4062                 if(is2T)
4063                         RF_Bmode = PHY_QueryRFReg(pAdapter, RF_PATH_B, RF_AC, bMask12Bits);
4064
4065                 //2. Set RF mode = standby mode
4066                 //Path-A
4067                 PHY_SetRFReg(pAdapter, RF_PATH_A, RF_AC, bMask12Bits, (RF_Amode&0x8FFFF)|0x10000);
4068
4069                 //Path-B
4070                 if(is2T)
4071                         PHY_SetRFReg(pAdapter, RF_PATH_B, RF_AC, bMask12Bits, (RF_Bmode&0x8FFFF)|0x10000);
4072         }
4073
4074         //3. Read RF reg18
4075         LC_Cal = PHY_QueryRFReg(pAdapter, RF_PATH_A, RF_CHNLBW, bMask12Bits);
4076
4077         //4. Set LC calibration begin
4078         PHY_SetRFReg(pAdapter, RF_PATH_A, RF_CHNLBW, bMask12Bits, LC_Cal|0x08000);
4079
4080         #ifdef CONFIG_LONG_DELAY_ISSUE
4081         rtw_msleep_os(100);
4082         #else
4083         rtw_mdelay_os(100);
4084         #endif
4085
4086         //Restore original situation
4087         if((tmpReg&0x70) != 0)  //Deal with contisuous TX case
4088         {
4089                 //Path-A
4090                 rtw_write8(pAdapter, 0xd03, tmpReg);
4091                 PHY_SetRFReg(pAdapter, RF_PATH_A, RF_AC, bMask12Bits, RF_Amode);
4092
4093                 //Path-B
4094                 if(is2T)
4095                         PHY_SetRFReg(pAdapter, RF_PATH_B, RF_AC, bMask12Bits, RF_Bmode);
4096         }
4097         else // Deal with Packet TX case
4098         {
4099                 rtw_write8(pAdapter, REG_TXPAUSE, 0x00);
4100         }
4101
4102 }
4103
4104
4105 //Analog Pre-distortion calibration
4106 #define         APK_BB_REG_NUM  8
4107 #define         APK_CURVE_REG_NUM 4
4108 #define         PATH_NUM                2
4109
4110 static VOID
4111 _PHY_APCalibrate(
4112         IN      PADAPTER        pAdapter,
4113         IN      char            delta,
4114         IN      BOOLEAN         is2T
4115         )
4116 {
4117         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);
4118         struct dm_priv  *pdmpriv = &pHalData->dmpriv;
4119
4120         u32                     regD[PATH_NUM];
4121         u32                     tmpReg, index, offset, i, apkbound;
4122         u8                      path, pathbound = PATH_NUM;
4123         u32                     BB_backup[APK_BB_REG_NUM];
4124         u32                     BB_REG[APK_BB_REG_NUM] = {
4125                                                 rFPGA1_TxBlock,         rOFDM0_TRxPathEnable,
4126                                                 rFPGA0_RFMOD,   rOFDM0_TRMuxPar,
4127                                                 rFPGA0_XCD_RFInterfaceSW,       rFPGA0_XAB_RFInterfaceSW,
4128                                                 rFPGA0_XA_RFInterfaceOE,        rFPGA0_XB_RFInterfaceOE };
4129         u32                     BB_AP_MODE[APK_BB_REG_NUM] = {
4130                                                 0x00000020, 0x00a05430, 0x02040000,
4131                                                 0x000800e4, 0x00204000 };
4132         u32                     BB_normal_AP_MODE[APK_BB_REG_NUM] = {
4133                                                 0x00000020, 0x00a05430, 0x02040000,
4134                                                 0x000800e4, 0x22204000 };
4135
4136         u32                     AFE_backup[IQK_ADDA_REG_NUM];
4137         u32                     AFE_REG[IQK_ADDA_REG_NUM] = {
4138                                                 rFPGA0_XCD_SwitchControl,       rBlue_Tooth,
4139                                                 rRx_Wait_CCA,           rTx_CCK_RFON,
4140                                                 rTx_CCK_BBON,   rTx_OFDM_RFON,
4141                                                 rTx_OFDM_BBON,  rTx_To_Rx,
4142                                                 rTx_To_Tx,              rRx_CCK,
4143                                                 rRx_OFDM,               rRx_Wait_RIFS,
4144                                                 rRx_TO_Rx,              rStandby,
4145                                                 rSleep,                         rPMPD_ANAEN };
4146
4147         u32                     MAC_backup[IQK_MAC_REG_NUM];
4148         u32                     MAC_REG[IQK_MAC_REG_NUM] = {
4149                                                 REG_TXPAUSE,            REG_BCN_CTRL,
4150                                                 REG_BCN_CTRL_1, REG_GPIO_MUXCFG};
4151
4152         u32                     APK_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = {
4153                                         {0x0852c, 0x1852c, 0x5852c, 0x1852c, 0x5852c},
4154                                         {0x2852e, 0x0852e, 0x3852e, 0x0852e, 0x0852e}
4155                                         };
4156
4157         u32                     APK_normal_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = {
4158                                         {0x0852c, 0x0a52c, 0x3a52c, 0x5a52c, 0x5a52c},  //path settings equal to path b settings
4159                                         {0x0852c, 0x0a52c, 0x5a52c, 0x5a52c, 0x5a52c}
4160                                         };
4161
4162         u32                     APK_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = {
4163                                         {0x52019, 0x52014, 0x52013, 0x5200f, 0x5208d},
4164                                         {0x5201a, 0x52019, 0x52016, 0x52033, 0x52050}
4165                                         };
4166
4167         u32                     APK_normal_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = {
4168                                         {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a},  //path settings equal to path b settings
4169                                         {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a}
4170                                         };
4171 #if 0
4172         u32                     APK_RF_value_A[PATH_NUM][APK_BB_REG_NUM] = {
4173                                         {0x1adb0, 0x1adb0, 0x1ada0, 0x1ad90, 0x1ad80},
4174                                         {0x00fb0, 0x00fb0, 0x00fa0, 0x00f90, 0x00f80}
4175                                         };
4176 #endif
4177         u32                     AFE_on_off[PATH_NUM] = {
4178                                         0x04db25a4, 0x0b1b25a4};        //path A on path B off / path A off path B on
4179
4180         u32                     APK_offset[PATH_NUM] = {
4181                                         rConfig_AntA, rConfig_AntB};
4182
4183         u32                     APK_normal_offset[PATH_NUM] = {
4184                                         rConfig_Pmpd_AntA, rConfig_Pmpd_AntB};
4185
4186         u32                     APK_value[PATH_NUM] = {
4187                                         0x92fc0000, 0x12fc0000};
4188
4189         u32                     APK_normal_value[PATH_NUM] = {
4190                                         0x92680000, 0x12680000};
4191
4192         char                    APK_delta_mapping[APK_BB_REG_NUM][13] = {
4193                                         {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6},
4194                                         {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6},
4195                                         {-6, -4, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6},
4196                                         {-1, -1, -1, -1, -1, -1, 0, 1, 2, 3, 4, 5, 6},
4197                                         {-11, -9, -7, -5, -3, -1, 0, 0, 0, 0, 0, 0, 0}
4198                                         };
4199
4200         u32                     APK_normal_setting_value_1[13] = {
4201                                         0x01017018, 0xf7ed8f84, 0x1b1a1816, 0x2522201e, 0x322e2b28,
4202                                         0x433f3a36, 0x5b544e49, 0x7b726a62, 0xa69a8f84, 0xdfcfc0b3,
4203                                         0x12680000, 0x00880000, 0x00880000
4204                                         };
4205
4206         u32                     APK_normal_setting_value_2[16] = {
4207                                         0x01c7021d, 0x01670183, 0x01000123, 0x00bf00e2, 0x008d00a3,
4208                                         0x0068007b, 0x004d0059, 0x003a0042, 0x002b0031, 0x001f0025,
4209                                         0x0017001b, 0x00110014, 0x000c000f, 0x0009000b, 0x00070008,
4210                                         0x00050006
4211                                         };
4212
4213         u32                     APK_result[PATH_NUM][APK_BB_REG_NUM];   //val_1_1a, val_1_2a, val_2a, val_3a, val_4a
4214         //u32                   AP_curve[PATH_NUM][APK_CURVE_REG_NUM];
4215
4216         int                     BB_offset, delta_V, delta_offset;
4217
4218 #if (MP_DRIVER == 1)
4219         PMPT_CONTEXT    pMptCtx = &pAdapter->mppriv.MptCtx;
4220
4221         pMptCtx->APK_bound[0] = 45;
4222         pMptCtx->APK_bound[1] = 52;
4223 #endif
4224
4225         //RTPRINT(FINIT, INIT_IQK, ("==>PHY_APCalibrate() delta %d\n", delta));
4226
4227         //RTPRINT(FINIT, INIT_IQK, ("AP Calibration for %s %s\n", (is2T ? "2T2R" : "1T1R"), (isNormal ? "Normal chip" : "Test chip")));
4228
4229         if(!is2T)
4230                 pathbound = 1;
4231
4232         //2 FOR NORMAL CHIP SETTINGS
4233
4234 // Temporarily do not allow normal driver to do the following settings because these offset
4235 // and value will cause RF internal PA to be unpredictably disabled by HW, such that RF Tx signal
4236 // will disappear after disable/enable card many times on 88CU. RF SD and DD have not find the
4237 // root cause, so we remove these actions temporarily. Added by tynli and SD3 Allen. 2010.05.31.
4238 #if (MP_DRIVER != 1)
4239         return;
4240 #endif
4241
4242         //settings adjust for normal chip
4243         for(index = 0; index < PATH_NUM; index ++)
4244         {
4245                 APK_offset[index] = APK_normal_offset[index];
4246                 APK_value[index] = APK_normal_value[index];
4247                 AFE_on_off[index] = 0x6fdb25a4;
4248         }
4249
4250         for(index = 0; index < APK_BB_REG_NUM; index ++)
4251         {
4252                 for(path = 0; path < pathbound; path++)
4253                 {
4254                         APK_RF_init_value[path][index] = APK_normal_RF_init_value[path][index];
4255                         APK_RF_value_0[path][index] = APK_normal_RF_value_0[path][index];
4256                 }
4257                 BB_AP_MODE[index] = BB_normal_AP_MODE[index];
4258         }
4259
4260         apkbound = 6;
4261
4262         //save BB default value
4263         for(index = 0; index < APK_BB_REG_NUM ; index++)
4264         {
4265                 if(index == 0)          //skip
4266                         continue;
4267                 BB_backup[index] = PHY_QueryBBReg(pAdapter, BB_REG[index], bMaskDWord);
4268         }
4269
4270         //save MAC default value
4271         _PHY_SaveMACRegisters(pAdapter, MAC_REG, MAC_backup);
4272
4273         //save AFE default value
4274         _PHY_SaveADDARegisters(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);
4275
4276         for(path = 0; path < pathbound; path++)
4277         {
4278                 if(path == RF_PATH_A)
4279                 {
4280                         //path A APK
4281                         //load APK setting
4282                         //path-A
4283                         offset = rPdp_AntA;
4284                         for(index = 0; index < 11; index ++)
4285                         {
4286                                 PHY_SetBBReg(pAdapter, offset, bMaskDWord, APK_normal_setting_value_1[index]);
4287                                 //RTPRINT(FINIT, INIT_IQK, ("PHY_APCalibrate() offset 0x%x value 0x%x\n", offset, PHY_QueryBBReg(pAdapter, offset, bMaskDWord)));
4288
4289                                 offset += 0x04;
4290                         }
4291
4292                         PHY_SetBBReg(pAdapter, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000);
4293
4294                         offset = rConfig_AntA;
4295                         for(; index < 13; index ++)
4296                         {
4297                                 PHY_SetBBReg(pAdapter, offset, bMaskDWord, APK_normal_setting_value_1[index]);
4298                                 //RTPRINT(FINIT, INIT_IQK, ("PHY_APCalibrate() offset 0x%x value 0x%x\n", offset, PHY_QueryBBReg(pAdapter, offset, bMaskDWord)));
4299
4300                                 offset += 0x04;
4301                         }
4302
4303                         //page-B1
4304                         PHY_SetBBReg(pAdapter, rFPGA0_IQK, bMaskDWord, 0x40000000);
4305
4306                         //path A
4307                         offset = rPdp_AntA;
4308                         for(index = 0; index < 16; index++)
4309                         {
4310                                 PHY_SetBBReg(pAdapter, offset, bMaskDWord, APK_normal_setting_value_2[index]);
4311                                 //RTPRINT(FINIT, INIT_IQK, ("PHY_APCalibrate() offset 0x%x value 0x%x\n", offset, PHY_QueryBBReg(pAdapter, offset, bMaskDWord)));
4312
4313                                 offset += 0x04;
4314                         }
4315                         PHY_SetBBReg(pAdapter, rFPGA0_IQK, bMaskDWord, 0x00000000);
4316                 }
4317                 else if(path == RF_PATH_B)
4318                 {
4319                         //path B APK
4320                         //load APK setting
4321                         //path-B
4322                         offset = rPdp_AntB;
4323                         for(index = 0; index < 10; index ++)
4324                         {
4325                                 PHY_SetBBReg(pAdapter, offset, bMaskDWord, APK_normal_setting_value_1[index]);
4326                                 //RTPRINT(FINIT, INIT_IQK, ("PHY_APCalibrate() offset 0x%x value 0x%x\n", offset, PHY_QueryBBReg(pAdapter, offset, bMaskDWord)));
4327
4328                                 offset += 0x04;
4329                         }
4330                         PHY_SetBBReg(pAdapter, rConfig_Pmpd_AntA, bMaskDWord, 0x12680000);
4331
4332                         PHY_SetBBReg(pAdapter, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000);
4333
4334                         offset = rConfig_AntA;
4335                         index = 11;
4336                         for(; index < 13; index ++) //offset 0xb68, 0xb6c
4337                         {
4338                                 PHY_SetBBReg(pAdapter, offset, bMaskDWord, APK_normal_setting_value_1[index]);
4339                                 //RTPRINT(FINIT, INIT_IQK, ("PHY_APCalibrate() offset 0x%x value 0x%x\n", offset, PHY_QueryBBReg(pAdapter, offset, bMaskDWord)));
4340
4341                                 offset += 0x04;
4342                         }
4343
4344                         //page-B1
4345                         PHY_SetBBReg(pAdapter, rFPGA0_IQK, bMaskDWord, 0x40000000);
4346
4347                         //path B
4348                         offset = 0xb60;
4349                         for(index = 0; index < 16; index++)
4350                         {
4351                                 PHY_SetBBReg(pAdapter, offset, bMaskDWord, APK_normal_setting_value_2[index]);
4352                                 //RTPRINT(FINIT, INIT_IQK, ("PHY_APCalibrate() offset 0x%x value 0x%x\n", offset, PHY_QueryBBReg(pAdapter, offset, bMaskDWord)));
4353
4354                                 offset += 0x04;
4355                         }
4356                         PHY_SetBBReg(pAdapter, rFPGA0_IQK, bMaskDWord, 0x00000000);
4357                 }
4358
4359                 //save RF default value
4360                 regD[path] = PHY_QueryRFReg(pAdapter, (RF_RADIO_PATH_E)path, RF_TXBIAS_A, bRFRegOffsetMask);
4361
4362                 //Path A AFE all on, path B AFE All off or vise versa
4363                 for(index = 0; index < IQK_ADDA_REG_NUM ; index++)
4364                         PHY_SetBBReg(pAdapter, AFE_REG[index], bMaskDWord, AFE_on_off[path]);
4365                 //RTPRINT(FINIT, INIT_IQK, ("PHY_APCalibrate() offset 0xe70 %x\n", PHY_QueryBBReg(pAdapter, 0xe70, bMaskDWord)));
4366
4367                 //BB to AP mode
4368                 if(path == 0)
4369                 {
4370                         for(index = 0; index < APK_BB_REG_NUM ; index++)
4371                         {
4372                                 if(index == 0)          //skip
4373                                         continue;
4374                                 else if (index < 5)
4375                                         PHY_SetBBReg(pAdapter, BB_REG[index], bMaskDWord, BB_AP_MODE[index]);
4376                                 else if (BB_REG[index] == 0x870)
4377                                         PHY_SetBBReg(pAdapter, BB_REG[index], bMaskDWord, BB_backup[index]|BIT10|BIT26);
4378                                 else
4379                                         PHY_SetBBReg(pAdapter, BB_REG[index], BIT10, 0x0);
4380                         }
4381                         PHY_SetBBReg(pAdapter, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00);
4382                         PHY_SetBBReg(pAdapter, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00);
4383                 }
4384                 else            //path B
4385                 {
4386                         PHY_SetBBReg(pAdapter, rTx_IQK_Tone_B, bMaskDWord, 0x01008c00);
4387                         PHY_SetBBReg(pAdapter, rRx_IQK_Tone_B, bMaskDWord, 0x01008c00);
4388                 }
4389
4390                 //RTPRINT(FINIT, INIT_IQK, ("PHY_APCalibrate() offset 0x800 %x\n", PHY_QueryBBReg(pAdapter, 0x800, bMaskDWord)));
4391
4392                 //MAC settings
4393                 _PHY_MACSettingCalibration(pAdapter, MAC_REG, MAC_backup);
4394
4395                 if(path == RF_PATH_A)   //Path B to standby mode
4396                 {
4397                         PHY_SetRFReg(pAdapter, RF_PATH_B, RF_AC, bRFRegOffsetMask, 0x10000);
4398                 }
4399                 else                    //Path A to standby mode
4400                 {
4401                         PHY_SetRFReg(pAdapter, RF_PATH_A, RF_AC, bRFRegOffsetMask, 0x10000);
4402                         PHY_SetRFReg(pAdapter, RF_PATH_A, RF_MODE1, bRFRegOffsetMask, 0x1000f);
4403                         PHY_SetRFReg(pAdapter, RF_PATH_A, RF_MODE2, bRFRegOffsetMask, 0x20103);
4404                 }
4405
4406                 delta_offset = ((delta+14)/2);
4407                 if(delta_offset < 0)
4408                         delta_offset = 0;
4409                 else if (delta_offset > 12)
4410                         delta_offset = 12;
4411
4412                 //AP calibration
4413                 for(index = 0; index < APK_BB_REG_NUM; index++)
4414                 {
4415                         if(index != 1)          //only DO PA11+PAD01001, AP RF setting
4416                                 continue;
4417
4418                         tmpReg = APK_RF_init_value[path][index];
4419 #if 1
4420                         if(!pdmpriv->bAPKThermalMeterIgnore)
4421                         {
4422                                 BB_offset = (tmpReg & 0xF0000) >> 16;
4423
4424                                 if(!(tmpReg & BIT15)) //sign bit 0
4425                                 {
4426                                         BB_offset = -BB_offset;
4427                                 }
4428
4429                                 delta_V = APK_delta_mapping[index][delta_offset];
4430
4431                                 BB_offset += delta_V;
4432
4433                                 //RTPRINT(FINIT, INIT_IQK, ("PHY_APCalibrate() APK num %d delta_V %d delta_offset %d\n", index, delta_V, delta_offset));
4434
4435                                 if(BB_offset < 0)
4436                                 {
4437                                         tmpReg = tmpReg & (~BIT15);
4438                                         BB_offset = -BB_offset;
4439                                 }
4440                                 else
4441                                 {
4442                                         tmpReg = tmpReg | BIT15;
4443                                 }
4444                                 tmpReg = (tmpReg & 0xFFF0FFFF) | (BB_offset << 16);
4445                         }
4446 #endif
4447
4448 #ifdef CONFIG_PCI_HCI
4449                         if(IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID))
4450                                 PHY_SetRFReg(pAdapter, (RF_RADIO_PATH_E)path, RF_IPA_A, bRFRegOffsetMask, 0x894ae);
4451                         else
4452 #endif
4453                                 PHY_SetRFReg(pAdapter, (RF_RADIO_PATH_E)path, RF_IPA_A, bRFRegOffsetMask, 0x8992e);
4454                         //RTPRINT(FINIT, INIT_IQK, ("PHY_APCalibrate() offset 0xc %x\n", PHY_QueryRFReg(pAdapter, (RF_RADIO_PATH_E)path, 0xc, bMaskDWord)));
4455                         PHY_SetRFReg(pAdapter, (RF_RADIO_PATH_E)path, RF_AC, bRFRegOffsetMask, APK_RF_value_0[path][index]);
4456                         //RTPRINT(FINIT, INIT_IQK, ("PHY_APCalibrate() offset 0x0 %x\n", PHY_QueryRFReg(pAdapter, (RF_RADIO_PATH_E)path, 0x0, bMaskDWord)));
4457                         PHY_SetRFReg(pAdapter, (RF_RADIO_PATH_E)path, RF_TXBIAS_A, bRFRegOffsetMask, tmpReg);
4458                         //RTPRINT(FINIT, INIT_IQK, ("PHY_APCalibrate() offset 0xd %x\n", PHY_QueryRFReg(pAdapter, (RF_RADIO_PATH_E)path, 0xd, bMaskDWord)));
4459
4460                         // PA11+PAD01111, one shot
4461                         i = 0;
4462                         do
4463                         {
4464                                 PHY_SetBBReg(pAdapter, rFPGA0_IQK, bMaskDWord, 0x80000000);
4465                                 {
4466                                         PHY_SetBBReg(pAdapter, APK_offset[path], bMaskDWord, APK_value[0]);
4467                                         //RTPRINT(FINIT, INIT_IQK, ("PHY_APCalibrate() offset 0x%x value 0x%x\n", APK_offset[path], PHY_QueryBBReg(pAdapter, APK_offset[path], bMaskDWord)));
4468                                         rtw_mdelay_os(3);
4469                                         PHY_SetBBReg(pAdapter, APK_offset[path], bMaskDWord, APK_value[1]);
4470                                         //RTPRINT(FINIT, INIT_IQK, ("PHY_APCalibrate() offset 0x%x value 0x%x\n", APK_offset[path], PHY_QueryBBReg(pAdapter, APK_offset[path], bMaskDWord)));
4471                                         #ifdef CONFIG_LONG_DELAY_ISSUE
4472                                         rtw_msleep_os(20);
4473                                         #else
4474                                         rtw_mdelay_os(20);
4475                                         #endif
4476                                 }
4477                                 PHY_SetBBReg(pAdapter, rFPGA0_IQK, bMaskDWord, 0x00000000);
4478
4479                                 if(path == RF_PATH_A)
4480                                         tmpReg = PHY_QueryBBReg(pAdapter, rAPK, 0x03E00000);
4481                                 else
4482                                         tmpReg = PHY_QueryBBReg(pAdapter, rAPK, 0xF8000000);
4483                                 //RTPRINT(FINIT, INIT_IQK, ("PHY_APCalibrate() offset 0xbd8[25:21] %x\n", tmpReg));
4484
4485                                 i++;
4486                         }
4487                         while(tmpReg > apkbound && i < 4);
4488
4489                         APK_result[path][index] = tmpReg;
4490                 }
4491         }
4492
4493         //reload MAC default value
4494         _PHY_ReloadMACRegisters(pAdapter, MAC_REG, MAC_backup);
4495
4496         //reload BB default value
4497         for(index = 0; index < APK_BB_REG_NUM ; index++)
4498         {
4499                 if(index == 0)          //skip
4500                         continue;
4501                 PHY_SetBBReg(pAdapter, BB_REG[index], bMaskDWord, BB_backup[index]);
4502         }
4503
4504         //reload AFE default value
4505         _PHY_ReloadADDARegisters(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);
4506
4507         //reload RF path default value
4508         for(path = 0; path < pathbound; path++)
4509         {
4510                 PHY_SetRFReg(pAdapter, (RF_RADIO_PATH_E)path, RF_TXBIAS_A, bRFRegOffsetMask, regD[path]);
4511                 if(path == RF_PATH_B)
4512                 {
4513                         PHY_SetRFReg(pAdapter, RF_PATH_A, RF_MODE1, bRFRegOffsetMask, 0x1000f);
4514                         PHY_SetRFReg(pAdapter, RF_PATH_A, RF_MODE2, bRFRegOffsetMask, 0x20101);
4515                 }
4516
4517                 //note no index == 0
4518                 if (APK_result[path][1] > 6)
4519                         APK_result[path][1] = 6;
4520                 //RTPRINT(FINIT, INIT_IQK, ("apk path %d result %d 0x%x \t", path, 1, APK_result[path][1]));
4521         }
4522
4523         //RTPRINT(FINIT, INIT_IQK, ("\n"));
4524
4525
4526         for(path = 0; path < pathbound; path++)
4527         {
4528                 PHY_SetRFReg(pAdapter, (RF_RADIO_PATH_E)path, RF_BS_PA_APSET_G1_G4, bRFRegOffsetMask,
4529                 ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (APK_result[path][1] << 5) | APK_result[path][1]));
4530                 if(path == RF_PATH_A)
4531                         PHY_SetRFReg(pAdapter, (RF_RADIO_PATH_E)path, RF_BS_PA_APSET_G5_G8, bRFRegOffsetMask,
4532                         ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x00 << 5) | 0x05));
4533                 else
4534                         PHY_SetRFReg(pAdapter, (RF_RADIO_PATH_E)path, RF_BS_PA_APSET_G5_G8, bRFRegOffsetMask,
4535                         ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x02 << 5) | 0x05));
4536                 PHY_SetRFReg(pAdapter, (RF_RADIO_PATH_E)path, RF_BS_PA_APSET_G9_G11, bRFRegOffsetMask,
4537                 ((0x08 << 15) | (0x08 << 10) | (0x08 << 5) | 0x08));
4538         }
4539
4540         pdmpriv->bAPKdone = _TRUE;
4541
4542         //RTPRINT(FINIT, INIT_IQK, ("<==PHY_APCalibrate()\n"));
4543 }
4544
4545 static VOID _PHY_SetRFPathSwitch(
4546         IN      PADAPTER        pAdapter,
4547         IN      BOOLEAN         bMain,
4548         IN      BOOLEAN         is2T
4549         )
4550 {
4551         u8      u1bTmp;
4552
4553         if(!pAdapter->hw_init_completed)
4554         {
4555                 u1bTmp = rtw_read8(pAdapter, REG_LEDCFG2) | BIT7;
4556                 rtw_write8(pAdapter, REG_LEDCFG2, u1bTmp);
4557                 //PHY_SetBBReg(pAdapter, REG_LEDCFG0, BIT23, 0x01);
4558                 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT13, 0x01);
4559         }
4560
4561         if(is2T)
4562         {
4563                 if(bMain)
4564                         PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6, 0x1);        //92C_Path_A
4565                 else
4566                         PHY_SetBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6, 0x2);        //BT
4567         }
4568         else
4569         {
4570
4571                 if(bMain)
4572                         PHY_SetBBReg(pAdapter, rFPGA0_XA_RFInterfaceOE, 0x300, 0x2);    //Main
4573                 else
4574                         PHY_SetBBReg(pAdapter, rFPGA0_XA_RFInterfaceOE, 0x300, 0x1);    //Aux
4575         }
4576
4577 }
4578
4579 //return value TRUE => Main; FALSE => Aux
4580
4581 static BOOLEAN _PHY_QueryRFPathSwitch(
4582         IN      PADAPTER        pAdapter,
4583         IN      BOOLEAN         is2T
4584         )
4585 {
4586 //      if(is2T)
4587 //              return _TRUE;
4588
4589         if(!pAdapter->hw_init_completed)
4590         {
4591                 PHY_SetBBReg(pAdapter, REG_LEDCFG0, BIT23, 0x01);
4592                 PHY_SetBBReg(pAdapter, rFPGA0_XAB_RFParameter, BIT13, 0x01);
4593         }
4594
4595         if(is2T)
4596         {
4597                 if(PHY_QueryBBReg(pAdapter, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6) == 0x01)
4598                         return _TRUE;
4599                 else
4600                         return _FALSE;
4601         }
4602         else
4603         {
4604                 if(PHY_QueryBBReg(pAdapter, rFPGA0_XA_RFInterfaceOE, 0x300) == 0x02)
4605                         return _TRUE;
4606                 else
4607                         return _FALSE;
4608         }
4609 }
4610
4611 VOID
4612 rtl8192c_PHY_IQCalibrate(
4613         IN      PADAPTER        pAdapter,
4614         IN      BOOLEAN         bReCovery
4615         )
4616 {
4617         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);
4618         struct dm_priv  *pdmpriv = &pHalData->dmpriv;
4619         s32                     result[4][8];   //last is final result
4620         u8                      i, final_candidate;
4621         BOOLEAN         bPathAOK, bPathBOK;
4622         s32                     RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC, RegTmp = 0;
4623         BOOLEAN         is12simular, is13simular, is23simular;
4624         BOOLEAN         bStartContTx = _FALSE, bSingleTone = _FALSE, bCarrierSuppression = _FALSE;
4625         u32                     IQK_BB_REG_92C[IQK_BB_REG_NUM] = {
4626                                         rOFDM0_XARxIQImbalance,         rOFDM0_XBRxIQImbalance,
4627                                         rOFDM0_ECCAThreshold,   rOFDM0_AGCRSSITable,
4628                                         rOFDM0_XATxIQImbalance,         rOFDM0_XBTxIQImbalance,
4629                                         rOFDM0_XCTxAFE,                         rOFDM0_XDTxAFE,
4630                                         rOFDM0_RxIQExtAnta};
4631
4632
4633 #if MP_DRIVER == 1
4634         bStartContTx = pAdapter->mppriv.MptCtx.bStartContTx;
4635         bSingleTone = pAdapter->mppriv.MptCtx.bSingleTone;
4636         bCarrierSuppression = pAdapter->mppriv.MptCtx.bCarrierSuppression;
4637 #endif
4638
4639         //ignore IQK when continuous Tx
4640         if(bStartContTx || bSingleTone || bCarrierSuppression)
4641                 return;
4642
4643 #if DISABLE_BB_RF
4644         return;
4645 #endif
4646
4647         if(bReCovery)
4648         {
4649                 _PHY_ReloadADDARegisters(pAdapter, IQK_BB_REG_92C, pdmpriv->IQK_BB_backup_recover, 9);
4650                 return;
4651         }
4652         DBG_8192C("IQK:Start!!!\n");
4653
4654         for(i = 0; i < 8; i++)
4655         {
4656                 result[0][i] = 0;
4657                 result[1][i] = 0;
4658                 result[2][i] = 0;
4659                 result[3][i] = 0;
4660         }
4661         final_candidate = 0xff;
4662         bPathAOK = _FALSE;
4663         bPathBOK = _FALSE;
4664         is12simular = _FALSE;
4665         is23simular = _FALSE;
4666         is13simular = _FALSE;
4667
4668         for (i=0; i<3; i++)
4669         {
4670                 if(IS_92C_SERIAL( pHalData->VersionID)){
4671                          _PHY_IQCalibrate(pAdapter, result, i, _TRUE);
4672                 }
4673                 else{
4674                         // For 88C 1T1R
4675                         _PHY_IQCalibrate(pAdapter, result, i, _FALSE);
4676                 }
4677
4678                 if(i == 1)
4679                 {
4680                         is12simular = _PHY_SimularityCompare(pAdapter, result, 0, 1);
4681                         if(is12simular)
4682                         {
4683                                 final_candidate = 0;
4684                                 break;
4685                         }
4686                 }
4687
4688                 if(i == 2)
4689                 {
4690                         is13simular = _PHY_SimularityCompare(pAdapter, result, 0, 2);
4691                         if(is13simular)
4692                         {
4693                                 final_candidate = 0;
4694                                 break;
4695                         }
4696
4697                         is23simular = _PHY_SimularityCompare(pAdapter, result, 1, 2);
4698                         if(is23simular)
4699                                 final_candidate = 1;
4700                         else
4701                         {
4702                                 for(i = 0; i < 8; i++)
4703                                         RegTmp += result[3][i];
4704
4705                                 if(RegTmp != 0)
4706                                         final_candidate = 3;
4707                                 else
4708                                         final_candidate = 0xFF;
4709                         }
4710                 }
4711         }
4712
4713         for (i=0; i<4; i++)
4714         {
4715                 RegE94 = result[i][0];
4716                 RegE9C = result[i][1];
4717                 RegEA4 = result[i][2];
4718                 RegEAC = result[i][3];
4719                 RegEB4 = result[i][4];
4720                 RegEBC = result[i][5];
4721                 RegEC4 = result[i][6];
4722                 RegECC = result[i][7];
4723                 //RTPRINT(FINIT, INIT_IQK, ("IQK: RegE94=%lx RegE9C=%lx RegEA4=%lx RegEAC=%lx RegEB4=%lx RegEBC=%lx RegEC4=%lx RegECC=%lx\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC));
4724         }
4725
4726         if(final_candidate != 0xff)
4727         {
4728                 pdmpriv->RegE94 = RegE94 = result[final_candidate][0];
4729                 pdmpriv->RegE9C = RegE9C = result[final_candidate][1];
4730                 RegEA4 = result[final_candidate][2];
4731                 RegEAC = result[final_candidate][3];
4732                 pdmpriv->RegEB4 = RegEB4 = result[final_candidate][4];
4733                 pdmpriv->RegEBC = RegEBC = result[final_candidate][5];
4734                 RegEC4 = result[final_candidate][6];
4735                 RegECC = result[final_candidate][7];
4736                 DBG_8192C("IQK: final_candidate is %x\n", final_candidate);
4737                 DBG_8192C("IQK: RegE94=%x RegE9C=%x RegEA4=%x RegEAC=%x RegEB4=%x RegEBC=%x RegEC4=%x RegECC=%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC);
4738                 bPathAOK = bPathBOK = _TRUE;
4739         }
4740         else
4741         {
4742                 RegE94 = RegEB4 = pdmpriv->RegE94 = pdmpriv->RegEB4 = 0x100;    //X default value
4743                 RegE9C = RegEBC = pdmpriv->RegE9C = pdmpriv->RegEBC = 0x0;              //Y default value
4744         }
4745
4746         if((RegE94 != 0)/*&&(RegEA4 != 0)*/)
4747                 _PHY_PathAFillIQKMatrix(pAdapter, bPathAOK, result, final_candidate, (RegEA4 == 0));
4748
4749         if(IS_92C_SERIAL( pHalData->VersionID)){
4750                 if((RegEB4 != 0)/*&&(RegEC4 != 0)*/)
4751                 _PHY_PathBFillIQKMatrix(pAdapter, bPathBOK, result, final_candidate, (RegEC4 == 0));
4752         }
4753
4754         _PHY_SaveADDARegisters(pAdapter, IQK_BB_REG_92C, pdmpriv->IQK_BB_backup_recover, 9);
4755
4756 }
4757
4758
4759 VOID
4760 rtl8192c_PHY_LCCalibrate(
4761         IN      PADAPTER        pAdapter
4762         )
4763 {
4764         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);
4765         struct mlme_ext_priv    *pmlmeext = &pAdapter->mlmeextpriv;
4766         BOOLEAN         bStartContTx = _FALSE, bSingleTone = _FALSE, bCarrierSuppression = _FALSE;
4767
4768 #if MP_DRIVER == 1
4769         bStartContTx = pAdapter->mppriv.MptCtx.bStartContTx;
4770         bSingleTone = pAdapter->mppriv.MptCtx.bSingleTone;
4771         bCarrierSuppression = pAdapter->mppriv.MptCtx.bCarrierSuppression;
4772 #endif
4773
4774 #if DISABLE_BB_RF
4775         return;
4776 #endif
4777
4778         //ignore IQK when continuous Tx
4779         if(bStartContTx || bSingleTone || bCarrierSuppression)
4780                 return;
4781
4782         if(pmlmeext->sitesurvey_res.state == SCAN_PROCESS)
4783                 return;
4784
4785         if(IS_92C_SERIAL( pHalData->VersionID)){
4786                 _PHY_LCCalibrate(pAdapter, _TRUE);
4787         }
4788         else{
4789                 // For 88C 1T1R
4790                 _PHY_LCCalibrate(pAdapter, _FALSE);
4791         }
4792 }
4793
4794 VOID
4795 rtl8192c_PHY_APCalibrate(
4796         IN      PADAPTER        pAdapter,
4797         IN      char            delta
4798         )
4799 {
4800         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);
4801         struct dm_priv  *pdmpriv = &pHalData->dmpriv;
4802
4803         //default disable APK, because Tx NG issue, suggest by Jenyu, 2011.11.25
4804         return;
4805
4806 #if DISABLE_BB_RF
4807         return;
4808 #endif
4809
4810         if(pdmpriv->bAPKdone)
4811                 return;
4812
4813         if(IS_92C_SERIAL( pHalData->VersionID)){
4814                 _PHY_APCalibrate(pAdapter, delta, _TRUE);
4815         }
4816         else{
4817                 // For 88C 1T1R
4818                 _PHY_APCalibrate(pAdapter, delta, _FALSE);
4819         }
4820 }
4821
4822 VOID rtl8192c_PHY_SetRFPathSwitch(
4823         IN      PADAPTER        pAdapter,
4824         IN      BOOLEAN         bMain
4825         )
4826 {
4827         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);
4828
4829 #if DISABLE_BB_RF
4830         return;
4831 #endif
4832
4833         if(IS_92C_SERIAL( pHalData->VersionID)){
4834                 _PHY_SetRFPathSwitch(pAdapter, bMain, _TRUE);
4835         }
4836         else{
4837                 // For 88C 1T1R
4838                 _PHY_SetRFPathSwitch(pAdapter, bMain, _FALSE);
4839         }
4840 }
4841