drivers/net/wireless/rtl8192c/include/rtl8192d_dm.h

   1 /******************************************************************************\r
   2  *\r
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.\r
   4  *                                        \r
   5  * This program is free software; you can redistribute it and/or modify it\r
   6  * under the terms of version 2 of the GNU General Public License as\r
   7  * published by the Free Software Foundation.\r
   8  *\r
   9  * This program is distributed in the hope that it will be useful, but WITHOUT\r
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
  12  * more details.\r
  13  *\r
  14  * You should have received a copy of the GNU General Public License along with\r
  15  * this program; if not, write to the Free Software Foundation, Inc.,\r
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA\r
  17  *\r
  18  *\r
  19  \r
  20 ******************************************************************************/\r
  21 #ifndef __RTL8192D_DM_H__\r
  22 #define __RTL8192D_DM_H__\r
  23 //============================================================\r
  24 // Description:\r
  25 //\r
  26 // This file is for 92CE/92CU dynamic mechanism only\r
  27 //\r
  28 //\r
  29 //============================================================\r
  30 //============================================================\r
  31 // Global var\r
  32 //============================================================\r
  33 \r
  34 extern u32 EDCAParam[maxAP][3] ;\r
  35 \r
  36 #define OFDM_TABLE_SIZE         37\r
  37 #define OFDM_TABLE_SIZE_92D     43\r
  38 #define CCK_TABLE_SIZE          33\r
  39 extern u32 OFDMSwingTable[OFDM_TABLE_SIZE_92D] ;\r
  40 \r
  41 extern u8 CCKSwingTable_Ch1_Ch13[CCK_TABLE_SIZE][8];\r
  42 \r
  43 extern u8 CCKSwingTable_Ch14 [CCK_TABLE_SIZE][8];\r
  44 \r
  45 //============================================================\r
  46 // structure and define\r
  47 //============================================================\r
  48 \r
  49 typedef struct _FALSE_ALARM_STATISTICS{\r
  50         u32     Cnt_Parity_Fail;\r
  51         u32     Cnt_Rate_Illegal;\r
  52         u32     Cnt_Crc8_fail;\r
  53         u32     Cnt_Mcs_fail;\r
  54         u32     Cnt_Ofdm_fail;\r
  55         u32     Cnt_Cck_fail;\r
  56         u32     Cnt_all;\r
  57         u32     Cnt_Fast_Fsync;\r
  58         u32     Cnt_SB_Search_fail;\r
  59 }FALSE_ALARM_STATISTICS, *PFALSE_ALARM_STATISTICS;\r
  60 \r
  61 typedef struct _Dynamic_Power_Saving_\r
  62 {\r
  63         u8              PreCCAState;\r
  64         u8              CurCCAState;\r
  65 \r
  66         u8              PreRFState;\r
  67         u8              CurRFState;\r
  68 \r
  69         //int           Rssi_val_min;\r
  70         \r
  71 }PS_T,*pPS_T;\r
  72 \r
  73 typedef struct _Dynamic_Initial_Gain_Threshold_\r
  74 {\r
  75         u8              Dig_Enable_Flag;\r
  76         u8              Dig_Ext_Port_Stage;\r
  77         \r
  78         int             RssiLowThresh;\r
  79         int             RssiHighThresh;\r
  80 \r
  81         u32             FALowThresh;\r
  82         u32             FAHighThresh;\r
  83 \r
  84         u8              CurSTAConnectState;\r
  85         u8              PreSTAConnectState;\r
  86         u8              CurMultiSTAConnectState;\r
  87 \r
  88         u8              PreIGValue;\r
  89         u8              CurIGValue;\r
  90 \r
  91         char            BackoffVal;\r
  92         char            BackoffVal_range_max;\r
  93         char            BackoffVal_range_min;\r
  94         u8              rx_gain_range_max;\r
  95         u8              rx_gain_range_min;\r
  96         u8              Rssi_val_min;\r
  97 \r
  98         u8              PreCCKPDState;\r
  99         u8              CurCCKPDState;\r
 100 \r
 101         u8              LargeFAHit;\r
 102         u8              ForbiddenIGI;\r
 103         u32             Recover_cnt;\r
 104 }DIG_T,*pDIG_T;\r
 105 typedef enum tag_Dynamic_Init_Gain_Operation_Type_Definition\r
 106 {\r
 107         DIG_TYPE_THRESH_HIGH    = 0,\r
 108         DIG_TYPE_THRESH_LOW     = 1,\r
 109         DIG_TYPE_BACKOFF                = 2,\r
 110         DIG_TYPE_RX_GAIN_MIN    = 3,\r
 111         DIG_TYPE_RX_GAIN_MAX    = 4,\r
 112         DIG_TYPE_ENABLE                 = 5,\r
 113         DIG_TYPE_DISABLE                = 6,\r
 114         DIG_OP_TYPE_MAX\r
 115 }DM_DIG_OP_E;\r
 116 \r
 117 typedef enum tag_CCK_Packet_Detection_Threshold_Type_Definition\r
 118 {\r
 119         CCK_PD_STAGE_LowRssi = 0,\r
 120         CCK_PD_STAGE_HighRssi = 1,\r
 121         CCK_PD_STAGE_MAX = 3,\r
 122 }DM_CCK_PDTH_E;\r
 123 \r
 124 typedef enum tag_1R_CCA_Type_Definition\r
 125 {\r
 126         CCA_MIN = 0,\r
 127         CCA_1R =1,\r
 128         CCA_2R = 2,\r
 129         CCA_MAX = 3,\r
 130 }DM_1R_CCA_E;\r
 131 \r
 132 typedef enum tag_RF_Type_Definition\r
 133 {\r
 134         RF_Save =0,\r
 135         RF_Normal = 1,\r
 136         RF_MAX = 2,\r
 137 }DM_RF_E;\r
 138 \r
 139 typedef enum tag_DIG_EXT_PORT_ALGO_Definition\r
 140 {\r
 141         DIG_EXT_PORT_STAGE_0 = 0,\r
 142         DIG_EXT_PORT_STAGE_1 = 1,\r
 143         DIG_EXT_PORT_STAGE_2 = 2,\r
 144         DIG_EXT_PORT_STAGE_3 = 3,\r
 145         DIG_EXT_PORT_STAGE_MAX = 4,\r
 146 }DM_DIG_EXT_PORT_ALG_E;\r
 147 \r
 148 \r
 149 typedef enum tag_DIG_Connect_Definition\r
 150 {\r
 151         DIG_STA_DISCONNECT = 0, \r
 152         DIG_STA_CONNECT = 1,\r
 153         DIG_STA_BEFORE_CONNECT = 2,\r
 154         DIG_MultiSTA_DISCONNECT = 3,\r
 155         DIG_MultiSTA_CONNECT = 4,\r
 156         DIG_CONNECT_MAX\r
 157 }DM_DIG_CONNECT_E;\r
 158 \r
 159 \r
 160 #define         DM_DIG_THRESH_HIGH                      40\r
 161 #define         DM_DIG_THRESH_LOW                       35\r
 162 \r
 163 #define         DM_FALSEALARM_THRESH_LOW        400\r
 164 #define         DM_FALSEALARM_THRESH_HIGH       1000\r
 165 \r
 166 #define         DM_DIG_MAX                                      0x3e\r
 167 #define         DM_DIG_MIN                                      0x1e //0x22//0x1c\r
 168 \r
 169 #define         DM_DIG_FA_UPPER                         0x32\r
 170 #define         DM_DIG_FA_LOWER                         0x20\r
 171 \r
 172 //vivi 92c&92d has different definition, 20110504\r
 173 //this is for 92c\r
 174 #define         DM_DIG_FA_TH0                           0x200//0x20\r
 175 #define         DM_DIG_FA_TH1                           0x300//0x100\r
 176 #define         DM_DIG_FA_TH2                           0x400//0x200\r
 177 //this is for 92d\r
 178 #define         DM_DIG_FA_TH0_92D                       0x100\r
 179 #define         DM_DIG_FA_TH1_92D                       0x400\r
 180 #define         DM_DIG_FA_TH2_92D                       0x600\r
 181 \r
 182 #define         DM_DIG_BACKOFF_MAX                      12\r
 183 #define         DM_DIG_BACKOFF_MIN                      (-4)\r
 184 #define         DM_DIG_BACKOFF_DEFAULT          10\r
 185 \r
 186 #define         RxPathSelection_SS_TH_low               30\r
 187 #define         RxPathSelection_diff_TH                 18\r
 188 \r
 189 #define         DM_RATR_STA_INIT                        0\r
 190 #define         DM_RATR_STA_HIGH                        1\r
 191 #define                 DM_RATR_STA_MIDDLE              2\r
 192 #define                 DM_RATR_STA_LOW                 3\r
 193 \r
 194 #define         CTSToSelfTHVal                                  30\r
 195 #define         RegC38_TH                                               20\r
 196 \r
 197 #define         WAIotTHVal                                              25\r
 198 \r
 199 //Dynamic Tx Power Control Threshold\r
 200 #define         TX_POWER_NEAR_FIELD_THRESH_LVL2 74\r
 201 #define         TX_POWER_NEAR_FIELD_THRESH_LVL1 67\r
 202 \r
 203 #define         TxHighPwrLevel_Normal           0       \r
 204 #define         TxHighPwrLevel_Level1           1\r
 205 #define         TxHighPwrLevel_Level2           2\r
 206 \r
 207 #define         DM_Type_ByFW                    0\r
 208 #define         DM_Type_ByDriver                1\r
 209 \r
 210 typedef struct _RATE_ADAPTIVE\r
 211 {\r
 212         u8                              RateAdaptiveDisabled;\r
 213         u8                              RATRState;\r
 214         u16                             reserve;        \r
 215         \r
 216         u32                             HighRSSIThreshForRA;\r
 217         u32                             High2LowRSSIThreshForRA;\r
 218         u8                              Low2HighRSSIThreshForRA40M;\r
 219         u32                             LowRSSIThreshForRA40M;  \r
 220         u8                              Low2HighRSSIThreshForRA20M;\r
 221         u32                             LowRSSIThreshForRA20M;  \r
 222         u32                             UpperRSSIThresholdRATR;\r
 223         u32                             MiddleRSSIThresholdRATR;\r
 224         u32                             LowRSSIThresholdRATR;\r
 225         u32                             LowRSSIThresholdRATR40M;\r
 226         u32                             LowRSSIThresholdRATR20M;\r
 227         u8                              PingRSSIEnable; //cosa add for Netcore long range ping issue\r
 228         u32                             PingRSSIRATR;   //cosa add for Netcore long range ping issue\r
 229         u32                             PingRSSIThreshForRA;//cosa add for Netcore long range ping issue\r
 230         u32                             LastRATR;\r
 231         u8                              PreRATRState;\r
 232         \r
 233 } RATE_ADAPTIVE, *PRATE_ADAPTIVE;\r
 234 \r
 235 typedef enum tag_SW_Antenna_Switch_Definition\r
 236 {\r
 237         Antenna_B = 1,\r
 238         Antenna_A = 2,\r
 239         Antenna_MAX = 3,\r
 240 }DM_SWAS_E;\r
 241 \r
 242 // 20100514 Joseph: Add definition for antenna switching test after link.\r
 243 // This indicates two different the steps. \r
 244 // In SWAW_STEP_PEAK, driver needs to switch antenna and listen to the signal on the air.\r
 245 // In SWAW_STEP_DETERMINE, driver just compares the signal captured in SWAW_STEP_PEAK\r
 246 // with original RSSI to determine if it is necessary to switch antenna.\r
 247 #define SWAW_STEP_PEAK          0\r
 248 #define SWAW_STEP_DETERMINE     1\r
 249 \r
 250 #define TP_MODE         0\r
 251 #define RSSI_MODE               1\r
 252 #define TRAFFIC_LOW     0\r
 253 #define TRAFFIC_HIGH    1\r
 254 \r
 255 //=============================\r
 256 //Neil Chen---2011--06--15--\r
 257 //==============================\r
 258 //3 PathDiv \r
 259 typedef struct _SW_Antenna_Switch_\r
 260 {\r
 261         u8              try_flag;\r
 262         s32             PreRSSI;\r
 263         u8              CurAntenna;\r
 264         u8              PreAntenna;\r
 265         u8              RSSI_Trying;\r
 266         u8              TestMode;\r
 267         u8              bTriggerAntennaSwitch;\r
 268         u8              SelectAntennaMap;\r
 269 \r
 270         // Before link Antenna Switch check\r
 271         u8              SWAS_NoLink_State;\r
 272         u32             SWAS_NoLink_BK_Reg860;\r
 273 }SWAT_T, *pSWAT_T;\r
 274 //========================================\r
 275 \r
 276 struct  dm_priv \r
 277 {\r
 278         u8      DM_Type;\r
 279         u8      DMFlag, DMFlag_tmp;\r
 280 \r
 281         //for DIG\r
 282         u8      bDMInitialGainEnable;\r
 283         //u8    binitialized; // for dm_initial_gain_Multi_STA use.\r
 284         DIG_T   DM_DigTable;\r
 285 \r
 286         PS_T    DM_PSTable;\r
 287 \r
 288         FALSE_ALARM_STATISTICS  FalseAlmCnt;    \r
 289         \r
 290         //for rate adaptive, in fact,  88c/92c fw will handle this\r
 291         u8      bUseRAMask;\r
 292         RATE_ADAPTIVE   RateAdaptive;\r
 293 \r
 294         //* Upper and Lower Signal threshold for Rate Adaptive*/\r
 295         int     UndecoratedSmoothedPWDB;\r
 296         int     EntryMinUndecoratedSmoothedPWDB;\r
 297         int     EntryMaxUndecoratedSmoothedPWDB;\r
 298         int     MinUndecoratedPWDBForDM;\r
 299         int     LastMinUndecoratedPWDBForDM;\r
 300 \r
 301         //for High Power\r
 302         u8      bDynamicTxPowerEnable;\r
 303         u8      LastDTPLvl;\r
 304         u8      DynamicTxHighPowerLvl;//Add by Jacken Tx Power Control for Near/Far Range 2008/03/06\r
 305                 \r
 306         //for tx power tracking\r
 307         u8      bTXPowerTracking;\r
 308         u8      TXPowercount;\r
 309         u8      bTXPowerTrackingInit;   \r
 310         u8      TxPowerTrackControl;    //for mp mode, turn off txpwrtracking as default\r
 311         u8      TM_Trigger;\r
 312 \r
 313         u8      ThermalMeter[2];        // ThermalMeter, index 0 for RFIC0, and 1 for RFIC1\r
 314         u8      ThermalValue;\r
 315         u8      ThermalValue_LCK;\r
 316         u8      ThermalValue_IQK;\r
 317         u8      ThermalValue_AVG[AVG_THERMAL_NUM];\r
 318         u8      ThermalValue_AVG_index;\r
 319         u8      ThermalValue_RxGain;\r
 320         u8      ThermalValue_Crystal;\r
 321         u8      Delta_IQK;\r
 322         u8      Delta_LCK;\r
 323         u8      bRfPiEnable;\r
 324         u8      bReloadtxpowerindex;\r
 325         u8      bDoneTxpower;\r
 326 \r
 327         //for APK\r
 328         u32     APKoutput[2][2];        //path A/B; output1_1a/output1_2a\r
 329         u8      bAPKdone;\r
 330         u8      bAPKThermalMeterIgnore;\r
 331 \r
 332         //for IQK\r
 333         u32     Reg874;\r
 334         u32     RegC08;\r
 335         u32     Reg88C;\r
 336         u8      Reg522;\r
 337         u8      Reg550;\r
 338         u8      Reg551;\r
 339         u32     Reg870;\r
 340         u32     ADDA_backup[IQK_ADDA_REG_NUM];\r
 341         u32     IQK_MAC_backup[IQK_MAC_REG_NUM];\r
 342         u32     IQK_BB_backup[IQK_BB_REG_NUM];\r
 343 \r
 344         u8      bCCKinCH14;\r
 345 \r
 346         char    CCK_index;\r
 347         //u8 Record_CCK_20Mindex;\r
 348         //u8 Record_CCK_40Mindex;\r
 349         char    OFDM_index[2];\r
 350 \r
 351         SWAT_T DM_SWAT_Table;\r
 352 \r
 353        //Neil Chen----2011--06--23-----\r
 354        //3 Path Diversity \r
 355         BOOLEAN         bPathDiv_Enable;        //For 92D Non-interrupt Antenna Diversity by Neil ,add by wl.2011.07.19\r
 356         BOOLEAN         RSSI_test;\r
 357         s32                     RSSI_sum_A;\r
 358         s32                     RSSI_cnt_A;\r
 359         s32                     RSSI_sum_B;\r
 360         s32                     RSSI_cnt_B;\r
 361         struct sta_info *RSSI_target;\r
 362         _timer          PathDivSwitchTimer;\r
 363 \r
 364         //for TxPwrTracking\r
 365         int     RegE94;\r
 366         int     RegE9C;\r
 367         int     RegEB4;\r
 368         int     RegEBC;\r
 369 #if MP_DRIVER == 1\r
 370         u8      RegC04_MP;\r
 371         u32     RegD04_MP;\r
 372 #endif\r
 373         u32     TXPowerTrackingCallbackCnt;     //cosa add for debug\r
 374 \r
 375         u32     prv_traffic_idx; // edca turbo\r
 376 \r
 377         u32     RegRF3C[2];     //pathA / pathB\r
 378 \r
 379         // Add for Reading Initial Data Rate SEL Register 0x484 during watchdog. Using for fill tx desc. 2011.3.21 by Thomas\r
 380         u8      INIDATA_RATE[32];\r
 381 };\r
 382 \r
 383 \r
 384 /*------------------------Export global variable----------------------------*/\r
 385 /*------------------------Export global variable----------------------------*/\r
 386 /*------------------------Export Marco Definition---------------------------*/\r
 387 //#define DM_MultiSTA_InitGainChangeNotify(Event) {DM_DigTable.CurMultiSTAConnectState = Event;}\r
 388 \r
 389 \r
 390 //============================================================\r
 391 // function prototype\r
 392 //============================================================\r
 393 void rtl8192d_init_dm_priv(IN PADAPTER Adapter);\r
 394 void rtl8192d_deinit_dm_priv(IN PADAPTER Adapter);\r
 395 void    rtl8192d_InitHalDm(IN PADAPTER Adapter);\r
 396 void    rtl8192d_HalDmWatchDog(IN PADAPTER Adapter);\r
 397 \r
 398 VOID rtl8192d_dm_CheckTXPowerTracking(IN PADAPTER Adapter);\r
 399 \r
 400 #endif  //__HAL8190PCIDM_H__\r