2 /* Linux device driver for RTL8180 / RTL8185 / RTL8187SE
4 * Copyright 2007 Michael Wu <flamingice@sourmilk.net>
5 * Copyright 2007,2014 Andrea Merello <andrea.merello@gmail.com>
7 * Based on the r8180 driver, which is:
8 * Copyright 2004-2005 Andrea Merello <andrea.merello@gmail.com>, et al.
10 * Thanks to Realtek for their support!
12 ************************************************************************
14 * The driver was extended to the RTL8187SE in 2014 by
15 * Andrea Merello <andrea.merello@gmail.com>
18 * - portions of rtl8187se Linux staging driver, Copyright Realtek corp.
19 * (available in drivers/staging/rtl8187se directory of Linux 3.14)
20 * - other GPL, unpublished (until now), Linux driver code,
21 * Copyright Larry Finger <Larry.Finger@lwfinger.net>
23 * A huge thanks goes to Sara V. Nari who forgives me when I'm
24 * sitting in front of my laptop at evening, week-end, night...
26 * A special thanks goes to Antonio Cuni, who helped me with
27 * some python userspace stuff I used to debug RTL8187SE code, and who
28 * bought a laptop with an unsupported Wi-Fi card some years ago...
30 * Thanks to Larry Finger for writing some code for rtl8187se and for
33 * Thanks to Dan Carpenter for reviewing my initial patch and for his
36 * Thanks to Bernhard Schiffner for his help in testing and for his
39 ************************************************************************
41 * This program is free software; you can redistribute it and/or modify
42 * it under the terms of the GNU General Public License version 2 as
43 * published by the Free Software Foundation.
46 #include <linux/interrupt.h>
47 #include <linux/pci.h>
48 #include <linux/slab.h>
49 #include <linux/delay.h>
50 #include <linux/etherdevice.h>
51 #include <linux/eeprom_93cx6.h>
52 #include <linux/module.h>
53 #include <net/mac80211.h>
60 #include "rtl8225se.h"
62 MODULE_AUTHOR("Michael Wu <flamingice@sourmilk.net>");
63 MODULE_AUTHOR("Andrea Merello <andrea.merello@gmail.com>");
64 MODULE_DESCRIPTION("RTL8180 / RTL8185 / RTL8187SE PCI wireless driver");
65 MODULE_LICENSE("GPL");
67 static const struct pci_device_id rtl8180_table[] = {
70 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8199) },
73 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8185) },
74 { PCI_DEVICE(PCI_VENDOR_ID_BELKIN, 0x700f) },
75 { PCI_DEVICE(PCI_VENDOR_ID_BELKIN, 0x701f) },
78 { PCI_DEVICE(PCI_VENDOR_ID_REALTEK, 0x8180) },
79 { PCI_DEVICE(0x1799, 0x6001) },
80 { PCI_DEVICE(0x1799, 0x6020) },
81 { PCI_DEVICE(PCI_VENDOR_ID_DLINK, 0x3300) },
82 { PCI_DEVICE(0x1186, 0x3301) },
83 { PCI_DEVICE(0x1432, 0x7106) },
87 MODULE_DEVICE_TABLE(pci, rtl8180_table);
89 static const struct ieee80211_rate rtl818x_rates[] = {
90 { .bitrate = 10, .hw_value = 0, },
91 { .bitrate = 20, .hw_value = 1, },
92 { .bitrate = 55, .hw_value = 2, },
93 { .bitrate = 110, .hw_value = 3, },
94 { .bitrate = 60, .hw_value = 4, },
95 { .bitrate = 90, .hw_value = 5, },
96 { .bitrate = 120, .hw_value = 6, },
97 { .bitrate = 180, .hw_value = 7, },
98 { .bitrate = 240, .hw_value = 8, },
99 { .bitrate = 360, .hw_value = 9, },
100 { .bitrate = 480, .hw_value = 10, },
101 { .bitrate = 540, .hw_value = 11, },
104 static const struct ieee80211_channel rtl818x_channels[] = {
105 { .center_freq = 2412 },
106 { .center_freq = 2417 },
107 { .center_freq = 2422 },
108 { .center_freq = 2427 },
109 { .center_freq = 2432 },
110 { .center_freq = 2437 },
111 { .center_freq = 2442 },
112 { .center_freq = 2447 },
113 { .center_freq = 2452 },
114 { .center_freq = 2457 },
115 { .center_freq = 2462 },
116 { .center_freq = 2467 },
117 { .center_freq = 2472 },
118 { .center_freq = 2484 },
121 /* Queues for rtl8187se card
132 * The complete map for DMA kick reg using use all queue is:
133 * static const int rtl8187se_queues_map[RTL8187SE_NR_TX_QUEUES] =
134 * {1, 6, 5, 4, 3, 2, 7};
136 * .. but.. Because for mac80211 4 queues are enough for QoS we use this
139 * BC | 7 | 4 <- currently not used yet
140 * MG | 1 | x <- Not used
141 * HI | 6 | x <- Not used
147 * Beacon queue could be used, but this is not finished yet.
149 * I thougth about using the other two queues but I decided not to do this:
151 * - I'm unsure whether the mac80211 will ever try to use more than 4 queues
154 * - I could route MGMT frames (currently sent over VO queue) to the MGMT
155 * queue but since mac80211 will do not know about it, I will probably gain
156 * some HW priority whenever the VO queue is not empty, but this gain is
157 * limited by the fact that I had to stop the mac80211 queue whenever one of
158 * the VO or MGMT queues is full, stopping also submitting of MGMT frame
161 * - I don't know how to set in the HW the contention window params for MGMT
162 * and HI-prio queues.
165 static const int rtl8187se_queues_map[RTL8187SE_NR_TX_QUEUES] = {5, 4, 3, 2, 7};
167 /* Queues for rtl8180/rtl8185 cards
175 * The complete map for DMA kick reg using all queue is:
176 * static const int rtl8180_queues_map[RTL8180_NR_TX_QUEUES] = {6, 5, 4, 7};
178 * .. but .. Because the mac80211 needs at least 4 queues for QoS or
179 * otherwise QoS can't be done, we use just one.
180 * Beacon queue could be used, but this is not finished yet.
184 * BC | 7 | 1 <- currently not used yet.
185 * HI | 6 | x <- not used
186 * NO | 5 | x <- not used
190 static const int rtl8180_queues_map[RTL8180_NR_TX_QUEUES] = {4, 7};
192 void rtl8180_write_phy(struct ieee80211_hw *dev, u8 addr, u32 data)
194 struct rtl8180_priv *priv = dev->priv;
198 buf = (data << 8) | addr;
200 rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->PHY[0], buf | 0x80);
202 rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->PHY[0], buf);
203 if (rtl818x_ioread8(priv, &priv->map->PHY[2]) == (data & 0xFF))
208 static void rtl8180_handle_rx(struct ieee80211_hw *dev)
210 struct rtl8180_priv *priv = dev->priv;
211 struct rtl818x_rx_cmd_desc *cmd_desc;
212 unsigned int count = 32;
213 u8 agc, sq, signal = 1;
217 void *entry = priv->rx_ring + priv->rx_idx * priv->rx_ring_sz;
218 struct sk_buff *skb = priv->rx_buf[priv->rx_idx];
222 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE) {
223 struct rtl8187se_rx_desc *desc = entry;
225 flags = le32_to_cpu(desc->flags);
226 /* if ownership flag is set, then we can trust the
227 * HW has written other fields. We must not trust
228 * other descriptor data read before we checked (read)
232 flags2 = le32_to_cpu(desc->flags2);
233 tsft = le64_to_cpu(desc->tsft);
235 struct rtl8180_rx_desc *desc = entry;
237 flags = le32_to_cpu(desc->flags);
240 flags2 = le32_to_cpu(desc->flags2);
241 tsft = le64_to_cpu(desc->tsft);
244 if (flags & RTL818X_RX_DESC_FLAG_OWN)
247 if (unlikely(flags & (RTL818X_RX_DESC_FLAG_DMA_FAIL |
248 RTL818X_RX_DESC_FLAG_FOF |
249 RTL818X_RX_DESC_FLAG_RX_ERR)))
252 struct ieee80211_rx_status rx_status = {0};
253 struct sk_buff *new_skb = dev_alloc_skb(MAX_RX_SIZE);
255 if (unlikely(!new_skb))
258 mapping = pci_map_single(priv->pdev,
259 skb_tail_pointer(new_skb),
260 MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
262 if (pci_dma_mapping_error(priv->pdev, mapping)) {
264 dev_err(&priv->pdev->dev, "RX DMA map error\n");
269 pci_unmap_single(priv->pdev,
270 *((dma_addr_t *)skb->cb),
271 MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
272 skb_put(skb, flags & 0xFFF);
274 rx_status.antenna = (flags2 >> 15) & 1;
275 rx_status.rate_idx = (flags >> 20) & 0xF;
276 agc = (flags2 >> 17) & 0x7F;
278 switch (priv->chip_family) {
279 case RTL818X_CHIP_FAMILY_RTL8185:
280 if (rx_status.rate_idx > 3)
281 signal = -clamp_t(u8, agc, 25, 90) - 9;
283 signal = -clamp_t(u8, agc, 30, 95);
285 case RTL818X_CHIP_FAMILY_RTL8180:
287 signal = priv->rf->calc_rssi(agc, sq);
289 case RTL818X_CHIP_FAMILY_RTL8187SE:
290 /* TODO: rtl8187se rssi */
294 rx_status.signal = signal;
295 rx_status.freq = dev->conf.chandef.chan->center_freq;
296 rx_status.band = dev->conf.chandef.chan->band;
297 rx_status.mactime = tsft;
298 rx_status.flag |= RX_FLAG_MACTIME_START;
299 if (flags & RTL818X_RX_DESC_FLAG_SPLCP)
300 rx_status.flag |= RX_FLAG_SHORTPRE;
301 if (flags & RTL818X_RX_DESC_FLAG_CRC32_ERR)
302 rx_status.flag |= RX_FLAG_FAILED_FCS_CRC;
304 memcpy(IEEE80211_SKB_RXCB(skb), &rx_status, sizeof(rx_status));
305 ieee80211_rx_irqsafe(dev, skb);
308 priv->rx_buf[priv->rx_idx] = skb;
309 *((dma_addr_t *) skb->cb) = mapping;
314 cmd_desc->rx_buf = cpu_to_le32(*((dma_addr_t *)skb->cb));
315 cmd_desc->flags = cpu_to_le32(RTL818X_RX_DESC_FLAG_OWN |
317 if (priv->rx_idx == 31)
319 cpu_to_le32(RTL818X_RX_DESC_FLAG_EOR);
320 priv->rx_idx = (priv->rx_idx + 1) % 32;
324 static void rtl8180_handle_tx(struct ieee80211_hw *dev, unsigned int prio)
326 struct rtl8180_priv *priv = dev->priv;
327 struct rtl8180_tx_ring *ring = &priv->tx_ring[prio];
329 while (skb_queue_len(&ring->queue)) {
330 struct rtl8180_tx_desc *entry = &ring->desc[ring->idx];
332 struct ieee80211_tx_info *info;
333 u32 flags = le32_to_cpu(entry->flags);
335 if (flags & RTL818X_TX_DESC_FLAG_OWN)
338 ring->idx = (ring->idx + 1) % ring->entries;
339 skb = __skb_dequeue(&ring->queue);
340 pci_unmap_single(priv->pdev, le32_to_cpu(entry->tx_buf),
341 skb->len, PCI_DMA_TODEVICE);
343 info = IEEE80211_SKB_CB(skb);
344 ieee80211_tx_info_clear_status(info);
346 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK) &&
347 (flags & RTL818X_TX_DESC_FLAG_TX_OK))
348 info->flags |= IEEE80211_TX_STAT_ACK;
350 info->status.rates[0].count = (flags & 0xFF) + 1;
352 ieee80211_tx_status_irqsafe(dev, skb);
353 if (ring->entries - skb_queue_len(&ring->queue) == 2)
354 ieee80211_wake_queue(dev, prio);
358 static irqreturn_t rtl8187se_interrupt(int irq, void *dev_id)
360 struct ieee80211_hw *dev = dev_id;
361 struct rtl8180_priv *priv = dev->priv;
366 spin_lock_irqsave(&priv->lock, flags);
367 /* Note: 32-bit interrupt status */
368 reg = rtl818x_ioread32(priv, &priv->map->INT_STATUS_SE);
369 if (unlikely(reg == 0xFFFFFFFF)) {
370 spin_unlock_irqrestore(&priv->lock, flags);
374 rtl818x_iowrite32(priv, &priv->map->INT_STATUS_SE, reg);
376 if (reg & IMR_TIMEOUT1)
377 rtl818x_iowrite32(priv, &priv->map->INT_TIMEOUT, 0);
379 if (reg & (IMR_TBDOK | IMR_TBDER))
380 rtl8180_handle_tx(dev, 4);
382 if (reg & (IMR_TVODOK | IMR_TVODER))
383 rtl8180_handle_tx(dev, 0);
385 if (reg & (IMR_TVIDOK | IMR_TVIDER))
386 rtl8180_handle_tx(dev, 1);
388 if (reg & (IMR_TBEDOK | IMR_TBEDER))
389 rtl8180_handle_tx(dev, 2);
391 if (reg & (IMR_TBKDOK | IMR_TBKDER))
392 rtl8180_handle_tx(dev, 3);
394 if (reg & (IMR_ROK | IMR_RER | RTL818X_INT_SE_RX_DU | IMR_RQOSOK))
395 rtl8180_handle_rx(dev);
396 /* The interface sometimes generates several RX DMA descriptor errors
397 * at startup. Do not report these.
399 if ((reg & RTL818X_INT_SE_RX_DU) && desc_err++ > 2)
401 wiphy_err(dev->wiphy, "No RX DMA Descriptor avail\n");
403 spin_unlock_irqrestore(&priv->lock, flags);
407 static irqreturn_t rtl8180_interrupt(int irq, void *dev_id)
409 struct ieee80211_hw *dev = dev_id;
410 struct rtl8180_priv *priv = dev->priv;
413 spin_lock(&priv->lock);
414 reg = rtl818x_ioread16(priv, &priv->map->INT_STATUS);
415 if (unlikely(reg == 0xFFFF)) {
416 spin_unlock(&priv->lock);
420 rtl818x_iowrite16(priv, &priv->map->INT_STATUS, reg);
422 if (reg & (RTL818X_INT_TXB_OK | RTL818X_INT_TXB_ERR))
423 rtl8180_handle_tx(dev, 1);
425 if (reg & (RTL818X_INT_TXL_OK | RTL818X_INT_TXL_ERR))
426 rtl8180_handle_tx(dev, 0);
428 if (reg & (RTL818X_INT_RX_OK | RTL818X_INT_RX_ERR))
429 rtl8180_handle_rx(dev);
431 spin_unlock(&priv->lock);
436 static void rtl8180_tx(struct ieee80211_hw *dev,
437 struct ieee80211_tx_control *control,
440 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb);
441 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
442 struct rtl8180_priv *priv = dev->priv;
443 struct rtl8180_tx_ring *ring;
444 struct rtl8180_tx_desc *entry;
446 unsigned int idx, prio, hw_prio;
451 __le16 rts_duration = 0;
452 /* do arithmetic and then convert to le16 */
453 u16 frame_duration = 0;
455 prio = skb_get_queue_mapping(skb);
456 ring = &priv->tx_ring[prio];
458 mapping = pci_map_single(priv->pdev, skb->data,
459 skb->len, PCI_DMA_TODEVICE);
461 if (pci_dma_mapping_error(priv->pdev, mapping)) {
463 dev_err(&priv->pdev->dev, "TX DMA mapping error\n");
467 tx_flags = RTL818X_TX_DESC_FLAG_OWN | RTL818X_TX_DESC_FLAG_FS |
468 RTL818X_TX_DESC_FLAG_LS |
469 (ieee80211_get_tx_rate(dev, info)->hw_value << 24) |
472 if (priv->chip_family != RTL818X_CHIP_FAMILY_RTL8180)
473 tx_flags |= RTL818X_TX_DESC_FLAG_DMA |
474 RTL818X_TX_DESC_FLAG_NO_ENC;
476 rc_flags = info->control.rates[0].flags;
478 /* HW will perform RTS-CTS when only RTS flags is set.
479 * HW will perform CTS-to-self when both RTS and CTS flags are set.
480 * RTS rate and RTS duration will be used also for CTS-to-self.
482 if (rc_flags & IEEE80211_TX_RC_USE_RTS_CTS) {
483 tx_flags |= RTL818X_TX_DESC_FLAG_RTS;
484 tx_flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19;
485 rts_duration = ieee80211_rts_duration(dev, priv->vif,
487 } else if (rc_flags & IEEE80211_TX_RC_USE_CTS_PROTECT) {
488 tx_flags |= RTL818X_TX_DESC_FLAG_RTS | RTL818X_TX_DESC_FLAG_CTS;
489 tx_flags |= ieee80211_get_rts_cts_rate(dev, info)->hw_value << 19;
490 rts_duration = ieee80211_ctstoself_duration(dev, priv->vif,
494 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8180) {
495 unsigned int remainder;
497 plcp_len = DIV_ROUND_UP(16 * (skb->len + 4),
498 (ieee80211_get_tx_rate(dev, info)->bitrate * 2) / 10);
499 remainder = (16 * (skb->len + 4)) %
500 ((ieee80211_get_tx_rate(dev, info)->bitrate * 2) / 10);
505 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE) {
507 /* SIFS time (required by HW) is already included by
508 * ieee80211_generic_frame_duration
510 duration = ieee80211_generic_frame_duration(dev, priv->vif,
511 IEEE80211_BAND_2GHZ, skb->len,
512 ieee80211_get_tx_rate(dev, info));
514 frame_duration = priv->ack_time + le16_to_cpu(duration);
517 spin_lock_irqsave(&priv->lock, flags);
519 if (info->flags & IEEE80211_TX_CTL_ASSIGN_SEQ) {
520 if (info->flags & IEEE80211_TX_CTL_FIRST_FRAGMENT)
522 hdr->seq_ctrl &= cpu_to_le16(IEEE80211_SCTL_FRAG);
523 hdr->seq_ctrl |= cpu_to_le16(priv->seqno);
526 idx = (ring->idx + skb_queue_len(&ring->queue)) % ring->entries;
527 entry = &ring->desc[idx];
529 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE) {
530 entry->frame_duration = cpu_to_le16(frame_duration);
531 entry->frame_len_se = cpu_to_le16(skb->len);
534 entry->flags3 = cpu_to_le16(1<<4);
536 entry->frame_len = cpu_to_le32(skb->len);
538 entry->rts_duration = rts_duration;
539 entry->plcp_len = cpu_to_le16(plcp_len);
540 entry->tx_buf = cpu_to_le32(mapping);
542 entry->retry_limit = info->control.rates[0].count - 1;
544 /* We must be sure that tx_flags is written last because the HW
545 * looks at it to check if the rest of data is valid or not
548 entry->flags = cpu_to_le32(tx_flags);
549 /* We must be sure this has been written before followings HW
550 * register write, because this write will made the HW attempts
551 * to DMA the just-written data
555 __skb_queue_tail(&ring->queue, skb);
556 if (ring->entries - skb_queue_len(&ring->queue) < 2)
557 ieee80211_stop_queue(dev, prio);
559 spin_unlock_irqrestore(&priv->lock, flags);
561 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE) {
562 /* just poll: rings are stopped with TPPollStop reg */
563 hw_prio = rtl8187se_queues_map[prio];
564 rtl818x_iowrite8(priv, &priv->map->TX_DMA_POLLING,
567 hw_prio = rtl8180_queues_map[prio];
568 rtl818x_iowrite8(priv, &priv->map->TX_DMA_POLLING,
569 (1 << hw_prio) | /* ring to poll */
570 (1<<1) | (1<<2));/* stopped rings */
574 static void rtl8180_set_anaparam3(struct rtl8180_priv *priv, u16 anaparam3)
578 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
579 RTL818X_EEPROM_CMD_CONFIG);
581 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
582 rtl818x_iowrite8(priv, &priv->map->CONFIG3,
583 reg | RTL818X_CONFIG3_ANAPARAM_WRITE);
585 rtl818x_iowrite16(priv, &priv->map->ANAPARAM3, anaparam3);
587 rtl818x_iowrite8(priv, &priv->map->CONFIG3,
588 reg & ~RTL818X_CONFIG3_ANAPARAM_WRITE);
590 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
591 RTL818X_EEPROM_CMD_NORMAL);
594 void rtl8180_set_anaparam2(struct rtl8180_priv *priv, u32 anaparam2)
598 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
599 RTL818X_EEPROM_CMD_CONFIG);
601 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
602 rtl818x_iowrite8(priv, &priv->map->CONFIG3,
603 reg | RTL818X_CONFIG3_ANAPARAM_WRITE);
605 rtl818x_iowrite32(priv, &priv->map->ANAPARAM2, anaparam2);
607 rtl818x_iowrite8(priv, &priv->map->CONFIG3,
608 reg & ~RTL818X_CONFIG3_ANAPARAM_WRITE);
610 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
611 RTL818X_EEPROM_CMD_NORMAL);
614 void rtl8180_set_anaparam(struct rtl8180_priv *priv, u32 anaparam)
618 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
619 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
620 rtl818x_iowrite8(priv, &priv->map->CONFIG3,
621 reg | RTL818X_CONFIG3_ANAPARAM_WRITE);
622 rtl818x_iowrite32(priv, &priv->map->ANAPARAM, anaparam);
623 rtl818x_iowrite8(priv, &priv->map->CONFIG3,
624 reg & ~RTL818X_CONFIG3_ANAPARAM_WRITE);
625 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
628 static void rtl8187se_mac_config(struct ieee80211_hw *dev)
630 struct rtl8180_priv *priv = dev->priv;
633 rtl818x_iowrite32(priv, REG_ADDR4(0x1F0), 0);
634 rtl818x_ioread32(priv, REG_ADDR4(0x1F0));
635 rtl818x_iowrite32(priv, REG_ADDR4(0x1F4), 0);
636 rtl818x_ioread32(priv, REG_ADDR4(0x1F4));
637 rtl818x_iowrite8(priv, REG_ADDR1(0x1F8), 0);
638 rtl818x_ioread8(priv, REG_ADDR1(0x1F8));
639 /* Enable DA10 TX power saving */
640 reg = rtl818x_ioread8(priv, &priv->map->PHY_PR);
641 rtl818x_iowrite8(priv, &priv->map->PHY_PR, reg | 0x04);
643 rtl818x_iowrite16(priv, PI_DATA_REG, 0x1000);
644 rtl818x_iowrite16(priv, SI_DATA_REG, 0x1000);
645 /* AFE - default to power ON */
646 rtl818x_iowrite16(priv, REG_ADDR2(0x370), 0x0560);
647 rtl818x_iowrite16(priv, REG_ADDR2(0x372), 0x0560);
648 rtl818x_iowrite16(priv, REG_ADDR2(0x374), 0x0DA4);
649 rtl818x_iowrite16(priv, REG_ADDR2(0x376), 0x0DA4);
650 rtl818x_iowrite16(priv, REG_ADDR2(0x378), 0x0560);
651 rtl818x_iowrite16(priv, REG_ADDR2(0x37A), 0x0560);
652 rtl818x_iowrite16(priv, REG_ADDR2(0x37C), 0x00EC);
653 rtl818x_iowrite16(priv, REG_ADDR2(0x37E), 0x00EC);
654 rtl818x_iowrite8(priv, REG_ADDR1(0x24E), 0x01);
655 /* unknown, needed for suspend to RAM resume */
656 rtl818x_iowrite8(priv, REG_ADDR1(0x0A), 0x72);
659 static void rtl8187se_set_antenna_config(struct ieee80211_hw *dev, u8 def_ant,
662 struct rtl8180_priv *priv = dev->priv;
664 rtl8225_write_phy_cck(dev, 0x0C, 0x09);
667 rtl818x_iowrite8(priv, &priv->map->TX_ANTENNA, 0x00);
668 rtl8225_write_phy_cck(dev, 0x11, 0xBB);
669 rtl8225_write_phy_cck(dev, 0x01, 0xC7);
670 rtl8225_write_phy_ofdm(dev, 0x0D, 0x54);
671 rtl8225_write_phy_ofdm(dev, 0x18, 0xB2);
672 } else { /* main antenna */
673 rtl818x_iowrite8(priv, &priv->map->TX_ANTENNA, 0x03);
674 rtl8225_write_phy_cck(dev, 0x11, 0x9B);
675 rtl8225_write_phy_cck(dev, 0x01, 0xC7);
676 rtl8225_write_phy_ofdm(dev, 0x0D, 0x5C);
677 rtl8225_write_phy_ofdm(dev, 0x18, 0xB2);
679 } else { /* disable antenna diversity */
681 rtl818x_iowrite8(priv, &priv->map->TX_ANTENNA, 0x00);
682 rtl8225_write_phy_cck(dev, 0x11, 0xBB);
683 rtl8225_write_phy_cck(dev, 0x01, 0x47);
684 rtl8225_write_phy_ofdm(dev, 0x0D, 0x54);
685 rtl8225_write_phy_ofdm(dev, 0x18, 0x32);
686 } else { /* main antenna */
687 rtl818x_iowrite8(priv, &priv->map->TX_ANTENNA, 0x03);
688 rtl8225_write_phy_cck(dev, 0x11, 0x9B);
689 rtl8225_write_phy_cck(dev, 0x01, 0x47);
690 rtl8225_write_phy_ofdm(dev, 0x0D, 0x5C);
691 rtl8225_write_phy_ofdm(dev, 0x18, 0x32);
694 /* priv->curr_ant = def_ant; */
697 static void rtl8180_int_enable(struct ieee80211_hw *dev)
699 struct rtl8180_priv *priv = dev->priv;
701 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE) {
702 rtl818x_iowrite32(priv, &priv->map->IMR,
703 IMR_TBDER | IMR_TBDOK |
704 IMR_TVODER | IMR_TVODOK |
705 IMR_TVIDER | IMR_TVIDOK |
706 IMR_TBEDER | IMR_TBEDOK |
707 IMR_TBKDER | IMR_TBKDOK |
709 IMR_ROK | IMR_RQOSOK);
711 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0xFFFF);
715 static void rtl8180_int_disable(struct ieee80211_hw *dev)
717 struct rtl8180_priv *priv = dev->priv;
719 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE) {
720 rtl818x_iowrite32(priv, &priv->map->IMR, 0);
722 rtl818x_iowrite16(priv, &priv->map->INT_MASK, 0);
726 static void rtl8180_conf_basic_rates(struct ieee80211_hw *dev,
729 struct rtl8180_priv *priv = dev->priv;
734 max = fls(rates_mask) - 1;
735 min = ffs(rates_mask) - 1;
737 switch (priv->chip_family) {
739 case RTL818X_CHIP_FAMILY_RTL8180:
740 /* in 8180 this is NOT a BITMAP */
741 reg = rtl818x_ioread16(priv, &priv->map->BRSR);
744 rtl818x_iowrite16(priv, &priv->map->BRSR, reg);
747 case RTL818X_CHIP_FAMILY_RTL8185:
748 /* in 8185 this is a BITMAP */
749 rtl818x_iowrite16(priv, &priv->map->BRSR, rates_mask);
750 rtl818x_iowrite8(priv, &priv->map->RESP_RATE, (max << 4) | min);
753 case RTL818X_CHIP_FAMILY_RTL8187SE:
754 /* in 8187se this is a BITMAP */
755 rtl818x_iowrite16(priv, &priv->map->BRSR_8187SE, rates_mask);
760 static void rtl8180_config_cardbus(struct ieee80211_hw *dev)
762 struct rtl8180_priv *priv = dev->priv;
766 reg8 = rtl818x_ioread8(priv, &priv->map->CONFIG3);
768 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg8);
770 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE) {
771 rtl818x_iowrite16(priv, FEMR_SE, 0xffff);
773 reg16 = rtl818x_ioread16(priv, &priv->map->FEMR);
774 reg16 |= (1 << 15) | (1 << 14) | (1 << 4);
775 rtl818x_iowrite16(priv, &priv->map->FEMR, reg16);
780 static int rtl8180_init_hw(struct ieee80211_hw *dev)
782 struct rtl8180_priv *priv = dev->priv;
786 rtl818x_iowrite8(priv, &priv->map->CMD, 0);
787 rtl818x_ioread8(priv, &priv->map->CMD);
791 rtl8180_int_disable(dev);
792 rtl818x_ioread8(priv, &priv->map->CMD);
794 reg = rtl818x_ioread8(priv, &priv->map->CMD);
796 reg |= RTL818X_CMD_RESET;
797 rtl818x_iowrite8(priv, &priv->map->CMD, RTL818X_CMD_RESET);
798 rtl818x_ioread8(priv, &priv->map->CMD);
801 /* check success of reset */
802 if (rtl818x_ioread8(priv, &priv->map->CMD) & RTL818X_CMD_RESET) {
803 wiphy_err(dev->wiphy, "reset timeout!\n");
807 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_LOAD);
808 rtl818x_ioread8(priv, &priv->map->CMD);
811 if (rtl818x_ioread8(priv, &priv->map->CONFIG3) & (1 << 3)) {
812 rtl8180_config_cardbus(dev);
815 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE)
816 rtl818x_iowrite8(priv, &priv->map->MSR, RTL818X_MSR_ENEDCA);
818 rtl818x_iowrite8(priv, &priv->map->MSR, 0);
820 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8180)
821 rtl8180_set_anaparam(priv, priv->anaparam);
823 rtl818x_iowrite32(priv, &priv->map->RDSAR, priv->rx_ring_dma);
824 /* mac80211 queue have higher prio for lower index. The last queue
825 * (that mac80211 is not aware of) is reserved for beacons (and have
826 * the highest priority on the NIC)
828 if (priv->chip_family != RTL818X_CHIP_FAMILY_RTL8187SE) {
829 rtl818x_iowrite32(priv, &priv->map->TBDA,
830 priv->tx_ring[1].dma);
831 rtl818x_iowrite32(priv, &priv->map->TLPDA,
832 priv->tx_ring[0].dma);
834 rtl818x_iowrite32(priv, &priv->map->TBDA,
835 priv->tx_ring[4].dma);
836 rtl818x_iowrite32(priv, &priv->map->TVODA,
837 priv->tx_ring[0].dma);
838 rtl818x_iowrite32(priv, &priv->map->TVIDA,
839 priv->tx_ring[1].dma);
840 rtl818x_iowrite32(priv, &priv->map->TBEDA,
841 priv->tx_ring[2].dma);
842 rtl818x_iowrite32(priv, &priv->map->TBKDA,
843 priv->tx_ring[3].dma);
846 /* TODO: necessary? specs indicate not */
847 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
848 reg = rtl818x_ioread8(priv, &priv->map->CONFIG2);
849 rtl818x_iowrite8(priv, &priv->map->CONFIG2, reg & ~(1 << 3));
850 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8185) {
851 reg = rtl818x_ioread8(priv, &priv->map->CONFIG2);
852 rtl818x_iowrite8(priv, &priv->map->CONFIG2, reg | (1 << 4));
854 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
856 /* TODO: set CONFIG5 for calibrating AGC on rtl8180 + philips radio? */
858 /* TODO: turn off hw wep on rtl8180 */
860 rtl818x_iowrite32(priv, &priv->map->INT_TIMEOUT, 0);
862 if (priv->chip_family != RTL818X_CHIP_FAMILY_RTL8180) {
863 rtl818x_iowrite8(priv, &priv->map->WPA_CONF, 0);
864 rtl818x_iowrite8(priv, &priv->map->RATE_FALLBACK, 0);
866 rtl818x_iowrite8(priv, &priv->map->SECURITY, 0);
868 rtl818x_iowrite8(priv, &priv->map->PHY_DELAY, 0x6);
869 rtl818x_iowrite8(priv, &priv->map->CARRIER_SENSE_COUNTER, 0x4C);
872 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8185) {
873 /* TODO: set ClkRun enable? necessary? */
874 reg = rtl818x_ioread8(priv, &priv->map->GP_ENABLE);
875 rtl818x_iowrite8(priv, &priv->map->GP_ENABLE, reg & ~(1 << 6));
876 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
877 reg = rtl818x_ioread8(priv, &priv->map->CONFIG3);
878 rtl818x_iowrite8(priv, &priv->map->CONFIG3, reg | (1 << 2));
879 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
880 /* fix eccessive IFS after CTS-to-self */
884 reg = rtl818x_ioread8(priv, &priv->map->PGSELECT);
885 rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg | 1);
886 rtl818x_iowrite8(priv, REG_ADDR1(0xff), 0x35);
887 rtl818x_iowrite8(priv, &priv->map->PGSELECT, reg);
889 rtl818x_iowrite8(priv, REG_ADDR1(0x1ff), 0x35);
892 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE) {
894 /* the set auto rate fallback bitmask from 1M to 54 Mb/s */
895 rtl818x_iowrite16(priv, ARFR, 0xFFF);
896 rtl818x_ioread16(priv, ARFR);
898 /* stop unused queus (no dma alloc) */
899 rtl818x_iowrite8(priv, &priv->map->TPPOLL_STOP,
900 RTL818x_TPPOLL_STOP_MG | RTL818x_TPPOLL_STOP_HI);
902 rtl818x_iowrite8(priv, &priv->map->ACM_CONTROL, 0x00);
903 rtl818x_iowrite16(priv, &priv->map->TID_AC_MAP, 0xFA50);
905 rtl818x_iowrite16(priv, &priv->map->INT_MIG, 0);
907 /* some black magic here.. */
908 rtl8187se_mac_config(dev);
910 rtl818x_iowrite16(priv, RFSW_CTRL, 0x569A);
911 rtl818x_ioread16(priv, RFSW_CTRL);
913 rtl8180_set_anaparam(priv, RTL8225SE_ANAPARAM_ON);
914 rtl8180_set_anaparam2(priv, RTL8225SE_ANAPARAM2_ON);
915 rtl8180_set_anaparam3(priv, RTL8225SE_ANAPARAM3);
918 rtl818x_iowrite8(priv, &priv->map->CONFIG5,
919 rtl818x_ioread8(priv, &priv->map->CONFIG5) & 0x7F);
921 /*probably this switch led on */
922 rtl818x_iowrite8(priv, &priv->map->PGSELECT,
923 rtl818x_ioread8(priv, &priv->map->PGSELECT) | 0x08);
925 rtl818x_iowrite16(priv, &priv->map->RFPinsOutput, 0x0480);
926 rtl818x_iowrite16(priv, &priv->map->RFPinsEnable, 0x1BFF);
927 rtl818x_iowrite16(priv, &priv->map->RFPinsSelect, 0x2488);
929 rtl818x_iowrite32(priv, &priv->map->RF_TIMING, 0x4003);
931 /* the reference code mac hardcode table write
932 * this reg by doing byte-wide accesses.
933 * It does it just for lowest and highest byte..
935 reg32 = rtl818x_ioread32(priv, &priv->map->RF_PARA);
938 rtl818x_iowrite32(priv, &priv->map->RF_PARA, reg32);
940 /* stop unused queus (no dma alloc) */
941 rtl818x_iowrite8(priv, &priv->map->TX_DMA_POLLING,
946 /* default basic rates are 1,2 Mbps for rtl8180. 1,2,6,9,12,18,24 Mbps
947 * otherwise. bitmask 0x3 and 0x01f3 respectively.
948 * NOTE: currenty rtl8225 RF code changes basic rates, so we need to do
949 * this after rf init.
950 * TODO: try to find out whether RF code really needs to do this..
952 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8180)
953 rtl8180_conf_basic_rates(dev, 0x3);
955 rtl8180_conf_basic_rates(dev, 0x1f3);
957 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE)
958 rtl8187se_set_antenna_config(dev,
959 priv->antenna_diversity_default,
960 priv->antenna_diversity_en);
964 static int rtl8180_init_rx_ring(struct ieee80211_hw *dev)
966 struct rtl8180_priv *priv = dev->priv;
967 struct rtl818x_rx_cmd_desc *entry;
970 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE)
971 priv->rx_ring_sz = sizeof(struct rtl8187se_rx_desc);
973 priv->rx_ring_sz = sizeof(struct rtl8180_rx_desc);
975 priv->rx_ring = pci_zalloc_consistent(priv->pdev, priv->rx_ring_sz * 32,
977 if (!priv->rx_ring || (unsigned long)priv->rx_ring & 0xFF) {
978 wiphy_err(dev->wiphy, "Cannot allocate RX ring\n");
984 for (i = 0; i < 32; i++) {
985 struct sk_buff *skb = dev_alloc_skb(MAX_RX_SIZE);
987 entry = priv->rx_ring + priv->rx_ring_sz*i;
989 wiphy_err(dev->wiphy, "Cannot allocate RX skb\n");
992 priv->rx_buf[i] = skb;
993 mapping = (dma_addr_t *)skb->cb;
994 *mapping = pci_map_single(priv->pdev, skb_tail_pointer(skb),
995 MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
997 if (pci_dma_mapping_error(priv->pdev, *mapping)) {
999 wiphy_err(dev->wiphy, "Cannot map DMA for RX skb\n");
1003 entry->rx_buf = cpu_to_le32(*mapping);
1004 entry->flags = cpu_to_le32(RTL818X_RX_DESC_FLAG_OWN |
1007 entry->flags |= cpu_to_le32(RTL818X_RX_DESC_FLAG_EOR);
1011 static void rtl8180_free_rx_ring(struct ieee80211_hw *dev)
1013 struct rtl8180_priv *priv = dev->priv;
1016 for (i = 0; i < 32; i++) {
1017 struct sk_buff *skb = priv->rx_buf[i];
1021 pci_unmap_single(priv->pdev,
1022 *((dma_addr_t *)skb->cb),
1023 MAX_RX_SIZE, PCI_DMA_FROMDEVICE);
1027 pci_free_consistent(priv->pdev, priv->rx_ring_sz * 32,
1028 priv->rx_ring, priv->rx_ring_dma);
1029 priv->rx_ring = NULL;
1032 static int rtl8180_init_tx_ring(struct ieee80211_hw *dev,
1033 unsigned int prio, unsigned int entries)
1035 struct rtl8180_priv *priv = dev->priv;
1036 struct rtl8180_tx_desc *ring;
1040 ring = pci_zalloc_consistent(priv->pdev, sizeof(*ring) * entries,
1042 if (!ring || (unsigned long)ring & 0xFF) {
1043 wiphy_err(dev->wiphy, "Cannot allocate TX ring (prio = %d)\n",
1048 priv->tx_ring[prio].desc = ring;
1049 priv->tx_ring[prio].dma = dma;
1050 priv->tx_ring[prio].idx = 0;
1051 priv->tx_ring[prio].entries = entries;
1052 skb_queue_head_init(&priv->tx_ring[prio].queue);
1054 for (i = 0; i < entries; i++)
1055 ring[i].next_tx_desc =
1056 cpu_to_le32((u32)dma + ((i + 1) % entries) * sizeof(*ring));
1061 static void rtl8180_free_tx_ring(struct ieee80211_hw *dev, unsigned int prio)
1063 struct rtl8180_priv *priv = dev->priv;
1064 struct rtl8180_tx_ring *ring = &priv->tx_ring[prio];
1066 while (skb_queue_len(&ring->queue)) {
1067 struct rtl8180_tx_desc *entry = &ring->desc[ring->idx];
1068 struct sk_buff *skb = __skb_dequeue(&ring->queue);
1070 pci_unmap_single(priv->pdev, le32_to_cpu(entry->tx_buf),
1071 skb->len, PCI_DMA_TODEVICE);
1073 ring->idx = (ring->idx + 1) % ring->entries;
1076 pci_free_consistent(priv->pdev, sizeof(*ring->desc)*ring->entries,
1077 ring->desc, ring->dma);
1081 static int rtl8180_start(struct ieee80211_hw *dev)
1083 struct rtl8180_priv *priv = dev->priv;
1087 ret = rtl8180_init_rx_ring(dev);
1091 for (i = 0; i < (dev->queues + 1); i++)
1092 if ((ret = rtl8180_init_tx_ring(dev, i, 16)))
1093 goto err_free_rings;
1095 ret = rtl8180_init_hw(dev);
1097 goto err_free_rings;
1099 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE) {
1100 ret = request_irq(priv->pdev->irq, rtl8187se_interrupt,
1101 IRQF_SHARED, KBUILD_MODNAME, dev);
1103 ret = request_irq(priv->pdev->irq, rtl8180_interrupt,
1104 IRQF_SHARED, KBUILD_MODNAME, dev);
1108 wiphy_err(dev->wiphy, "failed to register IRQ handler\n");
1109 goto err_free_rings;
1112 rtl8180_int_enable(dev);
1114 /* in rtl8187se at MAR regs offset there is the management
1115 * TX descriptor DMA addres..
1117 if (priv->chip_family != RTL818X_CHIP_FAMILY_RTL8187SE) {
1118 rtl818x_iowrite32(priv, &priv->map->MAR[0], ~0);
1119 rtl818x_iowrite32(priv, &priv->map->MAR[1], ~0);
1122 reg = RTL818X_RX_CONF_ONLYERLPKT |
1123 RTL818X_RX_CONF_RX_AUTORESETPHY |
1124 RTL818X_RX_CONF_MGMT |
1125 RTL818X_RX_CONF_DATA |
1126 (7 << 8 /* MAX RX DMA */) |
1127 RTL818X_RX_CONF_BROADCAST |
1128 RTL818X_RX_CONF_NICMAC;
1130 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8185)
1131 reg |= RTL818X_RX_CONF_CSDM1 | RTL818X_RX_CONF_CSDM2;
1132 else if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8180) {
1133 reg |= (priv->rfparam & RF_PARAM_CARRIERSENSE1)
1134 ? RTL818X_RX_CONF_CSDM1 : 0;
1135 reg |= (priv->rfparam & RF_PARAM_CARRIERSENSE2)
1136 ? RTL818X_RX_CONF_CSDM2 : 0;
1138 reg &= ~(RTL818X_RX_CONF_CSDM1 | RTL818X_RX_CONF_CSDM2);
1141 priv->rx_conf = reg;
1142 rtl818x_iowrite32(priv, &priv->map->RX_CONF, reg);
1144 if (priv->chip_family != RTL818X_CHIP_FAMILY_RTL8180) {
1145 reg = rtl818x_ioread8(priv, &priv->map->CW_CONF);
1147 /* CW is not on per-packet basis.
1148 * in rtl8185 the CW_VALUE reg is used.
1149 * in rtl8187se the AC param regs are used.
1151 reg &= ~RTL818X_CW_CONF_PERPACKET_CW;
1152 /* retry limit IS on per-packet basis.
1153 * the short and long retry limit in TX_CONF
1156 reg |= RTL818X_CW_CONF_PERPACKET_RETRY;
1157 rtl818x_iowrite8(priv, &priv->map->CW_CONF, reg);
1159 reg = rtl818x_ioread8(priv, &priv->map->TX_AGC_CTL);
1160 /* TX antenna and TX gain are not on per-packet basis.
1161 * TX Antenna is selected by ANTSEL reg (RX in BB regs).
1162 * TX gain is selected with CCK_TX_AGC and OFDM_TX_AGC regs
1164 reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_GAIN;
1165 reg &= ~RTL818X_TX_AGC_CTL_PERPACKET_ANTSEL;
1166 reg |= RTL818X_TX_AGC_CTL_FEEDBACK_ANT;
1167 rtl818x_iowrite8(priv, &priv->map->TX_AGC_CTL, reg);
1169 /* disable early TX */
1170 rtl818x_iowrite8(priv, (u8 __iomem *)priv->map + 0xec, 0x3f);
1173 reg = rtl818x_ioread32(priv, &priv->map->TX_CONF);
1174 reg |= (6 << 21 /* MAX TX DMA */) |
1175 RTL818X_TX_CONF_NO_ICV;
1177 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE)
1178 reg |= 1<<30; /* "duration procedure mode" */
1180 if (priv->chip_family != RTL818X_CHIP_FAMILY_RTL8180)
1181 reg &= ~RTL818X_TX_CONF_PROBE_DTS;
1183 reg &= ~RTL818X_TX_CONF_HW_SEQNUM;
1185 reg &= ~RTL818X_TX_CONF_DISCW;
1187 /* different meaning, same value on both rtl8185 and rtl8180 */
1188 reg &= ~RTL818X_TX_CONF_SAT_HWPLCP;
1190 rtl818x_iowrite32(priv, &priv->map->TX_CONF, reg);
1192 reg = rtl818x_ioread8(priv, &priv->map->CMD);
1193 reg |= RTL818X_CMD_RX_ENABLE;
1194 reg |= RTL818X_CMD_TX_ENABLE;
1195 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
1200 rtl8180_free_rx_ring(dev);
1201 for (i = 0; i < (dev->queues + 1); i++)
1202 if (priv->tx_ring[i].desc)
1203 rtl8180_free_tx_ring(dev, i);
1208 static void rtl8180_stop(struct ieee80211_hw *dev)
1210 struct rtl8180_priv *priv = dev->priv;
1214 rtl8180_int_disable(dev);
1216 reg = rtl818x_ioread8(priv, &priv->map->CMD);
1217 reg &= ~RTL818X_CMD_TX_ENABLE;
1218 reg &= ~RTL818X_CMD_RX_ENABLE;
1219 rtl818x_iowrite8(priv, &priv->map->CMD, reg);
1221 priv->rf->stop(dev);
1223 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
1224 reg = rtl818x_ioread8(priv, &priv->map->CONFIG4);
1225 rtl818x_iowrite8(priv, &priv->map->CONFIG4, reg | RTL818X_CONFIG4_VCOOFF);
1226 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
1228 free_irq(priv->pdev->irq, dev);
1230 rtl8180_free_rx_ring(dev);
1231 for (i = 0; i < (dev->queues + 1); i++)
1232 rtl8180_free_tx_ring(dev, i);
1235 static u64 rtl8180_get_tsf(struct ieee80211_hw *dev,
1236 struct ieee80211_vif *vif)
1238 struct rtl8180_priv *priv = dev->priv;
1240 return rtl818x_ioread32(priv, &priv->map->TSFT[0]) |
1241 (u64)(rtl818x_ioread32(priv, &priv->map->TSFT[1])) << 32;
1244 static void rtl8180_beacon_work(struct work_struct *work)
1246 struct rtl8180_vif *vif_priv =
1247 container_of(work, struct rtl8180_vif, beacon_work.work);
1248 struct ieee80211_vif *vif =
1249 container_of((void *)vif_priv, struct ieee80211_vif, drv_priv);
1250 struct ieee80211_hw *dev = vif_priv->dev;
1251 struct ieee80211_mgmt *mgmt;
1252 struct sk_buff *skb;
1254 /* don't overflow the tx ring */
1255 if (ieee80211_queue_stopped(dev, 0))
1258 /* grab a fresh beacon */
1259 skb = ieee80211_beacon_get(dev, vif);
1264 * update beacon timestamp w/ TSF value
1265 * TODO: make hardware update beacon timestamp
1267 mgmt = (struct ieee80211_mgmt *)skb->data;
1268 mgmt->u.beacon.timestamp = cpu_to_le64(rtl8180_get_tsf(dev, vif));
1270 /* TODO: use actual beacon queue */
1271 skb_set_queue_mapping(skb, 0);
1273 rtl8180_tx(dev, NULL, skb);
1277 * schedule next beacon
1278 * TODO: use hardware support for beacon timing
1280 schedule_delayed_work(&vif_priv->beacon_work,
1281 usecs_to_jiffies(1024 * vif->bss_conf.beacon_int));
1284 static int rtl8180_add_interface(struct ieee80211_hw *dev,
1285 struct ieee80211_vif *vif)
1287 struct rtl8180_priv *priv = dev->priv;
1288 struct rtl8180_vif *vif_priv;
1291 * We only support one active interface at a time.
1296 switch (vif->type) {
1297 case NL80211_IFTYPE_STATION:
1298 case NL80211_IFTYPE_ADHOC:
1306 /* Initialize driver private area */
1307 vif_priv = (struct rtl8180_vif *)&vif->drv_priv;
1308 vif_priv->dev = dev;
1309 INIT_DELAYED_WORK(&vif_priv->beacon_work, rtl8180_beacon_work);
1310 vif_priv->enable_beacon = false;
1312 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_CONFIG);
1313 rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->MAC[0],
1314 le32_to_cpu(*(__le32 *)vif->addr));
1315 rtl818x_iowrite16(priv, (__le16 __iomem *)&priv->map->MAC[4],
1316 le16_to_cpu(*(__le16 *)(vif->addr + 4)));
1317 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, RTL818X_EEPROM_CMD_NORMAL);
1322 static void rtl8180_remove_interface(struct ieee80211_hw *dev,
1323 struct ieee80211_vif *vif)
1325 struct rtl8180_priv *priv = dev->priv;
1329 static int rtl8180_config(struct ieee80211_hw *dev, u32 changed)
1331 struct rtl8180_priv *priv = dev->priv;
1332 struct ieee80211_conf *conf = &dev->conf;
1334 priv->rf->set_chan(dev, conf);
1339 static void rtl8187se_conf_ac_parm(struct ieee80211_hw *dev, u8 queue)
1341 const struct ieee80211_tx_queue_params *params;
1342 struct rtl8180_priv *priv = dev->priv;
1351 params = &priv->queue_param[queue];
1353 cw_min = fls(params->cw_min);
1354 cw_max = fls(params->cw_max);
1356 aifs = 10 + params->aifs * priv->slot_time;
1358 /* TODO: check if txop HW is in us (mult by 32) */
1359 txop = params->txop;
1361 ac_param = txop << AC_PARAM_TXOP_LIMIT_SHIFT |
1362 cw_max << AC_PARAM_ECW_MAX_SHIFT |
1363 cw_min << AC_PARAM_ECW_MIN_SHIFT |
1364 aifs << AC_PARAM_AIFS_SHIFT;
1367 case IEEE80211_AC_BK:
1368 rtl818x_iowrite32(priv, &priv->map->AC_BK_PARAM, ac_param);
1370 case IEEE80211_AC_BE:
1371 rtl818x_iowrite32(priv, &priv->map->AC_BE_PARAM, ac_param);
1373 case IEEE80211_AC_VI:
1374 rtl818x_iowrite32(priv, &priv->map->AC_VI_PARAM, ac_param);
1376 case IEEE80211_AC_VO:
1377 rtl818x_iowrite32(priv, &priv->map->AC_VO_PARAM, ac_param);
1382 static int rtl8180_conf_tx(struct ieee80211_hw *dev,
1383 struct ieee80211_vif *vif, u16 queue,
1384 const struct ieee80211_tx_queue_params *params)
1386 struct rtl8180_priv *priv = dev->priv;
1389 /* nothing to do ? */
1390 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8180)
1393 cw_min = fls(params->cw_min);
1394 cw_max = fls(params->cw_max);
1396 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE) {
1397 priv->queue_param[queue] = *params;
1398 rtl8187se_conf_ac_parm(dev, queue);
1400 rtl818x_iowrite8(priv, &priv->map->CW_VAL,
1401 (cw_max << 4) | cw_min);
1405 static void rtl8180_conf_erp(struct ieee80211_hw *dev,
1406 struct ieee80211_bss_conf *info)
1408 struct rtl8180_priv *priv = dev->priv;
1413 /* TODO: should we do something ? */
1414 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8180)
1417 /* I _hope_ this means 10uS for the HW.
1418 * In reference code it is 0x22 for
1419 * both rtl8187L and rtl8187SE
1423 if (info->use_short_slot)
1424 priv->slot_time = 9;
1426 priv->slot_time = 20;
1428 /* 10 is SIFS time in uS */
1429 difs = 10 + 2 * priv->slot_time;
1430 eifs = 10 + difs + priv->ack_time;
1432 /* HW should use 4uS units for EIFS (I'm sure for rtl8185)*/
1433 hw_eifs = DIV_ROUND_UP(eifs, 4);
1436 rtl818x_iowrite8(priv, &priv->map->SLOT, priv->slot_time);
1437 rtl818x_iowrite8(priv, &priv->map->SIFS, sifs);
1438 rtl818x_iowrite8(priv, &priv->map->DIFS, difs);
1440 /* from reference code. set ack timeout reg = eifs reg */
1441 rtl818x_iowrite8(priv, &priv->map->CARRIER_SENSE_COUNTER, hw_eifs);
1443 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE)
1444 rtl818x_iowrite8(priv, &priv->map->EIFS_8187SE, hw_eifs);
1445 else if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8185) {
1446 /* rtl8187/rtl8185 HW bug. After EIFS is elapsed,
1447 * the HW still wait for DIFS.
1448 * HW uses 4uS units for EIFS.
1450 hw_eifs = DIV_ROUND_UP(eifs - difs, 4);
1452 rtl818x_iowrite8(priv, &priv->map->EIFS, hw_eifs);
1456 static void rtl8180_bss_info_changed(struct ieee80211_hw *dev,
1457 struct ieee80211_vif *vif,
1458 struct ieee80211_bss_conf *info,
1461 struct rtl8180_priv *priv = dev->priv;
1462 struct rtl8180_vif *vif_priv;
1466 vif_priv = (struct rtl8180_vif *)&vif->drv_priv;
1468 if (changed & BSS_CHANGED_BSSID) {
1469 rtl818x_iowrite16(priv, (__le16 __iomem *)&priv->map->BSSID[0],
1470 le16_to_cpu(*(__le16 *)info->bssid));
1471 rtl818x_iowrite32(priv, (__le32 __iomem *)&priv->map->BSSID[2],
1472 le32_to_cpu(*(__le32 *)(info->bssid + 2)));
1474 if (is_valid_ether_addr(info->bssid)) {
1475 if (vif->type == NL80211_IFTYPE_ADHOC)
1476 reg = RTL818X_MSR_ADHOC;
1478 reg = RTL818X_MSR_INFRA;
1480 reg = RTL818X_MSR_NO_LINK;
1482 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE)
1483 reg |= RTL818X_MSR_ENEDCA;
1485 rtl818x_iowrite8(priv, &priv->map->MSR, reg);
1488 if (changed & BSS_CHANGED_BASIC_RATES)
1489 rtl8180_conf_basic_rates(dev, info->basic_rates);
1491 if (changed & (BSS_CHANGED_ERP_SLOT | BSS_CHANGED_ERP_PREAMBLE)) {
1493 /* when preamble changes, acktime duration changes, and erp must
1494 * be recalculated. ACK time is calculated at lowest rate.
1495 * Since mac80211 include SIFS time we remove it (-10)
1498 le16_to_cpu(ieee80211_generic_frame_duration(dev,
1500 IEEE80211_BAND_2GHZ, 10,
1501 &priv->rates[0])) - 10;
1503 rtl8180_conf_erp(dev, info);
1505 /* mac80211 supplies aifs_n to driver and calls
1506 * conf_tx callback whether aifs_n changes, NOT
1507 * when aifs changes.
1508 * Aifs should be recalculated if slot changes.
1510 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE) {
1511 for (i = 0; i < 4; i++)
1512 rtl8187se_conf_ac_parm(dev, i);
1516 if (changed & BSS_CHANGED_BEACON_ENABLED)
1517 vif_priv->enable_beacon = info->enable_beacon;
1519 if (changed & (BSS_CHANGED_BEACON_ENABLED | BSS_CHANGED_BEACON)) {
1520 cancel_delayed_work_sync(&vif_priv->beacon_work);
1521 if (vif_priv->enable_beacon)
1522 schedule_work(&vif_priv->beacon_work.work);
1526 static u64 rtl8180_prepare_multicast(struct ieee80211_hw *dev,
1527 struct netdev_hw_addr_list *mc_list)
1529 return netdev_hw_addr_list_count(mc_list);
1532 static void rtl8180_configure_filter(struct ieee80211_hw *dev,
1533 unsigned int changed_flags,
1534 unsigned int *total_flags,
1537 struct rtl8180_priv *priv = dev->priv;
1539 if (changed_flags & FIF_FCSFAIL)
1540 priv->rx_conf ^= RTL818X_RX_CONF_FCS;
1541 if (changed_flags & FIF_CONTROL)
1542 priv->rx_conf ^= RTL818X_RX_CONF_CTRL;
1543 if (changed_flags & FIF_OTHER_BSS)
1544 priv->rx_conf ^= RTL818X_RX_CONF_MONITOR;
1545 if (*total_flags & FIF_ALLMULTI || multicast > 0)
1546 priv->rx_conf |= RTL818X_RX_CONF_MULTICAST;
1548 priv->rx_conf &= ~RTL818X_RX_CONF_MULTICAST;
1552 if (priv->rx_conf & RTL818X_RX_CONF_FCS)
1553 *total_flags |= FIF_FCSFAIL;
1554 if (priv->rx_conf & RTL818X_RX_CONF_CTRL)
1555 *total_flags |= FIF_CONTROL;
1556 if (priv->rx_conf & RTL818X_RX_CONF_MONITOR)
1557 *total_flags |= FIF_OTHER_BSS;
1558 if (priv->rx_conf & RTL818X_RX_CONF_MULTICAST)
1559 *total_flags |= FIF_ALLMULTI;
1561 rtl818x_iowrite32(priv, &priv->map->RX_CONF, priv->rx_conf);
1564 static const struct ieee80211_ops rtl8180_ops = {
1566 .start = rtl8180_start,
1567 .stop = rtl8180_stop,
1568 .add_interface = rtl8180_add_interface,
1569 .remove_interface = rtl8180_remove_interface,
1570 .config = rtl8180_config,
1571 .bss_info_changed = rtl8180_bss_info_changed,
1572 .conf_tx = rtl8180_conf_tx,
1573 .prepare_multicast = rtl8180_prepare_multicast,
1574 .configure_filter = rtl8180_configure_filter,
1575 .get_tsf = rtl8180_get_tsf,
1578 static void rtl8180_eeprom_register_read(struct eeprom_93cx6 *eeprom)
1580 struct rtl8180_priv *priv = eeprom->data;
1581 u8 reg = rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
1583 eeprom->reg_data_in = reg & RTL818X_EEPROM_CMD_WRITE;
1584 eeprom->reg_data_out = reg & RTL818X_EEPROM_CMD_READ;
1585 eeprom->reg_data_clock = reg & RTL818X_EEPROM_CMD_CK;
1586 eeprom->reg_chip_select = reg & RTL818X_EEPROM_CMD_CS;
1589 static void rtl8180_eeprom_register_write(struct eeprom_93cx6 *eeprom)
1591 struct rtl8180_priv *priv = eeprom->data;
1594 if (eeprom->reg_data_in)
1595 reg |= RTL818X_EEPROM_CMD_WRITE;
1596 if (eeprom->reg_data_out)
1597 reg |= RTL818X_EEPROM_CMD_READ;
1598 if (eeprom->reg_data_clock)
1599 reg |= RTL818X_EEPROM_CMD_CK;
1600 if (eeprom->reg_chip_select)
1601 reg |= RTL818X_EEPROM_CMD_CS;
1603 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD, reg);
1604 rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
1608 static void rtl8180_eeprom_read(struct rtl8180_priv *priv)
1610 struct eeprom_93cx6 eeprom;
1611 int eeprom_cck_table_adr;
1616 eeprom.register_read = rtl8180_eeprom_register_read;
1617 eeprom.register_write = rtl8180_eeprom_register_write;
1618 if (rtl818x_ioread32(priv, &priv->map->RX_CONF) & (1 << 6))
1619 eeprom.width = PCI_EEPROM_WIDTH_93C66;
1621 eeprom.width = PCI_EEPROM_WIDTH_93C46;
1623 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
1624 RTL818X_EEPROM_CMD_PROGRAM);
1625 rtl818x_ioread8(priv, &priv->map->EEPROM_CMD);
1628 eeprom_93cx6_read(&eeprom, 0x06, &eeprom_val);
1630 priv->rf_type = eeprom_val;
1632 eeprom_93cx6_read(&eeprom, 0x17, &eeprom_val);
1633 priv->csthreshold = eeprom_val >> 8;
1635 eeprom_93cx6_multiread(&eeprom, 0x7, (__le16 *)priv->mac_addr, 3);
1637 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE)
1638 eeprom_cck_table_adr = 0x30;
1640 eeprom_cck_table_adr = 0x10;
1643 for (i = 0; i < 14; i += 2) {
1645 eeprom_93cx6_read(&eeprom, eeprom_cck_table_adr + (i >> 1),
1647 priv->channels[i].hw_value = txpwr & 0xFF;
1648 priv->channels[i + 1].hw_value = txpwr >> 8;
1652 if (priv->chip_family != RTL818X_CHIP_FAMILY_RTL8180) {
1653 for (i = 0; i < 14; i += 2) {
1655 eeprom_93cx6_read(&eeprom, 0x20 + (i >> 1), &txpwr);
1656 priv->channels[i].hw_value |= (txpwr & 0xFF) << 8;
1657 priv->channels[i + 1].hw_value |= txpwr & 0xFF00;
1661 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8180) {
1663 eeprom_93cx6_multiread(&eeprom, 0xD, (__le16 *)&anaparam, 2);
1664 priv->anaparam = le32_to_cpu(anaparam);
1665 eeprom_93cx6_read(&eeprom, 0x19, &priv->rfparam);
1668 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE) {
1669 eeprom_93cx6_read(&eeprom, 0x3F, &eeprom_val);
1670 priv->antenna_diversity_en = !!(eeprom_val & 0x100);
1671 priv->antenna_diversity_default = (eeprom_val & 0xC00) == 0x400;
1673 eeprom_93cx6_read(&eeprom, 0x7C, &eeprom_val);
1674 priv->xtal_out = eeprom_val & 0xF;
1675 priv->xtal_in = (eeprom_val & 0xF0) >> 4;
1676 priv->xtal_cal = !!(eeprom_val & 0x1000);
1677 priv->thermal_meter_val = (eeprom_val & 0xF00) >> 8;
1678 priv->thermal_meter_en = !!(eeprom_val & 0x2000);
1681 rtl818x_iowrite8(priv, &priv->map->EEPROM_CMD,
1682 RTL818X_EEPROM_CMD_NORMAL);
1685 static int rtl8180_probe(struct pci_dev *pdev,
1686 const struct pci_device_id *id)
1688 struct ieee80211_hw *dev;
1689 struct rtl8180_priv *priv;
1690 unsigned long mem_addr, mem_len;
1691 unsigned int io_addr, io_len;
1693 const char *chip_name, *rf_name = NULL;
1696 err = pci_enable_device(pdev);
1698 printk(KERN_ERR "%s (rtl8180): Cannot enable new PCI device\n",
1703 err = pci_request_regions(pdev, KBUILD_MODNAME);
1705 printk(KERN_ERR "%s (rtl8180): Cannot obtain PCI resources\n",
1710 io_addr = pci_resource_start(pdev, 0);
1711 io_len = pci_resource_len(pdev, 0);
1712 mem_addr = pci_resource_start(pdev, 1);
1713 mem_len = pci_resource_len(pdev, 1);
1715 if (mem_len < sizeof(struct rtl818x_csr) ||
1716 io_len < sizeof(struct rtl818x_csr)) {
1717 printk(KERN_ERR "%s (rtl8180): Too short PCI resources\n",
1723 if ((err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32))) ||
1724 (err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))) {
1725 printk(KERN_ERR "%s (rtl8180): No suitable DMA available\n",
1730 pci_set_master(pdev);
1732 dev = ieee80211_alloc_hw(sizeof(*priv), &rtl8180_ops);
1734 printk(KERN_ERR "%s (rtl8180): ieee80211 alloc failed\n",
1744 SET_IEEE80211_DEV(dev, &pdev->dev);
1745 pci_set_drvdata(pdev, dev);
1747 priv->map_pio = false;
1748 priv->map = pci_iomap(pdev, 1, mem_len);
1750 priv->map = pci_iomap(pdev, 0, io_len);
1751 priv->map_pio = true;
1755 dev_err(&pdev->dev, "Cannot map device memory/PIO\n");
1760 BUILD_BUG_ON(sizeof(priv->channels) != sizeof(rtl818x_channels));
1761 BUILD_BUG_ON(sizeof(priv->rates) != sizeof(rtl818x_rates));
1763 memcpy(priv->channels, rtl818x_channels, sizeof(rtl818x_channels));
1764 memcpy(priv->rates, rtl818x_rates, sizeof(rtl818x_rates));
1766 priv->band.band = IEEE80211_BAND_2GHZ;
1767 priv->band.channels = priv->channels;
1768 priv->band.n_channels = ARRAY_SIZE(rtl818x_channels);
1769 priv->band.bitrates = priv->rates;
1770 priv->band.n_bitrates = 4;
1771 dev->wiphy->bands[IEEE80211_BAND_2GHZ] = &priv->band;
1773 dev->flags = IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING |
1774 IEEE80211_HW_RX_INCLUDES_FCS;
1775 dev->vif_data_size = sizeof(struct rtl8180_vif);
1776 dev->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION) |
1777 BIT(NL80211_IFTYPE_ADHOC);
1778 dev->max_signal = 65;
1780 reg = rtl818x_ioread32(priv, &priv->map->TX_CONF);
1781 reg &= RTL818X_TX_CONF_HWVER_MASK;
1783 case RTL818X_TX_CONF_R8180_ABCD:
1784 chip_name = "RTL8180";
1785 priv->chip_family = RTL818X_CHIP_FAMILY_RTL8180;
1788 case RTL818X_TX_CONF_R8180_F:
1789 chip_name = "RTL8180vF";
1790 priv->chip_family = RTL818X_CHIP_FAMILY_RTL8180;
1793 case RTL818X_TX_CONF_R8185_ABC:
1794 chip_name = "RTL8185";
1795 priv->chip_family = RTL818X_CHIP_FAMILY_RTL8185;
1798 case RTL818X_TX_CONF_R8185_D:
1799 chip_name = "RTL8185vD";
1800 priv->chip_family = RTL818X_CHIP_FAMILY_RTL8185;
1803 case RTL818X_TX_CONF_RTL8187SE:
1804 chip_name = "RTL8187SE";
1805 if (priv->map_pio) {
1807 "MMIO failed. PIO not supported on RTL8187SE\n");
1811 priv->chip_family = RTL818X_CHIP_FAMILY_RTL8187SE;
1815 printk(KERN_ERR "%s (rtl8180): Unknown chip! (0x%x)\n",
1816 pci_name(pdev), reg >> 25);
1821 /* we declare to MAC80211 all the queues except for beacon queue
1822 * that will be eventually handled by DRV.
1823 * TX rings are arranged in such a way that lower is the IDX,
1824 * higher is the priority, in order to achieve direct mapping
1825 * with mac80211, however the beacon queue is an exception and it
1826 * is mapped on the highst tx ring IDX.
1828 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE)
1829 dev->queues = RTL8187SE_NR_TX_QUEUES - 1;
1831 dev->queues = RTL8180_NR_TX_QUEUES - 1;
1833 if (priv->chip_family != RTL818X_CHIP_FAMILY_RTL8180) {
1834 priv->band.n_bitrates = ARRAY_SIZE(rtl818x_rates);
1835 pci_try_set_mwi(pdev);
1838 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8185)
1839 dev->flags |= IEEE80211_HW_SIGNAL_DBM;
1841 dev->flags |= IEEE80211_HW_SIGNAL_UNSPEC;
1843 rtl8180_eeprom_read(priv);
1845 switch (priv->rf_type) {
1846 case 1: rf_name = "Intersil";
1848 case 2: rf_name = "RFMD";
1850 case 3: priv->rf = &sa2400_rf_ops;
1852 case 4: priv->rf = &max2820_rf_ops;
1854 case 5: priv->rf = &grf5101_rf_ops;
1857 if (priv->chip_family == RTL818X_CHIP_FAMILY_RTL8187SE)
1858 priv->rf = rtl8187se_detect_rf(dev);
1860 priv->rf = rtl8180_detect_rf(dev);
1863 rf_name = "RTL8255";
1866 printk(KERN_ERR "%s (rtl8180): Unknown RF! (0x%x)\n",
1867 pci_name(pdev), priv->rf_type);
1873 printk(KERN_ERR "%s (rtl8180): %s RF frontend not supported!\n",
1874 pci_name(pdev), rf_name);
1879 if (!is_valid_ether_addr(priv->mac_addr)) {
1880 printk(KERN_WARNING "%s (rtl8180): Invalid hwaddr! Using"
1881 " randomly generated MAC addr\n", pci_name(pdev));
1882 eth_random_addr(priv->mac_addr);
1884 SET_IEEE80211_PERM_ADDR(dev, priv->mac_addr);
1886 spin_lock_init(&priv->lock);
1888 err = ieee80211_register_hw(dev);
1890 printk(KERN_ERR "%s (rtl8180): Cannot register device\n",
1895 wiphy_info(dev->wiphy, "hwaddr %pm, %s + %s\n",
1896 priv->mac_addr, chip_name, priv->rf->name);
1901 pci_iounmap(pdev, priv->map);
1904 ieee80211_free_hw(dev);
1907 pci_release_regions(pdev);
1908 pci_disable_device(pdev);
1912 static void rtl8180_remove(struct pci_dev *pdev)
1914 struct ieee80211_hw *dev = pci_get_drvdata(pdev);
1915 struct rtl8180_priv *priv;
1920 ieee80211_unregister_hw(dev);
1924 pci_iounmap(pdev, priv->map);
1925 pci_release_regions(pdev);
1926 pci_disable_device(pdev);
1927 ieee80211_free_hw(dev);
1931 static int rtl8180_suspend(struct pci_dev *pdev, pm_message_t state)
1933 pci_save_state(pdev);
1934 pci_set_power_state(pdev, pci_choose_state(pdev, state));
1938 static int rtl8180_resume(struct pci_dev *pdev)
1940 pci_set_power_state(pdev, PCI_D0);
1941 pci_restore_state(pdev);
1945 #endif /* CONFIG_PM */
1947 static struct pci_driver rtl8180_driver = {
1948 .name = KBUILD_MODNAME,
1949 .id_table = rtl8180_table,
1950 .probe = rtl8180_probe,
1951 .remove = rtl8180_remove,
1953 .suspend = rtl8180_suspend,
1954 .resume = rtl8180_resume,
1955 #endif /* CONFIG_PM */
1958 module_pci_driver(rtl8180_driver);