1 /******************************************************************************
\r
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
\r
5 * This program is free software; you can redistribute it and/or modify it
\r
6 * under the terms of version 2 of the GNU General Public License as
\r
7 * published by the Free Software Foundation.
\r
9 * This program is distributed in the hope that it will be useful, but WITHOUT
\r
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
\r
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
\r
14 * You should have received a copy of the GNU General Public License along with
\r
15 * this program; if not, write to the Free Software Foundation, Inc.,
\r
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
\r
19 ******************************************************************************/
\r
21 #ifndef __HAL_PG_H__
\r
22 #define __HAL_PG_H__
\r
24 //====================================================
\r
25 // EEPROM/Efuse PG Offset for 8192 CE/CU
\r
26 //====================================================
\r
27 #define EEPROM_VID_92C 0x0A
\r
28 #define EEPROM_PID_92C 0x0C
\r
29 #define EEPROM_DID_92C 0x0C
\r
30 #define EEPROM_SVID_92C 0x0E
\r
31 #define EEPROM_SMID_92C 0x10
\r
32 #define EEPROM_MAC_ADDR_92C 0x16
\r
34 #define EEPROM_MAC_ADDR 0x16
\r
35 #define EEPROM_TV_OPTION 0x50
\r
36 #define EEPROM_SUBCUSTOMER_ID_92C 0x59
\r
37 #define EEPROM_CCK_TX_PWR_INX 0x5A
\r
38 #define EEPROM_HT40_1S_TX_PWR_INX 0x60
\r
39 #define EEPROM_HT40_2S_TX_PWR_INX_DIFF 0x66
\r
40 #define EEPROM_HT20_TX_PWR_INX_DIFF 0x69
\r
41 #define EEPROM_OFDM_TX_PWR_INX_DIFF 0x6C
\r
42 #define EEPROM_HT40_MAX_PWR_OFFSET 0x6F
\r
43 #define EEPROM_HT20_MAX_PWR_OFFSET 0x72
\r
44 #define EEPROM_CHANNEL_PLAN_92C 0x75
\r
45 #define EEPROM_TSSI_A 0x76
\r
46 #define EEPROM_TSSI_B 0x77
\r
47 #define EEPROM_THERMAL_METER_92C 0x78
\r
48 #define EEPROM_RF_OPT1_92C 0x79
\r
49 #define EEPROM_RF_OPT2_92C 0x7A
\r
50 #define EEPROM_RF_OPT3_92C 0x7B
\r
51 #define EEPROM_RF_OPT4_92C 0x7C
\r
52 #define EEPROM_VERSION_92C 0x7E
\r
53 #define EEPROM_CUSTOMER_ID_92C 0x7F
\r
55 #define EEPROM_NORMAL_CHANNEL_PLAN 0x75
\r
56 #define EEPROM_NORMAL_BoardType_92C EEPROM_RF_OPT1_92C
\r
57 #define BOARD_TYPE_NORMAL_MASK 0xE0
\r
58 #define BOARD_TYPE_TEST_MASK 0xF
\r
59 #define EEPROM_TYPE_ID 0x7E
\r
62 #define EEPROM_PCIE_DEV_CAP_01 0xE0 // Express device capability in PCIe configuration space, i.e., map to offset 0x74
\r
63 #define EEPROM_PCIE_DEV_CAP_02 0xE1 // Express device capability in PCIe configuration space, i.e., map to offset 0x75
\r
65 // EEPROM address for Test chip
\r
66 #define EEPROM_TEST_USB_OPT 0x0E
\r
68 #define EEPROM_EASY_REPLACEMENT 0x50//BIT0 1 for build-in module, 0 for external dongle
\r
70 //====================================================
\r
71 // EEPROM/Efuse PG Offset for 8723AE/8723AU/8723AS
\r
72 //====================================================
\r
73 #define EEPROM_CCK_TX_PWR_INX_8723A 0x10
\r
74 #define EEPROM_HT40_1S_TX_PWR_INX_8723A 0x16
\r
75 #define EEPROM_HT20_TX_PWR_INX_DIFF_8723A 0x1C
\r
76 #define EEPROM_OFDM_TX_PWR_INX_DIFF_8723A 0x1F
\r
77 #define EEPROM_HT40_MAX_PWR_OFFSET_8723A 0x22
\r
78 #define EEPROM_HT20_MAX_PWR_OFFSET_8723A 0x25
\r
80 #define EEPROM_ChannelPlan_8723A 0x28
\r
81 #define EEPROM_TSSI_A_8723A 0x29
\r
82 #define EEPROM_THERMAL_METER_8723A 0x2A
\r
83 #define RF_OPTION1_8723A 0x2B
\r
84 #define RF_OPTION2_8723A 0x2C
\r
85 #define RF_OPTION3_8723A 0x2D
\r
86 #define RF_OPTION4_8723A 0x2E
\r
87 #define EEPROM_VERSION_8723A 0x30
\r
88 #define EEPROM_CustomID_8723A 0x31
\r
89 #define EEPROM_SubCustomID_8723A 0x32
\r
90 #define EEPROM_XTAL_K_8723A 0x33
\r
91 #define EEPROM_Chipset_8723A 0x34
\r
95 #define EEPROM_VID_8723AE 0x49
\r
96 #define EEPROM_DID_8723AE 0x4B
\r
97 #define EEPROM_SVID_8723AE 0x4D
\r
98 #define EEPROM_SMID_8723AE 0x4F
\r
99 #define EEPROM_MAC_ADDR_8723AE 0x67
\r
102 #define EEPROM_MAC_ADDR_8723AU 0xC6
\r
103 #define EEPROM_VID_8723AU 0xB7
\r
104 #define EEPROM_PID_8723AU 0xB9
\r
107 #define EEPROM_MAC_ADDR_8723AS 0xAA
\r
109 //====================================================
\r
110 // EEPROM/Efuse PG Offset for 8192 DE/DU
\r
111 //====================================================
\r
113 #define RTL8190_EEPROM_ID 0x8129 // 0-1
\r
114 #define EEPROM_HPON 0x02 // LDO settings.2-5
\r
115 #define EEPROM_CLK 0x06 // Clock settings.6-7
\r
116 #define EEPROM_MAC_FUNCTION 0x08 // SE Test mode.8
\r
118 #define EEPROM_MAC_ADDR_MAC0_92DE 0x55
\r
119 #define EEPROM_MAC_ADDR_MAC1_92DE 0x5B
\r
122 #define EEPROM_ENDPOINT_SETTING 0x10
\r
123 #define EEPROM_CHIRP_K 0x12 // Changed
\r
124 #define EEPROM_USB_PHY 0x13 // Changed
\r
125 #define EEPROM_STRING 0x1F
\r
126 #define EEPROM_SUBCUSTOMER_ID_92D 0x59
\r
128 #define EEPROM_MAC_ADDR_MAC0_92DU 0x19
\r
129 #define EEPROM_MAC_ADDR_MAC1_92DU 0x5B
\r
130 //----------------------------------------------------------------
\r
131 // 2.4G band Tx power index setting
\r
132 #define EEPROM_CCK_TX_PWR_INX_2G_92D 0x61
\r
133 #define EEPROM_HT40_1S_TX_PWR_INX_2G_92D 0x67
\r
134 #define EEPROM_HT40_2S_TX_PWR_INX_DIFF_2G_92D 0x6D
\r
135 #define EEPROM_HT20_TX_PWR_INX_DIFF_2G_92D 0x70
\r
136 #define EEPROM_OFDM_TX_PWR_INX_DIFF_2G_92D 0x73
\r
137 #define EEPROM_HT40_MAX_PWR_OFFSET_2G_92D 0x76
\r
138 #define EEPROM_HT20_MAX_PWR_OFFSET_2G_92D 0x79
\r
140 //5GL channel 32-64
\r
141 #define EEPROM_HT40_1S_TX_PWR_INX_5GL_92D 0x7C
\r
142 #define EEPROM_HT40_2S_TX_PWR_INX_DIFF_5GL_92D 0x82
\r
143 #define EEPROM_HT20_TX_PWR_INX_DIFF_5GL_92D 0x85
\r
144 #define EEPROM_OFDM_TX_PWR_INX_DIFF_5GL_92D 0x88
\r
145 #define EEPROM_HT40_MAX_PWR_OFFSET_5GL_92D 0x8B
\r
146 #define EEPROM_HT20_MAX_PWR_OFFSET_5GL_92D 0x8E
\r
148 //5GM channel 100-140
\r
149 #define EEPROM_HT40_1S_TX_PWR_INX_5GM_92D 0x91
\r
150 #define EEPROM_HT40_2S_TX_PWR_INX_DIFF_5GM_92D 0x97
\r
151 #define EEPROM_HT20_TX_PWR_INX_DIFF_5GM_92D 0x9A
\r
152 #define EEPROM_OFDM_TX_PWR_INX_DIFF_5GM_92D 0x9D
\r
153 #define EEPROM_HT40_MAX_PWR_OFFSET_5GM_92D 0xA0
\r
154 #define EEPROM_HT20_MAX_PWR_OFFSET_5GM_92D 0xA3
\r
156 //5GH channel 149-165
\r
157 #define EEPROM_HT40_1S_TX_PWR_INX_5GH_92D 0xA6
\r
158 #define EEPROM_HT40_2S_TX_PWR_INX_DIFF_5GH_92D 0xAC
\r
159 #define EEPROM_HT20_TX_PWR_INX_DIFF_5GH_92D 0xAF
\r
160 #define EEPROM_OFDM_TX_PWR_INX_DIFF_5GH_92D 0xB2
\r
161 #define EEPROM_HT40_MAX_PWR_OFFSET_5GH_92D 0xB5
\r
162 #define EEPROM_HT20_MAX_PWR_OFFSET_5GH_92D 0xB8
\r
165 #define EEPROM_CHANNEL_PLAN_92D 0xBB // Map of supported channels.
\r
166 #define EEPROM_TEST_CHANNEL_PLAN_92D 0xBB
\r
167 #define EEPROM_THERMAL_METER_92D 0xC3 //[4:0]
\r
168 #define EEPROM_IQK_DELTA_92D 0xBC
\r
169 #define EEPROM_LCK_DELTA_92D 0xBC
\r
170 #define EEPROM_XTAL_K_92D 0xBD //[7:5]
\r
171 #define EEPROM_TSSI_A_5G_92D 0xBE
\r
172 #define EEPROM_TSSI_B_5G_92D 0xBF
\r
173 #define EEPROM_TSSI_AB_5G_92D 0xC0
\r
175 #define EEPROM_RF_OPT1_92D 0xC4
\r
176 #define EEPROM_RF_OPT2_92D 0xC5
\r
177 #define EEPROM_RF_OPT3_92D 0xC6
\r
178 #define EEPROM_RF_OPT4_92D 0xC7
\r
179 #define EEPROM_RF_OPT5_92D 0xC8
\r
180 #define EEPROM_RF_OPT6_92D 0xC9
\r
181 #define EEPROM_RF_OPT7_92D 0xCC
\r
183 #define EEPROM_NORMAL_BoardType_92D EEPROM_RF_OPT1_92D //[7:5]
\r
185 #define EEPROM_WIDIPAIRING_ADDR 0xF0
\r
186 #define EEPROM_WIDIPAIRING_KEY 0xF6
\r
188 #define EEPROM_DEF_PART_NO 0x3FD //Byte
\r
189 #define EEPROME_CHIP_VERSION_L 0x3FF
\r
190 #define EEPROME_CHIP_VERSION_H 0x3FE
\r
192 //----------------------------------------------------------------
\r
194 #define EEPROM_VID_92DE 0x28
\r
195 #define EEPROM_PID_92DE 0x2A
\r
196 #define EEPROM_SVID_92DE 0x2C
\r
197 #define EEPROM_SMID_92DE 0x2E
\r
198 #define EEPROM_PATHDIV_92D 0xC4
\r
200 #define EEPROM_BOARD_OPTIONS_92D 0xC4
\r
201 #define EEPROM_5G_LNA_GAIN_92D 0xC6
\r
202 #define EEPROM_FEATURE_OPTIONS_92D 0xC7
\r
203 #define EEPROM_BT_SETTING_92D 0xC8
\r
205 #define EEPROM_VERSION_92D 0xCA
\r
206 #define EEPROM_CUSTOMER_ID_92D 0xCB
\r
208 #define EEPROM_VID_92DU 0xC
\r
209 #define EEPROM_PID_92DU 0xE
\r
211 //====================================================
\r
212 // EEPROM/Efuse PG Offset for 88EE/88EU/88ES
\r
213 //====================================================
\r
214 #define EEPROM_TX_PWR_INX_88E 0x10
\r
216 #define EEPROM_ChannelPlan_88E 0xB8
\r
217 #define EEPROM_XTAL_88E 0xB9
\r
218 #define EEPROM_THERMAL_METER_88E 0xBA
\r
219 #define EEPROM_IQK_LCK_88E 0xBB
\r
221 #define EEPROM_RF_BOARD_OPTION_88E 0xC1
\r
222 #define EEPROM_RF_FEATURE_OPTION_88E 0xC2
\r
223 #define EEPROM_RF_BT_SETTING_88E 0xC3
\r
224 #define EEPROM_VERSION_88E 0xC4
\r
225 #define EEPROM_CustomID_88E 0xC5
\r
226 #define EEPROM_RF_ANTENNA_OPT_88E 0xC9
\r
229 #define EEPROM_MAC_ADDR_88EE 0xD0
\r
230 #define EEPROM_VID_88EE 0xD6
\r
231 #define EEPROM_DID_88EE 0xD8
\r
232 #define EEPROM_SVID_88EE 0xDA
\r
233 #define EEPROM_SMID_88EE 0xDC
\r
236 #define EEPROM_MAC_ADDR_88EU 0xD7
\r
237 #define EEPROM_VID_88EU 0xD0
\r
238 #define EEPROM_PID_88EU 0xD2
\r
239 #define EEPROM_USB_OPTIONAL_FUNCTION0 0xD4 //92EU is the same
\r
240 #define EEPROM_USB_OPTIONAL_FUNCTION0_8811AU 0x104
\r
243 #define EEPROM_MAC_ADDR_88ES 0x11A
\r
244 //====================================================
\r
245 // EEPROM/Efuse PG Offset for 8192EE/8192EU/8192ES
\r
246 //====================================================
\r
247 // 0x10 ~ 0x63 = TX power area.
\r
248 #define EEPROM_TX_PWR_INX_8192E 0x10
\r
250 #define EEPROM_ChannelPlan_8192E 0xB8
\r
251 #define EEPROM_XTAL_8192E 0xB9
\r
252 #define EEPROM_THERMAL_METER_8192E 0xBA
\r
253 #define EEPROM_IQK_LCK_8192E 0xBB
\r
254 #define EEPROM_2G_5G_PA_TYPE_8192E 0xBC
\r
255 #define EEPROM_2G_LNA_TYPE_GAIN_SEL_8192E 0xBD
\r
256 #define EEPROM_5G_LNA_TYPE_GAIN_SEL_8192E 0xBF
\r
258 #define EEPROM_RF_BOARD_OPTION_8192E 0xC1
\r
259 #define EEPROM_RF_FEATURE_OPTION_8192E 0xC2
\r
260 #define EEPROM_RF_BT_SETTING_8192E 0xC3
\r
261 #define EEPROM_VERSION_8192E 0xC4
\r
262 #define EEPROM_CustomID_8192E 0xC5
\r
263 #define EEPROM_TX_BBSWING_2G_8192E 0xC6
\r
264 #define EEPROM_TX_BBSWING_5G_8192E 0xC7
\r
265 #define EEPROM_TX_PWR_CALIBRATE_RATE_8192E 0xC8
\r
266 #define EEPROM_RF_ANTENNA_OPT_8192E 0xC9
\r
269 #define EEPROM_MAC_ADDR_8192EE 0xD0
\r
270 #define EEPROM_VID_8192EE 0xD6
\r
271 #define EEPROM_DID_8192EE 0xD8
\r
272 #define EEPROM_SVID_8192EE 0xDA
\r
273 #define EEPROM_SMID_8192EE 0xDC
\r
276 #define EEPROM_MAC_ADDR_8192EU 0xD7
\r
277 #define EEPROM_VID_8192EU 0xD0
\r
278 #define EEPROM_PID_8192EU 0xD2
\r
279 #define EEPROM_PA_TYPE_8192EU 0xBC
\r
280 #define EEPROM_LNA_TYPE_2G_8192EU 0xBD
\r
281 #define EEPROM_LNA_TYPE_5G_8192EU 0xBF
\r
284 #define EEPROM_MAC_ADDR_8192ES 0x11B
\r
285 //====================================================
\r
286 // EEPROM/Efuse PG Offset for 8812AE/8812AU/8812AS
\r
287 //====================================================
\r
288 // 0x10 ~ 0x63 = TX power area.
\r
289 #define EEPROM_USB_MODE_8812 0x08
\r
290 #define EEPROM_TX_PWR_INX_8812 0x10
\r
292 #define EEPROM_ChannelPlan_8812 0xB8
\r
293 #define EEPROM_XTAL_8812 0xB9
\r
294 #define EEPROM_THERMAL_METER_8812 0xBA
\r
295 #define EEPROM_IQK_LCK_8812 0xBB
\r
296 #define EEPROM_2G_5G_PA_TYPE_8812 0xBC
\r
297 #define EEPROM_2G_LNA_TYPE_GAIN_SEL_8812 0xBD
\r
298 #define EEPROM_5G_LNA_TYPE_GAIN_SEL_8812 0xBF
\r
300 #define EEPROM_RF_BOARD_OPTION_8812 0xC1
\r
301 #define EEPROM_RF_FEATURE_OPTION_8812 0xC2
\r
302 #define EEPROM_RF_BT_SETTING_8812 0xC3
\r
303 #define EEPROM_VERSION_8812 0xC4
\r
304 #define EEPROM_CustomID_8812 0xC5
\r
305 #define EEPROM_TX_BBSWING_2G_8812 0xC6
\r
306 #define EEPROM_TX_BBSWING_5G_8812 0xC7
\r
307 #define EEPROM_TX_PWR_CALIBRATE_RATE_8812 0xC8
\r
308 #define EEPROM_RF_ANTENNA_OPT_8812 0xC9
\r
309 #define EEPROM_RFE_OPTION_8812 0xCA
\r
312 #define EEPROM_MAC_ADDR_8812AE 0xD0
\r
313 #define EEPROM_VID_8812AE 0xD6
\r
314 #define EEPROM_DID_8812AE 0xD8
\r
315 #define EEPROM_SVID_8812AE 0xDA
\r
316 #define EEPROM_SMID_8812AE 0xDC
\r
319 #define EEPROM_MAC_ADDR_8812AU 0xD7
\r
320 #define EEPROM_VID_8812AU 0xD0
\r
321 #define EEPROM_PID_8812AU 0xD2
\r
322 #define EEPROM_PA_TYPE_8812AU 0xBC
\r
323 #define EEPROM_LNA_TYPE_2G_8812AU 0xBD
\r
324 #define EEPROM_LNA_TYPE_5G_8812AU 0xBF
\r
326 //====================================================
\r
327 // EEPROM/Efuse PG Offset for 8821AE/8821AU/8821AS
\r
328 //====================================================
\r
329 #define EEPROM_TX_PWR_INX_8821 0x10
\r
331 #define EEPROM_ChannelPlan_8821 0xB8
\r
332 #define EEPROM_XTAL_8821 0xB9
\r
333 #define EEPROM_THERMAL_METER_8821 0xBA
\r
334 #define EEPROM_IQK_LCK_8821 0xBB
\r
337 #define EEPROM_RF_BOARD_OPTION_8821 0xC1
\r
338 #define EEPROM_RF_FEATURE_OPTION_8821 0xC2
\r
339 #define EEPROM_RF_BT_SETTING_8821 0xC3
\r
340 #define EEPROM_VERSION_8821 0xC4
\r
341 #define EEPROM_CustomID_8821 0xC5
\r
342 #define EEPROM_RF_ANTENNA_OPT_8821 0xC9
\r
345 #define EEPROM_MAC_ADDR_8821AE 0xD0
\r
346 #define EEPROM_VID_8821AE 0xD6
\r
347 #define EEPROM_DID_8821AE 0xD8
\r
348 #define EEPROM_SVID_8821AE 0xDA
\r
349 #define EEPROM_SMID_8821AE 0xDC
\r
352 #define EEPROM_PA_TYPE_8821AU 0xBC
\r
353 #define EEPROM_LNA_TYPE_8821AU 0xBF
\r
356 #define EEPROM_MAC_ADDR_8821AS 0x11A
\r
359 #define EEPROM_MAC_ADDR_8821AU 0x107
\r
360 #define EEPROM_VID_8821AU 0x100
\r
361 #define EEPROM_PID_8821AU 0x102
\r
364 //====================================================
\r
365 // EEPROM/Efuse PG Offset for 8192 SE/SU
\r
366 //====================================================
\r
367 #define EEPROM_VID_92SE 0x0A
\r
368 #define EEPROM_DID_92SE 0x0C
\r
369 #define EEPROM_SVID_92SE 0x0E
\r
370 #define EEPROM_SMID_92SE 0x10
\r
372 #define EEPROM_MAC_ADDR_92S 0x12
\r
374 #define EEPROM_TSSI_A_92SE 0x74
\r
375 #define EEPROM_TSSI_B_92SE 0x75
\r
377 #define EEPROM_Version_92SE 0x7C
\r
380 #define EEPROM_VID_92SU 0x08
\r
381 #define EEPROM_PID_92SU 0x0A
\r
383 #define EEPROM_Version_92SU 0x50
\r
384 #define EEPROM_TSSI_A_92SU 0x6b
\r
385 #define EEPROM_TSSI_B_92SU 0x6c
\r
387 //====================================================
\r
388 // EEPROM/Efuse PG Offset for 8723BE/8723BU/8723BS
\r
389 //====================================================
\r
390 // 0x10 ~ 0x63 = TX power area.
\r
391 #define EEPROM_TX_PWR_INX_8723B 0x10
\r
393 #define EEPROM_ChannelPlan_8723B 0xB8
\r
394 #define EEPROM_XTAL_8723B 0xB9
\r
395 #define EEPROM_THERMAL_METER_8723B 0xBA
\r
396 #define EEPROM_IQK_LCK_8723B 0xBB
\r
397 #define EEPROM_2G_5G_PA_TYPE_8723B 0xBC
\r
398 #define EEPROM_2G_LNA_TYPE_GAIN_SEL_8723B 0xBD
\r
399 #define EEPROM_5G_LNA_TYPE_GAIN_SEL_8723B 0xBF
\r
401 #define EEPROM_RF_BOARD_OPTION_8723B 0xC1
\r
402 #define EEPROM_FEATURE_OPTION_8723B 0xC2
\r
403 #define EEPROM_RF_BT_SETTING_8723B 0xC3
\r
404 #define EEPROM_VERSION_8723B 0xC4
\r
405 #define EEPROM_CustomID_8723B 0xC5
\r
406 #define EEPROM_TX_BBSWING_2G_8723B 0xC6
\r
407 #define EEPROM_TX_PWR_CALIBRATE_RATE_8723B 0xC8
\r
408 #define EEPROM_RF_ANTENNA_OPT_8723B 0xC9
\r
409 #define EEPROM_RFE_OPTION_8723B 0xCA
\r
412 #define EEPROM_MAC_ADDR_8723BE 0xD0
\r
413 #define EEPROM_VID_8723BE 0xD6
\r
414 #define EEPROM_DID_8723BE 0xD8
\r
415 #define EEPROM_SVID_8723BE 0xDA
\r
416 #define EEPROM_SMID_8723BE 0xDC
\r
419 #define EEPROM_MAC_ADDR_8723BU 0x107
\r
420 #define EEPROM_VID_8723BU 0x100
\r
421 #define EEPROM_PID_8723BU 0x102
\r
422 #define EEPROM_PA_TYPE_8723BU 0xBC
\r
423 #define EEPROM_LNA_TYPE_2G_8723BU 0xBD
\r
426 #define EEPROM_MAC_ADDR_8723BS 0x11A
\r
427 #define EEPROM_Voltage_ADDR_8723B 0x8
\r
430 //====================================================
\r
431 // EEPROM/Efuse Value Type
\r
432 //====================================================
\r
433 #define EETYPE_TX_PWR 0x0
\r
434 //====================================================
\r
435 // EEPROM/Efuse Default Value
\r
436 //====================================================
\r
437 #define EEPROM_CID_DEFAULT 0x0
\r
438 #define EEPROM_CID_DEFAULT_EXT 0xFF // Reserved for Realtek
\r
439 #define EEPROM_CID_TOSHIBA 0x4
\r
440 #define EEPROM_CID_CCX 0x10
\r
441 #define EEPROM_CID_QMI 0x0D
\r
442 #define EEPROM_CID_WHQL 0xFE
\r
444 #define EEPROM_CHANNEL_PLAN_FCC 0x0
\r
445 #define EEPROM_CHANNEL_PLAN_IC 0x1
\r
446 #define EEPROM_CHANNEL_PLAN_ETSI 0x2
\r
447 #define EEPROM_CHANNEL_PLAN_SPAIN 0x3
\r
448 #define EEPROM_CHANNEL_PLAN_FRANCE 0x4
\r
449 #define EEPROM_CHANNEL_PLAN_MKK 0x5
\r
450 #define EEPROM_CHANNEL_PLAN_MKK1 0x6
\r
451 #define EEPROM_CHANNEL_PLAN_ISRAEL 0x7
\r
452 #define EEPROM_CHANNEL_PLAN_TELEC 0x8
\r
453 #define EEPROM_CHANNEL_PLAN_GLOBAL_DOMAIN 0x9
\r
454 #define EEPROM_CHANNEL_PLAN_WORLD_WIDE_13 0xA
\r
455 #define EEPROM_CHANNEL_PLAN_NCC_TAIWAN 0xB
\r
456 #define EEPROM_CHANNEL_PLAN_CHIAN 0XC
\r
457 #define EEPROM_CHANNEL_PLAN_SINGAPORE_INDIA_MEXICO 0XD
\r
458 #define EEPROM_CHANNEL_PLAN_KOREA 0xE
\r
459 #define EEPROM_CHANNEL_PLAN_TURKEY 0xF
\r
460 #define EEPROM_CHANNEL_PLAN_JAPAN 0x10
\r
461 #define EEPROM_CHANNEL_PLAN_FCC_NO_DFS 0x11
\r
462 #define EEPROM_CHANNEL_PLAN_JAPAN_NO_DFS 0x12
\r
463 #define EEPROM_CHANNEL_PLAN_WORLD_WIDE_5G 0x13
\r
464 #define EEPROM_CHANNEL_PLAN_TAIWAN_NO_DFS 0x14
\r
466 #define EEPROM_USB_OPTIONAL1 0xE
\r
467 #define EEPROM_CHANNEL_PLAN_BY_HW_MASK 0x80
\r
469 #define RTL_EEPROM_ID 0x8129
\r
470 #define EEPROM_Default_TSSI 0x0
\r
471 #define EEPROM_Default_BoardType 0x02
\r
472 #define EEPROM_Default_ThermalMeter 0x12
\r
473 #define EEPROM_Default_ThermalMeter_92SU 0x7
\r
474 #define EEPROM_Default_ThermalMeter_88E 0x18
\r
475 #define EEPROM_Default_ThermalMeter_8812 0x18
\r
476 #define EEPROM_Default_ThermalMeter_8192E 0x1A
\r
477 #define EEPROM_Default_ThermalMeter_8723B 0x18
\r
480 #define EEPROM_Default_CrystalCap 0x0
\r
481 #define EEPROM_Default_CrystalCap_8723A 0x20
\r
482 #define EEPROM_Default_CrystalCap_88E 0x20
\r
483 #define EEPROM_Default_CrystalCap_8812 0x20
\r
484 #define EEPROM_Default_CrystalCap_8192E 0x20
\r
485 #define EEPROM_Default_CrystalCap_8723B 0x20
\r
486 #define EEPROM_Default_CrystalFreq 0x0
\r
487 #define EEPROM_Default_TxPowerLevel_92C 0x22
\r
488 #define EEPROM_Default_TxPowerLevel_2G 0x2C
\r
489 #define EEPROM_Default_TxPowerLevel_5G 0x22
\r
490 #define EEPROM_Default_TxPowerLevel 0x22
\r
491 #define EEPROM_Default_HT40_2SDiff 0x0
\r
492 #define EEPROM_Default_HT20_Diff 2
\r
493 #define EEPROM_Default_LegacyHTTxPowerDiff 0x3
\r
494 #define EEPROM_Default_LegacyHTTxPowerDiff_92C 0x3
\r
495 #define EEPROM_Default_LegacyHTTxPowerDiff_92D 0x4
\r
496 #define EEPROM_Default_HT40_PwrMaxOffset 0
\r
497 #define EEPROM_Default_HT20_PwrMaxOffset 0
\r
499 #define EEPROM_Default_PID 0x1234
\r
500 #define EEPROM_Default_VID 0x5678
\r
501 #define EEPROM_Default_CustomerID 0xAB
\r
502 #define EEPROM_Default_CustomerID_8188E 0x00
\r
503 #define EEPROM_Default_SubCustomerID 0xCD
\r
504 #define EEPROM_Default_Version 0
\r
506 #define EEPROM_Default_externalPA_C9 0x00
\r
507 #define EEPROM_Default_externalPA_CC 0xFF
\r
508 #define EEPROM_Default_internalPA_SP3T_C9 0xAA
\r
509 #define EEPROM_Default_internalPA_SP3T_CC 0xAF
\r
510 #define EEPROM_Default_internalPA_SPDT_C9 0xAA
\r
511 #ifdef CONFIG_PCI_HCI
\r
512 #define EEPROM_Default_internalPA_SPDT_CC 0xA0
\r
514 #define EEPROM_Default_internalPA_SPDT_CC 0xFA
\r
516 #define EEPROM_Default_PAType 0
\r
517 #define EEPROM_Default_LNAType 0
\r
519 //New EFUSE deafult value
\r
520 #define EEPROM_DEFAULT_24G_INDEX 0x2D
\r
521 #define EEPROM_DEFAULT_24G_HT20_DIFF 0X02
\r
522 #define EEPROM_DEFAULT_24G_OFDM_DIFF 0X04
\r
524 #define EEPROM_DEFAULT_5G_INDEX 0X2A
\r
525 #define EEPROM_DEFAULT_5G_HT20_DIFF 0X00
\r
526 #define EEPROM_DEFAULT_5G_OFDM_DIFF 0X04
\r
528 #define EEPROM_DEFAULT_DIFF 0XFE
\r
529 #define EEPROM_DEFAULT_CHANNEL_PLAN 0x7F
\r
530 #define EEPROM_DEFAULT_BOARD_OPTION 0x00
\r
531 #define EEPROM_DEFAULT_RFE_OPTION 0x04
\r
532 #define EEPROM_DEFAULT_FEATURE_OPTION 0x00
\r
533 #define EEPROM_DEFAULT_BT_OPTION 0x10
\r
536 #define EEPROM_DEFAULT_TX_CALIBRATE_RATE 0x00
\r
539 // For VHT series TX power by rate table.
\r
540 // VHT TX power by rate off setArray =
\r
541 // Band:-2G&5G = 0 / 1
\r
542 // RF: at most 4*4 = ABCD=0/1/2/3
\r
543 // CCK=0 OFDM=1/2 HT-MCS 0-15=3/4/56 VHT=7/8/9/10/11
\r
545 #define TX_PWR_BY_RATE_NUM_BAND 2
\r
546 #define TX_PWR_BY_RATE_NUM_RF 4
\r
547 #define TX_PWR_BY_RATE_NUM_RATE 84
\r
549 #define TXPWR_LMT_MAX_RF 4
\r
551 //----------------------------------------------------------------------------
\r
552 // EEPROM/EFUSE data structure definition.
\r
553 //----------------------------------------------------------------------------
\r
554 #define MAX_RF_PATH_NUM 2
\r
555 #define MAX_CHNL_GROUP 3+9
\r
556 typedef struct _TxPowerInfo{
\r
557 u8 CCKIndex[MAX_RF_PATH_NUM][MAX_CHNL_GROUP];
\r
558 u8 HT40_1SIndex[MAX_RF_PATH_NUM][MAX_CHNL_GROUP];
\r
559 u8 HT40_2SIndexDiff[MAX_RF_PATH_NUM][MAX_CHNL_GROUP];
\r
560 s8 HT20IndexDiff[MAX_RF_PATH_NUM][MAX_CHNL_GROUP];
\r
561 u8 OFDMIndexDiff[MAX_RF_PATH_NUM][MAX_CHNL_GROUP];
\r
562 u8 HT40MaxOffset[MAX_RF_PATH_NUM][MAX_CHNL_GROUP];
\r
563 u8 HT20MaxOffset[MAX_RF_PATH_NUM][MAX_CHNL_GROUP];
\r
566 u8 TSSI_A_5G[3]; //5GL/5GM/5GH
\r
568 }TxPowerInfo, *PTxPowerInfo;
\r
571 //For 88E new structure
\r
601 #define MAX_RF_PATH 4
\r
602 #define RF_PATH_MAX MAX_RF_PATH
\r
603 #define MAX_CHNL_GROUP_24G 6
\r
604 #define MAX_CHNL_GROUP_5G 14
\r
606 //It must always set to 4, otherwise read efuse table secquence will be wrong.
\r
607 #define MAX_TX_COUNT 4
\r
609 typedef struct _TxPowerInfo24G{
\r
610 u8 IndexCCK_Base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
\r
611 u8 IndexBW40_Base[MAX_RF_PATH][MAX_CHNL_GROUP_24G];
\r
612 //If only one tx, only BW20 and OFDM are used.
\r
613 s8 CCK_Diff[MAX_RF_PATH][MAX_TX_COUNT];
\r
614 s8 OFDM_Diff[MAX_RF_PATH][MAX_TX_COUNT];
\r
615 s8 BW20_Diff[MAX_RF_PATH][MAX_TX_COUNT];
\r
616 s8 BW40_Diff[MAX_RF_PATH][MAX_TX_COUNT];
\r
617 }TxPowerInfo24G, *PTxPowerInfo24G;
\r
619 typedef struct _TxPowerInfo5G{
\r
620 u8 IndexBW40_Base[MAX_RF_PATH][MAX_CHNL_GROUP_5G];
\r
621 //If only one tx, only BW20, OFDM, BW80 and BW160 are used.
\r
622 s8 OFDM_Diff[MAX_RF_PATH][MAX_TX_COUNT];
\r
623 s8 BW20_Diff[MAX_RF_PATH][MAX_TX_COUNT];
\r
624 s8 BW40_Diff[MAX_RF_PATH][MAX_TX_COUNT];
\r
625 s8 BW80_Diff[MAX_RF_PATH][MAX_TX_COUNT];
\r
626 s8 BW160_Diff[MAX_RF_PATH][MAX_TX_COUNT];
\r
627 }TxPowerInfo5G, *PTxPowerInfo5G;
\r
630 typedef enum _BT_Ant_NUM{
\r
633 } BT_Ant_NUM, *PBT_Ant_NUM;
\r
635 typedef enum _BT_CoType{
\r
648 } BT_CoType, *PBT_CoType;
\r
650 typedef enum _BT_RadioShared{
\r
651 BT_Radio_Shared = 0,
\r
652 BT_Radio_Individual = 1,
\r
653 } BT_RadioShared, *PBT_RadioShared;
\r
projects / firefly-linux-kernel-4.4.55.git / blob