1 /******************************************************************************
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3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
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5 * This program is free software; you can redistribute it and/or modify it
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6 * under the terms of version 2 of the GNU General Public License as
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7 * published by the Free Software Foundation.
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9 * This program is distributed in the hope that it will be useful, but WITHOUT
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10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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14 * You should have received a copy of the GNU General Public License along with
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15 * this program; if not, write to the Free Software Foundation, Inc.,
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16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
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19 ******************************************************************************/
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20 #ifndef __INC_HAL8812PHYREG_H__
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21 #define __INC_HAL8812PHYREG_H__
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22 /*--------------------------Define Parameters-------------------------------*/
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24 // BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF
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25 // 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
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26 // 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00
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27 // 3. RF register 0x00-2E
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28 // 4. Bit Mask for BB/RF register
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29 // 5. Other defintion for BB/RF R/W
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33 // BB Register Definition
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35 #define rCCAonSec_Jaguar 0x838
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36 #define rPwed_TH_Jaguar 0x830
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38 // BW and sideband setting
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39 #define rBWIndication_Jaguar 0x834
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40 #define rL1PeakTH_Jaguar 0x848
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41 #define rRFMOD_Jaguar 0x8ac //RF mode
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42 #define rADC_Buf_Clk_Jaguar 0x8c4
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43 #define rRFECTRL_Jaguar 0x900
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44 #define bRFMOD_Jaguar 0xc3
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45 #define rCCK_System_Jaguar 0xa00 // for cck sideband
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46 #define bCCK_System_Jaguar 0x10
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48 // Block & Path enable
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49 #define rOFDMCCKEN_Jaguar 0x808 // OFDM/CCK block enable
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50 #define bOFDMEN_Jaguar 0x20000000
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51 #define bCCKEN_Jaguar 0x10000000
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52 #define rRxPath_Jaguar 0x808 // Rx antenna
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53 #define bRxPath_Jaguar 0xff
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54 #define rTxPath_Jaguar 0x80c // Tx antenna
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55 #define bTxPath_Jaguar 0x0fffffff
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56 #define rCCK_RX_Jaguar 0xa04 // for cck rx path selection
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57 #define bCCK_RX_Jaguar 0x0c000000
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58 #define rVhtlen_Use_Lsig_Jaguar 0x8c3 // Use LSIG for VHT length
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60 // RF read/write-related
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61 #define rHSSIRead_Jaguar 0x8b0 // RF read addr
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62 #define bHSSIRead_addr_Jaguar 0xff
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63 #define bHSSIRead_trigger_Jaguar 0x100
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64 #define rA_PIRead_Jaguar 0xd04 // RF readback with PI
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65 #define rB_PIRead_Jaguar 0xd44 // RF readback with PI
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66 #define rA_SIRead_Jaguar 0xd08 // RF readback with SI
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67 #define rB_SIRead_Jaguar 0xd48 // RF readback with SI
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68 #define rRead_data_Jaguar 0xfffff
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69 #define rA_LSSIWrite_Jaguar 0xc90 // RF write addr
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70 #define rB_LSSIWrite_Jaguar 0xe90 // RF write addr
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71 #define bLSSIWrite_data_Jaguar 0x000fffff
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72 #define bLSSIWrite_addr_Jaguar 0x0ff00000
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76 // YN: mask the following register definition temporarily
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77 #define rFPGA0_XA_RFInterfaceOE 0x860 // RF Channel switch
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78 #define rFPGA0_XB_RFInterfaceOE 0x864
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80 #define rFPGA0_XAB_RFInterfaceSW 0x870 // RF Interface Software Control
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81 #define rFPGA0_XCD_RFInterfaceSW 0x874
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83 //#define rFPGA0_XAB_RFParameter 0x878 // RF Parameter
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84 //#define rFPGA0_XCD_RFParameter 0x87c
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86 //#define rFPGA0_AnalogParameter1 0x880 // Crystal cap setting RF-R/W protection for parameter4??
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87 //#define rFPGA0_AnalogParameter2 0x884
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88 //#define rFPGA0_AnalogParameter3 0x888
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89 //#define rFPGA0_AdDaClockEn 0x888 // enable ad/da clock1 for dual-phy
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90 //#define rFPGA0_AnalogParameter4 0x88c
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94 #define rCCK_TxFilter1_Jaguar 0xa20
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95 #define bCCK_TxFilter1_C0_Jaguar 0x00ff0000
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96 #define bCCK_TxFilter1_C1_Jaguar 0xff000000
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97 #define rCCK_TxFilter2_Jaguar 0xa24
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98 #define bCCK_TxFilter2_C2_Jaguar 0x000000ff
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99 #define bCCK_TxFilter2_C3_Jaguar 0x0000ff00
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100 #define bCCK_TxFilter2_C4_Jaguar 0x00ff0000
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101 #define bCCK_TxFilter2_C5_Jaguar 0xff000000
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102 #define rCCK_TxFilter3_Jaguar 0xa28
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103 #define bCCK_TxFilter3_C6_Jaguar 0x000000ff
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104 #define bCCK_TxFilter3_C7_Jaguar 0x0000ff00
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107 // YN: mask the following register definition temporarily
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108 //#define rPdp_AntA 0xb00
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109 //#define rPdp_AntA_4 0xb04
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110 //#define rConfig_Pmpd_AntA 0xb28
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111 //#define rConfig_AntA 0xb68
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112 //#define rConfig_AntB 0xb6c
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113 //#define rPdp_AntB 0xb70
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114 //#define rPdp_AntB_4 0xb74
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115 //#define rConfig_Pmpd_AntB 0xb98
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116 //#define rAPK 0xbd8
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119 #define rA_RxIQC_AB_Jaguar 0xc10 //RxIQ imblance matrix coeff. A & B
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120 #define rA_RxIQC_CD_Jaguar 0xc14 //RxIQ imblance matrix coeff. C & D
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121 #define rA_TxScale_Jaguar 0xc1c // Pah_A TX scaling factor
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122 #define rB_TxScale_Jaguar 0xe1c // Path_B TX scaling factor
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123 #define rB_RxIQC_AB_Jaguar 0xe10 //RxIQ imblance matrix coeff. A & B
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124 #define rB_RxIQC_CD_Jaguar 0xe14 //RxIQ imblance matrix coeff. C & D
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125 #define b_RxIQC_AC_Jaguar 0x02ff // bit mask for IQC matrix element A & C
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126 #define b_RxIQC_BD_Jaguar 0x02ff0000 // bit mask for IQC matrix element A & C
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130 #define rA_IGI_Jaguar 0xc50 // Initial Gain for path-A
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131 #define rB_IGI_Jaguar 0xe50 // Initial Gain for path-B
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132 #define rOFDM_FalseAlarm1_Jaguar 0xf48 // counter for break
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133 #define rOFDM_FalseAlarm2_Jaguar 0xf4c // counter for spoofing
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134 #define rCCK_FalseAlarm_Jaguar 0xa5c // counter for cck false alarm
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135 #define b_FalseAlarm_Jaguar 0xffff
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136 #define rCCK_CCA_Jaguar 0xa08 // cca threshold
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137 #define bCCK_CCA_Jaguar 0x00ff0000
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139 // Tx Power Ttraining-related
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140 #define rA_TxPwrTraing_Jaguar 0xc54
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141 #define rB_TxPwrTraing_Jaguar 0xe54
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144 #define rOFDM_ShortCFOAB_Jaguar 0xf60
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145 #define rOFDM_LongCFOAB_Jaguar 0xf64
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146 #define rOFDM_EndCFOAB_Jaguar 0xf70
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147 #define rOFDM_AGCReport_Jaguar 0xf84
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148 #define rOFDM_RxSNR_Jaguar 0xf88
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149 #define rOFDM_RxEVMCSI_Jaguar 0xf8c
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150 #define rOFDM_SIGReport_Jaguar 0xf90
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153 #define rEDCCA_Jaguar 0x8a4 // EDCCA
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154 #define bEDCCA_Jaguar 0xffff
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155 #define rAGC_table_Jaguar 0x82c // AGC tabel select
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156 #define bAGC_table_Jaguar 0x3
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157 #define b_sel5g_Jaguar 0x1000 // sel5g
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158 #define b_LNA_sw_Jaguar 0x8000 // HW/WS control for LNA
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159 #define rFc_area_Jaguar 0x860 // fc_area
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160 #define bFc_area_Jaguar 0x1ffe000
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161 #define rSingleTone_ContTx_Jaguar 0x914
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164 #define rA_RFE_Pinmux_Jaguar 0xcb0 // Path_A RFE cotrol pinmux
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165 #define rB_RFE_Pinmux_Jaguar 0xeb0 // Path_B RFE control pinmux
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166 #define rA_RFE_Inv_Jaguar 0xcb4 // Path_A RFE cotrol
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167 #define rB_RFE_Inv_Jaguar 0xeb4 // Path_B RFE control
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168 #define rA_RFE_Jaguar 0xcb8 // Path_A RFE cotrol
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169 #define rB_RFE_Jaguar 0xeb8 // Path_B RFE control
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170 #define r_ANTSEL_SW_Jaguar 0x900 // ANTSEL SW Control
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171 #define bMask_RFEInv_Jaguar 0x3ff00000
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172 #define bMask_AntselPathFollow_Jaguar 0x00030000
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175 #define rTxAGC_A_CCK11_CCK1_JAguar 0xc20
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176 #define rTxAGC_A_Ofdm18_Ofdm6_JAguar 0xc24
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177 #define rTxAGC_A_Ofdm54_Ofdm24_JAguar 0xc28
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178 #define rTxAGC_A_MCS3_MCS0_JAguar 0xc2c
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179 #define rTxAGC_A_MCS7_MCS4_JAguar 0xc30
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180 #define rTxAGC_A_MCS11_MCS8_JAguar 0xc34
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181 #define rTxAGC_A_MCS15_MCS12_JAguar 0xc38
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182 #define rTxAGC_A_Nss1Index3_Nss1Index0_JAguar 0xc3c
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183 #define rTxAGC_A_Nss1Index7_Nss1Index4_JAguar 0xc40
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184 #define rTxAGC_A_Nss2Index1_Nss1Index8_JAguar 0xc44
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185 #define rTxAGC_A_Nss2Index5_Nss2Index2_JAguar 0xc48
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186 #define rTxAGC_A_Nss2Index9_Nss2Index6_JAguar 0xc4c
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187 #define rTxAGC_B_CCK11_CCK1_JAguar 0xe20
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188 #define rTxAGC_B_Ofdm18_Ofdm6_JAguar 0xe24
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189 #define rTxAGC_B_Ofdm54_Ofdm24_JAguar 0xe28
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190 #define rTxAGC_B_MCS3_MCS0_JAguar 0xe2c
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191 #define rTxAGC_B_MCS7_MCS4_JAguar 0xe30
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192 #define rTxAGC_B_MCS11_MCS8_JAguar 0xe34
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193 #define rTxAGC_B_MCS15_MCS12_JAguar 0xe38
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194 #define rTxAGC_B_Nss1Index3_Nss1Index0_JAguar 0xe3c
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195 #define rTxAGC_B_Nss1Index7_Nss1Index4_JAguar 0xe40
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196 #define rTxAGC_B_Nss2Index1_Nss1Index8_JAguar 0xe44
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197 #define rTxAGC_B_Nss2Index5_Nss2Index2_JAguar 0xe48
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198 #define rTxAGC_B_Nss2Index9_Nss2Index6_JAguar 0xe4c
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199 #define bTxAGC_byte0_Jaguar 0xff
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200 #define bTxAGC_byte1_Jaguar 0xff00
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201 #define bTxAGC_byte2_Jaguar 0xff0000
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202 #define bTxAGC_byte3_Jaguar 0xff000000
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204 // IQK YN: temporaily mask this part
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205 //#define rFPGA0_IQK 0xe28
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206 //#define rTx_IQK_Tone_A 0xe30
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207 //#define rRx_IQK_Tone_A 0xe34
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208 //#define rTx_IQK_PI_A 0xe38
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209 //#define rRx_IQK_PI_A 0xe3c
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211 //#define rTx_IQK 0xe40
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212 //#define rRx_IQK 0xe44
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213 //#define rIQK_AGC_Pts 0xe48
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214 //#define rIQK_AGC_Rsp 0xe4c
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215 //#define rTx_IQK_Tone_B 0xe50
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216 //#define rRx_IQK_Tone_B 0xe54
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217 //#define rTx_IQK_PI_B 0xe58
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218 //#define rRx_IQK_PI_B 0xe5c
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219 //#define rIQK_AGC_Cont 0xe60
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223 #define rA_AFEPwr1_Jaguar 0xc60 // dynamic AFE power control
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224 #define rA_AFEPwr2_Jaguar 0xc64 // dynamic AFE power control
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225 #define rA_Rx_WaitCCA_Tx_CCKRFON_Jaguar 0xc68
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226 #define rA_Tx_CCKBBON_OFDMRFON_Jaguar 0xc6c
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227 #define rA_Tx_OFDMBBON_Tx2Rx_Jaguar 0xc70
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228 #define rA_Tx2Tx_RXCCK_Jaguar 0xc74
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229 #define rA_Rx_OFDM_WaitRIFS_Jaguar 0xc78
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230 #define rA_Rx2Rx_BT_Jaguar 0xc7c
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231 #define rA_sleep_nav_Jaguar 0xc80
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232 #define rA_pmpd_Jaguar 0xc84
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233 #define rB_AFEPwr1_Jaguar 0xe60 // dynamic AFE power control
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234 #define rB_AFEPwr2_Jaguar 0xe64 // dynamic AFE power control
\r
235 #define rB_Rx_WaitCCA_Tx_CCKRFON_Jaguar 0xe68
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236 #define rB_Tx_CCKBBON_OFDMRFON_Jaguar 0xe6c
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237 #define rB_Tx_OFDMBBON_Tx2Rx_Jaguar 0xe70
\r
238 #define rB_Tx2Tx_RXCCK_Jaguar 0xe74
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239 #define rB_Rx_OFDM_WaitRIFS_Jaguar 0xe78
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240 #define rB_Rx2Rx_BT_Jaguar 0xe7c
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241 #define rB_sleep_nav_Jaguar 0xe80
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242 #define rB_pmpd_Jaguar 0xe84
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245 // YN: mask these registers temporaily
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246 //#define rTx_Power_Before_IQK_A 0xe94
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247 //#define rTx_Power_After_IQK_A 0xe9c
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249 //#define rRx_Power_Before_IQK_A 0xea0
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250 //#define rRx_Power_Before_IQK_A_2 0xea4
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251 //#define rRx_Power_After_IQK_A 0xea8
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252 //#define rRx_Power_After_IQK_A_2 0xeac
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254 //#define rTx_Power_Before_IQK_B 0xeb4
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255 //#define rTx_Power_After_IQK_B 0xebc
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257 //#define rRx_Power_Before_IQK_B 0xec0
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258 //#define rRx_Power_Before_IQK_B_2 0xec4
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259 //#define rRx_Power_After_IQK_B 0xec8
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260 //#define rRx_Power_After_IQK_B_2 0xecc
\r
264 #define rA_RSSIDump_Jaguar 0xBF0
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265 #define rB_RSSIDump_Jaguar 0xBF1
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266 #define rS1_RXevmDump_Jaguar 0xBF4
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267 #define rS2_RXevmDump_Jaguar 0xBF5
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268 #define rA_RXsnrDump_Jaguar 0xBF6
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269 #define rB_RXsnrDump_Jaguar 0xBF7
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270 #define rA_CfoShortDump_Jaguar 0xBF8
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271 #define rB_CfoShortDump_Jaguar 0xBFA
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272 #define rA_CfoLongDump_Jaguar 0xBEC
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273 #define rB_CfoLongDump_Jaguar 0xBEE
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278 #define RF_AC_Jaguar 0x00 //
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279 #define RF_RF_Top_Jaguar 0x07 //
\r
280 #define RF_TXLOK_Jaguar 0x08 //
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281 #define RF_TXAPK_Jaguar 0x0B
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282 #define RF_CHNLBW_Jaguar 0x18 // RF channel and BW switch
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283 #define RF_RCK1_Jaguar 0x1c //
\r
284 #define RF_RCK2_Jaguar 0x1d
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285 #define RF_RCK3_Jaguar 0x1e
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286 #define RF_ModeTableAddr 0x30
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287 #define RF_ModeTableData0 0x31
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288 #define RF_ModeTableData1 0x32
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289 #define RF_TxLCTank_Jaguar 0x54
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290 #define RF_APK_Jaguar 0x63
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291 #define RF_LCK 0xB4
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292 #define RF_WeLut_Jaguar 0xEF
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294 #define bRF_CHNLBW_MOD_AG_Jaguar 0x70300
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295 #define bRF_CHNLBW_BW 0xc00
\r
299 // RL6052 Register definition
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301 #define RF_AC 0x00 //
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302 #define RF_IPA_A 0x0C //
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303 #define RF_TXBIAS_A 0x0D
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304 #define RF_BS_PA_APSET_G9_G11 0x0E
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305 #define RF_MODE1 0x10 //
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306 #define RF_MODE2 0x11 //
\r
307 #define RF_CHNLBW 0x18 // RF channel and BW switch
\r
308 #define RF_RCK_OS 0x30 // RF TX PA control
\r
309 #define RF_TXPA_G1 0x31 // RF TX PA control
\r
310 #define RF_TXPA_G2 0x32 // RF TX PA control
\r
311 #define RF_TXPA_G3 0x33 // RF TX PA control
\r
312 #define RF_0x52 0x52
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313 #define RF_WE_LUT 0xEF
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319 #define bBBResetB 0x100 // Useless now?
\r
320 #define bGlobalResetB 0x200
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321 #define bOFDMTxStart 0x4
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322 #define bCCKTxStart 0x8
\r
323 #define bCRC32Debug 0x100
\r
324 #define bPMACLoopback 0x10
\r
325 #define bTxLSIG 0xffffff
\r
326 #define bOFDMTxRate 0xf
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327 #define bOFDMTxReserved 0x10
\r
328 #define bOFDMTxLength 0x1ffe0
\r
329 #define bOFDMTxParity 0x20000
\r
330 #define bTxHTSIG1 0xffffff
\r
331 #define bTxHTMCSRate 0x7f
\r
332 #define bTxHTBW 0x80
\r
333 #define bTxHTLength 0xffff00
\r
334 #define bTxHTSIG2 0xffffff
\r
335 #define bTxHTSmoothing 0x1
\r
336 #define bTxHTSounding 0x2
\r
337 #define bTxHTReserved 0x4
\r
338 #define bTxHTAggreation 0x8
\r
339 #define bTxHTSTBC 0x30
\r
340 #define bTxHTAdvanceCoding 0x40
\r
341 #define bTxHTShortGI 0x80
\r
342 #define bTxHTNumberHT_LTF 0x300
\r
343 #define bTxHTCRC8 0x3fc00
\r
344 #define bCounterReset 0x10000
\r
345 #define bNumOfOFDMTx 0xffff
\r
346 #define bNumOfCCKTx 0xffff0000
\r
347 #define bTxIdleInterval 0xffff
\r
348 #define bOFDMService 0xffff0000
\r
349 #define bTxMACHeader 0xffffffff
\r
350 #define bTxDataInit 0xff
\r
351 #define bTxHTMode 0x100
\r
352 #define bTxDataType 0x30000
\r
353 #define bTxRandomSeed 0xffffffff
\r
354 #define bCCKTxPreamble 0x1
\r
355 #define bCCKTxSFD 0xffff0000
\r
356 #define bCCKTxSIG 0xff
\r
357 #define bCCKTxService 0xff00
\r
358 #define bCCKLengthExt 0x8000
\r
359 #define bCCKTxLength 0xffff0000
\r
360 #define bCCKTxCRC16 0xffff
\r
361 #define bCCKTxStatus 0x1
\r
362 #define bOFDMTxStatus 0x2
\r
366 // 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
\r
369 #define rPMAC_Reset 0x100
\r
370 #define rPMAC_TxStart 0x104
\r
371 #define rPMAC_TxLegacySIG 0x108
\r
372 #define rPMAC_TxHTSIG1 0x10c
\r
373 #define rPMAC_TxHTSIG2 0x110
\r
374 #define rPMAC_PHYDebug 0x114
\r
375 #define rPMAC_TxPacketNum 0x118
\r
376 #define rPMAC_TxIdle 0x11c
\r
377 #define rPMAC_TxMACHeader0 0x120
\r
378 #define rPMAC_TxMACHeader1 0x124
\r
379 #define rPMAC_TxMACHeader2 0x128
\r
380 #define rPMAC_TxMACHeader3 0x12c
\r
381 #define rPMAC_TxMACHeader4 0x130
\r
382 #define rPMAC_TxMACHeader5 0x134
\r
383 #define rPMAC_TxDataType 0x138
\r
384 #define rPMAC_TxRandomSeed 0x13c
\r
385 #define rPMAC_CCKPLCPPreamble 0x140
\r
386 #define rPMAC_CCKPLCPHeader 0x144
\r
387 #define rPMAC_CCKCRC16 0x148
\r
388 #define rPMAC_OFDMRxCRC32OK 0x170
\r
389 #define rPMAC_OFDMRxCRC32Er 0x174
\r
390 #define rPMAC_OFDMRxParityEr 0x178
\r
391 #define rPMAC_OFDMRxCRC8Er 0x17c
\r
392 #define rPMAC_CCKCRxRC16Er 0x180
\r
393 #define rPMAC_CCKCRxRC32Er 0x184
\r
394 #define rPMAC_CCKCRxRC32OK 0x188
\r
395 #define rPMAC_TxStatus 0x18c
\r
400 #define rFPGA0_RFMOD 0x800 //RF mode & CCK TxSC // RF BW Setting??
\r
402 #define rFPGA0_TxInfo 0x804 // Status report??
\r
403 #define rFPGA0_PSDFunction 0x808
\r
404 #define rFPGA0_TxGainStage 0x80c // Set TX PWR init gain?
\r
406 #define rFPGA0_XA_HSSIParameter1 0x820 // RF 3 wire register
\r
407 #define rFPGA0_XA_HSSIParameter2 0x824
\r
408 #define rFPGA0_XB_HSSIParameter1 0x828
\r
409 #define rFPGA0_XB_HSSIParameter2 0x82c
\r
411 #define rFPGA0_XAB_SwitchControl 0x858 // RF Channel switch
\r
412 #define rFPGA0_XCD_SwitchControl 0x85c
\r
414 #define rFPGA0_XAB_RFParameter 0x878 // RF Parameter
\r
415 #define rFPGA0_XCD_RFParameter 0x87c
\r
417 #define rFPGA0_AnalogParameter1 0x880 // Crystal cap setting RF-R/W protection for parameter4??
\r
418 #define rFPGA0_AnalogParameter2 0x884
\r
419 #define rFPGA0_AnalogParameter3 0x888
\r
420 #define rFPGA0_AdDaClockEn 0x888 // enable ad/da clock1 for dual-phy
\r
421 #define rFPGA0_AnalogParameter4 0x88c
\r
422 #define rFPGA0_XB_LSSIReadBack 0x8a4
\r
426 #define rFPGA1_RFMOD 0x900 //RF mode & OFDM TxSC // RF BW Setting??
\r
428 #define rFPGA1_TxBlock 0x904 // Useless now
\r
429 #define rFPGA1_DebugSelect 0x908 // Useless now
\r
430 #define rFPGA1_TxInfo 0x90c // Useless now // Status report??
\r
435 #define rCCK0_System 0xa00
\r
436 #define rCCK0_AFESetting 0xa04 // Disable init gain now // Select RX path by RSSI
\r
437 #define rCCK0_TxFilter1 0xa20
\r
438 #define rCCK0_TxFilter2 0xa24
\r
439 #define rCCK0_DebugPort 0xa28 //debug port and Tx filter3
\r
444 #define rPdp_AntA 0xb00
\r
445 #define rPdp_AntA_4 0xb04
\r
446 #define rConfig_Pmpd_AntA 0xb28
\r
447 #define rConfig_AntA 0xb68
\r
448 #define rConfig_AntB 0xb6c
\r
449 #define rPdp_AntB 0xb70
\r
450 #define rPdp_AntB_4 0xb74
\r
451 #define rConfig_Pmpd_AntB 0xb98
\r
457 #define rOFDM0_LSTF 0xc00
\r
459 #define rOFDM0_TRxPathEnable 0xc04
\r
460 #define rOFDM0_TRMuxPar 0xc08
\r
461 #define rOFDM0_TRSWIsolation 0xc0c
\r
463 #define rOFDM0_XARxAFE 0xc10 //RxIQ DC offset, Rx digital filter, DC notch filter
\r
464 #define rOFDM0_XARxIQImbalance 0xc14 //RxIQ imblance matrix
\r
465 #define rOFDM0_XBRxAFE 0xc18
\r
466 #define rOFDM0_XBRxIQImbalance 0xc1c
\r
467 #define rOFDM0_XCRxAFE 0xc20
\r
468 #define rOFDM0_XCRxIQImbalance 0xc24
\r
469 #define rOFDM0_XDRxAFE 0xc28
\r
470 #define rOFDM0_XDRxIQImbalance 0xc2c
\r
472 #define rOFDM0_RxDetector1 0xc30 //PD,BW & SBD // DM tune init gain
\r
473 #define rOFDM0_RxDetector2 0xc34 //SBD & Fame Sync.
\r
474 #define rOFDM0_RxDetector3 0xc38 //Frame Sync.
\r
475 #define rOFDM0_RxDetector4 0xc3c //PD, SBD, Frame Sync & Short-GI
\r
477 #define rOFDM0_RxDSP 0xc40 //Rx Sync Path
\r
478 #define rOFDM0_CFOandDAGC 0xc44 //CFO & DAGC
\r
479 #define rOFDM0_CCADropThreshold 0xc48 //CCA Drop threshold
\r
480 #define rOFDM0_ECCAThreshold 0xc4c // energy CCA
\r
482 #define rOFDM0_XAAGCCore1 0xc50 // DIG
\r
483 #define rOFDM0_XAAGCCore2 0xc54
\r
484 #define rOFDM0_XBAGCCore1 0xc58
\r
485 #define rOFDM0_XBAGCCore2 0xc5c
\r
486 #define rOFDM0_XCAGCCore1 0xc60
\r
487 #define rOFDM0_XCAGCCore2 0xc64
\r
488 #define rOFDM0_XDAGCCore1 0xc68
\r
489 #define rOFDM0_XDAGCCore2 0xc6c
\r
491 #define rOFDM0_AGCParameter1 0xc70
\r
492 #define rOFDM0_AGCParameter2 0xc74
\r
493 #define rOFDM0_AGCRSSITable 0xc78
\r
494 #define rOFDM0_HTSTFAGC 0xc7c
\r
496 #define rOFDM0_XATxIQImbalance 0xc80 // TX PWR TRACK and DIG
\r
497 #define rOFDM0_XATxAFE 0xc84
\r
498 #define rOFDM0_XBTxIQImbalance 0xc88
\r
499 #define rOFDM0_XBTxAFE 0xc8c
\r
500 #define rOFDM0_XCTxIQImbalance 0xc90
\r
501 #define rOFDM0_XCTxAFE 0xc94
\r
502 #define rOFDM0_XDTxIQImbalance 0xc98
\r
503 #define rOFDM0_XDTxAFE 0xc9c
\r
505 #define rOFDM0_RxIQExtAnta 0xca0
\r
506 #define rOFDM0_TxCoeff1 0xca4
\r
507 #define rOFDM0_TxCoeff2 0xca8
\r
508 #define rOFDM0_TxCoeff3 0xcac
\r
509 #define rOFDM0_TxCoeff4 0xcb0
\r
510 #define rOFDM0_TxCoeff5 0xcb4
\r
511 #define rOFDM0_TxCoeff6 0xcb8
\r
512 #define rOFDM0_RxHPParameter 0xce0
\r
513 #define rOFDM0_TxPseudoNoiseWgt 0xce4
\r
514 #define rOFDM0_FrameSync 0xcf0
\r
515 #define rOFDM0_DFSReport 0xcf4
\r
520 #define rOFDM1_LSTF 0xd00
\r
521 #define rOFDM1_TRxPathEnable 0xd04
\r
526 #define rTxAGC_A_Rate18_06 0xe00
\r
527 #define rTxAGC_A_Rate54_24 0xe04
\r
528 #define rTxAGC_A_CCK1_Mcs32 0xe08
\r
529 #define rTxAGC_A_Mcs03_Mcs00 0xe10
\r
530 #define rTxAGC_A_Mcs07_Mcs04 0xe14
\r
531 #define rTxAGC_A_Mcs11_Mcs08 0xe18
\r
532 #define rTxAGC_A_Mcs15_Mcs12 0xe1c
\r
534 #define rTxAGC_B_Rate18_06 0x830
\r
535 #define rTxAGC_B_Rate54_24 0x834
\r
536 #define rTxAGC_B_CCK1_55_Mcs32 0x838
\r
537 #define rTxAGC_B_Mcs03_Mcs00 0x83c
\r
538 #define rTxAGC_B_Mcs07_Mcs04 0x848
\r
539 #define rTxAGC_B_Mcs11_Mcs08 0x84c
\r
540 #define rTxAGC_B_Mcs15_Mcs12 0x868
\r
541 #define rTxAGC_B_CCK11_A_CCK2_11 0x86c
\r
543 #define rFPGA0_IQK 0xe28
\r
544 #define rTx_IQK_Tone_A 0xe30
\r
545 #define rRx_IQK_Tone_A 0xe34
\r
546 #define rTx_IQK_PI_A 0xe38
\r
547 #define rRx_IQK_PI_A 0xe3c
\r
549 #define rTx_IQK 0xe40
\r
550 #define rRx_IQK 0xe44
\r
551 #define rIQK_AGC_Pts 0xe48
\r
552 #define rIQK_AGC_Rsp 0xe4c
\r
553 #define rTx_IQK_Tone_B 0xe50
\r
554 #define rRx_IQK_Tone_B 0xe54
\r
555 #define rTx_IQK_PI_B 0xe58
\r
556 #define rRx_IQK_PI_B 0xe5c
\r
557 #define rIQK_AGC_Cont 0xe60
\r
559 #define rBlue_Tooth 0xe6c
\r
560 #define rRx_Wait_CCA 0xe70
\r
561 #define rTx_CCK_RFON 0xe74
\r
562 #define rTx_CCK_BBON 0xe78
\r
563 #define rTx_OFDM_RFON 0xe7c
\r
564 #define rTx_OFDM_BBON 0xe80
\r
565 #define rTx_To_Rx 0xe84
\r
566 #define rTx_To_Tx 0xe88
\r
567 #define rRx_CCK 0xe8c
\r
569 #define rTx_Power_Before_IQK_A 0xe94
\r
570 #define rTx_Power_After_IQK_A 0xe9c
\r
572 #define rRx_Power_Before_IQK_A 0xea0
\r
573 #define rRx_Power_Before_IQK_A_2 0xea4
\r
574 #define rRx_Power_After_IQK_A 0xea8
\r
575 #define rRx_Power_After_IQK_A_2 0xeac
\r
577 #define rTx_Power_Before_IQK_B 0xeb4
\r
578 #define rTx_Power_After_IQK_B 0xebc
\r
580 #define rRx_Power_Before_IQK_B 0xec0
\r
581 #define rRx_Power_Before_IQK_B_2 0xec4
\r
582 #define rRx_Power_After_IQK_B 0xec8
\r
583 #define rRx_Power_After_IQK_B_2 0xecc
\r
585 #define rRx_OFDM 0xed0
\r
586 #define rRx_Wait_RIFS 0xed4
\r
587 #define rRx_TO_Rx 0xed8
\r
588 #define rStandby 0xedc
\r
589 #define rSleep 0xee0
\r
590 #define rPMPD_ANAEN 0xeec
\r
594 #define bRFMOD 0x1 // Reg 0x800 rFPGA0_RFMOD
\r
595 #define bJapanMode 0x2
\r
596 #define bCCKTxSC 0x30
\r
597 #define bCCKEn 0x1000000
\r
598 #define bOFDMEn 0x2000000
\r
599 #define bXBTxAGC 0xf00 // Reg 80c rFPGA0_TxGainStage
\r
600 #define bXCTxAGC 0xf000
\r
601 #define bXDTxAGC 0xf0000
\r
604 #define bCCKBBMode 0x3 // Useless
\r
605 #define bCCKTxPowerSaving 0x80
\r
606 #define bCCKRxPowerSaving 0x40
\r
608 #define bCCKSideBand 0x10 // Reg 0xa00 rCCK0_System 20/40 switch
\r
610 #define bCCKScramble 0x8 // Useless
\r
611 #define bCCKAntDiversity 0x8000
\r
612 #define bCCKCarrierRecovery 0x4000
\r
613 #define bCCKTxRate 0x3000
\r
614 #define bCCKDCCancel 0x0800
\r
615 #define bCCKISICancel 0x0400
\r
616 #define bCCKMatchFilter 0x0200
\r
617 #define bCCKEqualizer 0x0100
\r
618 #define bCCKPreambleDetect 0x800000
\r
619 #define bCCKFastFalseCCA 0x400000
\r
620 #define bCCKChEstStart 0x300000
\r
621 #define bCCKCCACount 0x080000
\r
622 #define bCCKcs_lim 0x070000
\r
623 #define bCCKBistMode 0x80000000
\r
624 #define bCCKCCAMask 0x40000000
\r
625 #define bCCKTxDACPhase 0x4
\r
626 #define bCCKRxADCPhase 0x20000000 //r_rx_clk
\r
627 #define bCCKr_cp_mode0 0x0100
\r
628 #define bCCKTxDCOffset 0xf0
\r
629 #define bCCKRxDCOffset 0xf
\r
630 #define bCCKCCAMode 0xc000
\r
631 #define bCCKFalseCS_lim 0x3f00
\r
632 #define bCCKCS_ratio 0xc00000
\r
633 #define bCCKCorgBit_sel 0x300000
\r
634 #define bCCKPD_lim 0x0f0000
\r
635 #define bCCKNewCCA 0x80000000
\r
636 #define bCCKRxHPofIG 0x8000
\r
637 #define bCCKRxIG 0x7f00
\r
638 #define bCCKLNAPolarity 0x800000
\r
639 #define bCCKRx1stGain 0x7f0000
\r
640 #define bCCKRFExtend 0x20000000 //CCK Rx Iinital gain polarity
\r
641 #define bCCKRxAGCSatLevel 0x1f000000
\r
642 #define bCCKRxAGCSatCount 0xe0
\r
643 #define bCCKRxRFSettle 0x1f //AGCsamp_dly
\r
644 #define bCCKFixedRxAGC 0x8000
\r
645 //#define bCCKRxAGCFormat 0x4000 //remove to HSSI register 0x824
\r
646 #define bCCKAntennaPolarity 0x2000
\r
647 #define bCCKTxFilterType 0x0c00
\r
648 #define bCCKRxAGCReportType 0x0300
\r
649 #define bCCKRxDAGCEn 0x80000000
\r
650 #define bCCKRxDAGCPeriod 0x20000000
\r
651 #define bCCKRxDAGCSatLevel 0x1f000000
\r
652 #define bCCKTimingRecovery 0x800000
\r
653 #define bCCKTxC0 0x3f0000
\r
654 #define bCCKTxC1 0x3f000000
\r
655 #define bCCKTxC2 0x3f
\r
656 #define bCCKTxC3 0x3f00
\r
657 #define bCCKTxC4 0x3f0000
\r
658 #define bCCKTxC5 0x3f000000
\r
659 #define bCCKTxC6 0x3f
\r
660 #define bCCKTxC7 0x3f00
\r
661 #define bCCKDebugPort 0xff0000
\r
662 #define bCCKDACDebug 0x0f000000
\r
663 #define bCCKFalseAlarmEnable 0x8000
\r
664 #define bCCKFalseAlarmRead 0x4000
\r
665 #define bCCKTRSSI 0x7f
\r
666 #define bCCKRxAGCReport 0xfe
\r
667 #define bCCKRxReport_AntSel 0x80000000
\r
668 #define bCCKRxReport_MFOff 0x40000000
\r
669 #define bCCKRxRxReport_SQLoss 0x20000000
\r
670 #define bCCKRxReport_Pktloss 0x10000000
\r
671 #define bCCKRxReport_Lockedbit 0x08000000
\r
672 #define bCCKRxReport_RateError 0x04000000
\r
673 #define bCCKRxReport_RxRate 0x03000000
\r
674 #define bCCKRxFACounterLower 0xff
\r
675 #define bCCKRxFACounterUpper 0xff000000
\r
676 #define bCCKRxHPAGCStart 0xe000
\r
677 #define bCCKRxHPAGCFinal 0x1c00
\r
678 #define bCCKRxFalseAlarmEnable 0x8000
\r
679 #define bCCKFACounterFreeze 0x4000
\r
680 #define bCCKTxPathSel 0x10000000
\r
681 #define bCCKDefaultRxPath 0xc000000
\r
682 #define bCCKOptionRxPath 0x3000000
\r
685 #define bSTBCEn 0x4 // Useless
\r
686 #define bAntennaMapping 0x10
\r
688 #define bCFOAntSumD 0x200
\r
689 #define bPHYCounterReset 0x8000000
\r
690 #define bCFOReportGet 0x4000000
\r
691 #define bOFDMContinueTx 0x10000000
\r
692 #define bOFDMSingleCarrier 0x20000000
\r
693 #define bOFDMSingleTone 0x40000000
\r
697 // Other Definition
\r
700 #define bEnable 0x1 // Useless
\r
701 #define bDisable 0x0
\r
703 //byte endable for srwrite
\r
704 #define bByte0 0x1 // Useless
\r
712 //for PutRegsetting & GetRegSetting BitMask
\r
713 #define bMaskByte0 0xff // Reg 0xc50 rOFDM0_XAAGCCore~0xC6f
\r
714 #define bMaskByte1 0xff00
\r
715 #define bMaskByte2 0xff0000
\r
716 #define bMaskByte3 0xff000000
\r
717 #define bMaskHWord 0xffff0000
\r
718 #define bMaskLWord 0x0000ffff
\r
719 #define bMaskDWord 0xffffffff
\r
720 #define bMask12Bits 0xfff
\r
721 #define bMaskH4Bits 0xf0000000
\r
722 #define bMaskOFDM_D 0xffc00000
\r
723 #define bMaskCCK 0x3f3f3f3f
\r
726 /*--------------------------Define Parameters-------------------------------*/
\r
projects / firefly-linux-kernel-4.4.55.git / blob