drivers/net/wireless/rtl8188eu/hal/OUTSRC/rtl8188e/HalPhyRf_8188e.c

   1 /******************************************************************************\r
   2  *\r
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.\r
   4  *\r
   5  * This program is free software; you can redistribute it and/or modify it\r
   6  * under the terms of version 2 of the GNU General Public License as\r
   7  * published by the Free Software Foundation.\r
   8  *\r
   9  * This program is distributed in the hope that it will be useful, but WITHOUT\r
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or\r
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for\r
  12  * more details.\r
  13  *\r
  14  * You should have received a copy of the GNU General Public License along with\r
  15  * this program; if not, write to the Free Software Foundation, Inc.,\r
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA\r
  17  *\r
  18  *\r
  19  ******************************************************************************/\r
  20 \r
  21 \r
  22 #include "../odm_precomp.h"\r
  23 \r
  24 \r
  25 \r
  26 /*---------------------------Define Local Constant---------------------------*/\r
  27 // 2010/04/25 MH Define the max tx power tracking tx agc power.\r
  28 #define         ODM_TXPWRTRACK_MAX_IDX_88E              6\r
  29 \r
  30 /*---------------------------Define Local Constant---------------------------*/\r
  31 \r
  32 \r
  33 //3============================================================\r
  34 //3 Tx Power Tracking\r
  35 //3============================================================\r
  36 \r
  37 \r
  38 void setIqkMatrix_8188E(\r
  39         PDM_ODM_T       pDM_Odm,\r
  40         u1Byte          OFDM_index,\r
  41         u1Byte          RFPath,\r
  42         s4Byte          IqkResult_X,\r
  43         s4Byte          IqkResult_Y\r
  44         )\r
  45 {\r
  46         s4Byte                  ele_A=0, ele_D, ele_C=0, value32;\r
  47 \r
  48         ele_D = (OFDMSwingTable_New[OFDM_index] & 0xFFC00000)>>22;              \r
  49         \r
  50     //new element A = element D x X\r
  51         if((IqkResult_X != 0) && (*(pDM_Odm->pBandType) == ODM_BAND_2_4G))\r
  52         {\r
  53                 if ((IqkResult_X & 0x00000200) != 0)    //consider minus\r
  54                         IqkResult_X = IqkResult_X | 0xFFFFFC00;\r
  55                 ele_A = ((IqkResult_X * ele_D)>>8)&0x000003FF;\r
  56                         \r
  57                 //new element C = element D x Y\r
  58                 if ((IqkResult_Y & 0x00000200) != 0)\r
  59                         IqkResult_Y = IqkResult_Y | 0xFFFFFC00;\r
  60                 ele_C = ((IqkResult_Y * ele_D)>>8)&0x000003FF;\r
  61 \r
  62                 //if (RFPath == ODM_RF_PATH_A)\r
  63                 switch (RFPath)\r
  64                 {\r
  65                 case ODM_RF_PATH_A:\r
  66                         //wirte new elements A, C, D to regC80 and regC94, element B is always 0\r
  67                         value32 = (ele_D<<22)|((ele_C&0x3F)<<16)|ele_A;\r
  68                         ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord, value32);\r
  69 \r
  70                         value32 = (ele_C&0x000003C0)>>6;\r
  71                         ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskH4Bits, value32);\r
  72 \r
  73                         value32 = ((IqkResult_X * ele_D)>>7)&0x01;\r
  74                         ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT24, value32);                    \r
  75                         break;\r
  76                 case ODM_RF_PATH_B:\r
  77                         //wirte new elements A, C, D to regC88 and regC9C, element B is always 0\r
  78                         value32=(ele_D<<22)|((ele_C&0x3F)<<16) |ele_A;\r
  79                         ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord, value32);\r
  80 \r
  81                         value32 = (ele_C&0x000003C0)>>6;\r
  82                         ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, bMaskH4Bits, value32);    \r
  83                         \r
  84                         value32 = ((IqkResult_X * ele_D)>>7)&0x01;\r
  85                         ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT28, value32);\r
  86                         \r
  87                         break;                  \r
  88                 default:\r
  89                         break;\r
  90                 }       \r
  91         }\r
  92         else\r
  93         {\r
  94                 switch (RFPath)\r
  95                 {\r
  96                 case ODM_RF_PATH_A:\r
  97                         ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord, OFDMSwingTable_New[OFDM_index]);                              \r
  98                         ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, bMaskH4Bits, 0x00);\r
  99                         ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT24, 0x00);                       \r
 100                         break;\r
 101 \r
 102                 case ODM_RF_PATH_B:\r
 103                         ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord, OFDMSwingTable_New[OFDM_index]);                                                                              \r
 104                         ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, bMaskH4Bits, 0x00);       \r
 105                         ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT28, 0x00);                               \r
 106                         break;                  \r
 107 \r
 108                 default:\r
 109                         break;\r
 110                 }               \r
 111         }\r
 112 \r
 113     ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("TxPwrTracking path B: X = 0x%x, Y = 0x%x ele_A = 0x%x ele_C = 0x%x ele_D = 0x%x 0xeb4 = 0x%x 0xebc = 0x%x\n", \r
 114     (u4Byte)IqkResult_X, (u4Byte)IqkResult_Y, (u4Byte)ele_A, (u4Byte)ele_C, (u4Byte)ele_D, (u4Byte)IqkResult_X, (u4Byte)IqkResult_Y));                          \r
 115 }\r
 116 \r
 117 void DoIQK_8188E(\r
 118         PDM_ODM_T       pDM_Odm,\r
 119         u1Byte          DeltaThermalIndex,\r
 120         u1Byte          ThermalValue,   \r
 121         u1Byte          Threshold\r
 122         )\r
 123 {\r
 124 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
 125         PADAPTER                Adapter = pDM_Odm->Adapter;\r
 126         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(Adapter);\r
 127 #endif\r
 128 \r
 129         ODM_ResetIQKResult(pDM_Odm);            \r
 130 \r
 131 #if(DM_ODM_SUPPORT_TYPE  & ODM_WIN)\r
 132 #if (DEV_BUS_TYPE == RT_PCI_INTERFACE)  \r
 133 #if USE_WORKITEM\r
 134         PlatformAcquireMutex(&pHalData->mxChnlBwControl);\r
 135 #else\r
 136         PlatformAcquireSpinLock(Adapter, RT_CHANNEL_AND_BANDWIDTH_SPINLOCK);\r
 137 #endif\r
 138 #elif((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE))\r
 139         PlatformAcquireMutex(&pHalData->mxChnlBwControl);\r
 140 #endif\r
 141 #endif                  \r
 142 \r
 143 \r
 144         pDM_Odm->RFCalibrateInfo.ThermalValue_IQK= ThermalValue;\r
 145 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)\r
 146         PHY_IQCalibrate_8188E(pDM_Odm, FALSE);\r
 147 #else\r
 148         PHY_IQCalibrate_8188E(Adapter, FALSE);\r
 149 #endif\r
 150     \r
 151 #if(DM_ODM_SUPPORT_TYPE  & ODM_WIN)\r
 152 #if (DEV_BUS_TYPE == RT_PCI_INTERFACE)  \r
 153 #if USE_WORKITEM\r
 154         PlatformReleaseMutex(&pHalData->mxChnlBwControl);\r
 155 #else\r
 156         PlatformReleaseSpinLock(Adapter, RT_CHANNEL_AND_BANDWIDTH_SPINLOCK);\r
 157 #endif\r
 158 #elif((DEV_BUS_TYPE == RT_USB_INTERFACE) || (DEV_BUS_TYPE == RT_SDIO_INTERFACE))\r
 159         PlatformReleaseMutex(&pHalData->mxChnlBwControl);\r
 160 #endif\r
 161 #endif\r
 162 }\r
 163 \r
 164 /*-----------------------------------------------------------------------------\r
 165  * Function:    odm_TxPwrTrackSetPwr88E()\r
 166  *\r
 167  * Overview:    88E change all channel tx power accordign to flag.\r
 168  *                              OFDM & CCK are all different.\r
 169  *\r
 170  * Input:               NONE\r
 171  *\r
 172  * Output:              NONE\r
 173  *\r
 174  * Return:              NONE\r
 175  *\r
 176  * Revised History:\r
 177  *      When            Who             Remark\r
 178  *      04/23/2012      MHC             Create Version 0.  \r
 179  *\r
 180  *---------------------------------------------------------------------------*/\r
 181 VOID\r
 182 ODM_TxPwrTrackSetPwr88E(\r
 183         PDM_ODM_T                       pDM_Odm,\r
 184         PWRTRACK_METHOD         Method,\r
 185         u1Byte                          RFPath,\r
 186         u1Byte                          ChannelMappedIndex\r
 187         )\r
 188 {\r
 189         PADAPTER        Adapter = pDM_Odm->Adapter;\r
 190         PHAL_DATA_TYPE  pHalData = GET_HAL_DATA(Adapter);\r
 191         u1Byte          PwrTrackingLimit_OFDM = 30; //+0dB\r
 192         u1Byte      PwrTrackingLimit_CCK= 28;   //-2dB\r
 193         u1Byte          TxRate = 0xFF;\r
 194         u1Byte          Final_OFDM_Swing_Index = 0; \r
 195         u1Byte          Final_CCK_Swing_Index = 0; \r
 196         u1Byte          i = 0;\r
 197 \r
 198 #if (MP_DRIVER==1)\r
 199         if ( *(pDM_Odm->mp_mode) == 1)\r
 200         {\r
 201 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE ))\r
 202         #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))\r
 203                 PMPT_CONTEXT            pMptCtx = &(Adapter->MptCtx);\r
 204         #elif (DM_ODM_SUPPORT_TYPE & (ODM_CE))\r
 205                 PMPT_CONTEXT            pMptCtx = &(Adapter->mppriv.MptCtx);\r
 206         #endif\r
 207                 TxRate = MptToMgntRate(pMptCtx->MptRateIndex);\r
 208 #endif\r
 209         }\r
 210         else\r
 211 #endif\r
 212         {\r
 213                 u2Byte  rate     = *(pDM_Odm->pForcedDataRate);\r
 214         \r
 215                 if(!rate) //auto rate\r
 216                 {\r
 217                         if(pDM_Odm->TxRate != 0xFF)\r
 218                                 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN))\r
 219                                 TxRate = Adapter->HalFunc.GetHwRateFromMRateHandler(pDM_Odm->TxRate);\r
 220                                 #elif (DM_ODM_SUPPORT_TYPE & (ODM_CE))\r
 221                                 TxRate = HwRateToMRate(pDM_Odm->TxRate);\r
 222                                 #endif\r
 223                 }\r
 224                 else //force rate\r
 225                 {\r
 226                         TxRate = (u1Byte)rate;\r
 227                 }\r
 228         }\r
 229 \r
 230         ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("===>ODM_TxPwrTrackSetPwr8723B\n"));\r
 231 \r
 232         if(TxRate != 0xFF)\r
 233         {\r
 234                 //2 CCK\r
 235                 if((TxRate >= MGN_1M)&&(TxRate <= MGN_11M))\r
 236                         PwrTrackingLimit_CCK = 28;  //-2dB\r
 237                 //2 OFDM\r
 238                 else if((TxRate >= MGN_6M)&&(TxRate <= MGN_48M))\r
 239                         PwrTrackingLimit_OFDM= 36; //+3dB\r
 240                 else if(TxRate == MGN_54M)\r
 241                         PwrTrackingLimit_OFDM= 34; //+2dB\r
 242                         \r
 243                 //2 HT\r
 244                 else if((TxRate >= MGN_MCS0)&&(TxRate <= MGN_MCS2)) //QPSK/BPSK\r
 245                         PwrTrackingLimit_OFDM= 38; //+4dB\r
 246                 else if((TxRate >= MGN_MCS3)&&(TxRate <= MGN_MCS4)) //16QAM\r
 247                         PwrTrackingLimit_OFDM= 36; //+3dB\r
 248                 else if((TxRate >= MGN_MCS5)&&(TxRate <= MGN_MCS7)) //64QAM\r
 249                         PwrTrackingLimit_OFDM= 34; //+2dB\r
 250 \r
 251                 else    \r
 252                         PwrTrackingLimit_OFDM =  pDM_Odm->DefaultOfdmIndex;   //Default OFDM index = 30\r
 253         }\r
 254         ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("TxRate=0x%x, PwrTrackingLimit=%d\n", TxRate, PwrTrackingLimit_OFDM));\r
 255 \r
 256         if (Method == TXAGC) \r
 257         {\r
 258                 u4Byte  pwr = 0, TxAGC = 0;\r
 259                 PADAPTER Adapter = pDM_Odm->Adapter;\r
 260 \r
 261                 pDM_Odm->Remnant_OFDMSwingIdx[RFPath] = pDM_Odm->Absolute_OFDMSwingIdx[RFPath];   //Remnant index equal to aboslute compensate value.\r
 262 \r
 263                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD, ("odm_TxPwrTrackSetPwr88E CH=%d\n", *(pDM_Odm->pChannel)));\r
 264 \r
 265 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE ))\r
 266 \r
 267         #if (MP_DRIVER == 1)\r
 268                 if ( *(pDM_Odm->mp_mode) == 1) \r
 269                 {\r
 270                         pwr = PHY_QueryBBReg(Adapter, rTxAGC_A_Rate18_06, 0xFF);\r
 271                         pwr += pDM_Odm->RFCalibrateInfo.PowerIndexOffset[ODM_RF_PATH_A];\r
 272                         PHY_SetBBReg(Adapter, rTxAGC_A_CCK1_Mcs32, bMaskByte1, pwr);\r
 273                         TxAGC = (pwr<<16)|(pwr<<8)|(pwr);\r
 274                         PHY_SetBBReg(Adapter, rTxAGC_B_CCK11_A_CCK2_11, 0xffffff00, TxAGC);\r
 275                         //RT_DISP(FPHY, PHY_TXPWR, ("ODM_TxPwrTrackSetPwr88E: CCK Tx-rf(A) Power = 0x%x\n", TxAGC));            \r
 276 \r
 277                         pwr = PHY_QueryBBReg(Adapter, rTxAGC_A_Rate18_06, 0xFF);\r
 278                         pwr += (pDM_Odm->BbSwingIdxOfdm[ODM_RF_PATH_A] - pDM_Odm->BbSwingIdxOfdmBase[RF_PATH_A]);\r
 279                         TxAGC |= ((pwr<<24)|(pwr<<16)|(pwr<<8)|pwr);\r
 280                         PHY_SetBBReg(Adapter, rTxAGC_A_Rate18_06, bMaskDWord, TxAGC);\r
 281                         PHY_SetBBReg(Adapter, rTxAGC_A_Rate54_24, bMaskDWord, TxAGC);\r
 282                         PHY_SetBBReg(Adapter, rTxAGC_A_Mcs03_Mcs00, bMaskDWord, TxAGC);\r
 283                         PHY_SetBBReg(Adapter, rTxAGC_A_Mcs07_Mcs04, bMaskDWord, TxAGC);\r
 284                         PHY_SetBBReg(Adapter, rTxAGC_A_Mcs11_Mcs08, bMaskDWord, TxAGC);\r
 285                         PHY_SetBBReg(Adapter, rTxAGC_A_Mcs15_Mcs12, bMaskDWord, TxAGC);\r
 286                         //RT_DISP(FPHY, PHY_TXPWR, ("ODM_TxPwrTrackSetPwr88E: OFDM Tx-rf(A) Power = 0x%x\n", TxAGC));           \r
 287                 }\r
 288                 else\r
 289         #endif\r
 290                 {\r
 291                         //PHY_SetTxPowerLevel8188E(pDM_Odm->Adapter, *pDM_Odm->pChannel);\r
 292                         pDM_Odm->Modify_TxAGC_Flag_PathA = TRUE;\r
 293                         pDM_Odm->Modify_TxAGC_Flag_PathA_CCK = TRUE;\r
 294 \r
 295                         if (RFPath == ODM_RF_PATH_A)\r
 296                         {\r
 297                                 PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, CCK );\r
 298                                 PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, OFDM );\r
 299                                 PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, HT_MCS0_MCS7 );\r
 300                         }\r
 301                 }\r
 302         \r
 303                 \r
 304 #endif\r
 305 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)\r
 306                         //PHY_RF6052SetCCKTxPower(pDM_Odm->priv, *(pDM_Odm->pChannel));\r
 307                         //PHY_RF6052SetOFDMTxPower(pDM_Odm->priv, *(pDM_Odm->pChannel));\r
 308 #endif\r
 309                 \r
 310         } \r
 311         else if (Method == BBSWING)\r
 312         {\r
 313                 Final_OFDM_Swing_Index = pDM_Odm->DefaultOfdmIndex + pDM_Odm->Absolute_OFDMSwingIdx[RFPath];\r
 314                 Final_CCK_Swing_Index = pDM_Odm->DefaultCckIndex + pDM_Odm->Absolute_OFDMSwingIdx[RFPath]; \r
 315                 \r
 316                 if (Final_OFDM_Swing_Index >= PwrTrackingLimit_OFDM)\r
 317                         Final_OFDM_Swing_Index = PwrTrackingLimit_OFDM;\r
 318                 else if (Final_OFDM_Swing_Index < 0)\r
 319                         Final_OFDM_Swing_Index = 0;\r
 320 \r
 321                 if (Final_CCK_Swing_Index >= CCK_TABLE_SIZE)\r
 322                         Final_CCK_Swing_Index = CCK_TABLE_SIZE-1;\r
 323                 else if (pDM_Odm->BbSwingIdxCck < 0)\r
 324                         Final_CCK_Swing_Index = 0;\r
 325 \r
 326                 // Adjust BB swing by OFDM IQ matrix\r
 327                 if (RFPath == ODM_RF_PATH_A)\r
 328                 {\r
 329                         setIqkMatrix_8188E(pDM_Odm, Final_OFDM_Swing_Index, ODM_RF_PATH_A, \r
 330                                                  pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0],\r
 331                                                  pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]);                                         \r
 332                         // Adjust BB swing by CCK filter coefficient\r
 333                         if(!pDM_Odm->RFCalibrateInfo.bCCKinCH14){\r
 334                                 ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][0]);\r
 335                                 ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][1]);\r
 336                                 ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][2]);\r
 337                                 ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][3]);\r
 338                                 ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][4]);\r
 339                                 ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][5]);\r
 340                                 ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][6]);\r
 341                                 ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][7]);           \r
 342                         }\r
 343                         else\r
 344                         {\r
 345                                 ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][0]);\r
 346                                 ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][1]);\r
 347                                 ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][2]);\r
 348                                 ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][3]);\r
 349                                 ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][4]);\r
 350                                 ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][5]);\r
 351                                 ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][6]);\r
 352                                 ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][7]);       \r
 353                         }               \r
 354                 }\r
 355         }\r
 356         else if (Method == MIX_MODE)\r
 357         {\r
 358                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("pDM_Odm->DefaultOfdmIndex=%d,  pDM_Odm->DefaultCCKIndex=%d, pDM_Odm->Absolute_OFDMSwingIdx[RFPath]=%d, RF_Path = %d\n",\r
 359                         pDM_Odm->DefaultOfdmIndex, pDM_Odm->DefaultCckIndex, pDM_Odm->Absolute_OFDMSwingIdx[RFPath],RFPath ));\r
 360                         \r
 361                 Final_CCK_Swing_Index  = pDM_Odm->DefaultCckIndex + pDM_Odm->Absolute_OFDMSwingIdx[RFPath]; \r
 362                 Final_OFDM_Swing_Index = pDM_Odm->DefaultOfdmIndex + pDM_Odm->Absolute_OFDMSwingIdx[RFPath];\r
 363 \r
 364                 if(Final_OFDM_Swing_Index > PwrTrackingLimit_OFDM )     //BBSwing higher then Limit\r
 365                 {\r
 366                         pDM_Odm->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index - PwrTrackingLimit_OFDM;            \r
 367 \r
 368                         setIqkMatrix_8188E(pDM_Odm, PwrTrackingLimit_OFDM, ODM_RF_PATH_A, \r
 369                         pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0],\r
 370                         pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]);                  \r
 371 \r
 372                         pDM_Odm->Modify_TxAGC_Flag_PathA = TRUE;\r
 373 \r
 374                         PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, OFDM );\r
 375                         PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, HT_MCS0_MCS7 );\r
 376 \r
 377                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("******Path_A Over BBSwing Limit , PwrTrackingLimit = %d , Remnant TxAGC Value = %d \n", PwrTrackingLimit_OFDM, pDM_Odm->Remnant_OFDMSwingIdx[RFPath]));\r
 378                 }\r
 379                 else if (Final_OFDM_Swing_Index < 0)\r
 380                 {\r
 381                         pDM_Odm->Remnant_OFDMSwingIdx[RFPath] = Final_OFDM_Swing_Index ;     \r
 382 \r
 383                         setIqkMatrix_8188E(pDM_Odm, 0, ODM_RF_PATH_A, \r
 384                         pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0],\r
 385                         pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]);          \r
 386 \r
 387                         pDM_Odm->Modify_TxAGC_Flag_PathA = TRUE;\r
 388 \r
 389                         PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, OFDM );\r
 390                         PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, HT_MCS0_MCS7 );\r
 391 \r
 392                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("******Path_A Lower then BBSwing lower bound  0 , Remnant TxAGC Value = %d \n", pDM_Odm->Remnant_OFDMSwingIdx[RFPath]));\r
 393                 }\r
 394                 else\r
 395                 {\r
 396                         setIqkMatrix_8188E(pDM_Odm, Final_OFDM_Swing_Index, ODM_RF_PATH_A, \r
 397                         pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][0],\r
 398                         pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[ChannelMappedIndex].Value[0][1]);          \r
 399 \r
 400                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("******Path_A Compensate with BBSwing , Final_OFDM_Swing_Index = %d \n", Final_OFDM_Swing_Index));\r
 401 \r
 402                         if(pDM_Odm->Modify_TxAGC_Flag_PathA)  //If TxAGC has changed, reset TxAGC again\r
 403                         {\r
 404                                 pDM_Odm->Remnant_OFDMSwingIdx[RFPath] = 0;     \r
 405 \r
 406                                 PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, OFDM );\r
 407                                 PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, HT_MCS0_MCS7 );\r
 408 \r
 409                                 pDM_Odm->Modify_TxAGC_Flag_PathA = FALSE;\r
 410 \r
 411                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("******Path_A pDM_Odm->Modify_TxAGC_Flag = FALSE \n"));\r
 412                         }\r
 413                 }\r
 414 \r
 415                 if(Final_CCK_Swing_Index > PwrTrackingLimit_CCK)\r
 416                 {\r
 417                         pDM_Odm->Remnant_CCKSwingIdx = Final_CCK_Swing_Index - PwrTrackingLimit_CCK;\r
 418 \r
 419                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("******Path_A CCK Over Limit , PwrTrackingLimit_CCK = %d , pDM_Odm->Remnant_CCKSwingIdx  = %d \n", PwrTrackingLimit_CCK, pDM_Odm->Remnant_CCKSwingIdx));\r
 420 \r
 421                         // Adjust BB swing by CCK filter coefficient\r
 422                 \r
 423                         if(!pDM_Odm->RFCalibrateInfo.bCCKinCH14)\r
 424                         {\r
 425                                 ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch1_Ch13_New[PwrTrackingLimit_CCK][0]);\r
 426                                 ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch1_Ch13_New[PwrTrackingLimit_CCK][1]);\r
 427                                 ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch1_Ch13_New[PwrTrackingLimit_CCK][2]);\r
 428                                 ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch1_Ch13_New[PwrTrackingLimit_CCK][3]);\r
 429                                 ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch1_Ch13_New[PwrTrackingLimit_CCK][4]);\r
 430                                 ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch1_Ch13_New[PwrTrackingLimit_CCK][5]);\r
 431                                 ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch1_Ch13_New[PwrTrackingLimit_CCK][6]);\r
 432                                 ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch1_Ch13_New[PwrTrackingLimit_CCK][7]);            \r
 433                         }\r
 434                         else\r
 435                         {\r
 436                                 ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch14_New[PwrTrackingLimit_CCK][0]);\r
 437                                 ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch14_New[PwrTrackingLimit_CCK][1]);\r
 438                                 ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch14_New[PwrTrackingLimit_CCK][2]);\r
 439                                 ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch14_New[PwrTrackingLimit_CCK][3]);\r
 440                                 ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch14_New[PwrTrackingLimit_CCK][4]);\r
 441                                 ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch14_New[PwrTrackingLimit_CCK][5]);\r
 442                                 ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch14_New[PwrTrackingLimit_CCK][6]);\r
 443                                 ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch14_New[PwrTrackingLimit_CCK][7]);        \r
 444                         }               \r
 445 \r
 446                         pDM_Odm->Modify_TxAGC_Flag_PathA_CCK = TRUE;\r
 447 \r
 448                         PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, CCK );\r
 449                         \r
 450                 }\r
 451                 else if(Final_CCK_Swing_Index < 0)    // Lowest CCK Index = 0\r
 452                 {\r
 453                         pDM_Odm->Remnant_CCKSwingIdx = Final_CCK_Swing_Index;\r
 454 \r
 455                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("******Path_A CCK Under Limit , PwrTrackingLimit_CCK = %d , pDM_Odm->Remnant_CCKSwingIdx  = %d \n", 0, pDM_Odm->Remnant_CCKSwingIdx));\r
 456 \r
 457                         if(!pDM_Odm->RFCalibrateInfo.bCCKinCH14)\r
 458                         {\r
 459                                 ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch1_Ch13_New[0][0]);\r
 460                                 ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch1_Ch13_New[0][1]);\r
 461                                 ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch1_Ch13_New[0][2]);\r
 462                                 ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch1_Ch13_New[0][3]);\r
 463                                 ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch1_Ch13_New[0][4]);\r
 464                                 ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch1_Ch13_New[0][5]);\r
 465                                 ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch1_Ch13_New[0][6]);\r
 466                                 ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch1_Ch13_New[0][7]);               \r
 467                         }\r
 468                         else\r
 469                         {\r
 470                                 ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch14_New[0][0]);\r
 471                                 ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch14_New[0][1]);\r
 472                                 ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch14_New[0][2]);\r
 473                                 ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch14_New[0][3]);\r
 474                                 ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch14_New[0][4]);\r
 475                                 ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch14_New[0][5]);\r
 476                                 ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch14_New[0][6]);\r
 477                                 ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch14_New[0][7]);   \r
 478                         }\r
 479 \r
 480                         pDM_Odm->Modify_TxAGC_Flag_PathA_CCK = TRUE;\r
 481 \r
 482                         PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, CCK );\r
 483 \r
 484                 }\r
 485                 else\r
 486                 {\r
 487                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("******Path_A CCK Compensate with BBSwing , Final_CCK_Swing_Index = %d \n", Final_CCK_Swing_Index));  \r
 488 \r
 489                         if(!pDM_Odm->RFCalibrateInfo.bCCKinCH14)\r
 490                         {\r
 491                                 ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][0]);\r
 492                                 ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][1]);\r
 493                                 ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][2]);\r
 494                                 ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][3]);\r
 495                                 ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][4]);\r
 496                                 ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][5]);\r
 497                                 ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][6]);\r
 498                                 ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch1_Ch13_New[Final_CCK_Swing_Index][7]);           \r
 499                         }\r
 500                         else\r
 501                         {\r
 502                                 ODM_Write1Byte(pDM_Odm, 0xa22, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][0]);\r
 503                                 ODM_Write1Byte(pDM_Odm, 0xa23, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][1]);\r
 504                                 ODM_Write1Byte(pDM_Odm, 0xa24, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][2]);\r
 505                                 ODM_Write1Byte(pDM_Odm, 0xa25, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][3]);\r
 506                                 ODM_Write1Byte(pDM_Odm, 0xa26, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][4]);\r
 507                                 ODM_Write1Byte(pDM_Odm, 0xa27, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][5]);\r
 508                                 ODM_Write1Byte(pDM_Odm, 0xa28, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][6]);\r
 509                                 ODM_Write1Byte(pDM_Odm, 0xa29, CCKSwingTable_Ch14_New[Final_CCK_Swing_Index][7]);       \r
 510                         }               \r
 511 \r
 512                         if(pDM_Odm->Modify_TxAGC_Flag_PathA_CCK)  //If TxAGC has changed, reset TxAGC again\r
 513                         {\r
 514                                 pDM_Odm->Remnant_CCKSwingIdx = 0;\r
 515                                 PHY_SetTxPowerIndexByRateSection(Adapter, ODM_RF_PATH_A, pHalData->CurrentChannel, CCK );\r
 516                                 pDM_Odm->Modify_TxAGC_Flag_PathA_CCK= FALSE;\r
 517 \r
 518                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_TX_PWR_TRACK, ODM_DBG_LOUD,("******Path_A pDM_Odm->Modify_TxAGC_Flag_CCK = FALSE \n"));\r
 519                         }\r
 520                 }\r
 521         }\r
 522         else\r
 523         {\r
 524                 return;\r
 525         }\r
 526 }       // odm_TxPwrTrackSetPwr88E\r
 527 \r
 528 VOID\r
 529 GetDeltaSwingTable_8188E(\r
 530         IN      PDM_ODM_T                       pDM_Odm,\r
 531         OUT pu1Byte                     *TemperatureUP_A,\r
 532         OUT pu1Byte                     *TemperatureDOWN_A,\r
 533         OUT pu1Byte                     *TemperatureUP_B,\r
 534         OUT pu1Byte                     *TemperatureDOWN_B      \r
 535         )\r
 536 {\r
 537         *TemperatureUP_A = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E;\r
 538         *TemperatureDOWN_A = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E;   \r
 539         *TemperatureUP_B = (pu1Byte)DeltaSwingTableIdx_2GA_P_8188E;\r
 540         *TemperatureDOWN_B = (pu1Byte)DeltaSwingTableIdx_2GA_N_8188E;           \r
 541 }\r
 542 \r
 543 void ConfigureTxpowerTrack_8188E(\r
 544         PTXPWRTRACK_CFG pConfig\r
 545         )\r
 546 {\r
 547         pConfig->SwingTableSize_CCK = CCK_TABLE_SIZE;\r
 548         pConfig->SwingTableSize_OFDM = OFDM_TABLE_SIZE;\r
 549         pConfig->Threshold_IQK = IQK_THRESHOLD;\r
 550         pConfig->AverageThermalNum = AVG_THERMAL_NUM_88E;\r
 551         pConfig->RfPathCount = MAX_PATH_NUM_8188E;\r
 552         pConfig->ThermalRegAddr = RF_T_METER_88E;\r
 553                 \r
 554         pConfig->ODM_TxPwrTrackSetPwr = ODM_TxPwrTrackSetPwr88E;\r
 555         pConfig->DoIQK = DoIQK_8188E;\r
 556         pConfig->PHY_LCCalibrate = PHY_LCCalibrate_8188E;\r
 557         pConfig->GetDeltaSwingTable = GetDeltaSwingTable_8188E;\r
 558 }\r
 559 \r
 560 //1 7.  IQK\r
 561 #define MAX_TOLERANCE           5\r
 562 #define IQK_DELAY_TIME          1               //ms\r
 563 \r
 564 u1Byte                  //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK\r
 565 phy_PathA_IQK_8188E(\r
 566 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)\r
 567         IN PDM_ODM_T            pDM_Odm,\r
 568 #else\r
 569         IN      PADAPTER        pAdapter,\r
 570 #endif\r
 571         IN      BOOLEAN         configPathB\r
 572         )\r
 573 {\r
 574         u4Byte regEAC, regE94, regE9C, regEA4;\r
 575         u1Byte result = 0x00;\r
 576 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
 577         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);     \r
 578         #if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
 579         PDM_ODM_T               pDM_Odm = &pHalData->odmpriv;\r
 580         #endif\r
 581         #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
 582         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;\r
 583         #endif\r
 584 #endif  \r
 585         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQK!\n"));\r
 586 \r
 587     //1 Tx IQK\r
 588         //path-A IQK setting\r
 589         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A IQK setting!\n"));\r
 590         ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x10008c1c);\r
 591         ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x30008c1c);\r
 592         ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x8214032a);\r
 593         ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28160000);\r
 594 \r
 595         //LO calibration setting\r
 596         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n"));\r
 597         ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x00462911);\r
 598 \r
 599         //One shot, path A LOK & IQK\r
 600         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n"));\r
 601         ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);\r
 602         ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);\r
 603         \r
 604         // delay x ms\r
 605         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_88E));\r
 606         //PlatformStallExecution(IQK_DELAY_TIME_88E*1000);\r
 607         ODM_delay_ms(IQK_DELAY_TIME_88E);\r
 608 \r
 609         // Check failed\r
 610         regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord);\r
 611         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC));\r
 612         regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord);\r
 613         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x\n", regE94));\r
 614         regE9C= ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord);\r
 615         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("0xe9c = 0x%x\n", regE9C));\r
 616         regEA4= ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord);\r
 617         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xea4 = 0x%x\n", regEA4));\r
 618 \r
 619         if(!(regEAC & BIT28) &&         \r
 620                 (((regE94 & 0x03FF0000)>>16) != 0x142) &&\r
 621                 (((regE9C & 0x03FF0000)>>16) != 0x42) )\r
 622                 result |= 0x01;\r
 623         else                                                    //if Tx not OK, ignore Rx\r
 624                 return result;\r
 625 \r
 626 #if 0\r
 627         if(!(regEAC & BIT27) &&         //if Tx is OK, check whether Rx is OK\r
 628                 (((regEA4 & 0x03FF0000)>>16) != 0x132) &&\r
 629                 (((regEAC & 0x03FF0000)>>16) != 0x36))\r
 630                 result |= 0x02;\r
 631         else\r
 632                 RT_DISP(FINIT, INIT_IQK, ("Path A Rx IQK fail!!\n"));\r
 633 #endif  \r
 634 \r
 635         return result;\r
 636 \r
 637 \r
 638         }\r
 639 \r
 640 u1Byte                  //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK\r
 641 phy_PathA_RxIQK(\r
 642 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)\r
 643         IN PDM_ODM_T            pDM_Odm,\r
 644 #else\r
 645         IN      PADAPTER        pAdapter,\r
 646 #endif\r
 647         IN      BOOLEAN         configPathB\r
 648         )\r
 649 {\r
 650         u4Byte regEAC, regE94, regE9C, regEA4, u4tmp;\r
 651         u1Byte result = 0x00;\r
 652 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
 653         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);\r
 654         #if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
 655         PDM_ODM_T               pDM_Odm = &pHalData->odmpriv;\r
 656         #endif\r
 657         #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
 658         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;\r
 659         #endif\r
 660 #endif  \r
 661         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK!\n"));\r
 662 \r
 663         //1 Get TXIMR setting\r
 664         //modify RXIQK mode table\r
 665         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A Rx IQK modify RXIQK mode table!\n"));\r
 666         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000);      \r
 667         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, bRFRegOffsetMask, 0x800a0 );\r
 668         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000 );\r
 669         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f );\r
 670         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf117B );\r
 671         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x80800000);\r
 672         \r
 673         //IQK setting\r
 674         ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00);\r
 675         ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x81004800);\r
 676 \r
 677         //path-A IQK setting\r
 678         ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x10008c1c);\r
 679         ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x30008c1c);\r
 680         ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82160804);\r
 681         ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28160000);    \r
 682 \r
 683         //LO calibration setting\r
 684         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n"));\r
 685         ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911);\r
 686 \r
 687         //One shot, path A LOK & IQK\r
 688         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n"));\r
 689         ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);\r
 690         ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);\r
 691         \r
 692         // delay x ms\r
 693         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_88E));\r
 694         //PlatformStallExecution(IQK_DELAY_TIME_88E*1000);\r
 695         ODM_delay_ms(IQK_DELAY_TIME_88E);\r
 696         \r
 697 \r
 698         // Check failed\r
 699         regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord);\r
 700         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xeac = 0x%x\n", regEAC));   \r
 701         regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord);\r
 702         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe94 = 0x%x\n", regE94));\r
 703         regE9C= ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord);\r
 704         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe9c = 0x%x\n", regE9C));\r
 705 \r
 706         if(!(regEAC & BIT28) &&         \r
 707                 (((regE94 & 0x03FF0000)>>16) != 0x142) &&\r
 708                 (((regE9C & 0x03FF0000)>>16) != 0x42) )\r
 709                 result |= 0x01;\r
 710         else                                                    //if Tx not OK, ignore Rx\r
 711                 return result;\r
 712 \r
 713         u4tmp = 0x80007C00 | (regE94&0x3FF0000)  | ((regE9C&0x3FF0000) >> 16);  \r
 714         ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, u4tmp);\r
 715         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xe40 = 0x%x u4tmp = 0x%x \n", ODM_GetBBReg(pDM_Odm, rTx_IQK, bMaskDWord), u4tmp));  \r
 716         \r
 717 \r
 718         //1 RX IQK\r
 719         //modify RXIQK mode table\r
 720         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path-A Rx IQK modify RXIQK mode table 2!\n"));\r
 721         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000);              \r
 722         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_WE_LUT, bRFRegOffsetMask, 0x800a0 );\r
 723         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_RCK_OS, bRFRegOffsetMask, 0x30000 );\r
 724         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G1, bRFRegOffsetMask, 0x0000f );\r
 725         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_TXPA_G2, bRFRegOffsetMask, 0xf7ffa );\r
 726         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x80800000);\r
 727 \r
 728         //IQK setting\r
 729         ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x01004800);\r
 730 \r
 731         //path-A IQK setting\r
 732         ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x30008c1c);\r
 733         ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x10008c1c);\r
 734         ODM_SetBBReg(pDM_Odm, rTx_IQK_PI_A, bMaskDWord, 0x82160c05);\r
 735         ODM_SetBBReg(pDM_Odm, rRx_IQK_PI_A, bMaskDWord, 0x28160c05);    \r
 736 \r
 737         //LO calibration setting\r
 738         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LO calibration setting!\n"));\r
 739         ODM_SetBBReg(pDM_Odm, rIQK_AGC_Rsp, bMaskDWord, 0x0046a911);\r
 740 \r
 741         //One shot, path A LOK & IQK\r
 742         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n"));\r
 743         ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf9000000);\r
 744         ODM_SetBBReg(pDM_Odm, rIQK_AGC_Pts, bMaskDWord, 0xf8000000);\r
 745         \r
 746         // delay x ms\r
 747         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path A LOK & IQK.\n", IQK_DELAY_TIME_88E));\r
 748         //PlatformStallExecution(IQK_DELAY_TIME_88E*1000);\r
 749         ODM_delay_ms(IQK_DELAY_TIME_88E);\r
 750 \r
 751         // Check failed\r
 752         regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord);\r
 753         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("0xeac = 0x%x\n", regEAC));\r
 754         regE94 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord);\r
 755         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("0xe94 = 0x%x\n", regE94));\r
 756         regE9C= ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord);\r
 757         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("0xe9c = 0x%x\n", regE9C));\r
 758         regEA4= ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord);\r
 759         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("0xea4 = 0x%x\n", regEA4));\r
 760 \r
 761 #if 0   \r
 762         if(!(regEAC & BIT28) &&         \r
 763                 (((regE94 & 0x03FF0000)>>16) != 0x142) &&\r
 764                 (((regE9C & 0x03FF0000)>>16) != 0x42) )\r
 765                 result |= 0x01;\r
 766         else                                                    //if Tx not OK, ignore Rx\r
 767                 return result;\r
 768 #endif  \r
 769 \r
 770         if(!(regEAC & BIT27) &&         //if Tx is OK, check whether Rx is OK\r
 771                 (((regEA4 & 0x03FF0000)>>16) != 0x132) &&\r
 772                 (((regEAC & 0x03FF0000)>>16) != 0x36))\r
 773                 result |= 0x02;\r
 774         else\r
 775                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("Path A Rx IQK fail!!\n"));\r
 776         \r
 777         return result;\r
 778 \r
 779 \r
 780 }\r
 781 \r
 782 u1Byte                          //bit0 = 1 => Tx OK, bit1 = 1 => Rx OK\r
 783 phy_PathB_IQK_8188E(\r
 784 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)\r
 785         IN PDM_ODM_T            pDM_Odm\r
 786 #else\r
 787         IN      PADAPTER        pAdapter\r
 788 #endif\r
 789         )\r
 790 {\r
 791         u4Byte regEAC, regEB4, regEBC, regEC4, regECC;\r
 792         u1Byte  result = 0x00;\r
 793 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
 794         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);\r
 795         #if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
 796         PDM_ODM_T               pDM_Odm = &pHalData->odmpriv;\r
 797         #endif\r
 798         #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
 799         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;\r
 800         #endif\r
 801 #endif  \r
 802         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("Path B IQK!\n"));\r
 803 \r
 804         //One shot, path B LOK & IQK\r
 805         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("One shot, path A LOK & IQK!\n"));\r
 806         ODM_SetBBReg(pDM_Odm, rIQK_AGC_Cont, bMaskDWord, 0x00000002);\r
 807         ODM_SetBBReg(pDM_Odm, rIQK_AGC_Cont, bMaskDWord, 0x00000000);\r
 808 \r
 809         // delay x ms\r
 810         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Delay %d ms for One shot, path B LOK & IQK.\n", IQK_DELAY_TIME_88E));\r
 811         //PlatformStallExecution(IQK_DELAY_TIME_88E*1000);\r
 812         ODM_delay_ms(IQK_DELAY_TIME_88E);\r
 813         \r
 814         // Check failed\r
 815         regEAC = ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord);\r
 816         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("0xeac = 0x%x\n", regEAC));\r
 817         regEB4 = ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_B, bMaskDWord);\r
 818         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("0xeb4 = 0x%x\n", regEB4));\r
 819         regEBC= ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_B, bMaskDWord);\r
 820         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("0xebc = 0x%x\n", regEBC));\r
 821         regEC4= ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_B_2, bMaskDWord);\r
 822         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xec4 = 0x%x\n", regEC4));\r
 823         regECC= ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_B_2, bMaskDWord);\r
 824         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("0xecc = 0x%x\n", regECC));\r
 825 \r
 826         if(!(regEAC & BIT31) &&\r
 827                 (((regEB4 & 0x03FF0000)>>16) != 0x142) &&\r
 828                 (((regEBC & 0x03FF0000)>>16) != 0x42))\r
 829                 result |= 0x01;\r
 830         else\r
 831                 return result;\r
 832 \r
 833         if(!(regEAC & BIT30) &&\r
 834                 (((regEC4 & 0x03FF0000)>>16) != 0x132) &&\r
 835                 (((regECC & 0x03FF0000)>>16) != 0x36))\r
 836                 result |= 0x02;\r
 837         else\r
 838                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("Path B Rx IQK fail!!\n"));\r
 839         \r
 840 \r
 841         return result;\r
 842 \r
 843 }\r
 844 \r
 845 VOID\r
 846 _PHY_PathAFillIQKMatrix(\r
 847 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)\r
 848         IN PDM_ODM_T            pDM_Odm,\r
 849 #else\r
 850         IN      PADAPTER        pAdapter,\r
 851 #endif\r
 852         IN  BOOLEAN     bIQKOK,\r
 853         IN      s4Byte          result[][8],\r
 854         IN      u1Byte          final_candidate,\r
 855         IN  BOOLEAN             bTxOnly\r
 856         )\r
 857 {\r
 858         u4Byte  Oldval_0, X, TX0_A, reg;\r
 859         s4Byte  Y, TX0_C;\r
 860 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
 861         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);             \r
 862         #if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
 863         PDM_ODM_T               pDM_Odm = &pHalData->odmpriv;\r
 864         #endif\r
 865         #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
 866         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;\r
 867         #endif\r
 868 #endif  \r
 869         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("Path A IQ Calibration %s !\n",(bIQKOK)?"Success":"Failed"));\r
 870 \r
 871         if(final_candidate == 0xFF)\r
 872                 return;\r
 873 \r
 874         else if(bIQKOK)\r
 875         {\r
 876                 Oldval_0 = (ODM_GetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, bMaskDWord) >> 22) & 0x3FF;\r
 877 \r
 878                 X = result[final_candidate][0];\r
 879                 if ((X & 0x00000200) != 0)\r
 880                         X = X | 0xFFFFFC00;                             \r
 881                 TX0_A = (X * Oldval_0) >> 8;\r
 882                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("X = 0x%x, TX0_A = 0x%x, Oldval_0 0x%x\n", X, TX0_A, Oldval_0));\r
 883                 ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, 0x3FF, TX0_A);\r
 884 \r
 885                 ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(31), ((X* Oldval_0>>7) & 0x1));\r
 886      \r
 887                 Y = result[final_candidate][1];\r
 888                 if ((Y & 0x00000200) != 0)\r
 889                         Y = Y | 0xFFFFFC00;             \r
 890 \r
 891         \r
 892                 TX0_C = (Y * Oldval_0) >> 8;\r
 893                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("Y = 0x%x, TX = 0x%x\n", Y, TX0_C));\r
 894                 ODM_SetBBReg(pDM_Odm, rOFDM0_XCTxAFE, 0xF0000000, ((TX0_C&0x3C0)>>6));\r
 895                 ODM_SetBBReg(pDM_Odm, rOFDM0_XATxIQImbalance, 0x003F0000, (TX0_C&0x3F));\r
 896 \r
 897                 ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(29), ((Y* Oldval_0>>7) & 0x1));\r
 898 \r
 899                 if(bTxOnly)\r
 900                 {\r
 901                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("_PHY_PathAFillIQKMatrix only Tx OK\n"));            \r
 902                         return;\r
 903                 }\r
 904 \r
 905                 reg = result[final_candidate][2];\r
 906 #if (DM_ODM_SUPPORT_TYPE==ODM_AP)               \r
 907                 if( RTL_ABS(reg ,0x100) >= 16) \r
 908                         reg = 0x100;\r
 909 #endif\r
 910                 ODM_SetBBReg(pDM_Odm, rOFDM0_XARxIQImbalance, 0x3FF, reg);\r
 911         \r
 912                 reg = result[final_candidate][3] & 0x3F;\r
 913                 ODM_SetBBReg(pDM_Odm, rOFDM0_XARxIQImbalance, 0xFC00, reg);\r
 914 \r
 915                 reg = (result[final_candidate][3] >> 6) & 0xF;\r
 916                 ODM_SetBBReg(pDM_Odm, rOFDM0_RxIQExtAnta, 0xF0000000, reg);\r
 917         }\r
 918 }\r
 919 \r
 920 VOID\r
 921 _PHY_PathBFillIQKMatrix(\r
 922 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)\r
 923         IN PDM_ODM_T            pDM_Odm,\r
 924 #else\r
 925         IN      PADAPTER        pAdapter,\r
 926 #endif\r
 927         IN  BOOLEAN     bIQKOK,\r
 928         IN      s4Byte          result[][8],\r
 929         IN      u1Byte          final_candidate,\r
 930         IN      BOOLEAN         bTxOnly                 //do Tx only\r
 931         )\r
 932 {\r
 933         u4Byte  Oldval_1, X, TX1_A, reg;\r
 934         s4Byte  Y, TX1_C;\r
 935 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
 936         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);             \r
 937         #if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
 938         PDM_ODM_T               pDM_Odm = &pHalData->odmpriv;\r
 939         #endif\r
 940         #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
 941         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;\r
 942         #endif\r
 943 #endif  \r
 944         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQ Calibration %s !\n",(bIQKOK)?"Success":"Failed"));\r
 945 \r
 946         if(final_candidate == 0xFF)\r
 947                 return;\r
 948 \r
 949         else if(bIQKOK)\r
 950         {\r
 951                 Oldval_1 = (ODM_GetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, bMaskDWord) >> 22) & 0x3FF;\r
 952 \r
 953                 X = result[final_candidate][4];\r
 954                 if ((X & 0x00000200) != 0)\r
 955                         X = X | 0xFFFFFC00;             \r
 956                 TX1_A = (X * Oldval_1) >> 8;\r
 957                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("X = 0x%x, TX1_A = 0x%x\n", X, TX1_A));\r
 958                 ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, 0x3FF, TX1_A);\r
 959 \r
 960                 ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(27), ((X* Oldval_1>>7) & 0x1));\r
 961 \r
 962                 Y = result[final_candidate][5];\r
 963                 if ((Y & 0x00000200) != 0)\r
 964                         Y = Y | 0xFFFFFC00;             \r
 965 \r
 966                 TX1_C = (Y * Oldval_1) >> 8;\r
 967                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("Y = 0x%x, TX1_C = 0x%x\n", Y, TX1_C));\r
 968                 ODM_SetBBReg(pDM_Odm, rOFDM0_XDTxAFE, 0xF0000000, ((TX1_C&0x3C0)>>6));\r
 969                 ODM_SetBBReg(pDM_Odm, rOFDM0_XBTxIQImbalance, 0x003F0000, (TX1_C&0x3F));\r
 970 \r
 971                 ODM_SetBBReg(pDM_Odm, rOFDM0_ECCAThreshold, BIT(25), ((Y* Oldval_1>>7) & 0x1));\r
 972 \r
 973                 if(bTxOnly)\r
 974                         return;\r
 975 \r
 976                 reg = result[final_candidate][6];\r
 977                 ODM_SetBBReg(pDM_Odm, rOFDM0_XBRxIQImbalance, 0x3FF, reg);\r
 978         \r
 979                 reg = result[final_candidate][7] & 0x3F;\r
 980                 ODM_SetBBReg(pDM_Odm, rOFDM0_XBRxIQImbalance, 0xFC00, reg);\r
 981 \r
 982                 reg = (result[final_candidate][7] >> 6) & 0xF;\r
 983                 ODM_SetBBReg(pDM_Odm, rOFDM0_AGCRSSITable, 0x0000F000, reg);\r
 984         }\r
 985 }\r
 986 \r
 987 //\r
 988 // 2011/07/26 MH Add an API for testing IQK fail case.\r
 989 //\r
 990 // MP Already declare in odm.c \r
 991 #if !(DM_ODM_SUPPORT_TYPE & ODM_WIN) \r
 992 BOOLEAN\r
 993 ODM_CheckPowerStatus(\r
 994         IN      PADAPTER                Adapter)\r
 995 {\r
 996 /*\r
 997         HAL_DATA_TYPE           *pHalData = GET_HAL_DATA(Adapter);\r
 998         PDM_ODM_T                       pDM_Odm = &pHalData->DM_OutSrc;\r
 999         RT_RF_POWER_STATE       rtState;\r
1000         PMGNT_INFO                      pMgntInfo       = &(Adapter->MgntInfo);\r
1001 \r
1002         // 2011/07/27 MH We are not testing ready~~!! We may fail to get correct value when init sequence.\r
1003         if (pMgntInfo->init_adpt_in_progress == TRUE)\r
1004         {\r
1005                 ODM_RT_TRACE(pDM_Odm,COMP_INIT, DBG_LOUD, ("ODM_CheckPowerStatus Return TRUE, due to initadapter"));\r
1006                 return  TRUE;\r
1007         }\r
1008         \r
1009         //\r
1010         //      2011/07/19 MH We can not execute tx pwoer tracking/ LLC calibrate or IQK.\r
1011         //\r
1012         Adapter->HalFunc.GetHwRegHandler(Adapter, HW_VAR_RF_STATE, (pu1Byte)(&rtState));        \r
1013         if(Adapter->bDriverStopped || Adapter->bDriverIsGoingToPnpSetPowerSleep || rtState == eRfOff)\r
1014         {\r
1015                 ODM_RT_TRACE(pDM_Odm,COMP_INIT, DBG_LOUD, ("ODM_CheckPowerStatus Return FALSE, due to %d/%d/%d\n", \r
1016                 Adapter->bDriverStopped, Adapter->bDriverIsGoingToPnpSetPowerSleep, rtState));\r
1017                 return  FALSE;\r
1018         }\r
1019 */\r
1020         return  TRUE;\r
1021 }\r
1022 #endif\r
1023 \r
1024 VOID\r
1025 _PHY_SaveADDARegisters(\r
1026 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1027         IN PDM_ODM_T            pDM_Odm,\r
1028 #else\r
1029         IN      PADAPTER        pAdapter,\r
1030 #endif\r
1031         IN      pu4Byte         ADDAReg,\r
1032         IN      pu4Byte         ADDABackup,\r
1033         IN      u4Byte          RegisterNum\r
1034         )\r
1035 {\r
1036         u4Byte  i;\r
1037 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1038         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);\r
1039         #if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
1040         PDM_ODM_T               pDM_Odm = &pHalData->odmpriv;\r
1041         #endif\r
1042         #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
1043         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;\r
1044         #endif\r
1045         \r
1046         if (ODM_CheckPowerStatus(pAdapter) == FALSE)\r
1047                 return;\r
1048 #endif\r
1049         \r
1050         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Save ADDA parameters.\n"));\r
1051         for( i = 0 ; i < RegisterNum ; i++){\r
1052                 ADDABackup[i] = ODM_GetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord);\r
1053         }\r
1054 }\r
1055 \r
1056 \r
1057 VOID\r
1058 _PHY_SaveMACRegisters(\r
1059 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1060         IN PDM_ODM_T            pDM_Odm,\r
1061 #else\r
1062         IN      PADAPTER        pAdapter,\r
1063 #endif\r
1064         IN      pu4Byte         MACReg,\r
1065         IN      pu4Byte         MACBackup\r
1066         )\r
1067 {\r
1068         u4Byte  i;\r
1069 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1070         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);\r
1071         #if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
1072         PDM_ODM_T               pDM_Odm = &pHalData->odmpriv;\r
1073         #endif\r
1074         #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
1075         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;\r
1076         #endif\r
1077 #endif  \r
1078         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Save MAC parameters.\n"));\r
1079         for( i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++){\r
1080                 MACBackup[i] = ODM_Read1Byte(pDM_Odm, MACReg[i]);               \r
1081         }\r
1082         MACBackup[i] = ODM_Read4Byte(pDM_Odm, MACReg[i]);               \r
1083 \r
1084 }\r
1085 \r
1086 \r
1087 VOID\r
1088 _PHY_ReloadADDARegisters(\r
1089 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1090         IN PDM_ODM_T            pDM_Odm,\r
1091 #else\r
1092         IN      PADAPTER        pAdapter,\r
1093 #endif\r
1094         IN      pu4Byte         ADDAReg,\r
1095         IN      pu4Byte         ADDABackup,\r
1096         IN      u4Byte          RegiesterNum\r
1097         )\r
1098 {\r
1099         u4Byte  i;\r
1100 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1101         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);\r
1102         #if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
1103         PDM_ODM_T               pDM_Odm = &pHalData->odmpriv;\r
1104         #endif\r
1105         #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
1106         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;\r
1107         #endif\r
1108 #endif\r
1109         \r
1110         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Reload ADDA power saving parameters !\n"));\r
1111         for(i = 0 ; i < RegiesterNum; i++)\r
1112         {\r
1113                 ODM_SetBBReg(pDM_Odm, ADDAReg[i], bMaskDWord, ADDABackup[i]);\r
1114         }\r
1115 }\r
1116 \r
1117 VOID\r
1118 _PHY_ReloadMACRegisters(\r
1119 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1120         IN PDM_ODM_T            pDM_Odm,\r
1121 #else\r
1122         IN      PADAPTER        pAdapter,\r
1123 #endif\r
1124         IN      pu4Byte         MACReg,\r
1125         IN      pu4Byte         MACBackup\r
1126         )\r
1127 {\r
1128         u4Byte  i;\r
1129 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1130         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);\r
1131         #if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
1132         PDM_ODM_T               pDM_Odm = &pHalData->odmpriv;\r
1133         #endif\r
1134         #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
1135         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;\r
1136         #endif\r
1137 #endif\r
1138         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("Reload MAC parameters !\n"));\r
1139         for(i = 0 ; i < (IQK_MAC_REG_NUM - 1); i++){\r
1140                 ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)MACBackup[i]);\r
1141         }\r
1142         ODM_Write4Byte(pDM_Odm, MACReg[i], MACBackup[i]);       \r
1143 }\r
1144 \r
1145 \r
1146 VOID\r
1147 _PHY_PathADDAOn(\r
1148 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1149         IN PDM_ODM_T            pDM_Odm,\r
1150 #else\r
1151         IN      PADAPTER        pAdapter,\r
1152 #endif\r
1153         IN      pu4Byte         ADDAReg,\r
1154         IN      BOOLEAN         isPathAOn,\r
1155         IN      BOOLEAN         is2T\r
1156         )\r
1157 {\r
1158         u4Byte  pathOn;\r
1159         u4Byte  i;\r
1160 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1161         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);\r
1162         #if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
1163         PDM_ODM_T               pDM_Odm = &pHalData->odmpriv;\r
1164         #endif\r
1165         #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
1166         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;\r
1167         #endif\r
1168 #endif\r
1169         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("ADDA ON.\n"));\r
1170 \r
1171         pathOn = isPathAOn ? 0x04db25a4 : 0x0b1b25a4;\r
1172         if(FALSE == is2T){\r
1173                 pathOn = 0x0bdb25a0;\r
1174                 ODM_SetBBReg(pDM_Odm, ADDAReg[0], bMaskDWord, 0x0b1b25a0);\r
1175         }\r
1176         else{\r
1177                 ODM_SetBBReg(pDM_Odm,ADDAReg[0], bMaskDWord, pathOn);\r
1178         }\r
1179         \r
1180         for( i = 1 ; i < IQK_ADDA_REG_NUM ; i++){\r
1181                 ODM_SetBBReg(pDM_Odm,ADDAReg[i], bMaskDWord, pathOn);\r
1182         }\r
1183         \r
1184 }\r
1185 \r
1186 VOID\r
1187 _PHY_MACSettingCalibration(\r
1188 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1189         IN PDM_ODM_T            pDM_Odm,\r
1190 #else\r
1191         IN      PADAPTER        pAdapter,\r
1192 #endif\r
1193         IN      pu4Byte         MACReg,\r
1194         IN      pu4Byte         MACBackup       \r
1195         )\r
1196 {\r
1197         u4Byte  i = 0;\r
1198 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1199         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);\r
1200         #if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
1201         PDM_ODM_T               pDM_Odm = &pHalData->odmpriv;\r
1202         #endif\r
1203         #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
1204         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;\r
1205         #endif\r
1206 #endif  \r
1207         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("MAC settings for Calibration.\n"));\r
1208 \r
1209         ODM_Write1Byte(pDM_Odm, MACReg[i], 0x3F);\r
1210 \r
1211         for(i = 1 ; i < (IQK_MAC_REG_NUM - 1); i++){\r
1212                 ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)(MACBackup[i]&(~BIT3)));\r
1213         }\r
1214         ODM_Write1Byte(pDM_Odm, MACReg[i], (u1Byte)(MACBackup[i]&(~BIT5)));     \r
1215 \r
1216 }\r
1217 \r
1218 VOID\r
1219 _PHY_PathAStandBy(\r
1220 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1221         IN PDM_ODM_T            pDM_Odm\r
1222 #else\r
1223         IN PADAPTER     pAdapter\r
1224 #endif\r
1225         )\r
1226 {\r
1227 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1228         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);\r
1229         #if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
1230         PDM_ODM_T               pDM_Odm = &pHalData->odmpriv;\r
1231         #endif\r
1232         #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
1233         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;\r
1234         #endif\r
1235 #endif  \r
1236         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("Path-A standby mode!\n"));\r
1237 \r
1238         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x0);\r
1239         ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x00010000);\r
1240         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x80800000);\r
1241 }\r
1242 \r
1243 VOID\r
1244 _PHY_PIModeSwitch(\r
1245 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1246         IN PDM_ODM_T            pDM_Odm,\r
1247 #else\r
1248         IN      PADAPTER        pAdapter,\r
1249 #endif\r
1250         IN      BOOLEAN         PIMode\r
1251         )\r
1252 {\r
1253         u4Byte  mode;\r
1254 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1255         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);\r
1256         #if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
1257         PDM_ODM_T               pDM_Odm = &pHalData->odmpriv;\r
1258         #endif\r
1259         #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
1260         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;\r
1261         #endif\r
1262 #endif  \r
1263         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("BB Switch to %s mode!\n", (PIMode ? "PI" : "SI")));\r
1264 \r
1265         mode = PIMode ? 0x01000100 : 0x01000000;\r
1266         ODM_SetBBReg(pDM_Odm, rFPGA0_XA_HSSIParameter1, bMaskDWord, mode);\r
1267         ODM_SetBBReg(pDM_Odm, rFPGA0_XB_HSSIParameter1, bMaskDWord, mode);\r
1268 }\r
1269 \r
1270 BOOLEAN                                                 \r
1271 phy_SimularityCompare_8188E(\r
1272 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1273         IN PDM_ODM_T            pDM_Odm,\r
1274 #else\r
1275         IN      PADAPTER        pAdapter,\r
1276 #endif\r
1277         IN      s4Byte          result[][8],\r
1278         IN      u1Byte           c1,\r
1279         IN      u1Byte           c2\r
1280         )\r
1281 {\r
1282         u4Byte          i, j, diff, SimularityBitMap, bound = 0;\r
1283 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1284         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);     \r
1285         #if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
1286         PDM_ODM_T               pDM_Odm = &pHalData->odmpriv;\r
1287         #endif\r
1288         #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
1289         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;\r
1290         #endif\r
1291 #endif  \r
1292         u1Byte          final_candidate[2] = {0xFF, 0xFF};      //for path A and path B\r
1293         BOOLEAN         bResult = TRUE;\r
1294 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1295         BOOLEAN         is2T = IS_92C_SERIAL( pHalData->VersionID);\r
1296 #else\r
1297         BOOLEAN         is2T = 0;\r
1298 #endif\r
1299         \r
1300         if(is2T)\r
1301                 bound = 8;\r
1302         else\r
1303                 bound = 4;\r
1304 \r
1305         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("===> IQK:phy_SimularityCompare_8188E c1 %d c2 %d!!!\n", c1, c2));\r
1306 \r
1307 \r
1308         SimularityBitMap = 0;\r
1309         \r
1310         for( i = 0; i < bound; i++ )\r
1311         {\r
1312                 diff = (result[c1][i] > result[c2][i]) ? (result[c1][i] - result[c2][i]) : (result[c2][i] - result[c1][i]);\r
1313                 if (diff > MAX_TOLERANCE)\r
1314                 {\r
1315                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("IQK:phy_SimularityCompare_8188E differnece overflow index %d compare1 0x%x compare2 0x%x!!!\n",  i, result[c1][i], result[c2][i]));\r
1316                 \r
1317                         if((i == 2 || i == 6) && !SimularityBitMap)\r
1318                         {\r
1319                                 if(result[c1][i]+result[c1][i+1] == 0)\r
1320                                         final_candidate[(i/4)] = c2;\r
1321                                 else if (result[c2][i]+result[c2][i+1] == 0)\r
1322                                         final_candidate[(i/4)] = c1;\r
1323                                 else\r
1324                                         SimularityBitMap = SimularityBitMap|(1<<i);                                     \r
1325                         }\r
1326                         else\r
1327                                 SimularityBitMap = SimularityBitMap|(1<<i);\r
1328                 }\r
1329         }\r
1330         \r
1331         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:phy_SimularityCompare_8188E SimularityBitMap   %d !!!\n", SimularityBitMap));\r
1332         \r
1333         if ( SimularityBitMap == 0)\r
1334         {\r
1335                 for( i = 0; i < (bound/4); i++ )\r
1336                 {\r
1337                         if(final_candidate[i] != 0xFF)\r
1338                         {\r
1339                                 for( j = i*4; j < (i+1)*4-2; j++)\r
1340                                         result[3][j] = result[final_candidate[i]][j];\r
1341                                 bResult = FALSE;\r
1342                         }\r
1343                 }\r
1344                 return bResult;\r
1345         }\r
1346         else if (!(SimularityBitMap & 0x0F))                    //path A OK\r
1347         {\r
1348                 for(i = 0; i < 4; i++)\r
1349                         result[3][i] = result[c1][i];\r
1350                 return FALSE;\r
1351         }\r
1352         else if (!(SimularityBitMap & 0xF0) && is2T)    //path B OK\r
1353         {\r
1354                 for(i = 4; i < 8; i++)\r
1355                         result[3][i] = result[c1][i];\r
1356                 return FALSE;\r
1357         }       \r
1358         else            \r
1359                 return FALSE;\r
1360         \r
1361 }\r
1362 \r
1363 \r
1364 \r
1365 VOID    \r
1366 phy_IQCalibrate_8188E(\r
1367 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1368         IN PDM_ODM_T            pDM_Odm,\r
1369 #else\r
1370         IN      PADAPTER        pAdapter,\r
1371 #endif\r
1372         IN      s4Byte          result[][8],\r
1373         IN      u1Byte          t,\r
1374         IN      BOOLEAN         is2T\r
1375         )\r
1376 {\r
1377 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1378         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);     \r
1379         #if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
1380         PDM_ODM_T               pDM_Odm = &pHalData->odmpriv;\r
1381         #endif\r
1382         #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
1383         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;\r
1384         #endif\r
1385 #endif  \r
1386         u4Byte                  i;\r
1387         u1Byte                  PathAOK=0, PathBOK=0;\r
1388         u4Byte                  ADDA_REG[IQK_ADDA_REG_NUM] = {  \r
1389                                                 rFPGA0_XCD_SwitchControl,       rBlue_Tooth,    \r
1390                                                 rRx_Wait_CCA,           rTx_CCK_RFON,\r
1391                                                 rTx_CCK_BBON,   rTx_OFDM_RFON,  \r
1392                                                 rTx_OFDM_BBON,  rTx_To_Rx,\r
1393                                                 rTx_To_Tx,              rRx_CCK,        \r
1394                                                 rRx_OFDM,               rRx_Wait_RIFS,\r
1395                                                 rRx_TO_Rx,              rStandby,       \r
1396                                                 rSleep,                         rPMPD_ANAEN };\r
1397         u4Byte                  IQK_MAC_REG[IQK_MAC_REG_NUM] = {\r
1398                                                 REG_TXPAUSE,            REG_BCN_CTRL,   \r
1399                                                 REG_BCN_CTRL_1, REG_GPIO_MUXCFG};\r
1400                                         \r
1401         //since 92C & 92D have the different define in IQK_BB_REG       \r
1402         u4Byte  IQK_BB_REG_92C[IQK_BB_REG_NUM] = {\r
1403                                                         rOFDM0_TRxPathEnable,           rOFDM0_TRMuxPar,        \r
1404                                                         rFPGA0_XCD_RFInterfaceSW,       rConfig_AntA,   rConfig_AntB,\r
1405                                                         rFPGA0_XAB_RFInterfaceSW,       rFPGA0_XA_RFInterfaceOE,        \r
1406                                                         rFPGA0_XB_RFInterfaceOE,        rCCK0_AFESetting        \r
1407                                                         };      \r
1408 \r
1409         u4Byte  retryCount = 2;\r
1410 \r
1411         if ( *(pDM_Odm->mp_mode) == 1)\r
1412                 retryCount = 9;\r
1413 \r
1414         // Note: IQ calibration must be performed after loading \r
1415         //              PHY_REG.txt , and radio_a, radio_b.txt  \r
1416         \r
1417         //u4Byte bbvalue;\r
1418 \r
1419 #if (DM_ODM_SUPPORT_TYPE & (ODM_AP|ODM_ADSL))\r
1420 #ifdef MP_TEST\r
1421                 if(pDM_Odm->priv->pshare->rf_ft_var.mp_specific)\r
1422                         retryCount = 9; \r
1423 #endif\r
1424 #endif\r
1425 \r
1426 \r
1427         if(t==0)\r
1428         {\r
1429 //               bbvalue = ODM_GetBBReg(pDM_Odm, rFPGA0_RFMOD, bMaskDWord);\r
1430 //                      RT_DISP(FINIT, INIT_IQK, ("phy_IQCalibrate_8188E()==>0x%08x\n",bbvalue));\r
1431 \r
1432                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQ Calibration for %s for %d times\n", (is2T ? "2T2R" : "1T1R"), t));\r
1433         \r
1434                 // Save ADDA parameters, turn Path A ADDA on\r
1435 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1436                 _PHY_SaveADDARegisters(pAdapter, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM);\r
1437                 _PHY_SaveMACRegisters(pAdapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup);\r
1438                 _PHY_SaveADDARegisters(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM);                               \r
1439 #else\r
1440                 _PHY_SaveADDARegisters(pDM_Odm, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM);\r
1441                 _PHY_SaveMACRegisters(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup);\r
1442                 _PHY_SaveADDARegisters(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM);                \r
1443 #endif\r
1444         }\r
1445         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQ Calibration for %s for %d times\n", (is2T ? "2T2R" : "1T1R"), t));\r
1446         \r
1447 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1448         \r
1449         _PHY_PathADDAOn(pAdapter, ADDA_REG, TRUE, is2T);\r
1450 #else\r
1451         _PHY_PathADDAOn(pDM_Odm, ADDA_REG, TRUE, is2T);\r
1452 #endif\r
1453                 \r
1454         \r
1455         if(t==0)\r
1456         {\r
1457                 pDM_Odm->RFCalibrateInfo.bRfPiEnable = (u1Byte)ODM_GetBBReg(pDM_Odm, rFPGA0_XA_HSSIParameter1, BIT(8));\r
1458         }\r
1459         \r
1460         if(!pDM_Odm->RFCalibrateInfo.bRfPiEnable){\r
1461                 // Switch BB to PI mode to do IQ Calibration.\r
1462 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1463                 _PHY_PIModeSwitch(pAdapter, TRUE);\r
1464 #else\r
1465                 _PHY_PIModeSwitch(pDM_Odm, TRUE);\r
1466 #endif\r
1467         }\r
1468         \r
1469 \r
1470         //MAC settings\r
1471 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1472         _PHY_MACSettingCalibration(pAdapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup);\r
1473 #else\r
1474         _PHY_MACSettingCalibration(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup);\r
1475 #endif\r
1476         \r
1477         //BB setting\r
1478         //ODM_SetBBReg(pDM_Odm, rFPGA0_RFMOD, BIT24, 0x00);             \r
1479         ODM_SetBBReg(pDM_Odm, rCCK0_AFESetting, 0x0f000000, 0xf);\r
1480         ODM_SetBBReg(pDM_Odm, rOFDM0_TRxPathEnable, bMaskDWord, 0x03a05600);\r
1481         ODM_SetBBReg(pDM_Odm, rOFDM0_TRMuxPar, bMaskDWord, 0x000800e4);\r
1482         ODM_SetBBReg(pDM_Odm, rFPGA0_XCD_RFInterfaceSW, bMaskDWord, 0x22204000);\r
1483 \r
1484         \r
1485         ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFInterfaceSW, BIT10, 0x01);\r
1486         ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFInterfaceSW, BIT26, 0x01);   \r
1487         ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, BIT10, 0x00);\r
1488         ODM_SetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT10, 0x00);    \r
1489         \r
1490 \r
1491         if(is2T)\r
1492         {\r
1493                 ODM_SetBBReg(pDM_Odm, rFPGA0_XA_LSSIParameter, bMaskDWord, 0x00010000);\r
1494                 ODM_SetBBReg(pDM_Odm, rFPGA0_XB_LSSIParameter, bMaskDWord, 0x00010000);\r
1495         }\r
1496 \r
1497         //Page B init\r
1498         //AP or IQK\r
1499         ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x0f600000);\r
1500         \r
1501         if(is2T)\r
1502         {\r
1503                 ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x0f600000);\r
1504         }\r
1505 \r
1506         // IQ calibration setting\r
1507         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK setting!\n"));           \r
1508         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x80800000);\r
1509         ODM_SetBBReg(pDM_Odm, rTx_IQK, bMaskDWord, 0x01007c00);\r
1510         ODM_SetBBReg(pDM_Odm, rRx_IQK, bMaskDWord, 0x81004800);\r
1511 \r
1512         for(i = 0 ; i < retryCount ; i++){\r
1513 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1514                 PathAOK = phy_PathA_IQK_8188E(pAdapter, is2T);\r
1515 #else\r
1516                 PathAOK = phy_PathA_IQK_8188E(pDM_Odm, is2T);\r
1517 #endif\r
1518 //              if(PathAOK == 0x03){\r
1519                 if(PathAOK == 0x01){\r
1520                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Tx IQK Success!!\n"));\r
1521                                 result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16;\r
1522                                 result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16;\r
1523                         break;\r
1524                 }\r
1525 #if 0           \r
1526                 else if (i == (retryCount-1) && PathAOK == 0x01)        //Tx IQK OK\r
1527                 {\r
1528                         RT_DISP(FINIT, INIT_IQK, ("Path A IQK Only  Tx Success!!\n"));\r
1529                         \r
1530                         result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16;\r
1531                         result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16;                        \r
1532                 }\r
1533 #endif          \r
1534         }\r
1535 \r
1536         for(i = 0 ; i < retryCount ; i++){\r
1537 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1538                 PathAOK = phy_PathA_RxIQK(pAdapter, is2T);\r
1539 #else\r
1540                 PathAOK = phy_PathA_RxIQK(pDM_Odm, is2T);\r
1541 #endif\r
1542                 if(PathAOK == 0x03){\r
1543                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("Path A Rx IQK Success!!\n"));\r
1544 //                              result[t][0] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_A, bMaskDWord)&0x3FF0000)>>16;\r
1545 //                              result[t][1] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_A, bMaskDWord)&0x3FF0000)>>16;\r
1546                                 result[t][2] = (ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_A_2, bMaskDWord)&0x3FF0000)>>16;\r
1547                                 result[t][3] = (ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_A_2, bMaskDWord)&0x3FF0000)>>16;\r
1548                         break;\r
1549                 }\r
1550                 else\r
1551                 {\r
1552                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A Rx IQK Fail!!\n"));           \r
1553                 }\r
1554         }\r
1555 \r
1556         if(0x00 == PathAOK){            \r
1557                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path A IQK failed!!\n"));            \r
1558         }\r
1559 \r
1560         if(is2T){\r
1561 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1562                 _PHY_PathAStandBy(pAdapter);\r
1563 \r
1564                 // Turn Path B ADDA on\r
1565                 _PHY_PathADDAOn(pAdapter, ADDA_REG, FALSE, is2T);\r
1566 #else\r
1567                 _PHY_PathAStandBy(pDM_Odm);\r
1568 \r
1569                 // Turn Path B ADDA on\r
1570                 _PHY_PathADDAOn(pDM_Odm, ADDA_REG, FALSE, is2T);\r
1571 #endif\r
1572 \r
1573                 for(i = 0 ; i < retryCount ; i++){\r
1574 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1575                         PathBOK = phy_PathB_IQK_8188E(pAdapter);\r
1576 #else\r
1577                         PathBOK = phy_PathB_IQK_8188E(pDM_Odm);\r
1578 #endif\r
1579                         if(PathBOK == 0x03){\r
1580                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQK Success!!\n"));\r
1581                                 result[t][4] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_B, bMaskDWord)&0x3FF0000)>>16;\r
1582                                 result[t][5] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_B, bMaskDWord)&0x3FF0000)>>16;\r
1583                                 result[t][6] = (ODM_GetBBReg(pDM_Odm, rRx_Power_Before_IQK_B_2, bMaskDWord)&0x3FF0000)>>16;\r
1584                                 result[t][7] = (ODM_GetBBReg(pDM_Odm, rRx_Power_After_IQK_B_2, bMaskDWord)&0x3FF0000)>>16;\r
1585                                 break;\r
1586                         }\r
1587                         else if (i == (retryCount - 1) && PathBOK == 0x01)      //Tx IQK OK\r
1588                         {\r
1589                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B Only Tx IQK Success!!\n"));\r
1590                                 result[t][4] = (ODM_GetBBReg(pDM_Odm, rTx_Power_Before_IQK_B, bMaskDWord)&0x3FF0000)>>16;\r
1591                                 result[t][5] = (ODM_GetBBReg(pDM_Odm, rTx_Power_After_IQK_B, bMaskDWord)&0x3FF0000)>>16;                                \r
1592                         }\r
1593                 }\r
1594 \r
1595                 if(0x00 == PathBOK){            \r
1596                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("Path B IQK failed!!\n"));            \r
1597                 }\r
1598         }\r
1599 \r
1600         //Back to BB mode, load original value\r
1601         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK:Back to BB mode, load original value!\n"));\r
1602         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0);\r
1603 \r
1604         if(t!=0)\r
1605         {\r
1606                 if(!pDM_Odm->RFCalibrateInfo.bRfPiEnable){\r
1607                         // Switch back BB to SI mode after finish IQ Calibration.\r
1608 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1609                         _PHY_PIModeSwitch(pAdapter, FALSE);\r
1610 #else\r
1611                         _PHY_PIModeSwitch(pDM_Odm, FALSE);\r
1612 #endif\r
1613                 }\r
1614 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1615 \r
1616                 // Reload ADDA power saving parameters\r
1617                 _PHY_ReloadADDARegisters(pAdapter, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM);\r
1618 \r
1619                 // Reload MAC parameters\r
1620                 _PHY_ReloadMACRegisters(pAdapter, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup);\r
1621                 \r
1622                 _PHY_ReloadADDARegisters(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM);\r
1623 #else\r
1624                 // Reload ADDA power saving parameters\r
1625                 _PHY_ReloadADDARegisters(pDM_Odm, ADDA_REG, pDM_Odm->RFCalibrateInfo.ADDA_backup, IQK_ADDA_REG_NUM);\r
1626 \r
1627                 // Reload MAC parameters\r
1628                 _PHY_ReloadMACRegisters(pDM_Odm, IQK_MAC_REG, pDM_Odm->RFCalibrateInfo.IQK_MAC_backup);\r
1629                 \r
1630                 _PHY_ReloadADDARegisters(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup, IQK_BB_REG_NUM);\r
1631 #endif\r
1632                 \r
1633 \r
1634                         // Restore RX initial gain\r
1635                         ODM_SetBBReg(pDM_Odm, rFPGA0_XA_LSSIParameter, bMaskDWord, 0x00032ed3);\r
1636                         if(is2T){\r
1637                                 ODM_SetBBReg(pDM_Odm, rFPGA0_XB_LSSIParameter, bMaskDWord, 0x00032ed3);\r
1638                         }\r
1639                 \r
1640                 //load 0xe30 IQC default value\r
1641                 ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00);          \r
1642                 ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00);                          \r
1643                 \r
1644         }\r
1645         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_IQCalibrate_8188E() <==\n"));\r
1646         \r
1647 }\r
1648 \r
1649 \r
1650 VOID    \r
1651 phy_LCCalibrate_8188E(\r
1652         IN PDM_ODM_T            pDM_Odm,\r
1653         IN      BOOLEAN         is2T\r
1654         )\r
1655 {\r
1656         u1Byte  tmpReg;\r
1657         u4Byte  RF_Amode=0, RF_Bmode=0, LC_Cal;\r
1658 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1659         PADAPTER pAdapter = pDM_Odm->Adapter;\r
1660 #endif  \r
1661         //Check continuous TX and Packet TX\r
1662         tmpReg = ODM_Read1Byte(pDM_Odm, 0xd03);\r
1663 \r
1664         if((tmpReg&0x70) != 0)                  //Deal with contisuous TX case\r
1665                 ODM_Write1Byte(pDM_Odm, 0xd03, tmpReg&0x8F);    //disable all continuous TX\r
1666         else                                                    // Deal with Packet TX case\r
1667                 ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0xFF);                     // block all queues\r
1668 \r
1669         if((tmpReg&0x70) != 0)\r
1670         {\r
1671                 //1. Read original RF mode\r
1672                 //Path-A\r
1673 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1674                 RF_Amode = PHY_QueryRFReg(pAdapter, ODM_RF_PATH_A, RF_AC, bMask12Bits);\r
1675 \r
1676                 //Path-B\r
1677                 if(is2T)\r
1678                         RF_Bmode = PHY_QueryRFReg(pAdapter, ODM_RF_PATH_B, RF_AC, bMask12Bits); \r
1679 #else\r
1680                 RF_Amode = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMask12Bits);\r
1681 \r
1682                 //Path-B\r
1683                 if(is2T)\r
1684                         RF_Bmode = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMask12Bits);    \r
1685 #endif  \r
1686 \r
1687                 //2. Set RF mode = standby mode\r
1688                 //Path-A\r
1689                 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMask12Bits, (RF_Amode&0x8FFFF)|0x10000);\r
1690 \r
1691                 //Path-B\r
1692                 if(is2T)\r
1693                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMask12Bits, (RF_Bmode&0x8FFFF)|0x10000);                   \r
1694         }\r
1695         \r
1696         //3. Read RF reg18\r
1697 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1698         LC_Cal = PHY_QueryRFReg(pAdapter, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits);\r
1699 #else\r
1700         LC_Cal = ODM_GetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits);\r
1701 #endif  \r
1702         \r
1703         //4. Set LC calibration begin   bit15\r
1704         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_CHNLBW, bMask12Bits, LC_Cal|0x08000);\r
1705 \r
1706         ODM_delay_ms(100);              \r
1707 \r
1708 \r
1709         //Restore original situation\r
1710         if((tmpReg&0x70) != 0)  //Deal with contisuous TX case \r
1711         {  \r
1712                 //Path-A\r
1713                 ODM_Write1Byte(pDM_Odm, 0xd03, tmpReg);\r
1714                 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMask12Bits, RF_Amode);\r
1715                 \r
1716                 //Path-B\r
1717                 if(is2T)\r
1718                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMask12Bits, RF_Bmode);\r
1719         }\r
1720         else // Deal with Packet TX case\r
1721         {\r
1722                 ODM_Write1Byte(pDM_Odm, REG_TXPAUSE, 0x00);     \r
1723         }\r
1724 }\r
1725 \r
1726 //Analog Pre-distortion calibration\r
1727 #define         APK_BB_REG_NUM  8\r
1728 #define         APK_CURVE_REG_NUM 4\r
1729 #define         PATH_NUM                2\r
1730 \r
1731 VOID    \r
1732 phy_APCalibrate_8188E(\r
1733 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1734         IN PDM_ODM_T            pDM_Odm,\r
1735 #else\r
1736         IN      PADAPTER        pAdapter,\r
1737 #endif\r
1738         IN      s1Byte          delta,\r
1739         IN      BOOLEAN         is2T\r
1740         )\r
1741 {\r
1742 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1743         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);\r
1744         #if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
1745         PDM_ODM_T               pDM_Odm = &pHalData->odmpriv;\r
1746         #endif\r
1747         #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
1748         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;\r
1749         #endif\r
1750 #endif\r
1751         u4Byte                  regD[PATH_NUM];\r
1752         u4Byte                  tmpReg, index, offset,  apkbound;\r
1753         u1Byte                  path, i, pathbound = PATH_NUM;          \r
1754         u4Byte                  BB_backup[APK_BB_REG_NUM];\r
1755         u4Byte                  BB_REG[APK_BB_REG_NUM] = {      \r
1756                                                 rFPGA1_TxBlock,         rOFDM0_TRxPathEnable, \r
1757                                                 rFPGA0_RFMOD,   rOFDM0_TRMuxPar, \r
1758                                                 rFPGA0_XCD_RFInterfaceSW,       rFPGA0_XAB_RFInterfaceSW, \r
1759                                                 rFPGA0_XA_RFInterfaceOE,        rFPGA0_XB_RFInterfaceOE };\r
1760         u4Byte                  BB_AP_MODE[APK_BB_REG_NUM] = {  \r
1761                                                 0x00000020, 0x00a05430, 0x02040000, \r
1762                                                 0x000800e4, 0x00204000 };\r
1763         u4Byte                  BB_normal_AP_MODE[APK_BB_REG_NUM] = {   \r
1764                                                 0x00000020, 0x00a05430, 0x02040000, \r
1765                                                 0x000800e4, 0x22204000 };                                               \r
1766 \r
1767         u4Byte                  AFE_backup[IQK_ADDA_REG_NUM];\r
1768         u4Byte                  AFE_REG[IQK_ADDA_REG_NUM] = {   \r
1769                                                 rFPGA0_XCD_SwitchControl,       rBlue_Tooth,    \r
1770                                                 rRx_Wait_CCA,           rTx_CCK_RFON,\r
1771                                                 rTx_CCK_BBON,   rTx_OFDM_RFON,  \r
1772                                                 rTx_OFDM_BBON,  rTx_To_Rx,\r
1773                                                 rTx_To_Tx,              rRx_CCK,        \r
1774                                                 rRx_OFDM,               rRx_Wait_RIFS,\r
1775                                                 rRx_TO_Rx,              rStandby,       \r
1776                                                 rSleep,                         rPMPD_ANAEN };\r
1777 \r
1778         u4Byte                  MAC_backup[IQK_MAC_REG_NUM];\r
1779         u4Byte                  MAC_REG[IQK_MAC_REG_NUM] = {\r
1780                                                 REG_TXPAUSE,            REG_BCN_CTRL,   \r
1781                                                 REG_BCN_CTRL_1, REG_GPIO_MUXCFG};\r
1782 \r
1783         u4Byte                  APK_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = {\r
1784                                         {0x0852c, 0x1852c, 0x5852c, 0x1852c, 0x5852c},\r
1785                                         {0x2852e, 0x0852e, 0x3852e, 0x0852e, 0x0852e}\r
1786                                         };      \r
1787 \r
1788         u4Byte                  APK_normal_RF_init_value[PATH_NUM][APK_BB_REG_NUM] = {\r
1789                                         {0x0852c, 0x0a52c, 0x3a52c, 0x5a52c, 0x5a52c},  //path settings equal to path b settings\r
1790                                         {0x0852c, 0x0a52c, 0x5a52c, 0x5a52c, 0x5a52c}\r
1791                                         };\r
1792         \r
1793         u4Byte                  APK_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = {\r
1794                                         {0x52019, 0x52014, 0x52013, 0x5200f, 0x5208d},\r
1795                                         {0x5201a, 0x52019, 0x52016, 0x52033, 0x52050}\r
1796                                         };\r
1797 \r
1798         u4Byte                  APK_normal_RF_value_0[PATH_NUM][APK_BB_REG_NUM] = {\r
1799                                         {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a},  //path settings equal to path b settings\r
1800                                         {0x52019, 0x52017, 0x52010, 0x5200d, 0x5206a}\r
1801                                         };\r
1802 \r
1803         u4Byte                  AFE_on_off[PATH_NUM] = {\r
1804                                         0x04db25a4, 0x0b1b25a4};        //path A on path B off / path A off path B on\r
1805 \r
1806         u4Byte                  APK_offset[PATH_NUM] = {\r
1807                                         rConfig_AntA, rConfig_AntB};\r
1808 \r
1809         u4Byte                  APK_normal_offset[PATH_NUM] = {\r
1810                                         rConfig_Pmpd_AntA, rConfig_Pmpd_AntB};\r
1811                                         \r
1812         u4Byte                  APK_value[PATH_NUM] = {\r
1813                                         0x92fc0000, 0x12fc0000};                                        \r
1814 \r
1815         u4Byte                  APK_normal_value[PATH_NUM] = {\r
1816                                         0x92680000, 0x12680000};                                        \r
1817 \r
1818         s1Byte                  APK_delta_mapping[APK_BB_REG_NUM][13] = {\r
1819                                         {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6},\r
1820                                         {-4, -3, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6},                                                                                  \r
1821                                         {-6, -4, -2, -2, -1, -1, 0, 1, 2, 3, 4, 5, 6},\r
1822                                         {-1, -1, -1, -1, -1, -1, 0, 1, 2, 3, 4, 5, 6},\r
1823                                         {-11, -9, -7, -5, -3, -1, 0, 0, 0, 0, 0, 0, 0}\r
1824                                         };\r
1825         \r
1826         u4Byte                  APK_normal_setting_value_1[13] = {\r
1827                                         0x01017018, 0xf7ed8f84, 0x1b1a1816, 0x2522201e, 0x322e2b28,\r
1828                                         0x433f3a36, 0x5b544e49, 0x7b726a62, 0xa69a8f84, 0xdfcfc0b3,\r
1829                                         0x12680000, 0x00880000, 0x00880000\r
1830                                         };\r
1831 \r
1832         u4Byte                  APK_normal_setting_value_2[16] = {\r
1833                                         0x01c7021d, 0x01670183, 0x01000123, 0x00bf00e2, 0x008d00a3,\r
1834                                         0x0068007b, 0x004d0059, 0x003a0042, 0x002b0031, 0x001f0025,\r
1835                                         0x0017001b, 0x00110014, 0x000c000f, 0x0009000b, 0x00070008,\r
1836                                         0x00050006\r
1837                                         };\r
1838         \r
1839         u4Byte                  APK_result[PATH_NUM][APK_BB_REG_NUM];   //val_1_1a, val_1_2a, val_2a, val_3a, val_4a\r
1840 //      u4Byte                  AP_curve[PATH_NUM][APK_CURVE_REG_NUM];\r
1841 \r
1842         s4Byte                  BB_offset, delta_V, delta_offset;\r
1843 \r
1844 #if MP_DRIVER == 1\r
1845 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
1846         PMPT_CONTEXT    pMptCtx = &(pAdapter->mppriv.MptCtx);   \r
1847 #else\r
1848         PMPT_CONTEXT    pMptCtx = &(pAdapter->MptCtx);  \r
1849 #endif\r
1850 \r
1851         if ( *(pDM_Odm->mp_mode) == 1)\r
1852         {\r
1853                 pMptCtx->APK_bound[0] = 45;\r
1854                 pMptCtx->APK_bound[1] = 52;             \r
1855         }\r
1856 #endif\r
1857 \r
1858         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("==>phy_APCalibrate_8188E() delta %d\n", delta));\r
1859         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("AP Calibration for %s\n", (is2T ? "2T2R" : "1T1R")));\r
1860         if(!is2T)\r
1861                 pathbound = 1;\r
1862 \r
1863         //2 FOR NORMAL CHIP SETTINGS\r
1864 \r
1865 // Temporarily do not allow normal driver to do the following settings because these offset\r
1866 // and value will cause RF internal PA to be unpredictably disabled by HW, such that RF Tx signal\r
1867 // will disappear after disable/enable card many times on 88CU. RF SD and DD have not find the\r
1868 // root cause, so we remove these actions temporarily. Added by tynli and SD3 Allen. 2010.05.31.\r
1869 //#if MP_DRIVER != 1\r
1870         if (*(pDM_Odm->mp_mode) != 1)\r
1871                 return;\r
1872 //#endif\r
1873         //settings adjust for normal chip\r
1874         for(index = 0; index < PATH_NUM; index ++)\r
1875         {\r
1876                 APK_offset[index] = APK_normal_offset[index];\r
1877                 APK_value[index] = APK_normal_value[index];\r
1878                 AFE_on_off[index] = 0x6fdb25a4;\r
1879         }\r
1880 \r
1881         for(index = 0; index < APK_BB_REG_NUM; index ++)\r
1882         {\r
1883                 for(path = 0; path < pathbound; path++)\r
1884                 {\r
1885                         APK_RF_init_value[path][index] = APK_normal_RF_init_value[path][index];\r
1886                         APK_RF_value_0[path][index] = APK_normal_RF_value_0[path][index];\r
1887                 }\r
1888                 BB_AP_MODE[index] = BB_normal_AP_MODE[index];\r
1889         }                       \r
1890 \r
1891         apkbound = 6;\r
1892         \r
1893         //save BB default value\r
1894         for(index = 0; index < APK_BB_REG_NUM ; index++)\r
1895         {\r
1896                 if(index == 0)          //skip \r
1897                         continue;                               \r
1898                 BB_backup[index] = ODM_GetBBReg(pDM_Odm, BB_REG[index], bMaskDWord);\r
1899         }\r
1900         \r
1901         //save MAC default value                                                                                                        \r
1902 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1903         _PHY_SaveMACRegisters(pAdapter, MAC_REG, MAC_backup);\r
1904         \r
1905         //save AFE default value\r
1906         _PHY_SaveADDARegisters(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);\r
1907 #else\r
1908         _PHY_SaveMACRegisters(pDM_Odm, MAC_REG, MAC_backup);\r
1909         \r
1910         //save AFE default value\r
1911         _PHY_SaveADDARegisters(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);\r
1912 #endif\r
1913 \r
1914         for(path = 0; path < pathbound; path++)\r
1915         {\r
1916 \r
1917 \r
1918                 if(path == ODM_RF_PATH_A)\r
1919                 {\r
1920                         //path A APK\r
1921                         //load APK setting\r
1922                         //path-A                \r
1923                         offset = rPdp_AntA;\r
1924                         for(index = 0; index < 11; index ++)                    \r
1925                         {\r
1926                                 ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]);\r
1927                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord)));      \r
1928                                 \r
1929                                 offset += 0x04;\r
1930                         }\r
1931                         \r
1932                         ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000);\r
1933                         \r
1934                         offset = rConfig_AntA;\r
1935                         for(; index < 13; index ++)             \r
1936                         {\r
1937                                 ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]);\r
1938                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord)));      \r
1939                                 \r
1940                                 offset += 0x04;\r
1941                         }       \r
1942                         \r
1943                         //page-B1\r
1944                         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x40000000);\r
1945                 \r
1946                         //path A\r
1947                         offset = rPdp_AntA;\r
1948                         for(index = 0; index < 16; index++)\r
1949                         {\r
1950                                 ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_2[index]);           \r
1951                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord)));      \r
1952                                 \r
1953                                 offset += 0x04;\r
1954                         }                               \r
1955                         ODM_SetBBReg(pDM_Odm,  rFPGA0_IQK, bMaskDWord, 0x00000000);                                                     \r
1956                 }\r
1957                 else if(path == ODM_RF_PATH_B)\r
1958                 {\r
1959                         //path B APK\r
1960                         //load APK setting\r
1961                         //path-B                \r
1962                         offset = rPdp_AntB;\r
1963                         for(index = 0; index < 10; index ++)                    \r
1964                         {\r
1965                                 ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]);\r
1966                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord)));      \r
1967                                 \r
1968                                 offset += 0x04;\r
1969                         }\r
1970                         ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x12680000);                       \r
1971 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
1972                         PHY_SetBBReg(pAdapter, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000);\r
1973 #else\r
1974                         PHY_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x12680000);\r
1975 #endif\r
1976                         \r
1977                         offset = rConfig_AntA;\r
1978                         index = 11;\r
1979                         for(; index < 13; index ++) //offset 0xb68, 0xb6c               \r
1980                         {\r
1981                                 ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_1[index]);\r
1982                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord)));     \r
1983                                 \r
1984                                 offset += 0x04;\r
1985                         }       \r
1986                         \r
1987                         //page-B1\r
1988                         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x40000000);\r
1989                         \r
1990                         //path B\r
1991                         offset = 0xb60;\r
1992                         for(index = 0; index < 16; index++)\r
1993                         {\r
1994                                 ODM_SetBBReg(pDM_Odm, offset, bMaskDWord, APK_normal_setting_value_2[index]);           \r
1995                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", offset, ODM_GetBBReg(pDM_Odm, offset, bMaskDWord)));     \r
1996                                 \r
1997                                 offset += 0x04;\r
1998                         }                               \r
1999                         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0);                                                       \r
2000                 }\r
2001         \r
2002                 //save RF default value\r
2003 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
2004                 regD[path] = PHY_QueryRFReg(pAdapter, path, RF_TXBIAS_A, bMaskDWord);\r
2005 #else\r
2006                 regD[path] = ODM_GetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_TXBIAS_A, bMaskDWord);\r
2007 #endif\r
2008                 \r
2009                 //Path A AFE all on, path B AFE All off or vise versa\r
2010                 for(index = 0; index < IQK_ADDA_REG_NUM ; index++)\r
2011                         ODM_SetBBReg(pDM_Odm, AFE_REG[index], bMaskDWord, AFE_on_off[path]);\r
2012                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xe70 %x\n", ODM_GetBBReg(pDM_Odm, rRx_Wait_CCA, bMaskDWord)));               \r
2013 \r
2014                 //BB to AP mode\r
2015                 if(path == 0)\r
2016                 {                               \r
2017                         for(index = 0; index < APK_BB_REG_NUM ; index++)\r
2018                         {\r
2019 \r
2020                                 if(index == 0)          //skip \r
2021                                         continue;                       \r
2022                                 else if (index < 5)\r
2023                                 ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_AP_MODE[index]);\r
2024                                 else if (BB_REG[index] == 0x870)\r
2025                                         ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index]|BIT10|BIT26);\r
2026                                 else\r
2027                                         ODM_SetBBReg(pDM_Odm, BB_REG[index], BIT10, 0x0);                                       \r
2028                         }\r
2029 \r
2030                         ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00);                  \r
2031                         ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00);                                  \r
2032                 }\r
2033                 else            //path B\r
2034                 {\r
2035                         ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x01008c00);                  \r
2036                         ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x01008c00);                                  \r
2037                 \r
2038                 }\r
2039 \r
2040                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x800 %x\n", ODM_GetBBReg(pDM_Odm, 0x800, bMaskDWord)));                              \r
2041 \r
2042                 //MAC settings\r
2043 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
2044                 _PHY_MACSettingCalibration(pAdapter, MAC_REG, MAC_backup);\r
2045 #else\r
2046                 _PHY_MACSettingCalibration(pDM_Odm, MAC_REG, MAC_backup);\r
2047 #endif\r
2048                 \r
2049                 if(path == ODM_RF_PATH_A)       //Path B to standby mode\r
2050                 {\r
2051                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMaskDWord, 0x10000);                       \r
2052                 }\r
2053                 else                    //Path A to standby mode\r
2054                 {\r
2055                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMaskDWord, 0x10000);                       \r
2056                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f);                    \r
2057                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE2, bMaskDWord, 0x20103);                                            \r
2058                 }\r
2059 \r
2060                 delta_offset = ((delta+14)/2);\r
2061                 if(delta_offset < 0)\r
2062                         delta_offset = 0;\r
2063                 else if (delta_offset > 12)\r
2064                         delta_offset = 12;\r
2065                         \r
2066                 //AP calibration\r
2067                 for(index = 0; index < APK_BB_REG_NUM; index++)\r
2068                 {\r
2069                         if(index != 1)  //only DO PA11+PAD01001, AP RF setting\r
2070                                 continue;\r
2071                                         \r
2072                         tmpReg = APK_RF_init_value[path][index];\r
2073 #if 1                   \r
2074                         if(!pDM_Odm->RFCalibrateInfo.bAPKThermalMeterIgnore)\r
2075                         {\r
2076                                 BB_offset = (tmpReg & 0xF0000) >> 16;\r
2077 \r
2078                                 if(!(tmpReg & BIT15)) //sign bit 0\r
2079                                 {\r
2080                                         BB_offset = -BB_offset;\r
2081                                 }\r
2082 \r
2083                                 delta_V = APK_delta_mapping[index][delta_offset];\r
2084                                 \r
2085                                 BB_offset += delta_V;\r
2086 \r
2087                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() APK index %d tmpReg 0x%x delta_V %d delta_offset %d\n", index, tmpReg, delta_V, delta_offset));              \r
2088                                 \r
2089                                 if(BB_offset < 0)\r
2090                                 {\r
2091                                         tmpReg = tmpReg & (~BIT15);\r
2092                                         BB_offset = -BB_offset;\r
2093                                 }\r
2094                                 else\r
2095                                 {\r
2096                                         tmpReg = tmpReg | BIT15;\r
2097                                 }\r
2098                                 tmpReg = (tmpReg & 0xFFF0FFFF) | (BB_offset << 16);\r
2099                         }\r
2100 #endif\r
2101 \r
2102                         ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_IPA_A, bMaskDWord, 0x8992e);\r
2103 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
2104                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xc %x\n", PHY_QueryRFReg(pAdapter, path, RF_IPA_A, bMaskDWord)));            \r
2105                         ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_AC, bMaskDWord, APK_RF_value_0[path][index]);\r
2106                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("phy_APCalibrate_8188E() offset 0x0 %x\n", PHY_QueryRFReg(pAdapter, path, RF_AC, bMaskDWord)));              \r
2107                         ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_TXBIAS_A, bMaskDWord, tmpReg);\r
2108                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xd %x\n", PHY_QueryRFReg(pAdapter, path, RF_TXBIAS_A, bMaskDWord)));                                 \r
2109 #else\r
2110                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xc %x\n", ODM_GetRFReg(pDM_Odm, path, RF_IPA_A, bMaskDWord)));               \r
2111                         ODM_SetRFReg(pDM_Odm, path, RF_AC, bMaskDWord, APK_RF_value_0[path][index]);\r
2112                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("phy_APCalibrate_8188E() offset 0x0 %x\n", ODM_GetRFReg(pDM_Odm, path, RF_AC, bMaskDWord)));         \r
2113                         ODM_SetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord, tmpReg);\r
2114                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xd %x\n", ODM_GetRFReg(pDM_Odm, path, RF_TXBIAS_A, bMaskDWord)));                                    \r
2115 #endif\r
2116                         \r
2117                         // PA11+PAD01111, one shot      \r
2118                         i = 0;\r
2119                         do\r
2120                         {\r
2121                                 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x80000000);\r
2122                                 {\r
2123                                         ODM_SetBBReg(pDM_Odm, APK_offset[path], bMaskDWord, APK_value[0]);              \r
2124                                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", APK_offset[path], ODM_GetBBReg(pDM_Odm, APK_offset[path], bMaskDWord)));\r
2125                                         ODM_delay_ms(3);                                \r
2126                                         ODM_SetBBReg(pDM_Odm, APK_offset[path], bMaskDWord, APK_value[1]);\r
2127                                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0x%x value 0x%x\n", APK_offset[path], ODM_GetBBReg(pDM_Odm, APK_offset[path], bMaskDWord)));\r
2128 \r
2129                                         ODM_delay_ms(20);\r
2130                                 }\r
2131                                 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000);\r
2132 \r
2133                                 if(path == ODM_RF_PATH_A)\r
2134                                         tmpReg = ODM_GetBBReg(pDM_Odm, rAPK, 0x03E00000);\r
2135                                 else\r
2136                                         tmpReg = ODM_GetBBReg(pDM_Odm, rAPK, 0xF8000000);\r
2137                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_APCalibrate_8188E() offset 0xbd8[25:21] %x\n", tmpReg));         \r
2138                                 \r
2139 \r
2140                                 i++;\r
2141                         }\r
2142                         while(tmpReg > apkbound && i < 4);\r
2143 \r
2144                         APK_result[path][index] = tmpReg;\r
2145                 }\r
2146         }\r
2147 \r
2148         //reload MAC default value      \r
2149 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
2150         _PHY_ReloadMACRegisters(pAdapter, MAC_REG, MAC_backup);\r
2151 #else\r
2152         _PHY_ReloadMACRegisters(pDM_Odm, MAC_REG, MAC_backup);\r
2153 #endif\r
2154         \r
2155         //reload BB default value       \r
2156         for(index = 0; index < APK_BB_REG_NUM ; index++)\r
2157         {\r
2158 \r
2159                 if(index == 0)          //skip \r
2160                         continue;                                       \r
2161                 ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index]);\r
2162         }\r
2163 \r
2164         //reload AFE default value\r
2165 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
2166         _PHY_ReloadADDARegisters(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);\r
2167 #else\r
2168         _PHY_ReloadADDARegisters(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);\r
2169 #endif\r
2170 \r
2171         //reload RF path default value\r
2172         for(path = 0; path < pathbound; path++)\r
2173         {\r
2174                 ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, 0xd, bMaskDWord, regD[path]);\r
2175                 if(path == ODM_RF_PATH_B)\r
2176                 {\r
2177                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f);                    \r
2178                         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE2, bMaskDWord, 0x20101);                                            \r
2179                 }\r
2180 \r
2181                 //note no index == 0\r
2182                 if (APK_result[path][1] > 6)\r
2183                         APK_result[path][1] = 6;\r
2184                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("apk path %d result %d 0x%x \t", path, 1, APK_result[path][1]));                                      \r
2185         }\r
2186 \r
2187         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("\n"));\r
2188         \r
2189 \r
2190         for(path = 0; path < pathbound; path++)\r
2191         {\r
2192                 ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, 0x3, bMaskDWord, \r
2193                 ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (APK_result[path][1] << 5) | APK_result[path][1]));\r
2194                 if(path == ODM_RF_PATH_A)\r
2195                         ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, 0x4, bMaskDWord, \r
2196                         ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x00 << 5) | 0x05));              \r
2197                 else\r
2198                 ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, 0x4, bMaskDWord, \r
2199                         ((APK_result[path][1] << 15) | (APK_result[path][1] << 10) | (0x02 << 5) | 0x05));                                              \r
2200 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
2201                 if(!IS_HARDWARE_TYPE_8723A(pAdapter))           \r
2202                         ODM_SetRFReg(pDM_Odm, (ODM_RF_RADIO_PATH_E)path, RF_BS_PA_APSET_G9_G11, bMaskDWord, \r
2203                         ((0x08 << 15) | (0x08 << 10) | (0x08 << 5) | 0x08));                    \r
2204 #endif          \r
2205         }\r
2206 \r
2207         pDM_Odm->RFCalibrateInfo.bAPKdone = TRUE;\r
2208 \r
2209         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<==phy_APCalibrate_8188E()\n"));\r
2210 }\r
2211 \r
2212 \r
2213 \r
2214 #define         DP_BB_REG_NUM           7\r
2215 #define         DP_RF_REG_NUM           1\r
2216 #define         DP_RETRY_LIMIT          10\r
2217 #define         DP_PATH_NUM             2\r
2218 #define         DP_DPK_NUM                      3\r
2219 #define         DP_DPK_VALUE_NUM        2\r
2220 \r
2221 \r
2222 \r
2223 \r
2224 \r
2225 VOID\r
2226 PHY_IQCalibrate_8188E(\r
2227 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)\r
2228         IN PDM_ODM_T            pDM_Odm,\r
2229 #else\r
2230         IN      PADAPTER        pAdapter,\r
2231 #endif\r
2232         IN      BOOLEAN         bReCovery\r
2233         )\r
2234 {\r
2235 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
2236         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);     \r
2237 \r
2238         #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
2239         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc; \r
2240         #else  // (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
2241         PDM_ODM_T               pDM_Odm = &pHalData->odmpriv;   \r
2242         #endif\r
2243 \r
2244         #if (MP_DRIVER == 1)\r
2245         #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)    \r
2246         PMPT_CONTEXT    pMptCtx = &(pAdapter->MptCtx);  \r
2247         #else// (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
2248         PMPT_CONTEXT    pMptCtx = &(pAdapter->mppriv.MptCtx);           \r
2249         #endif  \r
2250         #endif//(MP_DRIVER == 1)\r
2251 #endif  \r
2252 \r
2253         s4Byte                  result[4][8];   //last is final result\r
2254         u1Byte                  i, final_candidate, Indexforchannel;\r
2255     u1Byte          channelToIQK = 7;\r
2256         BOOLEAN                 bPathAOK, bPathBOK;\r
2257         s4Byte                  RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC, RegTmp = 0;\r
2258         BOOLEAN                 is12simular, is13simular, is23simular;  \r
2259         BOOLEAN                 bStartContTx = FALSE, bSingleTone = FALSE, bCarrierSuppression = FALSE;\r
2260         u4Byte                  IQK_BB_REG_92C[IQK_BB_REG_NUM] = {\r
2261                                         rOFDM0_XARxIQImbalance,         rOFDM0_XBRxIQImbalance, \r
2262                                         rOFDM0_ECCAThreshold,   rOFDM0_AGCRSSITable,\r
2263                                         rOFDM0_XATxIQImbalance,         rOFDM0_XBTxIQImbalance, \r
2264                                         rOFDM0_XCTxAFE,                         rOFDM0_XDTxAFE, \r
2265                                         rOFDM0_RxIQExtAnta};\r
2266         u4Byte          StartTime; \r
2267         s4Byte          ProgressingTime;\r
2268 \r
2269 #if (DM_ODM_SUPPORT_TYPE & (ODM_WIN|ODM_CE) )\r
2270         if (ODM_CheckPowerStatus(pAdapter) == FALSE)\r
2271                 return;\r
2272 #else\r
2273         prtl8192cd_priv priv = pDM_Odm->priv;\r
2274 \r
2275 #ifdef MP_TEST\r
2276         if(priv->pshare->rf_ft_var.mp_specific)\r
2277         {\r
2278                 if((OPMODE & WIFI_MP_CTX_PACKET) || (OPMODE & WIFI_MP_CTX_ST))\r
2279                         return;\r
2280         }\r
2281 #endif\r
2282 \r
2283         if(priv->pshare->IQK_88E_done)\r
2284                 bReCovery= 1;\r
2285         priv->pshare->IQK_88E_done = 1;\r
2286 \r
2287 #endif  \r
2288 \r
2289 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
2290         if(!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION))\r
2291         {\r
2292                 return;\r
2293         }\r
2294 #endif          \r
2295 \r
2296 #if MP_DRIVER == 1      \r
2297         if (*(pDM_Odm->mp_mode) == 1)\r
2298         {\r
2299                 bStartContTx = pMptCtx->bStartContTx;\r
2300                 bSingleTone = pMptCtx->bSingleTone;\r
2301                 bCarrierSuppression = pMptCtx->bCarrierSuppression;     \r
2302         }\r
2303 #endif\r
2304         \r
2305         // 20120213<Kordan> Turn on when continuous Tx to pass lab testing. (required by Edlu)\r
2306         if(bSingleTone || bCarrierSuppression)\r
2307                 return;\r
2308 \r
2309 #if DISABLE_BB_RF\r
2310         return;\r
2311 #endif\r
2312 \r
2313         if (pDM_Odm->RFCalibrateInfo.bIQKInProgress) \r
2314                 return;\r
2315 \r
2316         ODM_AcquireSpinLock(pDM_Odm, RT_IQK_SPINLOCK);\r
2317         pDM_Odm->RFCalibrateInfo.bIQKInProgress = TRUE;\r
2318         ODM_ReleaseSpinLock(pDM_Odm, RT_IQK_SPINLOCK);\r
2319 \r
2320 \r
2321 #if (DM_ODM_SUPPORT_TYPE & (ODM_CE|ODM_AP))\r
2322         if(bReCovery)\r
2323 #else//for ODM_WIN\r
2324         if(bReCovery && (!pAdapter->bInHctTest))  //YJ,add for PowerTest,120405\r
2325 #endif  \r
2326         {\r
2327                 ODM_RT_TRACE(pDM_Odm, ODM_COMP_INIT, ODM_DBG_LOUD, ("PHY_IQCalibrate_8188E: Return due to bReCovery!\n"));\r
2328 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
2329                 _PHY_ReloadADDARegisters(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9);\r
2330 #else\r
2331                 _PHY_ReloadADDARegisters(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9);\r
2332 #endif\r
2333                 return;         \r
2334         }\r
2335         StartTime = ODM_GetCurrentTime( pDM_Odm);\r
2336         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("IQK:Start!!!\n"));\r
2337 \r
2338 \r
2339 \r
2340         for(i = 0; i < 8; i++)\r
2341         {\r
2342                 result[0][i] = 0;\r
2343                 result[1][i] = 0;\r
2344                 result[2][i] = 0;\r
2345                 result[3][i] = 0;\r
2346         }\r
2347         final_candidate = 0xff;\r
2348         bPathAOK = FALSE;\r
2349         bPathBOK = FALSE;\r
2350         is12simular = FALSE;\r
2351         is23simular = FALSE;\r
2352         is13simular = FALSE;\r
2353 \r
2354 \r
2355         for (i=0; i<3; i++)\r
2356         {\r
2357 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
2358 \r
2359                 if(IS_92C_SERIAL( pHalData->VersionID))\r
2360                 {\r
2361                         phy_IQCalibrate_8188E(pAdapter, result, i, TRUE);\r
2362                 }\r
2363                 else\r
2364 #endif                  \r
2365                 {\r
2366                         // For 88C 1T1R\r
2367 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
2368                         phy_IQCalibrate_8188E(pAdapter, result, i, FALSE);\r
2369 #else\r
2370                         phy_IQCalibrate_8188E(pDM_Odm, result, i, FALSE);\r
2371 #endif                  \r
2372                 }\r
2373                 \r
2374                 if(i == 1)\r
2375                 {\r
2376 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
2377                         is12simular = phy_SimularityCompare_8188E(pAdapter, result, 0, 1);\r
2378 #else\r
2379                         is12simular = phy_SimularityCompare_8188E(pDM_Odm, result, 0, 1);\r
2380 #endif                  \r
2381                         if(is12simular)\r
2382                         {\r
2383                                 final_candidate = 0;\r
2384                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is12simular final_candidate is %x\n",final_candidate));                         \r
2385                                 break;\r
2386                         }\r
2387                 }\r
2388                 \r
2389                 if(i == 2)\r
2390                 {\r
2391 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
2392                         is13simular = phy_SimularityCompare_8188E(pAdapter, result, 0, 2);\r
2393 #else\r
2394                         is13simular = phy_SimularityCompare_8188E(pDM_Odm, result, 0, 2);\r
2395 #endif                  \r
2396                         if(is13simular)\r
2397                         {\r
2398                                 final_candidate = 0;                    \r
2399                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is13simular final_candidate is %x\n",final_candidate));\r
2400                                 \r
2401                                 break;\r
2402                         }\r
2403 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
2404                         is23simular = phy_SimularityCompare_8188E(pAdapter, result, 1, 2);\r
2405 #else\r
2406                         is23simular = phy_SimularityCompare_8188E(pDM_Odm, result, 1, 2);\r
2407 #endif                  \r
2408                         if(is23simular)\r
2409                         {\r
2410                                 final_candidate = 1;\r
2411                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: is23simular final_candidate is %x\n",final_candidate));                         \r
2412                         }\r
2413                         else\r
2414                         {\r
2415                                 for(i = 0; i < 8; i++)\r
2416                                         RegTmp += result[3][i];\r
2417 \r
2418                                 if(RegTmp != 0)\r
2419                                         final_candidate = 3;                    \r
2420                                 else\r
2421                                         final_candidate = 0xFF;\r
2422                         }\r
2423                 }\r
2424         }\r
2425 //      RT_TRACE(COMP_INIT,DBG_LOUD,("Release Mutex in IQCalibrate \n"));\r
2426 \r
2427         for (i=0; i<4; i++)\r
2428         {\r
2429                 RegE94 = result[i][0];\r
2430                 RegE9C = result[i][1];\r
2431                 RegEA4 = result[i][2];\r
2432                 RegEAC = result[i][3];\r
2433                 RegEB4 = result[i][4];\r
2434                 RegEBC = result[i][5];\r
2435                 RegEC4 = result[i][6];\r
2436                 RegECC = result[i][7];\r
2437                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("IQK: RegE94=%x RegE9C=%x RegEA4=%x RegEAC=%x RegEB4=%x RegEBC=%x RegEC4=%x RegECC=%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC));\r
2438         }\r
2439         \r
2440         if(final_candidate != 0xff)\r
2441         {\r
2442                 pDM_Odm->RFCalibrateInfo.RegE94 = RegE94 = result[final_candidate][0];\r
2443                 pDM_Odm->RFCalibrateInfo.RegE9C = RegE9C = result[final_candidate][1];\r
2444                 RegEA4 = result[final_candidate][2];\r
2445                 RegEAC = result[final_candidate][3];\r
2446                 pDM_Odm->RFCalibrateInfo.RegEB4 = RegEB4 = result[final_candidate][4];\r
2447                 pDM_Odm->RFCalibrateInfo.RegEBC = RegEBC = result[final_candidate][5];\r
2448                 RegEC4 = result[final_candidate][6];\r
2449                 RegECC = result[final_candidate][7];\r
2450                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("IQK: final_candidate is %x\n",final_candidate));\r
2451                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("IQK: RegE94=%x RegE9C=%x RegEA4=%x RegEAC=%x RegEB4=%x RegEBC=%x RegEC4=%x RegECC=%x\n ", RegE94, RegE9C, RegEA4, RegEAC, RegEB4, RegEBC, RegEC4, RegECC));\r
2452                 bPathAOK = bPathBOK = TRUE;\r
2453         }\r
2454         else\r
2455         {\r
2456                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("IQK: FAIL use default value\n"));\r
2457         \r
2458                 pDM_Odm->RFCalibrateInfo.RegE94 = pDM_Odm->RFCalibrateInfo.RegEB4 = 0x100;      //X default value\r
2459                 pDM_Odm->RFCalibrateInfo.RegE9C = pDM_Odm->RFCalibrateInfo.RegEBC = 0x0;                //Y default value\r
2460         }\r
2461         \r
2462         if((RegE94 != 0)/*&&(RegEA4 != 0)*/)\r
2463         {\r
2464 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
2465                 _PHY_PathAFillIQKMatrix(pAdapter, bPathAOK, result, final_candidate, (RegEA4 == 0));\r
2466 #else\r
2467                 _PHY_PathAFillIQKMatrix(pDM_Odm, bPathAOK, result, final_candidate, (RegEA4 == 0));\r
2468 #endif\r
2469         }\r
2470         \r
2471 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
2472         if (IS_92C_SERIAL(pHalData->VersionID))\r
2473         {\r
2474                 if((RegEB4 != 0)/*&&(RegEC4 != 0)*/)\r
2475                 {\r
2476                         _PHY_PathBFillIQKMatrix(pAdapter, bPathBOK, result, final_candidate, (RegEC4 == 0));\r
2477                 }\r
2478         }\r
2479 #endif\r
2480 \r
2481 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
2482     Indexforchannel = ODM_GetRightChnlPlaceforIQK(pHalData->CurrentChannel);\r
2483 #else\r
2484         Indexforchannel = 0;    \r
2485 #endif\r
2486 \r
2487 //To Fix BSOD when final_candidate is 0xff\r
2488 //by sherry 20120321\r
2489         if(final_candidate < 4)\r
2490         {\r
2491                 for(i = 0; i < IQK_Matrix_REG_NUM; i++)\r
2492                         pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[Indexforchannel].Value[0][i] = result[final_candidate][i];\r
2493                 pDM_Odm->RFCalibrateInfo.IQKMatrixRegSetting[Indexforchannel].bIQKDone = TRUE;          \r
2494         }\r
2495         //RT_DISP(FINIT, INIT_IQK, ("\nIQK OK Indexforchannel %d.\n", Indexforchannel));\r
2496         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("\nIQK OK Indexforchannel %d.\n", Indexforchannel));\r
2497 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
2498 \r
2499         _PHY_SaveADDARegisters(pAdapter, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, 9);\r
2500 #else\r
2501         _PHY_SaveADDARegisters(pDM_Odm, IQK_BB_REG_92C, pDM_Odm->RFCalibrateInfo.IQK_BB_backup_recover, IQK_BB_REG_NUM);\r
2502 #endif  \r
2503 \r
2504         ODM_AcquireSpinLock(pDM_Odm, RT_IQK_SPINLOCK);\r
2505         pDM_Odm->RFCalibrateInfo.bIQKInProgress = FALSE;\r
2506         ODM_ReleaseSpinLock(pDM_Odm, RT_IQK_SPINLOCK);\r
2507 \r
2508         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("IQK finished\n"));\r
2509         ProgressingTime = ODM_GetProgressingTime( pDM_Odm, StartTime);\r
2510         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("IQK ProgressingTime = %d\n", ProgressingTime));\r
2511 \r
2512 }\r
2513 \r
2514 \r
2515 VOID\r
2516 PHY_LCCalibrate_8188E(\r
2517         IN PDM_ODM_T            pDM_Odm\r
2518         )\r
2519 {\r
2520         BOOLEAN                 bStartContTx = FALSE, bSingleTone = FALSE, bCarrierSuppression = FALSE;\r
2521         u4Byte                  timeout = 2000, timecount = 0;\r
2522         u4Byte                  StartTime; \r
2523         s4Byte                  ProgressingTime;\r
2524 \r
2525 \r
2526         \r
2527 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
2528         PADAPTER        pAdapter = pDM_Odm->Adapter;\r
2529         //HAL_DATA_TYPE *pHalData = GET_HAL_DATA(pAdapter);     \r
2530 \r
2531         #if (MP_DRIVER == 1)\r
2532         #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)    \r
2533         PMPT_CONTEXT    pMptCtx = &(pAdapter->MptCtx);  \r
2534         #else// (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
2535         PMPT_CONTEXT    pMptCtx = &(pAdapter->mppriv.MptCtx);           \r
2536         #endif  \r
2537         #endif//(MP_DRIVER == 1)\r
2538 #endif  \r
2539 \r
2540 #if MP_DRIVER == 1      \r
2541         if (*(pDM_Odm->mp_mode) == 1)\r
2542         {\r
2543                 bStartContTx = pMptCtx->bStartContTx;\r
2544                 bSingleTone = pMptCtx->bSingleTone;\r
2545                 bCarrierSuppression = pMptCtx->bCarrierSuppression;     \r
2546         }\r
2547 #endif\r
2548 \r
2549 \r
2550 #if DISABLE_BB_RF\r
2551         return;\r
2552 #endif\r
2553 \r
2554 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
2555         if(!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION))\r
2556         {\r
2557                 return;\r
2558         }\r
2559 #endif  \r
2560         // 20120213<Kordan> Turn on when continuous Tx to pass lab testing. (required by Edlu)\r
2561         if(bSingleTone || bCarrierSuppression)\r
2562                 return;\r
2563 \r
2564         StartTime = ODM_GetCurrentTime( pDM_Odm);\r
2565         while(*(pDM_Odm->pbScanInProcess) && timecount < timeout)\r
2566         {\r
2567                 ODM_delay_ms(50);\r
2568                 timecount += 50;\r
2569         }       \r
2570         \r
2571         pDM_Odm->RFCalibrateInfo.bLCKInProgress = TRUE;\r
2572 \r
2573         //ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LCK:Start!!!interface %d currentband %x delay %d ms\n", pDM_Odm->interfaceIndex, pHalData->CurrentBandType92D, timecount));\r
2574         phy_LCCalibrate_8188E(pDM_Odm, FALSE);\r
2575 \r
2576         pDM_Odm->RFCalibrateInfo.bLCKInProgress = FALSE;\r
2577 \r
2578         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("LCK:Finish!!!interface %d\n", pDM_Odm->InterfaceIndex));\r
2579         ProgressingTime = ODM_GetProgressingTime( pDM_Odm, StartTime);\r
2580         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("LCK ProgressingTime = %d\n", ProgressingTime));\r
2581 }\r
2582 \r
2583 VOID\r
2584 PHY_APCalibrate_8188E(\r
2585 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)\r
2586         IN PDM_ODM_T            pDM_Odm,\r
2587 #else\r
2588         IN      PADAPTER        pAdapter,\r
2589 #endif\r
2590         IN      s1Byte          delta   \r
2591         )\r
2592 {\r
2593 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
2594         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);\r
2595         #if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
2596         PDM_ODM_T               pDM_Odm = &pHalData->odmpriv;\r
2597         #endif\r
2598         #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
2599         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;\r
2600         #endif\r
2601 #endif  \r
2602 #if DISABLE_BB_RF\r
2603         return;\r
2604 #endif\r
2605 \r
2606         return;\r
2607 #if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
2608         if(!(pDM_Odm->SupportAbility & ODM_RF_CALIBRATION))\r
2609         {\r
2610                 return;\r
2611         }\r
2612 #endif  \r
2613 \r
2614 #if FOR_BRAZIL_PRETEST != 1\r
2615         if(pDM_Odm->RFCalibrateInfo.bAPKdone)\r
2616 #endif          \r
2617                 return;\r
2618 \r
2619 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
2620         if(IS_92C_SERIAL( pHalData->VersionID)){\r
2621                 phy_APCalibrate_8188E(pAdapter, delta, TRUE);\r
2622         }\r
2623         else\r
2624 #endif\r
2625         {\r
2626                 // For 88C 1T1R\r
2627 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
2628                 phy_APCalibrate_8188E(pAdapter, delta, FALSE);\r
2629 #else\r
2630                 phy_APCalibrate_8188E(pDM_Odm, delta, FALSE);\r
2631 #endif\r
2632         }\r
2633 }\r
2634 VOID phy_SetRFPathSwitch_8188E(\r
2635 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)\r
2636         IN PDM_ODM_T            pDM_Odm,\r
2637 #else\r
2638         IN      PADAPTER        pAdapter,\r
2639 #endif\r
2640         IN      BOOLEAN         bMain,\r
2641         IN      BOOLEAN         is2T\r
2642         )\r
2643 {\r
2644 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
2645         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);\r
2646         #if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
2647         PDM_ODM_T               pDM_Odm = &pHalData->odmpriv;\r
2648         #elif (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
2649         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;\r
2650         #endif\r
2651 \r
2652         #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
2653         if(!pAdapter->bHWInitReady)     \r
2654         #elif  (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
2655         if(pAdapter->hw_init_completed == _FALSE)\r
2656         #endif\r
2657         {\r
2658                 u1Byte  u1bTmp;\r
2659                 u1bTmp = ODM_Read1Byte(pDM_Odm, REG_LEDCFG2) | BIT7;\r
2660                 ODM_Write1Byte(pDM_Odm, REG_LEDCFG2, u1bTmp);\r
2661                 //ODM_SetBBReg(pDM_Odm, REG_LEDCFG0, BIT23, 0x01);\r
2662                 ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFParameter, BIT13, 0x01);\r
2663         }\r
2664         \r
2665 #endif          \r
2666 \r
2667         if(is2T)        //92C\r
2668         {\r
2669                 if(bMain)\r
2670                         ODM_SetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6, 0x1); //92C_Path_A                    \r
2671                 else\r
2672                         ODM_SetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6, 0x2); //BT                                                    \r
2673         }\r
2674         else                    //88C\r
2675         {\r
2676         \r
2677                 // <20120504, Kordan> [8188E] We should make AntDiversity controlled by HW (0x870[9:8] = 0), \r
2678                 // otherwise the following action has no effect. (0x860[9:8] has the effect only if AntDiversity controlled by SW)\r
2679                 ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFInterfaceSW, BIT8|BIT9, 0x0);        \r
2680                 ODM_SetBBReg(pDM_Odm, 0x914, bMaskLWord, 0x0201);                                         // Set up the Ant mapping table\r
2681                 \r
2682                 if(bMain) \r
2683                 {\r
2684                         //ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, BIT8|BIT9, 0x2);                 // Tx Main (SW control)(The right antenna)\r
2685                         //4 [ Tx ]\r
2686                         ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, BIT14|BIT13|BIT12, 0x1);  // Tx Main (HW control)(The right antenna)\r
2687                         \r
2688                         //4 [ Rx ]\r
2689                         ODM_SetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5|BIT4|BIT3, 0x1); // AntDivType = TRDiv, right antenna       \r
2690                         if (pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV)\r
2691                                 ODM_SetBBReg(pDM_Odm, rConfig_ram64x16, BIT31, 0x1);                             // RxCG, Default is RxCG. AntDivType = 2RDiv, left antenna     \r
2692                         \r
2693                 }                       \r
2694                 else\r
2695                 {\r
2696                         //ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, BIT8|BIT9, 0x1);                 // Tx Aux (SW control)(The left antenna)                      \r
2697                         //4 [ Tx ]\r
2698                         ODM_SetBBReg(pDM_Odm, rFPGA0_XA_RFInterfaceOE, BIT14|BIT13|BIT12, 0x0);   // Tx Aux (HW control)(The left antenna)\r
2699                         \r
2700                         //4 [ Rx ]                      \r
2701                         ODM_SetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5|BIT4|BIT3, 0x0); // AntDivType = TRDiv, left antenna                \r
2702                         if (pDM_Odm->AntDivType == CGCS_RX_HW_ANTDIV)\r
2703                                 ODM_SetBBReg(pDM_Odm, rConfig_ram64x16, BIT31, 0x0);                             // RxCS, AntDivType = 2RDiv, right antenna     \r
2704                 }               \r
2705                 \r
2706         }       \r
2707 }\r
2708 VOID PHY_SetRFPathSwitch_8188E(\r
2709 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)\r
2710         IN PDM_ODM_T            pDM_Odm,\r
2711 #else\r
2712         IN      PADAPTER        pAdapter,\r
2713 #endif\r
2714         IN      BOOLEAN         bMain\r
2715         )\r
2716 {\r
2717 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
2718         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);\r
2719 #endif\r
2720 \r
2721 #if DISABLE_BB_RF\r
2722         return;\r
2723 #endif\r
2724 \r
2725 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
2726         if (IS_92C_SERIAL(pHalData->VersionID))\r
2727         {\r
2728                 phy_SetRFPathSwitch_8188E(pAdapter, bMain, TRUE);\r
2729         }\r
2730         else\r
2731 #endif          \r
2732         {\r
2733                 // For 88C 1T1R\r
2734 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
2735                 phy_SetRFPathSwitch_8188E(pAdapter, bMain, FALSE);\r
2736 #else\r
2737                 phy_SetRFPathSwitch_8188E(pDM_Odm, bMain, FALSE);\r
2738 #endif\r
2739         }\r
2740 }\r
2741 \r
2742 #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
2743 //digital predistortion\r
2744 VOID    \r
2745 phy_DigitalPredistortion(\r
2746 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
2747         IN      PADAPTER        pAdapter,\r
2748 #else\r
2749         IN PDM_ODM_T    pDM_Odm,\r
2750 #endif\r
2751         IN      BOOLEAN         is2T\r
2752         )\r
2753 {\r
2754 #if (RT_PLATFORM == PLATFORM_WINDOWS)\r
2755 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
2756         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);\r
2757         #if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
2758         PDM_ODM_T               pDM_Odm = &pHalData->odmpriv;\r
2759         #endif\r
2760         #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
2761         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;\r
2762         #endif\r
2763 #endif  \r
2764 \r
2765         u4Byte                  tmpReg, tmpReg2, index,  i;             \r
2766         u1Byte                  path, pathbound = PATH_NUM;\r
2767         u4Byte                  AFE_backup[IQK_ADDA_REG_NUM];\r
2768         u4Byte                  AFE_REG[IQK_ADDA_REG_NUM] = {   \r
2769                                                 rFPGA0_XCD_SwitchControl,       rBlue_Tooth,    \r
2770                                                 rRx_Wait_CCA,           rTx_CCK_RFON,\r
2771                                                 rTx_CCK_BBON,   rTx_OFDM_RFON,  \r
2772                                                 rTx_OFDM_BBON,  rTx_To_Rx,\r
2773                                                 rTx_To_Tx,              rRx_CCK,        \r
2774                                                 rRx_OFDM,               rRx_Wait_RIFS,\r
2775                                                 rRx_TO_Rx,              rStandby,       \r
2776                                                 rSleep,                         rPMPD_ANAEN };\r
2777 \r
2778         u4Byte                  BB_backup[DP_BB_REG_NUM];       \r
2779         u4Byte                  BB_REG[DP_BB_REG_NUM] = {\r
2780                                                 rOFDM0_TRxPathEnable, rFPGA0_RFMOD, \r
2781                                                 rOFDM0_TRMuxPar,        rFPGA0_XCD_RFInterfaceSW,\r
2782                                                 rFPGA0_XAB_RFInterfaceSW, rFPGA0_XA_RFInterfaceOE, \r
2783                                                 rFPGA0_XB_RFInterfaceOE};                                               \r
2784         u4Byte                  BB_settings[DP_BB_REG_NUM] = {\r
2785                                                 0x00a05430, 0x02040000, 0x000800e4, 0x22208000, \r
2786                                                 0x0, 0x0, 0x0}; \r
2787 \r
2788         u4Byte                  RF_backup[DP_PATH_NUM][DP_RF_REG_NUM];\r
2789         u4Byte                  RF_REG[DP_RF_REG_NUM] = {\r
2790                                                 RF_TXBIAS_A};\r
2791 \r
2792         u4Byte                  MAC_backup[IQK_MAC_REG_NUM];\r
2793         u4Byte                  MAC_REG[IQK_MAC_REG_NUM] = {\r
2794                                                 REG_TXPAUSE,            REG_BCN_CTRL,   \r
2795                                                 REG_BCN_CTRL_1, REG_GPIO_MUXCFG};\r
2796 \r
2797         u4Byte                  Tx_AGC[DP_DPK_NUM][DP_DPK_VALUE_NUM] = {\r
2798                                                 {0x1e1e1e1e, 0x03901e1e},\r
2799                                                 {0x18181818, 0x03901818},\r
2800                                                 {0x0e0e0e0e, 0x03900e0e}\r
2801                                         };\r
2802 \r
2803         u4Byte                  AFE_on_off[PATH_NUM] = {\r
2804                                         0x04db25a4, 0x0b1b25a4};        //path A on path B off / path A off path B on\r
2805 \r
2806         u1Byte                  RetryCount = 0;\r
2807 \r
2808 \r
2809         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("==>phy_DigitalPredistortion()\n"));\r
2810         \r
2811         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("phy_DigitalPredistortion for %s\n", (is2T ? "2T2R" : "1T1R")));\r
2812 \r
2813         //save BB default value\r
2814         for(index=0; index<DP_BB_REG_NUM; index++)\r
2815                 BB_backup[index] = ODM_GetBBReg(pDM_Odm, BB_REG[index], bMaskDWord);\r
2816 \r
2817         //save MAC default value\r
2818 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
2819         _PHY_SaveMACRegisters(pAdapter, BB_REG, MAC_backup);\r
2820 #else\r
2821         _PHY_SaveMACRegisters(pDM_Odm, BB_REG, MAC_backup);\r
2822 #endif  \r
2823 \r
2824         //save RF default value\r
2825         for(path=0; path<DP_PATH_NUM; path++)\r
2826         {\r
2827                 for(index=0; index<DP_RF_REG_NUM; index++)\r
2828 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
2829                         RF_backup[path][index] = PHY_QueryRFReg(pAdapter, path, RF_REG[index], bMaskDWord);     \r
2830 #else\r
2831                         RF_backup[path][index] = ODM_GetRFReg(pAdapter, path, RF_REG[index], bMaskDWord);       \r
2832 #endif  \r
2833         }       \r
2834         \r
2835         //save AFE default value\r
2836 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
2837         _PHY_SaveADDARegisters(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);\r
2838 #else\r
2839                 _PHY_SaveADDARegisters(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);\r
2840 #endif  \r
2841         \r
2842         //Path A/B AFE all on\r
2843         for(index = 0; index < IQK_ADDA_REG_NUM ; index++)\r
2844                 ODM_SetBBReg(pDM_Odm, AFE_REG[index], bMaskDWord, 0x6fdb25a4);\r
2845 \r
2846         //BB register setting\r
2847         for(index = 0; index < DP_BB_REG_NUM; index++)\r
2848         {\r
2849                 if(index < 4)\r
2850                         ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_settings[index]);\r
2851                 else if (index == 4)\r
2852                         ODM_SetBBReg(pDM_Odm,BB_REG[index], bMaskDWord, BB_backup[index]|BIT10|BIT26);                  \r
2853                 else\r
2854                         ODM_SetBBReg(pDM_Odm, BB_REG[index], BIT10, 0x00);                      \r
2855         }\r
2856 \r
2857         //MAC register setting\r
2858 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
2859         _PHY_MACSettingCalibration(pAdapter, MAC_REG, MAC_backup);\r
2860 #else\r
2861         _PHY_MACSettingCalibration(pDM_Odm, MAC_REG, MAC_backup);\r
2862 #endif  \r
2863 \r
2864         //PAGE-E IQC setting    \r
2865         ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_A, bMaskDWord, 0x01008c00);          \r
2866         ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_A, bMaskDWord, 0x01008c00);  \r
2867         ODM_SetBBReg(pDM_Odm, rTx_IQK_Tone_B, bMaskDWord, 0x01008c00);  \r
2868         ODM_SetBBReg(pDM_Odm, rRx_IQK_Tone_B, bMaskDWord, 0x01008c00);  \r
2869         \r
2870         //path_A DPK\r
2871         //Path B to standby mode\r
2872         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMaskDWord, 0x10000);\r
2873 \r
2874         // PA gain = 11 & PAD1 => tx_agc 1f ~11\r
2875         // PA gain = 11 & PAD2 => tx_agc 10~0e\r
2876         // PA gain = 01 => tx_agc 0b~0d\r
2877         // PA gain = 00 => tx_agc 0a~00\r
2878         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x40000000);      \r
2879         ODM_SetBBReg(pDM_Odm, 0xbc0, bMaskDWord, 0x0005361f);           \r
2880         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000);      \r
2881 \r
2882         //do inner loopback DPK 3 times \r
2883         for(i = 0; i < 3; i++)\r
2884         {\r
2885                 //PA gain = 11 & PAD2 => tx_agc = 0x0f/0x0c/0x07\r
2886                 for(index = 0; index < 3; index++)\r
2887                         ODM_SetBBReg(pDM_Odm, 0xe00+index*4, bMaskDWord, Tx_AGC[i][0]);                 \r
2888                 ODM_SetBBReg(pDM_Odm,0xe00+index*4, bMaskDWord, Tx_AGC[i][1]);                  \r
2889                 for(index = 0; index < 4; index++)\r
2890                         ODM_SetBBReg(pDM_Odm,0xe10+index*4, bMaskDWord, Tx_AGC[i][0]);                  \r
2891         \r
2892                 // PAGE_B for Path-A inner loopback DPK setting\r
2893                 ODM_SetBBReg(pDM_Odm,rPdp_AntA, bMaskDWord, 0x02097098);\r
2894                 ODM_SetBBReg(pDM_Odm,rPdp_AntA_4, bMaskDWord, 0xf76d9f84);\r
2895                 ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87);\r
2896                 ODM_SetBBReg(pDM_Odm,rConfig_AntA, bMaskDWord, 0x00880000);             \r
2897                 \r
2898                 //----send one shot signal----//\r
2899                 // Path A\r
2900                 ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x80047788);\r
2901                 ODM_delay_ms(1);\r
2902                 ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x00047788);\r
2903                 ODM_delay_ms(50);\r
2904         }\r
2905 \r
2906         //PA gain = 11 => tx_agc = 1a\r
2907         for(index = 0; index < 3; index++)              \r
2908                 ODM_SetBBReg(pDM_Odm,0xe00+index*4, bMaskDWord, 0x34343434);    \r
2909         ODM_SetBBReg(pDM_Odm,0xe08+index*4, bMaskDWord, 0x03903434);    \r
2910         for(index = 0; index < 4; index++)              \r
2911                 ODM_SetBBReg(pDM_Odm,0xe10+index*4, bMaskDWord, 0x34343434);    \r
2912 \r
2913         //====================================\r
2914         // PAGE_B for Path-A DPK setting\r
2915         //====================================\r
2916         // open inner loopback @ b00[19]:10 od 0xb00 0x01097018\r
2917         ODM_SetBBReg(pDM_Odm,rPdp_AntA, bMaskDWord, 0x02017098);\r
2918         ODM_SetBBReg(pDM_Odm,rPdp_AntA_4, bMaskDWord, 0xf76d9f84);\r
2919         ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87);\r
2920         ODM_SetBBReg(pDM_Odm,rConfig_AntA, bMaskDWord, 0x00880000);             \r
2921 \r
2922         //rf_lpbk_setup\r
2923         //1.rf 00:5205a, rf 0d:0e52c\r
2924         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x0c, bMaskDWord, 0x8992b);\r
2925         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x0d, bMaskDWord, 0x0e52c);        \r
2926         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, 0x00, bMaskDWord, 0x5205a );               \r
2927 \r
2928         //----send one shot signal----//\r
2929         // Path A\r
2930         ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x800477c0);\r
2931         ODM_delay_ms(1);\r
2932         ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntA, bMaskDWord, 0x000477c0);\r
2933         ODM_delay_ms(50);\r
2934 \r
2935         while(RetryCount < DP_RETRY_LIMIT && !pDM_Odm->RFCalibrateInfo.bDPPathAOK)\r
2936         {\r
2937                 //----read back measurement results----//\r
2938                 ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x0c297018);\r
2939                 tmpReg = ODM_GetBBReg(pDM_Odm, 0xbe0, bMaskDWord);\r
2940                 ODM_delay_ms(10);\r
2941                 ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x0c29701f);\r
2942                 tmpReg2 = ODM_GetBBReg(pDM_Odm, 0xbe8, bMaskDWord);\r
2943                 ODM_delay_ms(10);\r
2944 \r
2945                 tmpReg = (tmpReg & bMaskHWord) >> 16;\r
2946                 tmpReg2 = (tmpReg2 & bMaskHWord) >> 16;         \r
2947                 if(tmpReg < 0xf0 || tmpReg > 0x105 || tmpReg2 > 0xff )\r
2948                 {\r
2949                         ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x02017098);\r
2950                 \r
2951                         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x80000000);\r
2952                         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000);\r
2953                         ODM_delay_ms(1);\r
2954                         ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x800477c0);\r
2955                         ODM_delay_ms(1);                        \r
2956                         ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x000477c0);                       \r
2957                         ODM_delay_ms(50);                       \r
2958                         RetryCount++;                   \r
2959                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A DPK RetryCount %d 0xbe0[31:16] %x 0xbe8[31:16] %x\n", RetryCount, tmpReg, tmpReg2));                                                                          \r
2960                 }\r
2961                 else\r
2962                 {\r
2963                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A DPK Sucess\n"));              \r
2964                         pDM_Odm->RFCalibrateInfo.bDPPathAOK = TRUE;\r
2965                         break;\r
2966                 }               \r
2967         }\r
2968         RetryCount = 0;\r
2969         \r
2970         //DPP path A\r
2971         if(pDM_Odm->RFCalibrateInfo.bDPPathAOK)\r
2972         {       \r
2973                 // DP settings\r
2974                 ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x01017098);\r
2975                 ODM_SetBBReg(pDM_Odm, rPdp_AntA_4, bMaskDWord, 0x776d9f84);\r
2976                 ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntA, bMaskDWord, 0x0004ab87);\r
2977                 ODM_SetBBReg(pDM_Odm, rConfig_AntA, bMaskDWord, 0x00880000);\r
2978                 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x40000000);\r
2979 \r
2980                 for(i=rPdp_AntA; i<=0xb3c; i+=4)\r
2981                 {\r
2982                         ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x40004000);       \r
2983                         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path A ofsset = 0x%x\n", i));                \r
2984                 }\r
2985                 \r
2986                 //pwsf\r
2987                 ODM_SetBBReg(pDM_Odm, 0xb40, bMaskDWord, 0x40404040);   \r
2988                 ODM_SetBBReg(pDM_Odm, 0xb44, bMaskDWord, 0x28324040);                   \r
2989                 ODM_SetBBReg(pDM_Odm, 0xb48, bMaskDWord, 0x10141920);                                   \r
2990 \r
2991                 for(i=0xb4c; i<=0xb5c; i+=4)\r
2992                 {\r
2993                         ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x0c0c0c0c);       \r
2994                 }               \r
2995 \r
2996                 //TX_AGC boundary\r
2997                 ODM_SetBBReg(pDM_Odm, 0xbc0, bMaskDWord, 0x0005361f);   \r
2998                 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000);                                      \r
2999         }\r
3000         else\r
3001         {\r
3002                 ODM_SetBBReg(pDM_Odm, rPdp_AntA, bMaskDWord, 0x00000000);       \r
3003                 ODM_SetBBReg(pDM_Odm, rPdp_AntA_4, bMaskDWord, 0x00000000);                     \r
3004         }\r
3005 \r
3006         //DPK path B\r
3007         if(is2T)\r
3008         {\r
3009                 //Path A to standby mode\r
3010                 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_AC, bMaskDWord, 0x10000);\r
3011                 \r
3012                 // LUTs => tx_agc\r
3013                 // PA gain = 11 & PAD1, => tx_agc 1f ~11\r
3014                 // PA gain = 11 & PAD2, => tx_agc 10 ~0e\r
3015                 // PA gain = 01 => tx_agc 0b ~0d\r
3016                 // PA gain = 00 => tx_agc 0a ~00\r
3017                 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x40000000);      \r
3018                 ODM_SetBBReg(pDM_Odm, 0xbc4, bMaskDWord, 0x0005361f);           \r
3019                 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000);      \r
3020 \r
3021                 //do inner loopback DPK 3 times \r
3022                 for(i = 0; i < 3; i++)\r
3023                 {\r
3024                         //PA gain = 11 & PAD2 => tx_agc = 0x0f/0x0c/0x07\r
3025                         for(index = 0; index < 4; index++)\r
3026                                 ODM_SetBBReg(pDM_Odm, 0x830+index*4, bMaskDWord, Tx_AGC[i][0]);                 \r
3027                         for(index = 0; index < 2; index++)\r
3028                                 ODM_SetBBReg(pDM_Odm, 0x848+index*4, bMaskDWord, Tx_AGC[i][0]);                 \r
3029                         for(index = 0; index < 2; index++)\r
3030                                 ODM_SetBBReg(pDM_Odm, 0x868+index*4, bMaskDWord, Tx_AGC[i][0]);                 \r
3031                 \r
3032                         // PAGE_B for Path-A inner loopback DPK setting\r
3033                         ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02097098);\r
3034                         ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0xf76d9f84);\r
3035                         ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87);\r
3036                         ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000);            \r
3037                         \r
3038                         //----send one shot signal----//\r
3039                         // Path B\r
3040                         ODM_SetBBReg(pDM_Odm,rConfig_Pmpd_AntB, bMaskDWord, 0x80047788);\r
3041                         ODM_delay_ms(1);\r
3042                         ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x00047788);\r
3043                         ODM_delay_ms(50);\r
3044                 }\r
3045 \r
3046                 // PA gain = 11 => tx_agc = 1a  \r
3047                 for(index = 0; index < 4; index++)\r
3048                         ODM_SetBBReg(pDM_Odm, 0x830+index*4, bMaskDWord, 0x34343434);   \r
3049                 for(index = 0; index < 2; index++)\r
3050                         ODM_SetBBReg(pDM_Odm, 0x848+index*4, bMaskDWord, 0x34343434);   \r
3051                 for(index = 0; index < 2; index++)\r
3052                         ODM_SetBBReg(pDM_Odm, 0x868+index*4, bMaskDWord, 0x34343434);   \r
3053 \r
3054                 // PAGE_B for Path-B DPK setting\r
3055                 ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02017098);               \r
3056                 ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0xf76d9f84);             \r
3057                 ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87);               \r
3058                 ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000);            \r
3059 \r
3060                 // RF lpbk switches on\r
3061                 ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x0101000f);           \r
3062                 ODM_SetBBReg(pDM_Odm, 0x840, bMaskDWord, 0x01120103);           \r
3063 \r
3064                 //Path-B RF lpbk\r
3065                 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x0c, bMaskDWord, 0x8992b);\r
3066                 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, 0x0d, bMaskDWord, 0x0e52c);\r
3067                 ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_B, RF_AC, bMaskDWord, 0x5205a); \r
3068 \r
3069                 //----send one shot signal----//\r
3070                 ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x800477c0);               \r
3071                 ODM_delay_ms(1);        \r
3072                 ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x000477c0);               \r
3073                 ODM_delay_ms(50);\r
3074                 \r
3075                 while(RetryCount < DP_RETRY_LIMIT && !pDM_Odm->RFCalibrateInfo.bDPPathBOK)\r
3076                 {\r
3077                         //----read back measurement results----//\r
3078                         ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x0c297018);               \r
3079                         tmpReg = ODM_GetBBReg(pDM_Odm, 0xbf0, bMaskDWord);\r
3080                         ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x0c29701f);               \r
3081                         tmpReg2 = ODM_GetBBReg(pDM_Odm, 0xbf8, bMaskDWord);\r
3082                         \r
3083                         tmpReg = (tmpReg & bMaskHWord) >> 16;\r
3084                         tmpReg2 = (tmpReg2 & bMaskHWord) >> 16;\r
3085                         \r
3086                         if(tmpReg < 0xf0 || tmpReg > 0x105 || tmpReg2 > 0xff)\r
3087                         {\r
3088                                 ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x02017098);               \r
3089                         \r
3090                                 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x80000000);\r
3091                                 ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000);\r
3092                                 ODM_delay_ms(1);\r
3093                                 ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x800477c0);               \r
3094                                 ODM_delay_ms(1);        \r
3095                                 ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x000477c0);               \r
3096                                 ODM_delay_ms(50);                       \r
3097                                 RetryCount++;                   \r
3098                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD,  ("path B DPK RetryCount %d 0xbf0[31:16] %x, 0xbf8[31:16] %x\n", RetryCount , tmpReg, tmpReg2));                                                                                                               \r
3099                         }\r
3100                         else\r
3101                         {\r
3102                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B DPK Success\n"));                                             \r
3103                                 pDM_Odm->RFCalibrateInfo.bDPPathBOK = TRUE;\r
3104                                 break;\r
3105                         }                                               \r
3106                 }\r
3107         \r
3108                 //DPP path B\r
3109                 if(pDM_Odm->RFCalibrateInfo.bDPPathBOK)\r
3110                 {\r
3111                         // DP setting\r
3112                         // LUT by SRAM\r
3113                         ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x01017098);\r
3114                         ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0x776d9f84);\r
3115                         ODM_SetBBReg(pDM_Odm, rConfig_Pmpd_AntB, bMaskDWord, 0x0004ab87);\r
3116                         ODM_SetBBReg(pDM_Odm, rConfig_AntB, bMaskDWord, 0x00880000);\r
3117                         \r
3118                         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x40000000);\r
3119                         for(i=0xb60; i<=0xb9c; i+=4)\r
3120                         {\r
3121                                 ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x40004000);       \r
3122                                 ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("path B ofsset = 0x%x\n", i));\r
3123                         }\r
3124 \r
3125                         // PWSF\r
3126                         ODM_SetBBReg(pDM_Odm, 0xba0, bMaskDWord, 0x40404040);   \r
3127                         ODM_SetBBReg(pDM_Odm, 0xba4, bMaskDWord, 0x28324050);                   \r
3128                         ODM_SetBBReg(pDM_Odm, 0xba8, bMaskDWord, 0x0c141920);                                   \r
3129 \r
3130                         for(i=0xbac; i<=0xbbc; i+=4)\r
3131                         {\r
3132                                 ODM_SetBBReg(pDM_Odm, i, bMaskDWord, 0x0c0c0c0c);       \r
3133                         }               \r
3134                         \r
3135                         // tx_agc boundary\r
3136                         ODM_SetBBReg(pDM_Odm, 0xbc4, bMaskDWord, 0x0005361f);   \r
3137                         ODM_SetBBReg(pDM_Odm, rFPGA0_IQK, bMaskDWord, 0x00000000);                      \r
3138                         \r
3139                 }\r
3140                 else\r
3141                 {\r
3142                         ODM_SetBBReg(pDM_Odm, rPdp_AntB, bMaskDWord, 0x00000000);       \r
3143                         ODM_SetBBReg(pDM_Odm, rPdp_AntB_4, bMaskDWord, 0x00000000);                                     \r
3144                 }\r
3145         }\r
3146         \r
3147         //reload BB default value\r
3148         for(index=0; index<DP_BB_REG_NUM; index++)\r
3149                 ODM_SetBBReg(pDM_Odm, BB_REG[index], bMaskDWord, BB_backup[index]);\r
3150         \r
3151         //reload RF default value\r
3152         for(path = 0; path<DP_PATH_NUM; path++)\r
3153         {\r
3154                 for( i = 0 ; i < DP_RF_REG_NUM ; i++){\r
3155                         ODM_SetRFReg(pDM_Odm, path, RF_REG[i], bMaskDWord, RF_backup[path][i]);\r
3156                 }\r
3157         }\r
3158         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE1, bMaskDWord, 0x1000f);    //standby mode\r
3159         ODM_SetRFReg(pDM_Odm, ODM_RF_PATH_A, RF_MODE2, bMaskDWord, 0x20101);            //RF lpbk switches off\r
3160 \r
3161         //reload AFE default value\r
3162 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
3163         _PHY_ReloadADDARegisters(pAdapter, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);      \r
3164 \r
3165         //reload MAC default value      \r
3166         _PHY_ReloadMACRegisters(pAdapter, MAC_REG, MAC_backup);\r
3167 #else\r
3168         _PHY_ReloadADDARegisters(pDM_Odm, AFE_REG, AFE_backup, IQK_ADDA_REG_NUM);       \r
3169 \r
3170         //reload MAC default value      \r
3171         _PHY_ReloadMACRegisters(pDM_Odm, MAC_REG, MAC_backup);\r
3172 #endif          \r
3173 \r
3174         pDM_Odm->RFCalibrateInfo.bDPdone = TRUE;\r
3175         ODM_RT_TRACE(pDM_Odm,ODM_COMP_CALIBRATION, ODM_DBG_LOUD, ("<==phy_DigitalPredistortion()\n"));\r
3176 #endif          \r
3177 }\r
3178 \r
3179 VOID\r
3180 PHY_DigitalPredistortion_8188E(\r
3181 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
3182         IN      PADAPTER        pAdapter\r
3183 #else\r
3184         IN PDM_ODM_T    pDM_Odm\r
3185 #endif          \r
3186         )\r
3187 {\r
3188 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
3189         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);\r
3190         #if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
3191         PDM_ODM_T               pDM_Odm = &pHalData->odmpriv;\r
3192         #endif\r
3193         #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
3194         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;\r
3195         #endif\r
3196 #endif  \r
3197 #if DISABLE_BB_RF\r
3198         return;\r
3199 #endif\r
3200 \r
3201         return;\r
3202 \r
3203         if(pDM_Odm->RFCalibrateInfo.bDPdone)\r
3204                 return;\r
3205 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
3206 \r
3207         if(pDM_Odm->RFType == ODM_2T2R){\r
3208                 phy_DigitalPredistortion(pAdapter, TRUE);\r
3209         }\r
3210         else\r
3211 #endif          \r
3212         {\r
3213                 // For 88C 1T1R\r
3214                 phy_DigitalPredistortion(pAdapter, FALSE);\r
3215         }\r
3216 }\r
3217         \r
3218 \r
3219 \r
3220 //return value TRUE => Main; FALSE => Aux\r
3221 \r
3222 BOOLEAN phy_QueryRFPathSwitch_8188E(\r
3223 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)\r
3224         IN PDM_ODM_T            pDM_Odm,\r
3225 #else\r
3226         IN      PADAPTER        pAdapter,\r
3227 #endif\r
3228         IN      BOOLEAN         is2T\r
3229         )\r
3230 {\r
3231 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
3232         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);\r
3233         #if (DM_ODM_SUPPORT_TYPE == ODM_CE)\r
3234         PDM_ODM_T               pDM_Odm = &pHalData->odmpriv;\r
3235         #endif\r
3236         #if (DM_ODM_SUPPORT_TYPE == ODM_WIN)\r
3237         PDM_ODM_T               pDM_Odm = &pHalData->DM_OutSrc;\r
3238         #endif\r
3239 #endif  \r
3240         if(!pAdapter->bHWInitReady)\r
3241         {\r
3242                 u1Byte  u1bTmp;\r
3243                 u1bTmp = ODM_Read1Byte(pDM_Odm, REG_LEDCFG2) | BIT7;\r
3244                 ODM_Write1Byte(pDM_Odm, REG_LEDCFG2, u1bTmp);\r
3245                 //ODM_SetBBReg(pDM_Odm, REG_LEDCFG0, BIT23, 0x01);\r
3246                 ODM_SetBBReg(pDM_Odm, rFPGA0_XAB_RFParameter, BIT13, 0x01);\r
3247         }\r
3248 \r
3249         if(is2T)                //\r
3250         {\r
3251                 if(ODM_GetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5|BIT6) == 0x01)\r
3252                         return TRUE;\r
3253                 else \r
3254                         return FALSE;\r
3255         }\r
3256         else\r
3257         {\r
3258                 if((ODM_GetBBReg(pDM_Odm, rFPGA0_XB_RFInterfaceOE, BIT5|BIT4|BIT3) == 0x1))\r
3259                         return TRUE;\r
3260                 else \r
3261                         return FALSE;\r
3262         }\r
3263 }\r
3264 \r
3265 \r
3266 \r
3267 //return value TRUE => Main; FALSE => Aux\r
3268 BOOLEAN PHY_QueryRFPathSwitch_8188E(    \r
3269 #if (DM_ODM_SUPPORT_TYPE & ODM_AP)\r
3270         IN PDM_ODM_T            pDM_Odm\r
3271 #else\r
3272         IN      PADAPTER        pAdapter\r
3273 #endif\r
3274         )\r
3275 {\r
3276         HAL_DATA_TYPE   *pHalData = GET_HAL_DATA(pAdapter);\r
3277 \r
3278 #if DISABLE_BB_RF\r
3279         return TRUE;\r
3280 #endif\r
3281 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
3282 \r
3283         //if(IS_92C_SERIAL( pHalData->VersionID)){\r
3284         if(IS_2T2R( pHalData->VersionID)){\r
3285                 return phy_QueryRFPathSwitch_8188E(pAdapter, TRUE);\r
3286         }\r
3287         else\r
3288 #endif          \r
3289         {\r
3290                 // For 88C 1T1R\r
3291 #if !(DM_ODM_SUPPORT_TYPE & ODM_AP)\r
3292                 return phy_QueryRFPathSwitch_8188E(pAdapter, FALSE);\r
3293 #else\r
3294                 return phy_QueryRFPathSwitch_8188E(pDM_Odm, FALSE);\r
3295 #endif\r
3296         }\r
3297 }\r
3298 #endif\r
3299 \r