2 Copyright (C) 2004 - 2007 rt2x00 SourceForge Project
3 <http://rt2x00.serialmonkey.com>
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the
17 Free Software Foundation, Inc.,
18 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
23 Abstract: rt61pci device specific routines.
24 Supported chipsets: RT2561, RT2561s, RT2661.
28 * Set enviroment defines for rt2x00.h
30 #define DRV_NAME "rt61pci"
32 #include <linux/delay.h>
33 #include <linux/etherdevice.h>
34 #include <linux/init.h>
35 #include <linux/kernel.h>
36 #include <linux/module.h>
37 #include <linux/pci.h>
38 #include <linux/eeprom_93cx6.h>
41 #include "rt2x00pci.h"
46 * BBP and RF register require indirect register access,
47 * and use the CSR registers PHY_CSR3 and PHY_CSR4 to achieve this.
48 * These indirect registers work with busy bits,
49 * and we will try maximal REGISTER_BUSY_COUNT times to access
50 * the register while taking a REGISTER_BUSY_DELAY us delay
51 * between each attampt. When the busy bit is still set at that time,
52 * the access attempt is considered to have failed,
53 * and we will print an error.
55 static u32 rt61pci_bbp_check(const struct rt2x00_dev *rt2x00dev)
60 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
61 rt2x00pci_register_read(rt2x00dev, PHY_CSR3, ®);
62 if (!rt2x00_get_field32(reg, PHY_CSR3_BUSY))
64 udelay(REGISTER_BUSY_DELAY);
70 static void rt61pci_bbp_write(const struct rt2x00_dev *rt2x00dev,
71 const unsigned int word, const u8 value)
76 * Wait until the BBP becomes ready.
78 reg = rt61pci_bbp_check(rt2x00dev);
79 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
80 ERROR(rt2x00dev, "PHY_CSR3 register busy. Write failed.\n");
85 * Write the data into the BBP.
88 rt2x00_set_field32(®, PHY_CSR3_VALUE, value);
89 rt2x00_set_field32(®, PHY_CSR3_REGNUM, word);
90 rt2x00_set_field32(®, PHY_CSR3_BUSY, 1);
91 rt2x00_set_field32(®, PHY_CSR3_READ_CONTROL, 0);
93 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
96 static void rt61pci_bbp_read(const struct rt2x00_dev *rt2x00dev,
97 const unsigned int word, u8 *value)
102 * Wait until the BBP becomes ready.
104 reg = rt61pci_bbp_check(rt2x00dev);
105 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
106 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
111 * Write the request into the BBP.
114 rt2x00_set_field32(®, PHY_CSR3_REGNUM, word);
115 rt2x00_set_field32(®, PHY_CSR3_BUSY, 1);
116 rt2x00_set_field32(®, PHY_CSR3_READ_CONTROL, 1);
118 rt2x00pci_register_write(rt2x00dev, PHY_CSR3, reg);
121 * Wait until the BBP becomes ready.
123 reg = rt61pci_bbp_check(rt2x00dev);
124 if (rt2x00_get_field32(reg, PHY_CSR3_BUSY)) {
125 ERROR(rt2x00dev, "PHY_CSR3 register busy. Read failed.\n");
130 *value = rt2x00_get_field32(reg, PHY_CSR3_VALUE);
133 static void rt61pci_rf_write(const struct rt2x00_dev *rt2x00dev,
134 const unsigned int word, const u32 value)
142 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
143 rt2x00pci_register_read(rt2x00dev, PHY_CSR4, ®);
144 if (!rt2x00_get_field32(reg, PHY_CSR4_BUSY))
146 udelay(REGISTER_BUSY_DELAY);
149 ERROR(rt2x00dev, "PHY_CSR4 register busy. Write failed.\n");
154 rt2x00_set_field32(®, PHY_CSR4_VALUE, value);
155 rt2x00_set_field32(®, PHY_CSR4_NUMBER_OF_BITS, 21);
156 rt2x00_set_field32(®, PHY_CSR4_IF_SELECT, 0);
157 rt2x00_set_field32(®, PHY_CSR4_BUSY, 1);
159 rt2x00pci_register_write(rt2x00dev, PHY_CSR4, reg);
160 rt2x00_rf_write(rt2x00dev, word, value);
163 static void rt61pci_mcu_request(const struct rt2x00_dev *rt2x00dev,
164 const u8 command, const u8 token,
165 const u8 arg0, const u8 arg1)
169 rt2x00pci_register_read(rt2x00dev, H2M_MAILBOX_CSR, ®);
171 if (rt2x00_get_field32(reg, H2M_MAILBOX_CSR_OWNER)) {
172 ERROR(rt2x00dev, "mcu request error. "
173 "Request 0x%02x failed for token 0x%02x.\n",
178 rt2x00_set_field32(®, H2M_MAILBOX_CSR_OWNER, 1);
179 rt2x00_set_field32(®, H2M_MAILBOX_CSR_CMD_TOKEN, token);
180 rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG0, arg0);
181 rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG1, arg1);
182 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, reg);
184 rt2x00pci_register_read(rt2x00dev, HOST_CMD_CSR, ®);
185 rt2x00_set_field32(®, HOST_CMD_CSR_HOST_COMMAND, command);
186 rt2x00_set_field32(®, HOST_CMD_CSR_INTERRUPT_MCU, 1);
187 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, reg);
190 static void rt61pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
192 struct rt2x00_dev *rt2x00dev = eeprom->data;
195 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, ®);
197 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
198 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
199 eeprom->reg_data_clock =
200 !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
201 eeprom->reg_chip_select =
202 !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
205 static void rt61pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
207 struct rt2x00_dev *rt2x00dev = eeprom->data;
210 rt2x00_set_field32(®, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
211 rt2x00_set_field32(®, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
212 rt2x00_set_field32(®, E2PROM_CSR_DATA_CLOCK,
213 !!eeprom->reg_data_clock);
214 rt2x00_set_field32(®, E2PROM_CSR_CHIP_SELECT,
215 !!eeprom->reg_chip_select);
217 rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
220 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
221 #define CSR_OFFSET(__word) ( CSR_REG_BASE + ((__word) * sizeof(u32)) )
223 static void rt61pci_read_csr(const struct rt2x00_dev *rt2x00dev,
224 const unsigned int word, u32 *data)
226 rt2x00pci_register_read(rt2x00dev, CSR_OFFSET(word), data);
229 static void rt61pci_write_csr(const struct rt2x00_dev *rt2x00dev,
230 const unsigned int word, u32 data)
232 rt2x00pci_register_write(rt2x00dev, CSR_OFFSET(word), data);
235 static const struct rt2x00debug rt61pci_rt2x00debug = {
236 .owner = THIS_MODULE,
238 .read = rt61pci_read_csr,
239 .write = rt61pci_write_csr,
240 .word_size = sizeof(u32),
241 .word_count = CSR_REG_SIZE / sizeof(u32),
244 .read = rt2x00_eeprom_read,
245 .write = rt2x00_eeprom_write,
246 .word_size = sizeof(u16),
247 .word_count = EEPROM_SIZE / sizeof(u16),
250 .read = rt61pci_bbp_read,
251 .write = rt61pci_bbp_write,
252 .word_size = sizeof(u8),
253 .word_count = BBP_SIZE / sizeof(u8),
256 .read = rt2x00_rf_read,
257 .write = rt61pci_rf_write,
258 .word_size = sizeof(u32),
259 .word_count = RF_SIZE / sizeof(u32),
262 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
264 #ifdef CONFIG_RT61PCI_RFKILL
265 static int rt61pci_rfkill_poll(struct rt2x00_dev *rt2x00dev)
269 rt2x00pci_register_read(rt2x00dev, MAC_CSR13, ®);
270 return rt2x00_get_field32(reg, MAC_CSR13_BIT5);;
272 #endif /* CONFIG_RT2400PCI_RFKILL */
275 * Configuration handlers.
277 static void rt61pci_config_mac_addr(struct rt2x00_dev *rt2x00dev, u8 *addr)
282 memset(®, 0, sizeof(reg));
283 memcpy(®, addr, ETH_ALEN);
285 tmp = le32_to_cpu(reg[1]);
286 rt2x00_set_field32(&tmp, MAC_CSR3_UNICAST_TO_ME_MASK, 0xff);
287 reg[1] = cpu_to_le32(tmp);
290 * The MAC address is passed to us as an array of bytes,
291 * that array is little endian, so no need for byte ordering.
293 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR2, ®, sizeof(reg));
296 static void rt61pci_config_bssid(struct rt2x00_dev *rt2x00dev, u8 *bssid)
301 memset(®, 0, sizeof(reg));
302 memcpy(®, bssid, ETH_ALEN);
304 tmp = le32_to_cpu(reg[1]);
305 rt2x00_set_field32(&tmp, MAC_CSR5_BSS_ID_MASK, 3);
306 reg[1] = cpu_to_le32(tmp);
309 * The BSSID is passed to us as an array of bytes,
310 * that array is little endian, so no need for byte ordering.
312 rt2x00pci_register_multiwrite(rt2x00dev, MAC_CSR4, ®, sizeof(reg));
315 static void rt61pci_config_type(struct rt2x00_dev *rt2x00dev, const int type)
317 struct interface *intf = &rt2x00dev->interface;
321 * Clear current synchronisation setup.
322 * For the Beacon base registers we only need to clear
323 * the first byte since that byte contains the VALID and OWNER
324 * bits which (when set to 0) will invalidate the entire beacon.
326 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, 0);
327 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE0, 0);
328 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE1, 0);
329 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE2, 0);
330 rt2x00pci_register_write(rt2x00dev, HW_BEACON_BASE3, 0);
333 * Enable synchronisation.
335 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, ®);
336 rt2x00_set_field32(®, TXRX_CSR9_TSF_TICKING, 1);
337 rt2x00_set_field32(®, TXRX_CSR9_TBTT_ENABLE, 1);
338 rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 0);
339 if (is_interface_type(intf, IEEE80211_IF_TYPE_IBSS) ||
340 is_interface_type(intf, IEEE80211_IF_TYPE_AP))
341 rt2x00_set_field32(®, TXRX_CSR9_TSF_SYNC, 2);
342 else if (is_interface_type(intf, IEEE80211_IF_TYPE_STA))
343 rt2x00_set_field32(®, TXRX_CSR9_TSF_SYNC, 1);
345 rt2x00_set_field32(®, TXRX_CSR9_TSF_SYNC, 0);
346 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
349 static void rt61pci_config_rate(struct rt2x00_dev *rt2x00dev, const int rate)
351 struct ieee80211_conf *conf = &rt2x00dev->hw->conf;
356 if (DEVICE_GET_RATE_FIELD(rate, PREAMBLE))
357 preamble = SHORT_PREAMBLE;
362 * Extract the allowed ratemask from the device specific rate value,
363 * We need to set TXRX_CSR5 to the basic rate mask so we need to mask
364 * off the non-basic rates.
366 reg = DEVICE_GET_RATE_FIELD(rate, RATEMASK) & DEV_BASIC_RATEMASK;
368 rt2x00pci_register_write(rt2x00dev, TXRX_CSR5, reg);
370 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, ®);
371 value = ((conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME) ?
373 PLCP + preamble + get_duration(ACK_SIZE, 10);
374 rt2x00_set_field32(®, TXRX_CSR0_RX_ACK_TIMEOUT, value);
375 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
377 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, ®);
378 if (preamble == SHORT_PREAMBLE)
379 rt2x00_set_field32(®, TXRX_CSR4_AUTORESPOND_PREAMBLE, 1);
381 rt2x00_set_field32(®, TXRX_CSR4_AUTORESPOND_PREAMBLE, 0);
382 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
385 static void rt61pci_config_phymode(struct rt2x00_dev *rt2x00dev,
388 struct ieee80211_hw_mode *mode;
389 struct ieee80211_rate *rate;
391 if (phymode == MODE_IEEE80211A)
392 rt2x00dev->curr_hwmode = HWMODE_A;
393 else if (phymode == MODE_IEEE80211B)
394 rt2x00dev->curr_hwmode = HWMODE_B;
396 rt2x00dev->curr_hwmode = HWMODE_G;
398 mode = &rt2x00dev->hwmodes[rt2x00dev->curr_hwmode];
399 rate = &mode->rates[mode->num_rates - 1];
401 rt61pci_config_rate(rt2x00dev, rate->val2);
404 static void rt61pci_config_lock_channel(struct rt2x00_dev *rt2x00dev,
405 struct rf_channel *rf,
412 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER, TXPOWER_TO_DEV(txpower));
413 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
415 smart = !(rt2x00_rf(&rt2x00dev->chip, RF5225) ||
416 rt2x00_rf(&rt2x00dev->chip, RF2527));
418 rt61pci_bbp_read(rt2x00dev, 3, &r3);
419 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, smart);
420 rt61pci_bbp_write(rt2x00dev, 3, r3);
423 if (txpower > MAX_TXPOWER && txpower <= (MAX_TXPOWER + r94))
424 r94 += txpower - MAX_TXPOWER;
425 else if (txpower < MIN_TXPOWER && txpower >= (MIN_TXPOWER - r94))
427 rt61pci_bbp_write(rt2x00dev, 94, r94);
429 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
430 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
431 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
432 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
436 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
437 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
438 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
439 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
443 rt61pci_rf_write(rt2x00dev, 1, rf->rf1);
444 rt61pci_rf_write(rt2x00dev, 2, rf->rf2);
445 rt61pci_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
446 rt61pci_rf_write(rt2x00dev, 4, rf->rf4);
451 static void rt61pci_config_channel(struct rt2x00_dev *rt2x00dev,
452 const int index, const int channel,
455 struct rf_channel rf;
458 * Fill rf_reg structure.
460 memcpy(&rf, &rt2x00dev->spec.channels[index], sizeof(rf));
462 rt61pci_config_lock_channel(rt2x00dev, &rf, txpower);
465 static void rt61pci_config_txpower(struct rt2x00_dev *rt2x00dev,
468 struct rf_channel rf;
470 rt2x00_rf_read(rt2x00dev, 1, &rf.rf1);
471 rt2x00_rf_read(rt2x00dev, 2, &rf.rf2);
472 rt2x00_rf_read(rt2x00dev, 3, &rf.rf3);
473 rt2x00_rf_read(rt2x00dev, 4, &rf.rf4);
475 rt61pci_config_lock_channel(rt2x00dev, &rf, txpower);
478 static void rt61pci_config_antenna_5x(struct rt2x00_dev *rt2x00dev,
479 const int antenna_tx,
480 const int antenna_rx)
486 rt61pci_bbp_read(rt2x00dev, 3, &r3);
487 rt61pci_bbp_read(rt2x00dev, 4, &r4);
488 rt61pci_bbp_read(rt2x00dev, 77, &r77);
490 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE,
491 !rt2x00_rf(&rt2x00dev->chip, RF5225));
493 switch (antenna_rx) {
494 case ANTENNA_SW_DIVERSITY:
495 case ANTENNA_HW_DIVERSITY:
496 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
497 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
498 !!(rt2x00dev->curr_hwmode != HWMODE_A));
501 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
502 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
504 if (rt2x00dev->curr_hwmode == HWMODE_A)
505 rt2x00_set_field8(&r77, BBP_R77_PAIR, 0);
507 rt2x00_set_field8(&r77, BBP_R77_PAIR, 3);
510 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
511 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
513 if (rt2x00dev->curr_hwmode == HWMODE_A)
514 rt2x00_set_field8(&r77, BBP_R77_PAIR, 3);
516 rt2x00_set_field8(&r77, BBP_R77_PAIR, 0);
520 rt61pci_bbp_write(rt2x00dev, 77, r77);
521 rt61pci_bbp_write(rt2x00dev, 3, r3);
522 rt61pci_bbp_write(rt2x00dev, 4, r4);
525 static void rt61pci_config_antenna_2x(struct rt2x00_dev *rt2x00dev,
526 const int antenna_tx,
527 const int antenna_rx)
533 rt61pci_bbp_read(rt2x00dev, 3, &r3);
534 rt61pci_bbp_read(rt2x00dev, 4, &r4);
535 rt61pci_bbp_read(rt2x00dev, 77, &r77);
537 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE,
538 !rt2x00_rf(&rt2x00dev->chip, RF2527));
539 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END,
540 !test_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags));
542 switch (antenna_rx) {
543 case ANTENNA_SW_DIVERSITY:
544 case ANTENNA_HW_DIVERSITY:
545 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
548 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
549 rt2x00_set_field8(&r77, BBP_R77_PAIR, 3);
552 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
553 rt2x00_set_field8(&r77, BBP_R77_PAIR, 0);
557 rt61pci_bbp_write(rt2x00dev, 77, r77);
558 rt61pci_bbp_write(rt2x00dev, 3, r3);
559 rt61pci_bbp_write(rt2x00dev, 4, r4);
562 static void rt61pci_config_antenna_2529_rx(struct rt2x00_dev *rt2x00dev,
563 const int p1, const int p2)
567 rt2x00pci_register_read(rt2x00dev, MAC_CSR13, ®);
570 rt2x00_set_field32(®, MAC_CSR13_BIT4, !!p1);
571 rt2x00_set_field32(®, MAC_CSR13_BIT12, 0);
572 rt2x00pci_register_write(rt2x00dev, MAC_CSR13, reg);
575 rt2x00_set_field32(®, MAC_CSR13_BIT3, !p2);
576 rt2x00_set_field32(®, MAC_CSR13_BIT11, 0);
577 rt2x00pci_register_write(rt2x00dev, MAC_CSR13, reg);
581 static void rt61pci_config_antenna_2529(struct rt2x00_dev *rt2x00dev,
582 const int antenna_tx,
583 const int antenna_rx)
590 rt61pci_bbp_read(rt2x00dev, 3, &r3);
591 rt61pci_bbp_read(rt2x00dev, 4, &r4);
592 rt61pci_bbp_read(rt2x00dev, 77, &r77);
593 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
595 rt2x00_set_field8(&r3, BBP_R3_SMART_MODE, 0);
597 if (rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY) &&
598 rt2x00_get_field16(eeprom, EEPROM_NIC_TX_DIVERSITY)) {
599 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
600 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 1);
601 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 1);
602 } else if (rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY)) {
603 if (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_RX_FIXED) >= 2) {
604 rt2x00_set_field8(&r77, BBP_R77_PAIR, 3);
605 rt61pci_bbp_write(rt2x00dev, 77, r77);
607 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
608 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1);
609 } else if (!rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY) &&
610 rt2x00_get_field16(eeprom, EEPROM_NIC_TX_DIVERSITY)) {
611 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 2);
612 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
614 switch (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_RX_FIXED)) {
616 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 1);
619 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 0);
622 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 0);
625 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1);
628 } else if (!rt2x00_get_field16(eeprom, EEPROM_NIC_ENABLE_DIVERSITY) &&
629 !rt2x00_get_field16(eeprom, EEPROM_NIC_TX_DIVERSITY)) {
630 rt2x00_set_field8(&r4, BBP_R4_RX_ANTENNA, 1);
631 rt2x00_set_field8(&r4, BBP_R4_RX_FRAME_END, 0);
633 switch (rt2x00_get_field16(eeprom, EEPROM_NIC_TX_RX_FIXED)) {
635 rt2x00_set_field8(&r77, BBP_R77_PAIR, 0);
636 rt61pci_bbp_write(rt2x00dev, 77, r77);
637 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 1);
640 rt2x00_set_field8(&r77, BBP_R77_PAIR, 0);
641 rt61pci_bbp_write(rt2x00dev, 77, r77);
642 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 0);
645 rt2x00_set_field8(&r77, BBP_R77_PAIR, 3);
646 rt61pci_bbp_write(rt2x00dev, 77, r77);
647 rt61pci_config_antenna_2529_rx(rt2x00dev, 0, 0);
650 rt2x00_set_field8(&r77, BBP_R77_PAIR, 3);
651 rt61pci_bbp_write(rt2x00dev, 77, r77);
652 rt61pci_config_antenna_2529_rx(rt2x00dev, 1, 1);
657 rt61pci_bbp_write(rt2x00dev, 3, r3);
658 rt61pci_bbp_write(rt2x00dev, 4, r4);
664 * value[0] -> non-LNA
670 static const struct antenna_sel antenna_sel_a[] = {
671 { 96, { 0x58, 0x78 } },
672 { 104, { 0x38, 0x48 } },
673 { 75, { 0xfe, 0x80 } },
674 { 86, { 0xfe, 0x80 } },
675 { 88, { 0xfe, 0x80 } },
676 { 35, { 0x60, 0x60 } },
677 { 97, { 0x58, 0x58 } },
678 { 98, { 0x58, 0x58 } },
681 static const struct antenna_sel antenna_sel_bg[] = {
682 { 96, { 0x48, 0x68 } },
683 { 104, { 0x2c, 0x3c } },
684 { 75, { 0xfe, 0x80 } },
685 { 86, { 0xfe, 0x80 } },
686 { 88, { 0xfe, 0x80 } },
687 { 35, { 0x50, 0x50 } },
688 { 97, { 0x48, 0x48 } },
689 { 98, { 0x48, 0x48 } },
692 static void rt61pci_config_antenna(struct rt2x00_dev *rt2x00dev,
693 const int antenna_tx, const int antenna_rx)
695 const struct antenna_sel *sel;
700 rt2x00pci_register_read(rt2x00dev, PHY_CSR0, ®);
702 if (rt2x00dev->curr_hwmode == HWMODE_A) {
704 lna = test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
706 rt2x00_set_field32(®, PHY_CSR0_PA_PE_BG, 0);
707 rt2x00_set_field32(®, PHY_CSR0_PA_PE_A, 1);
709 sel = antenna_sel_bg;
710 lna = test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
712 rt2x00_set_field32(®, PHY_CSR0_PA_PE_BG, 1);
713 rt2x00_set_field32(®, PHY_CSR0_PA_PE_A, 0);
716 for (i = 0; i < ARRAY_SIZE(antenna_sel_a); i++)
717 rt61pci_bbp_write(rt2x00dev, sel[i].word, sel[i].value[lna]);
719 rt2x00pci_register_write(rt2x00dev, PHY_CSR0, reg);
721 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
722 rt2x00_rf(&rt2x00dev->chip, RF5325))
723 rt61pci_config_antenna_5x(rt2x00dev, antenna_tx, antenna_rx);
724 else if (rt2x00_rf(&rt2x00dev->chip, RF2527))
725 rt61pci_config_antenna_2x(rt2x00dev, antenna_tx, antenna_rx);
726 else if (rt2x00_rf(&rt2x00dev->chip, RF2529)) {
727 if (test_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags))
728 rt61pci_config_antenna_2x(rt2x00dev, antenna_tx,
731 rt61pci_config_antenna_2529(rt2x00dev, antenna_tx,
736 static void rt61pci_config_duration(struct rt2x00_dev *rt2x00dev,
737 const int short_slot_time,
738 const int beacon_int)
742 rt2x00pci_register_read(rt2x00dev, MAC_CSR9, ®);
743 rt2x00_set_field32(®, MAC_CSR9_SLOT_TIME,
744 short_slot_time ? SHORT_SLOT_TIME : SLOT_TIME);
745 rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
747 rt2x00pci_register_read(rt2x00dev, MAC_CSR8, ®);
748 rt2x00_set_field32(®, MAC_CSR8_SIFS, SIFS);
749 rt2x00_set_field32(®, MAC_CSR8_SIFS_AFTER_RX_OFDM, 3);
750 rt2x00_set_field32(®, MAC_CSR8_EIFS, EIFS);
751 rt2x00pci_register_write(rt2x00dev, MAC_CSR8, reg);
753 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, ®);
754 rt2x00_set_field32(®, TXRX_CSR0_TSF_OFFSET, IEEE80211_HEADER);
755 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
757 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, ®);
758 rt2x00_set_field32(®, TXRX_CSR4_AUTORESPOND_ENABLE, 1);
759 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
761 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, ®);
762 rt2x00_set_field32(®, TXRX_CSR9_BEACON_INTERVAL, beacon_int * 16);
763 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
766 static void rt61pci_config(struct rt2x00_dev *rt2x00dev,
767 const unsigned int flags,
768 struct ieee80211_conf *conf)
770 int short_slot_time = conf->flags & IEEE80211_CONF_SHORT_SLOT_TIME;
772 if (flags & CONFIG_UPDATE_PHYMODE)
773 rt61pci_config_phymode(rt2x00dev, conf->phymode);
774 if (flags & CONFIG_UPDATE_CHANNEL)
775 rt61pci_config_channel(rt2x00dev, conf->channel_val,
776 conf->channel, conf->power_level);
777 if ((flags & CONFIG_UPDATE_TXPOWER) && !(flags & CONFIG_UPDATE_CHANNEL))
778 rt61pci_config_txpower(rt2x00dev, conf->power_level);
779 if (flags & CONFIG_UPDATE_ANTENNA)
780 rt61pci_config_antenna(rt2x00dev, conf->antenna_sel_tx,
781 conf->antenna_sel_rx);
782 if (flags & (CONFIG_UPDATE_SLOT_TIME | CONFIG_UPDATE_BEACON_INT))
783 rt61pci_config_duration(rt2x00dev, short_slot_time,
790 static void rt61pci_enable_led(struct rt2x00_dev *rt2x00dev)
797 rt2x00pci_register_read(rt2x00dev, MAC_CSR14, ®);
798 rt2x00_set_field32(®, MAC_CSR14_ON_PERIOD, 70);
799 rt2x00_set_field32(®, MAC_CSR14_OFF_PERIOD, 30);
800 rt2x00pci_register_write(rt2x00dev, MAC_CSR14, reg);
802 led_reg = rt2x00dev->led_reg;
803 rt2x00_set_field16(&led_reg, MCU_LEDCS_RADIO_STATUS, 1);
804 if (rt2x00dev->rx_status.phymode == MODE_IEEE80211A)
805 rt2x00_set_field16(&led_reg, MCU_LEDCS_LINK_A_STATUS, 1);
807 rt2x00_set_field16(&led_reg, MCU_LEDCS_LINK_BG_STATUS, 1);
809 arg0 = led_reg & 0xff;
810 arg1 = (led_reg >> 8) & 0xff;
812 rt61pci_mcu_request(rt2x00dev, MCU_LED, 0xff, arg0, arg1);
815 static void rt61pci_disable_led(struct rt2x00_dev *rt2x00dev)
821 led_reg = rt2x00dev->led_reg;
822 rt2x00_set_field16(&led_reg, MCU_LEDCS_RADIO_STATUS, 0);
823 rt2x00_set_field16(&led_reg, MCU_LEDCS_LINK_BG_STATUS, 0);
824 rt2x00_set_field16(&led_reg, MCU_LEDCS_LINK_A_STATUS, 0);
826 arg0 = led_reg & 0xff;
827 arg1 = (led_reg >> 8) & 0xff;
829 rt61pci_mcu_request(rt2x00dev, MCU_LED, 0xff, arg0, arg1);
832 static void rt61pci_activity_led(struct rt2x00_dev *rt2x00dev, int rssi)
836 if (rt2x00dev->led_mode != LED_MODE_SIGNAL_STRENGTH)
840 * Led handling requires a positive value for the rssi,
841 * to do that correctly we need to add the correction.
843 rssi += rt2x00dev->rssi_offset;
858 rt61pci_mcu_request(rt2x00dev, MCU_LED_STRENGTH, 0xff, led, 0);
864 static void rt61pci_link_stats(struct rt2x00_dev *rt2x00dev)
869 * Update FCS error count from register.
871 rt2x00pci_register_read(rt2x00dev, STA_CSR0, ®);
872 rt2x00dev->link.rx_failed = rt2x00_get_field32(reg, STA_CSR0_FCS_ERROR);
875 * Update False CCA count from register.
877 rt2x00pci_register_read(rt2x00dev, STA_CSR1, ®);
878 rt2x00dev->link.false_cca =
879 rt2x00_get_field32(reg, STA_CSR1_FALSE_CCA_ERROR);
882 static void rt61pci_reset_tuner(struct rt2x00_dev *rt2x00dev)
884 rt61pci_bbp_write(rt2x00dev, 17, 0x20);
885 rt2x00dev->link.vgc_level = 0x20;
888 static void rt61pci_link_tuner(struct rt2x00_dev *rt2x00dev)
890 int rssi = rt2x00_get_link_rssi(&rt2x00dev->link);
896 * Update Led strength
898 rt61pci_activity_led(rt2x00dev, rssi);
900 rt61pci_bbp_read(rt2x00dev, 17, &r17);
903 * Determine r17 bounds.
905 if (rt2x00dev->rx_status.phymode == MODE_IEEE80211A) {
908 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags)) {
915 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags)) {
922 * Special big-R17 for very short distance
926 rt61pci_bbp_write(rt2x00dev, 17, 0x60);
931 * Special big-R17 for short distance
935 rt61pci_bbp_write(rt2x00dev, 17, up_bound);
940 * Special big-R17 for middle-short distance
944 if (r17 != low_bound)
945 rt61pci_bbp_write(rt2x00dev, 17, low_bound);
950 * Special mid-R17 for middle distance
954 if (r17 != low_bound)
955 rt61pci_bbp_write(rt2x00dev, 17, low_bound);
960 * Special case: Change up_bound based on the rssi.
961 * Lower up_bound when rssi is weaker then -74 dBm.
963 up_bound -= 2 * (-74 - rssi);
964 if (low_bound > up_bound)
965 up_bound = low_bound;
967 if (r17 > up_bound) {
968 rt61pci_bbp_write(rt2x00dev, 17, up_bound);
973 * r17 does not yet exceed upper limit, continue and base
974 * the r17 tuning on the false CCA count.
976 if (rt2x00dev->link.false_cca > 512 && r17 < up_bound) {
977 if (++r17 > up_bound)
979 rt61pci_bbp_write(rt2x00dev, 17, r17);
980 } else if (rt2x00dev->link.false_cca < 100 && r17 > low_bound) {
981 if (--r17 < low_bound)
983 rt61pci_bbp_write(rt2x00dev, 17, r17);
988 * Firmware name function.
990 static char *rt61pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
994 switch (rt2x00dev->chip.rt) {
996 fw_name = FIRMWARE_RT2561;
999 fw_name = FIRMWARE_RT2561s;
1002 fw_name = FIRMWARE_RT2661;
1013 * Initialization functions.
1015 static int rt61pci_load_firmware(struct rt2x00_dev *rt2x00dev, void *data,
1022 * Wait for stable hardware.
1024 for (i = 0; i < 100; i++) {
1025 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, ®);
1032 ERROR(rt2x00dev, "Unstable hardware.\n");
1037 * Prepare MCU and mailbox for firmware loading.
1040 rt2x00_set_field32(®, MCU_CNTL_CSR_RESET, 1);
1041 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1042 rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1043 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
1044 rt2x00pci_register_write(rt2x00dev, HOST_CMD_CSR, 0);
1047 * Write firmware to device.
1050 rt2x00_set_field32(®, MCU_CNTL_CSR_RESET, 1);
1051 rt2x00_set_field32(®, MCU_CNTL_CSR_SELECT_BANK, 1);
1052 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1054 rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
1057 rt2x00_set_field32(®, MCU_CNTL_CSR_SELECT_BANK, 0);
1058 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1060 rt2x00_set_field32(®, MCU_CNTL_CSR_RESET, 0);
1061 rt2x00pci_register_write(rt2x00dev, MCU_CNTL_CSR, reg);
1063 for (i = 0; i < 100; i++) {
1064 rt2x00pci_register_read(rt2x00dev, MCU_CNTL_CSR, ®);
1065 if (rt2x00_get_field32(reg, MCU_CNTL_CSR_READY))
1071 ERROR(rt2x00dev, "MCU Control register not ready.\n");
1076 * Reset MAC and BBP registers.
1079 rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 1);
1080 rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 1);
1081 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1083 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, ®);
1084 rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 0);
1085 rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 0);
1086 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1088 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, ®);
1089 rt2x00_set_field32(®, MAC_CSR1_HOST_READY, 1);
1090 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1095 static void rt61pci_init_rxring(struct rt2x00_dev *rt2x00dev)
1097 struct data_ring *ring = rt2x00dev->rx;
1098 struct data_desc *rxd;
1102 memset(ring->data_addr, 0x00, rt2x00_get_ring_size(ring));
1104 for (i = 0; i < ring->stats.limit; i++) {
1105 rxd = ring->entry[i].priv;
1107 rt2x00_desc_read(rxd, 5, &word);
1108 rt2x00_set_field32(&word, RXD_W5_BUFFER_PHYSICAL_ADDRESS,
1109 ring->entry[i].data_dma);
1110 rt2x00_desc_write(rxd, 5, word);
1112 rt2x00_desc_read(rxd, 0, &word);
1113 rt2x00_set_field32(&word, RXD_W0_OWNER_NIC, 1);
1114 rt2x00_desc_write(rxd, 0, word);
1117 rt2x00_ring_index_clear(rt2x00dev->rx);
1120 static void rt61pci_init_txring(struct rt2x00_dev *rt2x00dev, const int queue)
1122 struct data_ring *ring = rt2x00lib_get_ring(rt2x00dev, queue);
1123 struct data_desc *txd;
1127 memset(ring->data_addr, 0x00, rt2x00_get_ring_size(ring));
1129 for (i = 0; i < ring->stats.limit; i++) {
1130 txd = ring->entry[i].priv;
1132 rt2x00_desc_read(txd, 1, &word);
1133 rt2x00_set_field32(&word, TXD_W1_BUFFER_COUNT, 1);
1134 rt2x00_desc_write(txd, 1, word);
1136 rt2x00_desc_read(txd, 5, &word);
1137 rt2x00_set_field32(&word, TXD_W5_PID_TYPE, queue);
1138 rt2x00_set_field32(&word, TXD_W5_PID_SUBTYPE, i);
1139 rt2x00_desc_write(txd, 5, word);
1141 rt2x00_desc_read(txd, 6, &word);
1142 rt2x00_set_field32(&word, TXD_W6_BUFFER_PHYSICAL_ADDRESS,
1143 ring->entry[i].data_dma);
1144 rt2x00_desc_write(txd, 6, word);
1146 rt2x00_desc_read(txd, 0, &word);
1147 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1148 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 0);
1149 rt2x00_desc_write(txd, 0, word);
1152 rt2x00_ring_index_clear(ring);
1155 static int rt61pci_init_rings(struct rt2x00_dev *rt2x00dev)
1162 rt61pci_init_rxring(rt2x00dev);
1163 rt61pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA0);
1164 rt61pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA1);
1165 rt61pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA2);
1166 rt61pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA3);
1167 rt61pci_init_txring(rt2x00dev, IEEE80211_TX_QUEUE_DATA4);
1170 * Initialize registers.
1172 rt2x00pci_register_read(rt2x00dev, TX_RING_CSR0, ®);
1173 rt2x00_set_field32(®, TX_RING_CSR0_AC0_RING_SIZE,
1174 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].stats.limit);
1175 rt2x00_set_field32(®, TX_RING_CSR0_AC1_RING_SIZE,
1176 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].stats.limit);
1177 rt2x00_set_field32(®, TX_RING_CSR0_AC2_RING_SIZE,
1178 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA2].stats.limit);
1179 rt2x00_set_field32(®, TX_RING_CSR0_AC3_RING_SIZE,
1180 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA3].stats.limit);
1181 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR0, reg);
1183 rt2x00pci_register_read(rt2x00dev, TX_RING_CSR1, ®);
1184 rt2x00_set_field32(®, TX_RING_CSR1_MGMT_RING_SIZE,
1185 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA4].stats.limit);
1186 rt2x00_set_field32(®, TX_RING_CSR1_TXD_SIZE,
1187 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].desc_size /
1189 rt2x00pci_register_write(rt2x00dev, TX_RING_CSR1, reg);
1191 rt2x00pci_register_read(rt2x00dev, AC0_BASE_CSR, ®);
1192 rt2x00_set_field32(®, AC0_BASE_CSR_RING_REGISTER,
1193 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA0].data_dma);
1194 rt2x00pci_register_write(rt2x00dev, AC0_BASE_CSR, reg);
1196 rt2x00pci_register_read(rt2x00dev, AC1_BASE_CSR, ®);
1197 rt2x00_set_field32(®, AC1_BASE_CSR_RING_REGISTER,
1198 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA1].data_dma);
1199 rt2x00pci_register_write(rt2x00dev, AC1_BASE_CSR, reg);
1201 rt2x00pci_register_read(rt2x00dev, AC2_BASE_CSR, ®);
1202 rt2x00_set_field32(®, AC2_BASE_CSR_RING_REGISTER,
1203 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA2].data_dma);
1204 rt2x00pci_register_write(rt2x00dev, AC2_BASE_CSR, reg);
1206 rt2x00pci_register_read(rt2x00dev, AC3_BASE_CSR, ®);
1207 rt2x00_set_field32(®, AC3_BASE_CSR_RING_REGISTER,
1208 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA3].data_dma);
1209 rt2x00pci_register_write(rt2x00dev, AC3_BASE_CSR, reg);
1211 rt2x00pci_register_read(rt2x00dev, MGMT_BASE_CSR, ®);
1212 rt2x00_set_field32(®, MGMT_BASE_CSR_RING_REGISTER,
1213 rt2x00dev->tx[IEEE80211_TX_QUEUE_DATA4].data_dma);
1214 rt2x00pci_register_write(rt2x00dev, MGMT_BASE_CSR, reg);
1216 rt2x00pci_register_read(rt2x00dev, RX_RING_CSR, ®);
1217 rt2x00_set_field32(®, RX_RING_CSR_RING_SIZE,
1218 rt2x00dev->rx->stats.limit);
1219 rt2x00_set_field32(®, RX_RING_CSR_RXD_SIZE,
1220 rt2x00dev->rx->desc_size / 4);
1221 rt2x00_set_field32(®, RX_RING_CSR_RXD_WRITEBACK_SIZE, 4);
1222 rt2x00pci_register_write(rt2x00dev, RX_RING_CSR, reg);
1224 rt2x00pci_register_read(rt2x00dev, RX_BASE_CSR, ®);
1225 rt2x00_set_field32(®, RX_BASE_CSR_RING_REGISTER,
1226 rt2x00dev->rx->data_dma);
1227 rt2x00pci_register_write(rt2x00dev, RX_BASE_CSR, reg);
1229 rt2x00pci_register_read(rt2x00dev, TX_DMA_DST_CSR, ®);
1230 rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC0, 2);
1231 rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC1, 2);
1232 rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC2, 2);
1233 rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_AC3, 2);
1234 rt2x00_set_field32(®, TX_DMA_DST_CSR_DEST_MGMT, 0);
1235 rt2x00pci_register_write(rt2x00dev, TX_DMA_DST_CSR, reg);
1237 rt2x00pci_register_read(rt2x00dev, LOAD_TX_RING_CSR, ®);
1238 rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC0, 1);
1239 rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC1, 1);
1240 rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC2, 1);
1241 rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_AC3, 1);
1242 rt2x00_set_field32(®, LOAD_TX_RING_CSR_LOAD_TXD_MGMT, 1);
1243 rt2x00pci_register_write(rt2x00dev, LOAD_TX_RING_CSR, reg);
1245 rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, ®);
1246 rt2x00_set_field32(®, RX_CNTL_CSR_LOAD_RXD, 1);
1247 rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1252 static int rt61pci_init_registers(struct rt2x00_dev *rt2x00dev)
1256 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, ®);
1257 rt2x00_set_field32(®, TXRX_CSR0_AUTO_TX_SEQ, 1);
1258 rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX, 0);
1259 rt2x00_set_field32(®, TXRX_CSR0_TX_WITHOUT_WAITING, 0);
1260 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1262 rt2x00pci_register_read(rt2x00dev, TXRX_CSR1, ®);
1263 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID0, 47); /* CCK Signal */
1264 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID0_VALID, 1);
1265 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID1, 30); /* Rssi */
1266 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID1_VALID, 1);
1267 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID2, 42); /* OFDM Rate */
1268 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID2_VALID, 1);
1269 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID3, 30); /* Rssi */
1270 rt2x00_set_field32(®, TXRX_CSR1_BBP_ID3_VALID, 1);
1271 rt2x00pci_register_write(rt2x00dev, TXRX_CSR1, reg);
1274 * CCK TXD BBP registers
1276 rt2x00pci_register_read(rt2x00dev, TXRX_CSR2, ®);
1277 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID0, 13);
1278 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID0_VALID, 1);
1279 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID1, 12);
1280 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID1_VALID, 1);
1281 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID2, 11);
1282 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID2_VALID, 1);
1283 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID3, 10);
1284 rt2x00_set_field32(®, TXRX_CSR2_BBP_ID3_VALID, 1);
1285 rt2x00pci_register_write(rt2x00dev, TXRX_CSR2, reg);
1288 * OFDM TXD BBP registers
1290 rt2x00pci_register_read(rt2x00dev, TXRX_CSR3, ®);
1291 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID0, 7);
1292 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID0_VALID, 1);
1293 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID1, 6);
1294 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID1_VALID, 1);
1295 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID2, 5);
1296 rt2x00_set_field32(®, TXRX_CSR3_BBP_ID2_VALID, 1);
1297 rt2x00pci_register_write(rt2x00dev, TXRX_CSR3, reg);
1299 rt2x00pci_register_read(rt2x00dev, TXRX_CSR7, ®);
1300 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_6MBS, 59);
1301 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_9MBS, 53);
1302 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_12MBS, 49);
1303 rt2x00_set_field32(®, TXRX_CSR7_ACK_CTS_18MBS, 46);
1304 rt2x00pci_register_write(rt2x00dev, TXRX_CSR7, reg);
1306 rt2x00pci_register_read(rt2x00dev, TXRX_CSR8, ®);
1307 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_24MBS, 44);
1308 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_36MBS, 42);
1309 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_48MBS, 42);
1310 rt2x00_set_field32(®, TXRX_CSR8_ACK_CTS_54MBS, 42);
1311 rt2x00pci_register_write(rt2x00dev, TXRX_CSR8, reg);
1313 rt2x00pci_register_write(rt2x00dev, TXRX_CSR15, 0x0000000f);
1315 rt2x00pci_register_write(rt2x00dev, MAC_CSR6, 0x00000fff);
1317 rt2x00pci_register_read(rt2x00dev, MAC_CSR9, ®);
1318 rt2x00_set_field32(®, MAC_CSR9_CW_SELECT, 0);
1319 rt2x00pci_register_write(rt2x00dev, MAC_CSR9, reg);
1321 rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x0000071c);
1323 if (rt2x00dev->ops->lib->set_device_state(rt2x00dev, STATE_AWAKE))
1326 rt2x00pci_register_write(rt2x00dev, MAC_CSR13, 0x0000e000);
1329 * Invalidate all Shared Keys (SEC_CSR0),
1330 * and clear the Shared key Cipher algorithms (SEC_CSR1 & SEC_CSR5)
1332 rt2x00pci_register_write(rt2x00dev, SEC_CSR0, 0x00000000);
1333 rt2x00pci_register_write(rt2x00dev, SEC_CSR1, 0x00000000);
1334 rt2x00pci_register_write(rt2x00dev, SEC_CSR5, 0x00000000);
1336 rt2x00pci_register_write(rt2x00dev, PHY_CSR1, 0x000023b0);
1337 rt2x00pci_register_write(rt2x00dev, PHY_CSR5, 0x060a100c);
1338 rt2x00pci_register_write(rt2x00dev, PHY_CSR6, 0x00080606);
1339 rt2x00pci_register_write(rt2x00dev, PHY_CSR7, 0x00000a08);
1341 rt2x00pci_register_write(rt2x00dev, PCI_CFG_CSR, 0x28ca4404);
1343 rt2x00pci_register_write(rt2x00dev, TEST_MODE_CSR, 0x00000200);
1345 rt2x00pci_register_write(rt2x00dev, M2H_CMD_DONE_CSR, 0xffffffff);
1347 rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR0, ®);
1348 rt2x00_set_field32(®, AC_TXOP_CSR0_AC0_TX_OP, 0);
1349 rt2x00_set_field32(®, AC_TXOP_CSR0_AC1_TX_OP, 0);
1350 rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR0, reg);
1352 rt2x00pci_register_read(rt2x00dev, AC_TXOP_CSR1, ®);
1353 rt2x00_set_field32(®, AC_TXOP_CSR1_AC2_TX_OP, 192);
1354 rt2x00_set_field32(®, AC_TXOP_CSR1_AC3_TX_OP, 48);
1355 rt2x00pci_register_write(rt2x00dev, AC_TXOP_CSR1, reg);
1358 * We must clear the error counters.
1359 * These registers are cleared on read,
1360 * so we may pass a useless variable to store the value.
1362 rt2x00pci_register_read(rt2x00dev, STA_CSR0, ®);
1363 rt2x00pci_register_read(rt2x00dev, STA_CSR1, ®);
1364 rt2x00pci_register_read(rt2x00dev, STA_CSR2, ®);
1367 * Reset MAC and BBP registers.
1369 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, ®);
1370 rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 1);
1371 rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 1);
1372 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1374 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, ®);
1375 rt2x00_set_field32(®, MAC_CSR1_SOFT_RESET, 0);
1376 rt2x00_set_field32(®, MAC_CSR1_BBP_RESET, 0);
1377 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1379 rt2x00pci_register_read(rt2x00dev, MAC_CSR1, ®);
1380 rt2x00_set_field32(®, MAC_CSR1_HOST_READY, 1);
1381 rt2x00pci_register_write(rt2x00dev, MAC_CSR1, reg);
1386 static int rt61pci_init_bbp(struct rt2x00_dev *rt2x00dev)
1393 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1394 rt61pci_bbp_read(rt2x00dev, 0, &value);
1395 if ((value != 0xff) && (value != 0x00))
1396 goto continue_csr_init;
1397 NOTICE(rt2x00dev, "Waiting for BBP register.\n");
1398 udelay(REGISTER_BUSY_DELAY);
1401 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
1405 rt61pci_bbp_write(rt2x00dev, 3, 0x00);
1406 rt61pci_bbp_write(rt2x00dev, 15, 0x30);
1407 rt61pci_bbp_write(rt2x00dev, 21, 0xc8);
1408 rt61pci_bbp_write(rt2x00dev, 22, 0x38);
1409 rt61pci_bbp_write(rt2x00dev, 23, 0x06);
1410 rt61pci_bbp_write(rt2x00dev, 24, 0xfe);
1411 rt61pci_bbp_write(rt2x00dev, 25, 0x0a);
1412 rt61pci_bbp_write(rt2x00dev, 26, 0x0d);
1413 rt61pci_bbp_write(rt2x00dev, 34, 0x12);
1414 rt61pci_bbp_write(rt2x00dev, 37, 0x07);
1415 rt61pci_bbp_write(rt2x00dev, 39, 0xf8);
1416 rt61pci_bbp_write(rt2x00dev, 41, 0x60);
1417 rt61pci_bbp_write(rt2x00dev, 53, 0x10);
1418 rt61pci_bbp_write(rt2x00dev, 54, 0x18);
1419 rt61pci_bbp_write(rt2x00dev, 60, 0x10);
1420 rt61pci_bbp_write(rt2x00dev, 61, 0x04);
1421 rt61pci_bbp_write(rt2x00dev, 62, 0x04);
1422 rt61pci_bbp_write(rt2x00dev, 75, 0xfe);
1423 rt61pci_bbp_write(rt2x00dev, 86, 0xfe);
1424 rt61pci_bbp_write(rt2x00dev, 88, 0xfe);
1425 rt61pci_bbp_write(rt2x00dev, 90, 0x0f);
1426 rt61pci_bbp_write(rt2x00dev, 99, 0x00);
1427 rt61pci_bbp_write(rt2x00dev, 102, 0x16);
1428 rt61pci_bbp_write(rt2x00dev, 107, 0x04);
1430 DEBUG(rt2x00dev, "Start initialization from EEPROM...\n");
1431 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
1432 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
1434 if (eeprom != 0xffff && eeprom != 0x0000) {
1435 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
1436 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
1437 DEBUG(rt2x00dev, "BBP: 0x%02x, value: 0x%02x.\n",
1439 rt61pci_bbp_write(rt2x00dev, reg_id, value);
1442 DEBUG(rt2x00dev, "...End initialization from EEPROM.\n");
1448 * Device state switch handlers.
1450 static void rt61pci_toggle_rx(struct rt2x00_dev *rt2x00dev,
1451 enum dev_state state)
1455 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, ®);
1456 rt2x00_set_field32(®, TXRX_CSR0_DISABLE_RX,
1457 state == STATE_RADIO_RX_OFF);
1458 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
1461 static void rt61pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
1462 enum dev_state state)
1464 int mask = (state == STATE_RADIO_IRQ_OFF);
1468 * When interrupts are being enabled, the interrupt registers
1469 * should clear the register to assure a clean state.
1471 if (state == STATE_RADIO_IRQ_ON) {
1472 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, ®);
1473 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1475 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, ®);
1476 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg);
1480 * Only toggle the interrupts bits we are going to use.
1481 * Non-checked interrupt bits are disabled by default.
1483 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, ®);
1484 rt2x00_set_field32(®, INT_MASK_CSR_TXDONE, mask);
1485 rt2x00_set_field32(®, INT_MASK_CSR_RXDONE, mask);
1486 rt2x00_set_field32(®, INT_MASK_CSR_ENABLE_MITIGATION, mask);
1487 rt2x00_set_field32(®, INT_MASK_CSR_MITIGATION_PERIOD, 0xff);
1488 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
1490 rt2x00pci_register_read(rt2x00dev, MCU_INT_MASK_CSR, ®);
1491 rt2x00_set_field32(®, MCU_INT_MASK_CSR_0, mask);
1492 rt2x00_set_field32(®, MCU_INT_MASK_CSR_1, mask);
1493 rt2x00_set_field32(®, MCU_INT_MASK_CSR_2, mask);
1494 rt2x00_set_field32(®, MCU_INT_MASK_CSR_3, mask);
1495 rt2x00_set_field32(®, MCU_INT_MASK_CSR_4, mask);
1496 rt2x00_set_field32(®, MCU_INT_MASK_CSR_5, mask);
1497 rt2x00_set_field32(®, MCU_INT_MASK_CSR_6, mask);
1498 rt2x00_set_field32(®, MCU_INT_MASK_CSR_7, mask);
1499 rt2x00pci_register_write(rt2x00dev, MCU_INT_MASK_CSR, reg);
1502 static int rt61pci_enable_radio(struct rt2x00_dev *rt2x00dev)
1507 * Initialize all registers.
1509 if (rt61pci_init_rings(rt2x00dev) ||
1510 rt61pci_init_registers(rt2x00dev) ||
1511 rt61pci_init_bbp(rt2x00dev)) {
1512 ERROR(rt2x00dev, "Register initialization failed.\n");
1517 * Enable interrupts.
1519 rt61pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_ON);
1524 rt2x00pci_register_read(rt2x00dev, RX_CNTL_CSR, ®);
1525 rt2x00_set_field32(®, RX_CNTL_CSR_ENABLE_RX_DMA, 1);
1526 rt2x00pci_register_write(rt2x00dev, RX_CNTL_CSR, reg);
1531 rt61pci_enable_led(rt2x00dev);
1536 static void rt61pci_disable_radio(struct rt2x00_dev *rt2x00dev)
1543 rt61pci_disable_led(rt2x00dev);
1545 rt2x00pci_register_write(rt2x00dev, MAC_CSR10, 0x00001818);
1548 * Disable synchronisation.
1550 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, 0);
1555 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, ®);
1556 rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC0, 1);
1557 rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC1, 1);
1558 rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC2, 1);
1559 rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_AC3, 1);
1560 rt2x00_set_field32(®, TX_CNTL_CSR_ABORT_TX_MGMT, 1);
1561 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1564 * Disable interrupts.
1566 rt61pci_toggle_irq(rt2x00dev, STATE_RADIO_IRQ_OFF);
1569 static int rt61pci_set_state(struct rt2x00_dev *rt2x00dev, enum dev_state state)
1576 put_to_sleep = (state != STATE_AWAKE);
1578 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, ®);
1579 rt2x00_set_field32(®, MAC_CSR12_FORCE_WAKEUP, !put_to_sleep);
1580 rt2x00_set_field32(®, MAC_CSR12_PUT_TO_SLEEP, put_to_sleep);
1581 rt2x00pci_register_write(rt2x00dev, MAC_CSR12, reg);
1584 * Device is not guaranteed to be in the requested state yet.
1585 * We must wait until the register indicates that the
1586 * device has entered the correct state.
1588 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
1589 rt2x00pci_register_read(rt2x00dev, MAC_CSR12, ®);
1591 rt2x00_get_field32(reg, MAC_CSR12_BBP_CURRENT_STATE);
1592 if (current_state == !put_to_sleep)
1597 NOTICE(rt2x00dev, "Device failed to enter state %d, "
1598 "current device state %d.\n", !put_to_sleep, current_state);
1603 static int rt61pci_set_device_state(struct rt2x00_dev *rt2x00dev,
1604 enum dev_state state)
1609 case STATE_RADIO_ON:
1610 retval = rt61pci_enable_radio(rt2x00dev);
1612 case STATE_RADIO_OFF:
1613 rt61pci_disable_radio(rt2x00dev);
1615 case STATE_RADIO_RX_ON:
1616 case STATE_RADIO_RX_OFF:
1617 rt61pci_toggle_rx(rt2x00dev, state);
1619 case STATE_DEEP_SLEEP:
1623 retval = rt61pci_set_state(rt2x00dev, state);
1634 * TX descriptor initialization
1636 static void rt61pci_write_tx_desc(struct rt2x00_dev *rt2x00dev,
1637 struct data_desc *txd,
1638 struct txdata_entry_desc *desc,
1639 struct ieee80211_hdr *ieee80211hdr,
1640 unsigned int length,
1641 struct ieee80211_tx_control *control)
1646 * Start writing the descriptor words.
1648 rt2x00_desc_read(txd, 1, &word);
1649 rt2x00_set_field32(&word, TXD_W1_HOST_Q_ID, desc->queue);
1650 rt2x00_set_field32(&word, TXD_W1_AIFSN, desc->aifs);
1651 rt2x00_set_field32(&word, TXD_W1_CWMIN, desc->cw_min);
1652 rt2x00_set_field32(&word, TXD_W1_CWMAX, desc->cw_max);
1653 rt2x00_set_field32(&word, TXD_W1_IV_OFFSET, IEEE80211_HEADER);
1654 rt2x00_set_field32(&word, TXD_W1_HW_SEQUENCE, 1);
1655 rt2x00_desc_write(txd, 1, word);
1657 rt2x00_desc_read(txd, 2, &word);
1658 rt2x00_set_field32(&word, TXD_W2_PLCP_SIGNAL, desc->signal);
1659 rt2x00_set_field32(&word, TXD_W2_PLCP_SERVICE, desc->service);
1660 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_LOW, desc->length_low);
1661 rt2x00_set_field32(&word, TXD_W2_PLCP_LENGTH_HIGH, desc->length_high);
1662 rt2x00_desc_write(txd, 2, word);
1664 rt2x00_desc_read(txd, 5, &word);
1665 rt2x00_set_field32(&word, TXD_W5_TX_POWER,
1666 TXPOWER_TO_DEV(control->power_level));
1667 rt2x00_set_field32(&word, TXD_W5_WAITING_DMA_DONE_INT, 1);
1668 rt2x00_desc_write(txd, 5, word);
1670 rt2x00_desc_read(txd, 11, &word);
1671 rt2x00_set_field32(&word, TXD_W11_BUFFER_LENGTH0, length);
1672 rt2x00_desc_write(txd, 11, word);
1674 rt2x00_desc_read(txd, 0, &word);
1675 rt2x00_set_field32(&word, TXD_W0_OWNER_NIC, 1);
1676 rt2x00_set_field32(&word, TXD_W0_VALID, 1);
1677 rt2x00_set_field32(&word, TXD_W0_MORE_FRAG,
1678 test_bit(ENTRY_TXD_MORE_FRAG, &desc->flags));
1679 rt2x00_set_field32(&word, TXD_W0_ACK,
1680 !(control->flags & IEEE80211_TXCTL_NO_ACK));
1681 rt2x00_set_field32(&word, TXD_W0_TIMESTAMP,
1682 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &desc->flags));
1683 rt2x00_set_field32(&word, TXD_W0_OFDM,
1684 test_bit(ENTRY_TXD_OFDM_RATE, &desc->flags));
1685 rt2x00_set_field32(&word, TXD_W0_IFS, desc->ifs);
1686 rt2x00_set_field32(&word, TXD_W0_RETRY_MODE,
1688 IEEE80211_TXCTL_LONG_RETRY_LIMIT));
1689 rt2x00_set_field32(&word, TXD_W0_TKIP_MIC, 0);
1690 rt2x00_set_field32(&word, TXD_W0_DATABYTE_COUNT, length);
1691 rt2x00_set_field32(&word, TXD_W0_BURST,
1692 test_bit(ENTRY_TXD_BURST, &desc->flags));
1693 rt2x00_set_field32(&word, TXD_W0_CIPHER_ALG, CIPHER_NONE);
1694 rt2x00_desc_write(txd, 0, word);
1698 * TX data initialization
1700 static void rt61pci_kick_tx_queue(struct rt2x00_dev *rt2x00dev,
1705 if (queue == IEEE80211_TX_QUEUE_BEACON) {
1707 * For Wi-Fi faily generated beacons between participating
1708 * stations. Set TBTT phase adaptive adjustment step to 8us.
1710 rt2x00pci_register_write(rt2x00dev, TXRX_CSR10, 0x00001008);
1712 rt2x00pci_register_read(rt2x00dev, TXRX_CSR9, ®);
1713 if (!rt2x00_get_field32(reg, TXRX_CSR9_BEACON_GEN)) {
1714 rt2x00_set_field32(®, TXRX_CSR9_BEACON_GEN, 1);
1715 rt2x00pci_register_write(rt2x00dev, TXRX_CSR9, reg);
1720 rt2x00pci_register_read(rt2x00dev, TX_CNTL_CSR, ®);
1721 if (queue == IEEE80211_TX_QUEUE_DATA0)
1722 rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC0, 1);
1723 else if (queue == IEEE80211_TX_QUEUE_DATA1)
1724 rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC1, 1);
1725 else if (queue == IEEE80211_TX_QUEUE_DATA2)
1726 rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC2, 1);
1727 else if (queue == IEEE80211_TX_QUEUE_DATA3)
1728 rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_AC3, 1);
1729 else if (queue == IEEE80211_TX_QUEUE_DATA4)
1730 rt2x00_set_field32(®, TX_CNTL_CSR_KICK_TX_MGMT, 1);
1731 rt2x00pci_register_write(rt2x00dev, TX_CNTL_CSR, reg);
1735 * RX control handlers
1737 static int rt61pci_agc_to_rssi(struct rt2x00_dev *rt2x00dev, int rxd_w1)
1743 lna = rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_LNA);
1758 if (rt2x00dev->rx_status.phymode == MODE_IEEE80211A) {
1759 if (test_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags))
1762 if (lna == 3 || lna == 2)
1765 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &eeprom);
1766 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_A_1);
1768 if (test_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags))
1771 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &eeprom);
1772 offset -= rt2x00_get_field16(eeprom, EEPROM_RSSI_OFFSET_BG_1);
1775 return rt2x00_get_field32(rxd_w1, RXD_W1_RSSI_AGC) * 2 - offset;
1778 static void rt61pci_fill_rxdone(struct data_entry *entry,
1779 struct rxdata_entry_desc *desc)
1781 struct data_desc *rxd = entry->priv;
1785 rt2x00_desc_read(rxd, 0, &word0);
1786 rt2x00_desc_read(rxd, 1, &word1);
1789 if (rt2x00_get_field32(word0, RXD_W0_CRC_ERROR))
1790 desc->flags |= RX_FLAG_FAILED_FCS_CRC;
1793 * Obtain the status about this packet.
1795 desc->signal = rt2x00_get_field32(word1, RXD_W1_SIGNAL);
1796 desc->rssi = rt61pci_agc_to_rssi(entry->ring->rt2x00dev, word1);
1797 desc->ofdm = rt2x00_get_field32(word0, RXD_W0_OFDM);
1798 desc->size = rt2x00_get_field32(word0, RXD_W0_DATABYTE_COUNT);
1804 * Interrupt functions.
1806 static void rt61pci_txdone(struct rt2x00_dev *rt2x00dev)
1808 struct data_ring *ring;
1809 struct data_entry *entry;
1810 struct data_desc *txd;
1820 * During each loop we will compare the freshly read
1821 * STA_CSR4 register value with the value read from
1822 * the previous loop. If the 2 values are equal then
1823 * we should stop processing because the chance it
1824 * quite big that the device has been unplugged and
1825 * we risk going into an endless loop.
1830 rt2x00pci_register_read(rt2x00dev, STA_CSR4, ®);
1831 if (!rt2x00_get_field32(reg, STA_CSR4_VALID))
1839 * Skip this entry when it contains an invalid
1840 * ring identication number.
1842 type = rt2x00_get_field32(reg, STA_CSR4_PID_TYPE);
1843 ring = rt2x00lib_get_ring(rt2x00dev, type);
1844 if (unlikely(!ring))
1848 * Skip this entry when it contains an invalid
1851 index = rt2x00_get_field32(reg, STA_CSR4_PID_SUBTYPE);
1852 if (unlikely(index >= ring->stats.limit))
1855 entry = &ring->entry[index];
1857 rt2x00_desc_read(txd, 0, &word);
1859 if (rt2x00_get_field32(word, TXD_W0_OWNER_NIC) ||
1860 !rt2x00_get_field32(word, TXD_W0_VALID))
1864 * Obtain the status about this packet.
1866 tx_status = rt2x00_get_field32(reg, STA_CSR4_TX_RESULT);
1867 retry = rt2x00_get_field32(reg, STA_CSR4_RETRY_COUNT);
1869 rt2x00lib_txdone(entry, tx_status, retry);
1872 * Make this entry available for reuse.
1875 rt2x00_set_field32(&word, TXD_W0_VALID, 0);
1876 rt2x00_desc_write(txd, 0, word);
1877 rt2x00_ring_index_done_inc(entry->ring);
1880 * If the data ring was full before the txdone handler
1881 * we must make sure the packet queue in the mac80211 stack
1882 * is reenabled when the txdone handler has finished.
1884 if (!rt2x00_ring_full(ring))
1885 ieee80211_wake_queue(rt2x00dev->hw,
1886 entry->tx_status.control.queue);
1890 static irqreturn_t rt61pci_interrupt(int irq, void *dev_instance)
1892 struct rt2x00_dev *rt2x00dev = dev_instance;
1897 * Get the interrupt sources & saved to local variable.
1898 * Write register value back to clear pending interrupts.
1900 rt2x00pci_register_read(rt2x00dev, MCU_INT_SOURCE_CSR, ®_mcu);
1901 rt2x00pci_register_write(rt2x00dev, MCU_INT_SOURCE_CSR, reg_mcu);
1903 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, ®);
1904 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
1906 if (!reg && !reg_mcu)
1909 if (!test_bit(DEVICE_ENABLED_RADIO, &rt2x00dev->flags))
1913 * Handle interrupts, walk through all bits
1914 * and run the tasks, the bits are checked in order of
1919 * 1 - Rx ring done interrupt.
1921 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RXDONE))
1922 rt2x00pci_rxdone(rt2x00dev);
1925 * 2 - Tx ring done interrupt.
1927 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TXDONE))
1928 rt61pci_txdone(rt2x00dev);
1931 * 3 - Handle MCU command done.
1934 rt2x00pci_register_write(rt2x00dev,
1935 M2H_CMD_DONE_CSR, 0xffffffff);
1941 * Device probe functions.
1943 static int rt61pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
1945 struct eeprom_93cx6 eeprom;
1951 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, ®);
1953 eeprom.data = rt2x00dev;
1954 eeprom.register_read = rt61pci_eepromregister_read;
1955 eeprom.register_write = rt61pci_eepromregister_write;
1956 eeprom.width = rt2x00_get_field32(reg, E2PROM_CSR_TYPE_93C46) ?
1957 PCI_EEPROM_WIDTH_93C46 : PCI_EEPROM_WIDTH_93C66;
1958 eeprom.reg_data_in = 0;
1959 eeprom.reg_data_out = 0;
1960 eeprom.reg_data_clock = 0;
1961 eeprom.reg_chip_select = 0;
1963 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
1964 EEPROM_SIZE / sizeof(u16));
1967 * Start validation of the data that has been read.
1969 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
1970 if (!is_valid_ether_addr(mac)) {
1971 DECLARE_MAC_BUF(macbuf);
1973 random_ether_addr(mac);
1974 EEPROM(rt2x00dev, "MAC: %s\n", print_mac(macbuf, mac));
1977 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &word);
1978 if (word == 0xffff) {
1979 rt2x00_set_field16(&word, EEPROM_ANTENNA_NUM, 2);
1980 rt2x00_set_field16(&word, EEPROM_ANTENNA_TX_DEFAULT, 2);
1981 rt2x00_set_field16(&word, EEPROM_ANTENNA_RX_DEFAULT, 2);
1982 rt2x00_set_field16(&word, EEPROM_ANTENNA_FRAME_TYPE, 0);
1983 rt2x00_set_field16(&word, EEPROM_ANTENNA_DYN_TXAGC, 0);
1984 rt2x00_set_field16(&word, EEPROM_ANTENNA_HARDWARE_RADIO, 0);
1985 rt2x00_set_field16(&word, EEPROM_ANTENNA_RF_TYPE, RF5225);
1986 rt2x00_eeprom_write(rt2x00dev, EEPROM_ANTENNA, word);
1987 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
1990 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &word);
1991 if (word == 0xffff) {
1992 rt2x00_set_field16(&word, EEPROM_NIC_ENABLE_DIVERSITY, 0);
1993 rt2x00_set_field16(&word, EEPROM_NIC_TX_DIVERSITY, 0);
1994 rt2x00_set_field16(&word, EEPROM_NIC_TX_RX_FIXED, 0);
1995 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_BG, 0);
1996 rt2x00_set_field16(&word, EEPROM_NIC_CARDBUS_ACCEL, 0);
1997 rt2x00_set_field16(&word, EEPROM_NIC_EXTERNAL_LNA_A, 0);
1998 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC, word);
1999 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
2002 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &word);
2003 if (word == 0xffff) {
2004 rt2x00_set_field16(&word, EEPROM_LED_LED_MODE,
2006 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED, word);
2007 EEPROM(rt2x00dev, "Led: 0x%04x\n", word);
2010 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
2011 if (word == 0xffff) {
2012 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
2013 rt2x00_set_field16(&word, EEPROM_FREQ_SEQ, 0);
2014 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
2015 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
2018 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_BG, &word);
2019 if (word == 0xffff) {
2020 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
2021 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
2022 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
2023 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
2025 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_1);
2026 if (value < -10 || value > 10)
2027 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_1, 0);
2028 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_BG_2);
2029 if (value < -10 || value > 10)
2030 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_BG_2, 0);
2031 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_BG, word);
2034 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_OFFSET_A, &word);
2035 if (word == 0xffff) {
2036 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
2037 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
2038 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
2039 EEPROM(rt2x00dev, "RSSI OFFSET BG: 0x%04x\n", word);
2041 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_1);
2042 if (value < -10 || value > 10)
2043 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_1, 0);
2044 value = rt2x00_get_field16(word, EEPROM_RSSI_OFFSET_A_2);
2045 if (value < -10 || value > 10)
2046 rt2x00_set_field16(&word, EEPROM_RSSI_OFFSET_A_2, 0);
2047 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_OFFSET_A, word);
2053 static int rt61pci_init_eeprom(struct rt2x00_dev *rt2x00dev)
2061 * Read EEPROM word for configuration.
2063 rt2x00_eeprom_read(rt2x00dev, EEPROM_ANTENNA, &eeprom);
2066 * Identify RF chipset.
2067 * To determine the RT chip we have to read the
2068 * PCI header of the device.
2070 pci_read_config_word(rt2x00dev_pci(rt2x00dev),
2071 PCI_CONFIG_HEADER_DEVICE, &device);
2072 value = rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RF_TYPE);
2073 rt2x00pci_register_read(rt2x00dev, MAC_CSR0, ®);
2074 rt2x00_set_chip(rt2x00dev, device, value, reg);
2076 if (!rt2x00_rf(&rt2x00dev->chip, RF5225) &&
2077 !rt2x00_rf(&rt2x00dev->chip, RF5325) &&
2078 !rt2x00_rf(&rt2x00dev->chip, RF2527) &&
2079 !rt2x00_rf(&rt2x00dev->chip, RF2529)) {
2080 ERROR(rt2x00dev, "Invalid RF chipset detected.\n");
2085 * Identify default antenna configuration.
2087 rt2x00dev->hw->conf.antenna_sel_tx =
2088 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_TX_DEFAULT);
2089 rt2x00dev->hw->conf.antenna_sel_rx =
2090 rt2x00_get_field16(eeprom, EEPROM_ANTENNA_RX_DEFAULT);
2093 * Read the Frame type.
2095 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_FRAME_TYPE))
2096 __set_bit(CONFIG_FRAME_TYPE, &rt2x00dev->flags);
2099 * Determine number of antenna's.
2101 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_NUM) == 2)
2102 __set_bit(CONFIG_DOUBLE_ANTENNA, &rt2x00dev->flags);
2105 * Detect if this device has an hardware controlled radio.
2107 if (rt2x00_get_field16(eeprom, EEPROM_ANTENNA_HARDWARE_RADIO))
2108 __set_bit(CONFIG_SUPPORT_HW_BUTTON, &rt2x00dev->flags);
2111 * Read frequency offset and RF programming sequence.
2113 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
2114 if (rt2x00_get_field16(eeprom, EEPROM_FREQ_SEQ))
2115 __set_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags);
2117 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
2120 * Read external LNA informations.
2122 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC, &eeprom);
2124 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_A))
2125 __set_bit(CONFIG_EXTERNAL_LNA_A, &rt2x00dev->flags);
2126 if (rt2x00_get_field16(eeprom, EEPROM_NIC_EXTERNAL_LNA_BG))
2127 __set_bit(CONFIG_EXTERNAL_LNA_BG, &rt2x00dev->flags);
2130 * Store led settings, for correct led behaviour.
2131 * If the eeprom value is invalid,
2132 * switch to default led mode.
2134 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED, &eeprom);
2136 rt2x00dev->led_mode = rt2x00_get_field16(eeprom, EEPROM_LED_LED_MODE);
2138 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_LED_MODE,
2139 rt2x00dev->led_mode);
2140 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_0,
2141 rt2x00_get_field16(eeprom,
2142 EEPROM_LED_POLARITY_GPIO_0));
2143 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_1,
2144 rt2x00_get_field16(eeprom,
2145 EEPROM_LED_POLARITY_GPIO_1));
2146 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_2,
2147 rt2x00_get_field16(eeprom,
2148 EEPROM_LED_POLARITY_GPIO_2));
2149 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_3,
2150 rt2x00_get_field16(eeprom,
2151 EEPROM_LED_POLARITY_GPIO_3));
2152 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_GPIO_4,
2153 rt2x00_get_field16(eeprom,
2154 EEPROM_LED_POLARITY_GPIO_4));
2155 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_ACT,
2156 rt2x00_get_field16(eeprom, EEPROM_LED_POLARITY_ACT));
2157 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_READY_BG,
2158 rt2x00_get_field16(eeprom,
2159 EEPROM_LED_POLARITY_RDY_G));
2160 rt2x00_set_field16(&rt2x00dev->led_reg, MCU_LEDCS_POLARITY_READY_A,
2161 rt2x00_get_field16(eeprom,
2162 EEPROM_LED_POLARITY_RDY_A));
2168 * RF value list for RF5225 & RF5325
2169 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence disabled
2171 static const struct rf_channel rf_vals_noseq[] = {
2172 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2173 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2174 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2175 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2176 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2177 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2178 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2179 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2180 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2181 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2182 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2183 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2184 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2185 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2187 /* 802.11 UNI / HyperLan 2 */
2188 { 36, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa23 },
2189 { 40, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa03 },
2190 { 44, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa0b },
2191 { 48, 0x00002ccc, 0x000049aa, 0x0009be55, 0x000ffa13 },
2192 { 52, 0x00002ccc, 0x000049ae, 0x0009ae55, 0x000ffa1b },
2193 { 56, 0x00002ccc, 0x000049b2, 0x0009ae55, 0x000ffa23 },
2194 { 60, 0x00002ccc, 0x000049ba, 0x0009ae55, 0x000ffa03 },
2195 { 64, 0x00002ccc, 0x000049be, 0x0009ae55, 0x000ffa0b },
2197 /* 802.11 HyperLan 2 */
2198 { 100, 0x00002ccc, 0x00004a2a, 0x000bae55, 0x000ffa03 },
2199 { 104, 0x00002ccc, 0x00004a2e, 0x000bae55, 0x000ffa0b },
2200 { 108, 0x00002ccc, 0x00004a32, 0x000bae55, 0x000ffa13 },
2201 { 112, 0x00002ccc, 0x00004a36, 0x000bae55, 0x000ffa1b },
2202 { 116, 0x00002ccc, 0x00004a3a, 0x000bbe55, 0x000ffa23 },
2203 { 120, 0x00002ccc, 0x00004a82, 0x000bbe55, 0x000ffa03 },
2204 { 124, 0x00002ccc, 0x00004a86, 0x000bbe55, 0x000ffa0b },
2205 { 128, 0x00002ccc, 0x00004a8a, 0x000bbe55, 0x000ffa13 },
2206 { 132, 0x00002ccc, 0x00004a8e, 0x000bbe55, 0x000ffa1b },
2207 { 136, 0x00002ccc, 0x00004a92, 0x000bbe55, 0x000ffa23 },
2210 { 140, 0x00002ccc, 0x00004a9a, 0x000bbe55, 0x000ffa03 },
2211 { 149, 0x00002ccc, 0x00004aa2, 0x000bbe55, 0x000ffa1f },
2212 { 153, 0x00002ccc, 0x00004aa6, 0x000bbe55, 0x000ffa27 },
2213 { 157, 0x00002ccc, 0x00004aae, 0x000bbe55, 0x000ffa07 },
2214 { 161, 0x00002ccc, 0x00004ab2, 0x000bbe55, 0x000ffa0f },
2215 { 165, 0x00002ccc, 0x00004ab6, 0x000bbe55, 0x000ffa17 },
2217 /* MMAC(Japan)J52 ch 34,38,42,46 */
2218 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000ffa0b },
2219 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000ffa13 },
2220 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000ffa1b },
2221 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000ffa23 },
2225 * RF value list for RF5225 & RF5325
2226 * Supports: 2.4 GHz & 5.2 GHz, rf_sequence enabled
2228 static const struct rf_channel rf_vals_seq[] = {
2229 { 1, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa0b },
2230 { 2, 0x00002ccc, 0x00004786, 0x00068455, 0x000ffa1f },
2231 { 3, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa0b },
2232 { 4, 0x00002ccc, 0x0000478a, 0x00068455, 0x000ffa1f },
2233 { 5, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa0b },
2234 { 6, 0x00002ccc, 0x0000478e, 0x00068455, 0x000ffa1f },
2235 { 7, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa0b },
2236 { 8, 0x00002ccc, 0x00004792, 0x00068455, 0x000ffa1f },
2237 { 9, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa0b },
2238 { 10, 0x00002ccc, 0x00004796, 0x00068455, 0x000ffa1f },
2239 { 11, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa0b },
2240 { 12, 0x00002ccc, 0x0000479a, 0x00068455, 0x000ffa1f },
2241 { 13, 0x00002ccc, 0x0000479e, 0x00068455, 0x000ffa0b },
2242 { 14, 0x00002ccc, 0x000047a2, 0x00068455, 0x000ffa13 },
2244 /* 802.11 UNI / HyperLan 2 */
2245 { 36, 0x00002cd4, 0x0004481a, 0x00098455, 0x000c0a03 },
2246 { 40, 0x00002cd0, 0x00044682, 0x00098455, 0x000c0a03 },
2247 { 44, 0x00002cd0, 0x00044686, 0x00098455, 0x000c0a1b },
2248 { 48, 0x00002cd0, 0x0004468e, 0x00098655, 0x000c0a0b },
2249 { 52, 0x00002cd0, 0x00044692, 0x00098855, 0x000c0a23 },
2250 { 56, 0x00002cd0, 0x0004469a, 0x00098c55, 0x000c0a13 },
2251 { 60, 0x00002cd0, 0x000446a2, 0x00098e55, 0x000c0a03 },
2252 { 64, 0x00002cd0, 0x000446a6, 0x00099255, 0x000c0a1b },
2254 /* 802.11 HyperLan 2 */
2255 { 100, 0x00002cd4, 0x0004489a, 0x000b9855, 0x000c0a03 },
2256 { 104, 0x00002cd4, 0x000448a2, 0x000b9855, 0x000c0a03 },
2257 { 108, 0x00002cd4, 0x000448aa, 0x000b9855, 0x000c0a03 },
2258 { 112, 0x00002cd4, 0x000448b2, 0x000b9a55, 0x000c0a03 },
2259 { 116, 0x00002cd4, 0x000448ba, 0x000b9a55, 0x000c0a03 },
2260 { 120, 0x00002cd0, 0x00044702, 0x000b9a55, 0x000c0a03 },
2261 { 124, 0x00002cd0, 0x00044706, 0x000b9a55, 0x000c0a1b },
2262 { 128, 0x00002cd0, 0x0004470e, 0x000b9c55, 0x000c0a0b },
2263 { 132, 0x00002cd0, 0x00044712, 0x000b9c55, 0x000c0a23 },
2264 { 136, 0x00002cd0, 0x0004471a, 0x000b9e55, 0x000c0a13 },
2267 { 140, 0x00002cd0, 0x00044722, 0x000b9e55, 0x000c0a03 },
2268 { 149, 0x00002cd0, 0x0004472e, 0x000ba255, 0x000c0a1b },
2269 { 153, 0x00002cd0, 0x00044736, 0x000ba255, 0x000c0a0b },
2270 { 157, 0x00002cd4, 0x0004490a, 0x000ba255, 0x000c0a17 },
2271 { 161, 0x00002cd4, 0x00044912, 0x000ba255, 0x000c0a17 },
2272 { 165, 0x00002cd4, 0x0004491a, 0x000ba255, 0x000c0a17 },
2274 /* MMAC(Japan)J52 ch 34,38,42,46 */
2275 { 34, 0x00002ccc, 0x0000499a, 0x0009be55, 0x000c0a0b },
2276 { 38, 0x00002ccc, 0x0000499e, 0x0009be55, 0x000c0a13 },
2277 { 42, 0x00002ccc, 0x000049a2, 0x0009be55, 0x000c0a1b },
2278 { 46, 0x00002ccc, 0x000049a6, 0x0009be55, 0x000c0a23 },
2281 static void rt61pci_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
2283 struct hw_mode_spec *spec = &rt2x00dev->spec;
2288 * Initialize all hw fields.
2290 rt2x00dev->hw->flags =
2291 IEEE80211_HW_HOST_GEN_BEACON_TEMPLATE |
2292 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
2293 rt2x00dev->hw->extra_tx_headroom = 0;
2294 rt2x00dev->hw->max_signal = MAX_SIGNAL;
2295 rt2x00dev->hw->max_rssi = MAX_RX_SSI;
2296 rt2x00dev->hw->queues = 5;
2298 SET_IEEE80211_DEV(rt2x00dev->hw, &rt2x00dev_pci(rt2x00dev)->dev);
2299 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
2300 rt2x00_eeprom_addr(rt2x00dev,
2301 EEPROM_MAC_ADDR_0));
2304 * Convert tx_power array in eeprom.
2306 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_G_START);
2307 for (i = 0; i < 14; i++)
2308 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
2311 * Initialize hw_mode information.
2313 spec->num_modes = 2;
2314 spec->num_rates = 12;
2315 spec->tx_power_a = NULL;
2316 spec->tx_power_bg = txpower;
2317 spec->tx_power_default = DEFAULT_TXPOWER;
2319 if (!test_bit(CONFIG_RF_SEQUENCE, &rt2x00dev->flags)) {
2320 spec->num_channels = 14;
2321 spec->channels = rf_vals_noseq;
2323 spec->num_channels = 14;
2324 spec->channels = rf_vals_seq;
2327 if (rt2x00_rf(&rt2x00dev->chip, RF5225) ||
2328 rt2x00_rf(&rt2x00dev->chip, RF5325)) {
2329 spec->num_modes = 3;
2330 spec->num_channels = ARRAY_SIZE(rf_vals_seq);
2332 txpower = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A_START);
2333 for (i = 0; i < 14; i++)
2334 txpower[i] = TXPOWER_FROM_DEV(txpower[i]);
2336 spec->tx_power_a = txpower;
2340 static int rt61pci_probe_hw(struct rt2x00_dev *rt2x00dev)
2345 * Allocate eeprom data.
2347 retval = rt61pci_validate_eeprom(rt2x00dev);
2351 retval = rt61pci_init_eeprom(rt2x00dev);
2356 * Initialize hw specifications.
2358 rt61pci_probe_hw_mode(rt2x00dev);
2361 * This device requires firmware
2363 __set_bit(DRIVER_REQUIRE_FIRMWARE, &rt2x00dev->flags);
2366 * Set the rssi offset.
2368 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
2374 * IEEE80211 stack callback functions.
2376 static void rt61pci_configure_filter(struct ieee80211_hw *hw,
2377 unsigned int changed_flags,
2378 unsigned int *total_flags,
2380 struct dev_addr_list *mc_list)
2382 struct rt2x00_dev *rt2x00dev = hw->priv;
2383 struct interface *intf = &rt2x00dev->interface;
2387 * Mask off any flags we are going to ignore from
2388 * the total_flags field.
2399 * Apply some rules to the filters:
2400 * - Some filters imply different filters to be set.
2401 * - Some things we can't filter out at all.
2402 * - Some filters are set based on interface type.
2405 *total_flags |= FIF_ALLMULTI;
2406 if (changed_flags & FIF_OTHER_BSS ||
2407 changed_flags & FIF_PROMISC_IN_BSS)
2408 *total_flags |= FIF_PROMISC_IN_BSS | FIF_OTHER_BSS;
2409 if (is_interface_type(intf, IEEE80211_IF_TYPE_AP))
2410 *total_flags |= FIF_PROMISC_IN_BSS;
2413 * Check if there is any work left for us.
2415 if (intf->filter == *total_flags)
2417 intf->filter = *total_flags;
2420 * Start configuration steps.
2421 * Note that the version error will always be dropped
2422 * and broadcast frames will always be accepted since
2423 * there is no filter for it at this time.
2425 rt2x00pci_register_read(rt2x00dev, TXRX_CSR0, ®);
2426 rt2x00_set_field32(®, TXRX_CSR0_DROP_CRC,
2427 !(*total_flags & FIF_FCSFAIL));
2428 rt2x00_set_field32(®, TXRX_CSR0_DROP_PHYSICAL,
2429 !(*total_flags & FIF_PLCPFAIL));
2430 rt2x00_set_field32(®, TXRX_CSR0_DROP_CONTROL,
2431 !(*total_flags & FIF_CONTROL));
2432 rt2x00_set_field32(®, TXRX_CSR0_DROP_NOT_TO_ME,
2433 !(*total_flags & FIF_PROMISC_IN_BSS));
2434 rt2x00_set_field32(®, TXRX_CSR0_DROP_TO_DS,
2435 !(*total_flags & FIF_PROMISC_IN_BSS));
2436 rt2x00_set_field32(®, TXRX_CSR0_DROP_VERSION_ERROR, 1);
2437 rt2x00_set_field32(®, TXRX_CSR0_DROP_MULTICAST,
2438 !(*total_flags & FIF_ALLMULTI));
2439 rt2x00_set_field32(®, TXRX_CSR0_DROP_BORADCAST, 0);
2440 rt2x00_set_field32(®, TXRX_CSR0_DROP_ACK_CTS, 1);
2441 rt2x00pci_register_write(rt2x00dev, TXRX_CSR0, reg);
2444 static int rt61pci_set_retry_limit(struct ieee80211_hw *hw,
2445 u32 short_retry, u32 long_retry)
2447 struct rt2x00_dev *rt2x00dev = hw->priv;
2450 rt2x00pci_register_read(rt2x00dev, TXRX_CSR4, ®);
2451 rt2x00_set_field32(®, TXRX_CSR4_LONG_RETRY_LIMIT, long_retry);
2452 rt2x00_set_field32(®, TXRX_CSR4_SHORT_RETRY_LIMIT, short_retry);
2453 rt2x00pci_register_write(rt2x00dev, TXRX_CSR4, reg);
2458 static u64 rt61pci_get_tsf(struct ieee80211_hw *hw)
2460 struct rt2x00_dev *rt2x00dev = hw->priv;
2464 rt2x00pci_register_read(rt2x00dev, TXRX_CSR13, ®);
2465 tsf = (u64) rt2x00_get_field32(reg, TXRX_CSR13_HIGH_TSFTIMER) << 32;
2466 rt2x00pci_register_read(rt2x00dev, TXRX_CSR12, ®);
2467 tsf |= rt2x00_get_field32(reg, TXRX_CSR12_LOW_TSFTIMER);
2472 static void rt61pci_reset_tsf(struct ieee80211_hw *hw)
2474 struct rt2x00_dev *rt2x00dev = hw->priv;
2476 rt2x00pci_register_write(rt2x00dev, TXRX_CSR12, 0);
2477 rt2x00pci_register_write(rt2x00dev, TXRX_CSR13, 0);
2480 static int rt61pci_beacon_update(struct ieee80211_hw *hw, struct sk_buff *skb,
2481 struct ieee80211_tx_control *control)
2483 struct rt2x00_dev *rt2x00dev = hw->priv;
2486 * Just in case the ieee80211 doesn't set this,
2487 * but we need this queue set for the descriptor
2490 control->queue = IEEE80211_TX_QUEUE_BEACON;
2493 * We need to append the descriptor in front of the
2496 if (skb_headroom(skb) < TXD_DESC_SIZE) {
2497 if (pskb_expand_head(skb, TXD_DESC_SIZE, 0, GFP_ATOMIC)) {
2504 * First we create the beacon.
2506 skb_push(skb, TXD_DESC_SIZE);
2507 rt2x00lib_write_tx_desc(rt2x00dev, (struct data_desc *)skb->data,
2508 (struct ieee80211_hdr *)(skb->data +
2510 skb->len - TXD_DESC_SIZE, control);
2513 * Write entire beacon with descriptor to register,
2514 * and kick the beacon generator.
2516 rt2x00pci_register_multiwrite(rt2x00dev, HW_BEACON_BASE0, skb->data, skb->len);
2517 rt61pci_kick_tx_queue(rt2x00dev, IEEE80211_TX_QUEUE_BEACON);
2522 static const struct ieee80211_ops rt61pci_mac80211_ops = {
2524 .start = rt2x00mac_start,
2525 .stop = rt2x00mac_stop,
2526 .add_interface = rt2x00mac_add_interface,
2527 .remove_interface = rt2x00mac_remove_interface,
2528 .config = rt2x00mac_config,
2529 .config_interface = rt2x00mac_config_interface,
2530 .configure_filter = rt61pci_configure_filter,
2531 .get_stats = rt2x00mac_get_stats,
2532 .set_retry_limit = rt61pci_set_retry_limit,
2533 .conf_tx = rt2x00mac_conf_tx,
2534 .get_tx_stats = rt2x00mac_get_tx_stats,
2535 .get_tsf = rt61pci_get_tsf,
2536 .reset_tsf = rt61pci_reset_tsf,
2537 .beacon_update = rt61pci_beacon_update,
2540 static const struct rt2x00lib_ops rt61pci_rt2x00_ops = {
2541 .irq_handler = rt61pci_interrupt,
2542 .probe_hw = rt61pci_probe_hw,
2543 .get_firmware_name = rt61pci_get_firmware_name,
2544 .load_firmware = rt61pci_load_firmware,
2545 .initialize = rt2x00pci_initialize,
2546 .uninitialize = rt2x00pci_uninitialize,
2547 .set_device_state = rt61pci_set_device_state,
2548 #ifdef CONFIG_RT61PCI_RFKILL
2549 .rfkill_poll = rt61pci_rfkill_poll,
2550 #endif /* CONFIG_RT61PCI_RFKILL */
2551 .link_stats = rt61pci_link_stats,
2552 .reset_tuner = rt61pci_reset_tuner,
2553 .link_tuner = rt61pci_link_tuner,
2554 .write_tx_desc = rt61pci_write_tx_desc,
2555 .write_tx_data = rt2x00pci_write_tx_data,
2556 .kick_tx_queue = rt61pci_kick_tx_queue,
2557 .fill_rxdone = rt61pci_fill_rxdone,
2558 .config_mac_addr = rt61pci_config_mac_addr,
2559 .config_bssid = rt61pci_config_bssid,
2560 .config_type = rt61pci_config_type,
2561 .config = rt61pci_config,
2564 static const struct rt2x00_ops rt61pci_ops = {
2566 .rxd_size = RXD_DESC_SIZE,
2567 .txd_size = TXD_DESC_SIZE,
2568 .eeprom_size = EEPROM_SIZE,
2570 .lib = &rt61pci_rt2x00_ops,
2571 .hw = &rt61pci_mac80211_ops,
2572 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
2573 .debugfs = &rt61pci_rt2x00debug,
2574 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
2578 * RT61pci module information.
2580 static struct pci_device_id rt61pci_device_table[] = {
2582 { PCI_DEVICE(0x1814, 0x0301), PCI_DEVICE_DATA(&rt61pci_ops) },
2584 { PCI_DEVICE(0x1814, 0x0302), PCI_DEVICE_DATA(&rt61pci_ops) },
2586 { PCI_DEVICE(0x1814, 0x0401), PCI_DEVICE_DATA(&rt61pci_ops) },
2590 MODULE_AUTHOR(DRV_PROJECT);
2591 MODULE_VERSION(DRV_VERSION);
2592 MODULE_DESCRIPTION("Ralink RT61 PCI & PCMCIA Wireless LAN driver.");
2593 MODULE_SUPPORTED_DEVICE("Ralink RT2561, RT2561s & RT2661 "
2594 "PCI & PCMCIA chipset based cards");
2595 MODULE_DEVICE_TABLE(pci, rt61pci_device_table);
2596 MODULE_FIRMWARE(FIRMWARE_RT2561);
2597 MODULE_FIRMWARE(FIRMWARE_RT2561s);
2598 MODULE_FIRMWARE(FIRMWARE_RT2661);
2599 MODULE_LICENSE("GPL");
2601 static struct pci_driver rt61pci_driver = {
2603 .id_table = rt61pci_device_table,
2604 .probe = rt2x00pci_probe,
2605 .remove = __devexit_p(rt2x00pci_remove),
2606 .suspend = rt2x00pci_suspend,
2607 .resume = rt2x00pci_resume,
2610 static int __init rt61pci_init(void)
2612 return pci_register_driver(&rt61pci_driver);
2615 static void __exit rt61pci_exit(void)
2617 pci_unregister_driver(&rt61pci_driver);
2620 module_init(rt61pci_init);
2621 module_exit(rt61pci_exit);