2 Copyright (C) 2009 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
3 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
4 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
5 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
6 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
7 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
8 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
9 Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com>
10 <http://rt2x00.serialmonkey.com>
12 This program is free software; you can redistribute it and/or modify
13 it under the terms of the GNU General Public License as published by
14 the Free Software Foundation; either version 2 of the License, or
15 (at your option) any later version.
17 This program is distributed in the hope that it will be useful,
18 but WITHOUT ANY WARRANTY; without even the implied warranty of
19 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 GNU General Public License for more details.
22 You should have received a copy of the GNU General Public License
23 along with this program; if not, write to the
24 Free Software Foundation, Inc.,
25 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
30 Abstract: rt2800pci device specific routines.
31 Supported chipsets: RT2800E & RT2800ED.
34 #include <linux/delay.h>
35 #include <linux/etherdevice.h>
36 #include <linux/init.h>
37 #include <linux/kernel.h>
38 #include <linux/module.h>
39 #include <linux/pci.h>
40 #include <linux/platform_device.h>
41 #include <linux/eeprom_93cx6.h>
44 #include "rt2x00pci.h"
45 #include "rt2x00soc.h"
46 #include "rt2800lib.h"
48 #include "rt2800pci.h"
51 * Allow hardware encryption to be disabled.
53 static bool modparam_nohwcrypt = false;
54 module_param_named(nohwcrypt, modparam_nohwcrypt, bool, S_IRUGO);
55 MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption.");
57 static void rt2800pci_mcu_status(struct rt2x00_dev *rt2x00dev, const u8 token)
63 * SOC devices don't support MCU requests.
65 if (rt2x00_is_soc(rt2x00dev))
68 for (i = 0; i < 200; i++) {
69 rt2x00pci_register_read(rt2x00dev, H2M_MAILBOX_CID, ®);
71 if ((rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD0) == token) ||
72 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD1) == token) ||
73 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD2) == token) ||
74 (rt2x00_get_field32(reg, H2M_MAILBOX_CID_CMD3) == token))
77 udelay(REGISTER_BUSY_DELAY);
81 ERROR(rt2x00dev, "MCU request failed, no response from hardware\n");
83 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_STATUS, ~0);
84 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CID, ~0);
87 #if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
88 static void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
90 void __iomem *base_addr = ioremap(0x1F040000, EEPROM_SIZE);
92 memcpy_fromio(rt2x00dev->eeprom, base_addr, EEPROM_SIZE);
97 static inline void rt2800pci_read_eeprom_soc(struct rt2x00_dev *rt2x00dev)
100 #endif /* CONFIG_RALINK_RT288X || CONFIG_RALINK_RT305X */
103 static void rt2800pci_eepromregister_read(struct eeprom_93cx6 *eeprom)
105 struct rt2x00_dev *rt2x00dev = eeprom->data;
108 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, ®);
110 eeprom->reg_data_in = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_IN);
111 eeprom->reg_data_out = !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_OUT);
112 eeprom->reg_data_clock =
113 !!rt2x00_get_field32(reg, E2PROM_CSR_DATA_CLOCK);
114 eeprom->reg_chip_select =
115 !!rt2x00_get_field32(reg, E2PROM_CSR_CHIP_SELECT);
118 static void rt2800pci_eepromregister_write(struct eeprom_93cx6 *eeprom)
120 struct rt2x00_dev *rt2x00dev = eeprom->data;
123 rt2x00_set_field32(®, E2PROM_CSR_DATA_IN, !!eeprom->reg_data_in);
124 rt2x00_set_field32(®, E2PROM_CSR_DATA_OUT, !!eeprom->reg_data_out);
125 rt2x00_set_field32(®, E2PROM_CSR_DATA_CLOCK,
126 !!eeprom->reg_data_clock);
127 rt2x00_set_field32(®, E2PROM_CSR_CHIP_SELECT,
128 !!eeprom->reg_chip_select);
130 rt2x00pci_register_write(rt2x00dev, E2PROM_CSR, reg);
133 static void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
135 struct eeprom_93cx6 eeprom;
138 rt2x00pci_register_read(rt2x00dev, E2PROM_CSR, ®);
140 eeprom.data = rt2x00dev;
141 eeprom.register_read = rt2800pci_eepromregister_read;
142 eeprom.register_write = rt2800pci_eepromregister_write;
143 switch (rt2x00_get_field32(reg, E2PROM_CSR_TYPE))
146 eeprom.width = PCI_EEPROM_WIDTH_93C46;
149 eeprom.width = PCI_EEPROM_WIDTH_93C66;
152 eeprom.width = PCI_EEPROM_WIDTH_93C86;
155 eeprom.reg_data_in = 0;
156 eeprom.reg_data_out = 0;
157 eeprom.reg_data_clock = 0;
158 eeprom.reg_chip_select = 0;
160 eeprom_93cx6_multiread(&eeprom, EEPROM_BASE, rt2x00dev->eeprom,
161 EEPROM_SIZE / sizeof(u16));
164 static int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
166 return rt2800_efuse_detect(rt2x00dev);
169 static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
171 rt2800_read_eeprom_efuse(rt2x00dev);
174 static inline void rt2800pci_read_eeprom_pci(struct rt2x00_dev *rt2x00dev)
178 static inline int rt2800pci_efuse_detect(struct rt2x00_dev *rt2x00dev)
183 static inline void rt2800pci_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
186 #endif /* CONFIG_PCI */
191 static void rt2800pci_start_queue(struct data_queue *queue)
193 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
196 switch (queue->qid) {
198 rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, ®);
199 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 1);
200 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
203 rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, ®);
204 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_TICKING, 1);
205 rt2x00_set_field32(®, BCN_TIME_CFG_TBTT_ENABLE, 1);
206 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 1);
207 rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
209 rt2x00pci_register_read(rt2x00dev, INT_TIMER_EN, ®);
210 rt2x00_set_field32(®, INT_TIMER_EN_PRE_TBTT_TIMER, 1);
211 rt2x00pci_register_write(rt2x00dev, INT_TIMER_EN, reg);
218 static void rt2800pci_kick_queue(struct data_queue *queue)
220 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
221 struct queue_entry *entry;
223 switch (queue->qid) {
228 entry = rt2x00queue_get_entry(queue, Q_INDEX);
229 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX(queue->qid),
233 entry = rt2x00queue_get_entry(queue, Q_INDEX);
234 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX(5),
242 static void rt2800pci_stop_queue(struct data_queue *queue)
244 struct rt2x00_dev *rt2x00dev = queue->rt2x00dev;
247 switch (queue->qid) {
249 rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, ®);
250 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 0);
251 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
254 rt2x00pci_register_read(rt2x00dev, BCN_TIME_CFG, ®);
255 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_TICKING, 0);
256 rt2x00_set_field32(®, BCN_TIME_CFG_TBTT_ENABLE, 0);
257 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0);
258 rt2x00pci_register_write(rt2x00dev, BCN_TIME_CFG, reg);
260 rt2x00pci_register_read(rt2x00dev, INT_TIMER_EN, ®);
261 rt2x00_set_field32(®, INT_TIMER_EN_PRE_TBTT_TIMER, 0);
262 rt2x00pci_register_write(rt2x00dev, INT_TIMER_EN, reg);
265 * Wait for current invocation to finish. The tasklet
266 * won't be scheduled anymore afterwards since we disabled
267 * the TBTT and PRE TBTT timer.
269 tasklet_kill(&rt2x00dev->tbtt_tasklet);
270 tasklet_kill(&rt2x00dev->pretbtt_tasklet);
281 static char *rt2800pci_get_firmware_name(struct rt2x00_dev *rt2x00dev)
283 return FIRMWARE_RT2860;
286 static int rt2800pci_write_firmware(struct rt2x00_dev *rt2x00dev,
287 const u8 *data, const size_t len)
292 * enable Host program ram write selection
295 rt2x00_set_field32(®, PBF_SYS_CTRL_HOST_RAM_WRITE, 1);
296 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, reg);
299 * Write firmware to device.
301 rt2x00pci_register_multiwrite(rt2x00dev, FIRMWARE_IMAGE_BASE,
304 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000);
305 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00001);
307 rt2x00pci_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
308 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
314 * Initialization functions.
316 static bool rt2800pci_get_entry_state(struct queue_entry *entry)
318 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
321 if (entry->queue->qid == QID_RX) {
322 rt2x00_desc_read(entry_priv->desc, 1, &word);
324 return (!rt2x00_get_field32(word, RXD_W1_DMA_DONE));
326 rt2x00_desc_read(entry_priv->desc, 1, &word);
328 return (!rt2x00_get_field32(word, TXD_W1_DMA_DONE));
332 static void rt2800pci_clear_entry(struct queue_entry *entry)
334 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
335 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
336 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
339 if (entry->queue->qid == QID_RX) {
340 rt2x00_desc_read(entry_priv->desc, 0, &word);
341 rt2x00_set_field32(&word, RXD_W0_SDP0, skbdesc->skb_dma);
342 rt2x00_desc_write(entry_priv->desc, 0, word);
344 rt2x00_desc_read(entry_priv->desc, 1, &word);
345 rt2x00_set_field32(&word, RXD_W1_DMA_DONE, 0);
346 rt2x00_desc_write(entry_priv->desc, 1, word);
349 * Set RX IDX in register to inform hardware that we have
350 * handled this entry and it is available for reuse again.
352 rt2x00pci_register_write(rt2x00dev, RX_CRX_IDX,
355 rt2x00_desc_read(entry_priv->desc, 1, &word);
356 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 1);
357 rt2x00_desc_write(entry_priv->desc, 1, word);
361 static int rt2800pci_init_queues(struct rt2x00_dev *rt2x00dev)
363 struct queue_entry_priv_pci *entry_priv;
367 * Initialize registers.
369 entry_priv = rt2x00dev->tx[0].entries[0].priv_data;
370 rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR0, entry_priv->desc_dma);
371 rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT0,
372 rt2x00dev->tx[0].limit);
373 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX0, 0);
374 rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX0, 0);
376 entry_priv = rt2x00dev->tx[1].entries[0].priv_data;
377 rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR1, entry_priv->desc_dma);
378 rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT1,
379 rt2x00dev->tx[1].limit);
380 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX1, 0);
381 rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX1, 0);
383 entry_priv = rt2x00dev->tx[2].entries[0].priv_data;
384 rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR2, entry_priv->desc_dma);
385 rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT2,
386 rt2x00dev->tx[2].limit);
387 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX2, 0);
388 rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX2, 0);
390 entry_priv = rt2x00dev->tx[3].entries[0].priv_data;
391 rt2x00pci_register_write(rt2x00dev, TX_BASE_PTR3, entry_priv->desc_dma);
392 rt2x00pci_register_write(rt2x00dev, TX_MAX_CNT3,
393 rt2x00dev->tx[3].limit);
394 rt2x00pci_register_write(rt2x00dev, TX_CTX_IDX3, 0);
395 rt2x00pci_register_write(rt2x00dev, TX_DTX_IDX3, 0);
397 entry_priv = rt2x00dev->rx->entries[0].priv_data;
398 rt2x00pci_register_write(rt2x00dev, RX_BASE_PTR, entry_priv->desc_dma);
399 rt2x00pci_register_write(rt2x00dev, RX_MAX_CNT,
400 rt2x00dev->rx[0].limit);
401 rt2x00pci_register_write(rt2x00dev, RX_CRX_IDX,
402 rt2x00dev->rx[0].limit - 1);
403 rt2x00pci_register_write(rt2x00dev, RX_DRX_IDX, 0);
406 * Enable global DMA configuration
408 rt2x00pci_register_read(rt2x00dev, WPDMA_GLO_CFG, ®);
409 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
410 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
411 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
412 rt2x00pci_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
414 rt2x00pci_register_write(rt2x00dev, DELAY_INT_CFG, 0);
420 * Device state switch handlers.
422 static void rt2800pci_toggle_irq(struct rt2x00_dev *rt2x00dev,
423 enum dev_state state)
425 int mask = (state == STATE_RADIO_IRQ_ON);
430 * When interrupts are being enabled, the interrupt registers
431 * should clear the register to assure a clean state.
433 if (state == STATE_RADIO_IRQ_ON) {
434 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, ®);
435 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
438 spin_lock_irqsave(&rt2x00dev->irqmask_lock, flags);
439 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, ®);
440 rt2x00_set_field32(®, INT_MASK_CSR_RXDELAYINT, 0);
441 rt2x00_set_field32(®, INT_MASK_CSR_TXDELAYINT, 0);
442 rt2x00_set_field32(®, INT_MASK_CSR_RX_DONE, mask);
443 rt2x00_set_field32(®, INT_MASK_CSR_AC0_DMA_DONE, 0);
444 rt2x00_set_field32(®, INT_MASK_CSR_AC1_DMA_DONE, 0);
445 rt2x00_set_field32(®, INT_MASK_CSR_AC2_DMA_DONE, 0);
446 rt2x00_set_field32(®, INT_MASK_CSR_AC3_DMA_DONE, 0);
447 rt2x00_set_field32(®, INT_MASK_CSR_HCCA_DMA_DONE, 0);
448 rt2x00_set_field32(®, INT_MASK_CSR_MGMT_DMA_DONE, 0);
449 rt2x00_set_field32(®, INT_MASK_CSR_MCU_COMMAND, 0);
450 rt2x00_set_field32(®, INT_MASK_CSR_RXTX_COHERENT, 0);
451 rt2x00_set_field32(®, INT_MASK_CSR_TBTT, mask);
452 rt2x00_set_field32(®, INT_MASK_CSR_PRE_TBTT, mask);
453 rt2x00_set_field32(®, INT_MASK_CSR_TX_FIFO_STATUS, mask);
454 rt2x00_set_field32(®, INT_MASK_CSR_AUTO_WAKEUP, mask);
455 rt2x00_set_field32(®, INT_MASK_CSR_GPTIMER, 0);
456 rt2x00_set_field32(®, INT_MASK_CSR_RX_COHERENT, 0);
457 rt2x00_set_field32(®, INT_MASK_CSR_TX_COHERENT, 0);
458 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
459 spin_unlock_irqrestore(&rt2x00dev->irqmask_lock, flags);
461 if (state == STATE_RADIO_IRQ_OFF) {
463 * Wait for possibly running tasklets to finish.
465 tasklet_kill(&rt2x00dev->txstatus_tasklet);
466 tasklet_kill(&rt2x00dev->rxdone_tasklet);
467 tasklet_kill(&rt2x00dev->autowake_tasklet);
468 tasklet_kill(&rt2x00dev->tbtt_tasklet);
469 tasklet_kill(&rt2x00dev->pretbtt_tasklet);
473 static int rt2800pci_init_registers(struct rt2x00_dev *rt2x00dev)
480 rt2x00pci_register_read(rt2x00dev, WPDMA_RST_IDX, ®);
481 rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX0, 1);
482 rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX1, 1);
483 rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX2, 1);
484 rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX3, 1);
485 rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX4, 1);
486 rt2x00_set_field32(®, WPDMA_RST_IDX_DTX_IDX5, 1);
487 rt2x00_set_field32(®, WPDMA_RST_IDX_DRX_IDX0, 1);
488 rt2x00pci_register_write(rt2x00dev, WPDMA_RST_IDX, reg);
490 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e1f);
491 rt2x00pci_register_write(rt2x00dev, PBF_SYS_CTRL, 0x00000e00);
493 if (rt2x00_is_pcie(rt2x00dev) &&
494 (rt2x00_rt(rt2x00dev, RT3572) ||
495 rt2x00_rt(rt2x00dev, RT5390))) {
496 rt2x00pci_register_read(rt2x00dev, AUX_CTRL, ®);
497 rt2x00_set_field32(®, AUX_CTRL_FORCE_PCIE_CLK, 1);
498 rt2x00_set_field32(®, AUX_CTRL_WAKE_PCIE_EN, 1);
499 rt2x00pci_register_write(rt2x00dev, AUX_CTRL, reg);
502 rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
504 rt2x00pci_register_read(rt2x00dev, MAC_SYS_CTRL, ®);
505 rt2x00_set_field32(®, MAC_SYS_CTRL_RESET_CSR, 1);
506 rt2x00_set_field32(®, MAC_SYS_CTRL_RESET_BBP, 1);
507 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
509 rt2x00pci_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
514 static int rt2800pci_enable_radio(struct rt2x00_dev *rt2x00dev)
516 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
517 rt2800pci_init_queues(rt2x00dev)))
520 return rt2800_enable_radio(rt2x00dev);
523 static void rt2800pci_disable_radio(struct rt2x00_dev *rt2x00dev)
525 if (rt2x00_is_soc(rt2x00dev)) {
526 rt2800_disable_radio(rt2x00dev);
527 rt2x00pci_register_write(rt2x00dev, PWR_PIN_CFG, 0);
528 rt2x00pci_register_write(rt2x00dev, TX_PIN_CFG, 0);
532 static int rt2800pci_set_state(struct rt2x00_dev *rt2x00dev,
533 enum dev_state state)
535 if (state == STATE_AWAKE) {
536 rt2800_mcu_request(rt2x00dev, MCU_WAKEUP, TOKEN_WAKUP, 0, 0x02);
537 rt2800pci_mcu_status(rt2x00dev, TOKEN_WAKUP);
538 } else if (state == STATE_SLEEP) {
539 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_STATUS,
541 rt2x00pci_register_write(rt2x00dev, H2M_MAILBOX_CID,
543 rt2800_mcu_request(rt2x00dev, MCU_SLEEP, 0x01, 0xff, 0x01);
549 static int rt2800pci_set_device_state(struct rt2x00_dev *rt2x00dev,
550 enum dev_state state)
557 * Before the radio can be enabled, the device first has
558 * to be woken up. After that it needs a bit of time
559 * to be fully awake and then the radio can be enabled.
561 rt2800pci_set_state(rt2x00dev, STATE_AWAKE);
563 retval = rt2800pci_enable_radio(rt2x00dev);
565 case STATE_RADIO_OFF:
567 * After the radio has been disabled, the device should
568 * be put to sleep for powersaving.
570 rt2800pci_disable_radio(rt2x00dev);
571 rt2800pci_set_state(rt2x00dev, STATE_SLEEP);
573 case STATE_RADIO_IRQ_ON:
574 case STATE_RADIO_IRQ_OFF:
575 rt2800pci_toggle_irq(rt2x00dev, state);
577 case STATE_DEEP_SLEEP:
581 retval = rt2800pci_set_state(rt2x00dev, state);
588 if (unlikely(retval))
589 ERROR(rt2x00dev, "Device failed to enter state %d (%d).\n",
596 * TX descriptor initialization
598 static __le32 *rt2800pci_get_txwi(struct queue_entry *entry)
600 return (__le32 *) entry->skb->data;
603 static void rt2800pci_write_tx_desc(struct queue_entry *entry,
604 struct txentry_desc *txdesc)
606 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
607 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
608 __le32 *txd = entry_priv->desc;
612 * The buffers pointed by SD_PTR0/SD_LEN0 and SD_PTR1/SD_LEN1
613 * must contains a TXWI structure + 802.11 header + padding + 802.11
614 * data. We choose to have SD_PTR0/SD_LEN0 only contains TXWI and
615 * SD_PTR1/SD_LEN1 contains 802.11 header + padding + 802.11
616 * data. It means that LAST_SEC0 is always 0.
620 * Initialize TX descriptor
623 rt2x00_set_field32(&word, TXD_W0_SD_PTR0, skbdesc->skb_dma);
624 rt2x00_desc_write(txd, 0, word);
627 rt2x00_set_field32(&word, TXD_W1_SD_LEN1, entry->skb->len);
628 rt2x00_set_field32(&word, TXD_W1_LAST_SEC1,
629 !test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
630 rt2x00_set_field32(&word, TXD_W1_BURST,
631 test_bit(ENTRY_TXD_BURST, &txdesc->flags));
632 rt2x00_set_field32(&word, TXD_W1_SD_LEN0, TXWI_DESC_SIZE);
633 rt2x00_set_field32(&word, TXD_W1_LAST_SEC0, 0);
634 rt2x00_set_field32(&word, TXD_W1_DMA_DONE, 0);
635 rt2x00_desc_write(txd, 1, word);
638 rt2x00_set_field32(&word, TXD_W2_SD_PTR1,
639 skbdesc->skb_dma + TXWI_DESC_SIZE);
640 rt2x00_desc_write(txd, 2, word);
643 rt2x00_set_field32(&word, TXD_W3_WIV,
644 !test_bit(ENTRY_TXD_ENCRYPT_IV, &txdesc->flags));
645 rt2x00_set_field32(&word, TXD_W3_QSEL, 2);
646 rt2x00_desc_write(txd, 3, word);
649 * Register descriptor details in skb frame descriptor.
652 skbdesc->desc_len = TXD_DESC_SIZE;
656 * RX control handlers
658 static void rt2800pci_fill_rxdone(struct queue_entry *entry,
659 struct rxdone_entry_desc *rxdesc)
661 struct queue_entry_priv_pci *entry_priv = entry->priv_data;
662 __le32 *rxd = entry_priv->desc;
665 rt2x00_desc_read(rxd, 3, &word);
667 if (rt2x00_get_field32(word, RXD_W3_CRC_ERROR))
668 rxdesc->flags |= RX_FLAG_FAILED_FCS_CRC;
671 * Unfortunately we don't know the cipher type used during
672 * decryption. This prevents us from correct providing
673 * correct statistics through debugfs.
675 rxdesc->cipher_status = rt2x00_get_field32(word, RXD_W3_CIPHER_ERROR);
677 if (rt2x00_get_field32(word, RXD_W3_DECRYPTED)) {
679 * Hardware has stripped IV/EIV data from 802.11 frame during
680 * decryption. Unfortunately the descriptor doesn't contain
681 * any fields with the EIV/IV data either, so they can't
682 * be restored by rt2x00lib.
684 rxdesc->flags |= RX_FLAG_IV_STRIPPED;
687 * The hardware has already checked the Michael Mic and has
688 * stripped it from the frame. Signal this to mac80211.
690 rxdesc->flags |= RX_FLAG_MMIC_STRIPPED;
692 if (rxdesc->cipher_status == RX_CRYPTO_SUCCESS)
693 rxdesc->flags |= RX_FLAG_DECRYPTED;
694 else if (rxdesc->cipher_status == RX_CRYPTO_FAIL_MIC)
695 rxdesc->flags |= RX_FLAG_MMIC_ERROR;
698 if (rt2x00_get_field32(word, RXD_W3_MY_BSS))
699 rxdesc->dev_flags |= RXDONE_MY_BSS;
701 if (rt2x00_get_field32(word, RXD_W3_L2PAD))
702 rxdesc->dev_flags |= RXDONE_L2PAD;
705 * Process the RXWI structure that is at the start of the buffer.
707 rt2800_process_rxwi(entry, rxdesc);
711 * Interrupt functions.
713 static void rt2800pci_wakeup(struct rt2x00_dev *rt2x00dev)
715 struct ieee80211_conf conf = { .flags = 0 };
716 struct rt2x00lib_conf libconf = { .conf = &conf };
718 rt2800_config(rt2x00dev, &libconf, IEEE80211_CONF_CHANGE_PS);
721 static bool rt2800pci_txdone(struct rt2x00_dev *rt2x00dev)
723 struct data_queue *queue;
724 struct queue_entry *entry;
727 int max_tx_done = 16;
729 while (kfifo_get(&rt2x00dev->txstatus_fifo, &status)) {
730 qid = rt2x00_get_field32(status, TX_STA_FIFO_PID_QUEUE);
731 if (unlikely(qid >= QID_RX)) {
733 * Unknown queue, this shouldn't happen. Just drop
736 WARNING(rt2x00dev, "Got TX status report with "
737 "unexpected pid %u, dropping\n", qid);
741 queue = rt2x00queue_get_tx_queue(rt2x00dev, qid);
742 if (unlikely(queue == NULL)) {
744 * The queue is NULL, this shouldn't happen. Stop
745 * processing here and drop the tx status
747 WARNING(rt2x00dev, "Got TX status for an unavailable "
748 "queue %u, dropping\n", qid);
752 if (unlikely(rt2x00queue_empty(queue))) {
754 * The queue is empty. Stop processing here
755 * and drop the tx status.
757 WARNING(rt2x00dev, "Got TX status for an empty "
758 "queue %u, dropping\n", qid);
762 entry = rt2x00queue_get_entry(queue, Q_INDEX_DONE);
763 rt2800_txdone_entry(entry, status, rt2800pci_get_txwi(entry));
765 if (--max_tx_done == 0)
772 static inline void rt2800pci_enable_interrupt(struct rt2x00_dev *rt2x00dev,
773 struct rt2x00_field32 irq_field)
778 * Enable a single interrupt. The interrupt mask register
779 * access needs locking.
781 spin_lock_irq(&rt2x00dev->irqmask_lock);
782 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, ®);
783 rt2x00_set_field32(®, irq_field, 1);
784 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
785 spin_unlock_irq(&rt2x00dev->irqmask_lock);
788 static void rt2800pci_txstatus_tasklet(unsigned long data)
790 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
791 if (rt2800pci_txdone(rt2x00dev))
792 tasklet_schedule(&rt2x00dev->txstatus_tasklet);
795 * No need to enable the tx status interrupt here as we always
796 * leave it enabled to minimize the possibility of a tx status
797 * register overflow. See comment in interrupt handler.
801 static void rt2800pci_pretbtt_tasklet(unsigned long data)
803 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
804 rt2x00lib_pretbtt(rt2x00dev);
805 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
806 rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_PRE_TBTT);
809 static void rt2800pci_tbtt_tasklet(unsigned long data)
811 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
812 rt2x00lib_beacondone(rt2x00dev);
813 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
814 rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_TBTT);
817 static void rt2800pci_rxdone_tasklet(unsigned long data)
819 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
820 if (rt2x00pci_rxdone(rt2x00dev))
821 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
822 else if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
823 rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_RX_DONE);
826 static void rt2800pci_autowake_tasklet(unsigned long data)
828 struct rt2x00_dev *rt2x00dev = (struct rt2x00_dev *)data;
829 rt2800pci_wakeup(rt2x00dev);
830 if (test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
831 rt2800pci_enable_interrupt(rt2x00dev, INT_MASK_CSR_AUTO_WAKEUP);
834 static void rt2800pci_txstatus_interrupt(struct rt2x00_dev *rt2x00dev)
840 * The TX_FIFO_STATUS interrupt needs special care. We should
841 * read TX_STA_FIFO but we should do it immediately as otherwise
842 * the register can overflow and we would lose status reports.
844 * Hence, read the TX_STA_FIFO register and copy all tx status
845 * reports into a kernel FIFO which is handled in the txstatus
846 * tasklet. We use a tasklet to process the tx status reports
847 * because we can schedule the tasklet multiple times (when the
848 * interrupt fires again during tx status processing).
850 * Furthermore we don't disable the TX_FIFO_STATUS
851 * interrupt here but leave it enabled so that the TX_STA_FIFO
852 * can also be read while the tx status tasklet gets executed.
854 * Since we have only one producer and one consumer we don't
855 * need to lock the kfifo.
857 for (i = 0; i < rt2x00dev->ops->tx->entry_num; i++) {
858 rt2x00pci_register_read(rt2x00dev, TX_STA_FIFO, &status);
860 if (!rt2x00_get_field32(status, TX_STA_FIFO_VALID))
863 if (!kfifo_put(&rt2x00dev->txstatus_fifo, &status)) {
864 WARNING(rt2x00dev, "TX status FIFO overrun,"
865 "drop tx status report.\n");
870 /* Schedule the tasklet for processing the tx status. */
871 tasklet_schedule(&rt2x00dev->txstatus_tasklet);
874 static irqreturn_t rt2800pci_interrupt(int irq, void *dev_instance)
876 struct rt2x00_dev *rt2x00dev = dev_instance;
879 /* Read status and ACK all interrupts */
880 rt2x00pci_register_read(rt2x00dev, INT_SOURCE_CSR, ®);
881 rt2x00pci_register_write(rt2x00dev, INT_SOURCE_CSR, reg);
886 if (!test_bit(DEVICE_STATE_ENABLED_RADIO, &rt2x00dev->flags))
890 * Since INT_MASK_CSR and INT_SOURCE_CSR use the same bits
891 * for interrupts and interrupt masks we can just use the value of
892 * INT_SOURCE_CSR to create the interrupt mask.
896 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TX_FIFO_STATUS)) {
897 rt2800pci_txstatus_interrupt(rt2x00dev);
899 * Never disable the TX_FIFO_STATUS interrupt.
901 rt2x00_set_field32(&mask, INT_MASK_CSR_TX_FIFO_STATUS, 1);
904 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_PRE_TBTT))
905 tasklet_hi_schedule(&rt2x00dev->pretbtt_tasklet);
907 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_TBTT))
908 tasklet_hi_schedule(&rt2x00dev->tbtt_tasklet);
910 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_RX_DONE))
911 tasklet_schedule(&rt2x00dev->rxdone_tasklet);
913 if (rt2x00_get_field32(reg, INT_SOURCE_CSR_AUTO_WAKEUP))
914 tasklet_schedule(&rt2x00dev->autowake_tasklet);
917 * Disable all interrupts for which a tasklet was scheduled right now,
918 * the tasklet will reenable the appropriate interrupts.
920 spin_lock(&rt2x00dev->irqmask_lock);
921 rt2x00pci_register_read(rt2x00dev, INT_MASK_CSR, ®);
923 rt2x00pci_register_write(rt2x00dev, INT_MASK_CSR, reg);
924 spin_unlock(&rt2x00dev->irqmask_lock);
930 * Device probe functions.
932 static int rt2800pci_validate_eeprom(struct rt2x00_dev *rt2x00dev)
935 * Read EEPROM into buffer
937 if (rt2x00_is_soc(rt2x00dev))
938 rt2800pci_read_eeprom_soc(rt2x00dev);
939 else if (rt2800pci_efuse_detect(rt2x00dev))
940 rt2800pci_read_eeprom_efuse(rt2x00dev);
942 rt2800pci_read_eeprom_pci(rt2x00dev);
944 return rt2800_validate_eeprom(rt2x00dev);
947 static int rt2800pci_probe_hw(struct rt2x00_dev *rt2x00dev)
952 * Allocate eeprom data.
954 retval = rt2800pci_validate_eeprom(rt2x00dev);
958 retval = rt2800_init_eeprom(rt2x00dev);
963 * Initialize hw specifications.
965 retval = rt2800_probe_hw_mode(rt2x00dev);
970 * This device has multiple filters for control frames
971 * and has a separate filter for PS Poll frames.
973 __set_bit(CAPABILITY_CONTROL_FILTERS, &rt2x00dev->cap_flags);
974 __set_bit(CAPABILITY_CONTROL_FILTER_PSPOLL, &rt2x00dev->cap_flags);
977 * This device has a pre tbtt interrupt and thus fetches
978 * a new beacon directly prior to transmission.
980 __set_bit(CAPABILITY_PRE_TBTT_INTERRUPT, &rt2x00dev->cap_flags);
983 * This device requires firmware.
985 if (!rt2x00_is_soc(rt2x00dev))
986 __set_bit(REQUIRE_FIRMWARE, &rt2x00dev->cap_flags);
987 __set_bit(REQUIRE_DMA, &rt2x00dev->cap_flags);
988 __set_bit(REQUIRE_L2PAD, &rt2x00dev->cap_flags);
989 __set_bit(REQUIRE_TXSTATUS_FIFO, &rt2x00dev->cap_flags);
990 __set_bit(REQUIRE_TASKLET_CONTEXT, &rt2x00dev->cap_flags);
991 if (!modparam_nohwcrypt)
992 __set_bit(CAPABILITY_HW_CRYPTO, &rt2x00dev->cap_flags);
993 __set_bit(CAPABILITY_LINK_TUNING, &rt2x00dev->cap_flags);
994 __set_bit(REQUIRE_HT_TX_DESC, &rt2x00dev->cap_flags);
997 * Set the rssi offset.
999 rt2x00dev->rssi_offset = DEFAULT_RSSI_OFFSET;
1004 static const struct ieee80211_ops rt2800pci_mac80211_ops = {
1006 .start = rt2x00mac_start,
1007 .stop = rt2x00mac_stop,
1008 .add_interface = rt2x00mac_add_interface,
1009 .remove_interface = rt2x00mac_remove_interface,
1010 .config = rt2x00mac_config,
1011 .configure_filter = rt2x00mac_configure_filter,
1012 .set_key = rt2x00mac_set_key,
1013 .sw_scan_start = rt2x00mac_sw_scan_start,
1014 .sw_scan_complete = rt2x00mac_sw_scan_complete,
1015 .get_stats = rt2x00mac_get_stats,
1016 .get_tkip_seq = rt2800_get_tkip_seq,
1017 .set_rts_threshold = rt2800_set_rts_threshold,
1018 .sta_add = rt2x00mac_sta_add,
1019 .sta_remove = rt2x00mac_sta_remove,
1020 .bss_info_changed = rt2x00mac_bss_info_changed,
1021 .conf_tx = rt2800_conf_tx,
1022 .get_tsf = rt2800_get_tsf,
1023 .rfkill_poll = rt2x00mac_rfkill_poll,
1024 .ampdu_action = rt2800_ampdu_action,
1025 .flush = rt2x00mac_flush,
1026 .get_survey = rt2800_get_survey,
1027 .get_ringparam = rt2x00mac_get_ringparam,
1028 .tx_frames_pending = rt2x00mac_tx_frames_pending,
1031 static const struct rt2800_ops rt2800pci_rt2800_ops = {
1032 .register_read = rt2x00pci_register_read,
1033 .register_read_lock = rt2x00pci_register_read, /* same for PCI */
1034 .register_write = rt2x00pci_register_write,
1035 .register_write_lock = rt2x00pci_register_write, /* same for PCI */
1036 .register_multiread = rt2x00pci_register_multiread,
1037 .register_multiwrite = rt2x00pci_register_multiwrite,
1038 .regbusy_read = rt2x00pci_regbusy_read,
1039 .drv_write_firmware = rt2800pci_write_firmware,
1040 .drv_init_registers = rt2800pci_init_registers,
1041 .drv_get_txwi = rt2800pci_get_txwi,
1044 static const struct rt2x00lib_ops rt2800pci_rt2x00_ops = {
1045 .irq_handler = rt2800pci_interrupt,
1046 .txstatus_tasklet = rt2800pci_txstatus_tasklet,
1047 .pretbtt_tasklet = rt2800pci_pretbtt_tasklet,
1048 .tbtt_tasklet = rt2800pci_tbtt_tasklet,
1049 .rxdone_tasklet = rt2800pci_rxdone_tasklet,
1050 .autowake_tasklet = rt2800pci_autowake_tasklet,
1051 .probe_hw = rt2800pci_probe_hw,
1052 .get_firmware_name = rt2800pci_get_firmware_name,
1053 .check_firmware = rt2800_check_firmware,
1054 .load_firmware = rt2800_load_firmware,
1055 .initialize = rt2x00pci_initialize,
1056 .uninitialize = rt2x00pci_uninitialize,
1057 .get_entry_state = rt2800pci_get_entry_state,
1058 .clear_entry = rt2800pci_clear_entry,
1059 .set_device_state = rt2800pci_set_device_state,
1060 .rfkill_poll = rt2800_rfkill_poll,
1061 .link_stats = rt2800_link_stats,
1062 .reset_tuner = rt2800_reset_tuner,
1063 .link_tuner = rt2800_link_tuner,
1064 .gain_calibration = rt2800_gain_calibration,
1065 .start_queue = rt2800pci_start_queue,
1066 .kick_queue = rt2800pci_kick_queue,
1067 .stop_queue = rt2800pci_stop_queue,
1068 .flush_queue = rt2x00pci_flush_queue,
1069 .write_tx_desc = rt2800pci_write_tx_desc,
1070 .write_tx_data = rt2800_write_tx_data,
1071 .write_beacon = rt2800_write_beacon,
1072 .clear_beacon = rt2800_clear_beacon,
1073 .fill_rxdone = rt2800pci_fill_rxdone,
1074 .config_shared_key = rt2800_config_shared_key,
1075 .config_pairwise_key = rt2800_config_pairwise_key,
1076 .config_filter = rt2800_config_filter,
1077 .config_intf = rt2800_config_intf,
1078 .config_erp = rt2800_config_erp,
1079 .config_ant = rt2800_config_ant,
1080 .config = rt2800_config,
1081 .sta_add = rt2800_sta_add,
1082 .sta_remove = rt2800_sta_remove,
1085 static const struct data_queue_desc rt2800pci_queue_rx = {
1087 .data_size = AGGREGATION_SIZE,
1088 .desc_size = RXD_DESC_SIZE,
1089 .priv_size = sizeof(struct queue_entry_priv_pci),
1092 static const struct data_queue_desc rt2800pci_queue_tx = {
1094 .data_size = AGGREGATION_SIZE,
1095 .desc_size = TXD_DESC_SIZE,
1096 .priv_size = sizeof(struct queue_entry_priv_pci),
1099 static const struct data_queue_desc rt2800pci_queue_bcn = {
1101 .data_size = 0, /* No DMA required for beacons */
1102 .desc_size = TXWI_DESC_SIZE,
1103 .priv_size = sizeof(struct queue_entry_priv_pci),
1106 static const struct rt2x00_ops rt2800pci_ops = {
1107 .name = KBUILD_MODNAME,
1110 .eeprom_size = EEPROM_SIZE,
1112 .tx_queues = NUM_TX_QUEUES,
1113 .extra_tx_headroom = TXWI_DESC_SIZE,
1114 .rx = &rt2800pci_queue_rx,
1115 .tx = &rt2800pci_queue_tx,
1116 .bcn = &rt2800pci_queue_bcn,
1117 .lib = &rt2800pci_rt2x00_ops,
1118 .drv = &rt2800pci_rt2800_ops,
1119 .hw = &rt2800pci_mac80211_ops,
1120 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
1121 .debugfs = &rt2800_rt2x00debug,
1122 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
1126 * RT2800pci module information.
1129 static DEFINE_PCI_DEVICE_TABLE(rt2800pci_device_table) = {
1130 { PCI_DEVICE(0x1814, 0x0601) },
1131 { PCI_DEVICE(0x1814, 0x0681) },
1132 { PCI_DEVICE(0x1814, 0x0701) },
1133 { PCI_DEVICE(0x1814, 0x0781) },
1134 { PCI_DEVICE(0x1814, 0x3090) },
1135 { PCI_DEVICE(0x1814, 0x3091) },
1136 { PCI_DEVICE(0x1814, 0x3092) },
1137 { PCI_DEVICE(0x1432, 0x7708) },
1138 { PCI_DEVICE(0x1432, 0x7727) },
1139 { PCI_DEVICE(0x1432, 0x7728) },
1140 { PCI_DEVICE(0x1432, 0x7738) },
1141 { PCI_DEVICE(0x1432, 0x7748) },
1142 { PCI_DEVICE(0x1432, 0x7758) },
1143 { PCI_DEVICE(0x1432, 0x7768) },
1144 { PCI_DEVICE(0x1462, 0x891a) },
1145 { PCI_DEVICE(0x1a3b, 0x1059) },
1146 #ifdef CONFIG_RT2800PCI_RT33XX
1147 { PCI_DEVICE(0x1814, 0x3390) },
1149 #ifdef CONFIG_RT2800PCI_RT35XX
1150 { PCI_DEVICE(0x1432, 0x7711) },
1151 { PCI_DEVICE(0x1432, 0x7722) },
1152 { PCI_DEVICE(0x1814, 0x3060) },
1153 { PCI_DEVICE(0x1814, 0x3062) },
1154 { PCI_DEVICE(0x1814, 0x3562) },
1155 { PCI_DEVICE(0x1814, 0x3592) },
1156 { PCI_DEVICE(0x1814, 0x3593) },
1158 #ifdef CONFIG_RT2800PCI_RT53XX
1159 { PCI_DEVICE(0x1814, 0x5390) },
1160 { PCI_DEVICE(0x1814, 0x539a) },
1161 { PCI_DEVICE(0x1814, 0x539f) },
1165 #endif /* CONFIG_PCI */
1167 MODULE_AUTHOR(DRV_PROJECT);
1168 MODULE_VERSION(DRV_VERSION);
1169 MODULE_DESCRIPTION("Ralink RT2800 PCI & PCMCIA Wireless LAN driver.");
1170 MODULE_SUPPORTED_DEVICE("Ralink RT2860 PCI & PCMCIA chipset based cards");
1172 MODULE_FIRMWARE(FIRMWARE_RT2860);
1173 MODULE_DEVICE_TABLE(pci, rt2800pci_device_table);
1174 #endif /* CONFIG_PCI */
1175 MODULE_LICENSE("GPL");
1177 #if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
1178 static int rt2800soc_probe(struct platform_device *pdev)
1180 return rt2x00soc_probe(pdev, &rt2800pci_ops);
1183 static struct platform_driver rt2800soc_driver = {
1185 .name = "rt2800_wmac",
1186 .owner = THIS_MODULE,
1187 .mod_name = KBUILD_MODNAME,
1189 .probe = rt2800soc_probe,
1190 .remove = __devexit_p(rt2x00soc_remove),
1191 .suspend = rt2x00soc_suspend,
1192 .resume = rt2x00soc_resume,
1194 #endif /* CONFIG_RALINK_RT288X || CONFIG_RALINK_RT305X */
1197 static int rt2800pci_probe(struct pci_dev *pci_dev,
1198 const struct pci_device_id *id)
1200 return rt2x00pci_probe(pci_dev, &rt2800pci_ops);
1203 static struct pci_driver rt2800pci_driver = {
1204 .name = KBUILD_MODNAME,
1205 .id_table = rt2800pci_device_table,
1206 .probe = rt2800pci_probe,
1207 .remove = __devexit_p(rt2x00pci_remove),
1208 .suspend = rt2x00pci_suspend,
1209 .resume = rt2x00pci_resume,
1211 #endif /* CONFIG_PCI */
1213 static int __init rt2800pci_init(void)
1217 #if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
1218 ret = platform_driver_register(&rt2800soc_driver);
1223 ret = pci_register_driver(&rt2800pci_driver);
1225 #if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
1226 platform_driver_unregister(&rt2800soc_driver);
1235 static void __exit rt2800pci_exit(void)
1238 pci_unregister_driver(&rt2800pci_driver);
1240 #if defined(CONFIG_RALINK_RT288X) || defined(CONFIG_RALINK_RT305X)
1241 platform_driver_unregister(&rt2800soc_driver);
1245 module_init(rt2800pci_init);
1246 module_exit(rt2800pci_exit);