2 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
3 Copyright (C) 2010 Ivo van Doorn <IvDoorn@gmail.com>
4 Copyright (C) 2009 Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
5 Copyright (C) 2009 Gertjan van Wingerde <gwingerde@gmail.com>
7 Based on the original rt2800pci.c and rt2800usb.c.
8 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
9 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
10 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
11 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
12 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
13 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
14 <http://rt2x00.serialmonkey.com>
16 This program is free software; you can redistribute it and/or modify
17 it under the terms of the GNU General Public License as published by
18 the Free Software Foundation; either version 2 of the License, or
19 (at your option) any later version.
21 This program is distributed in the hope that it will be useful,
22 but WITHOUT ANY WARRANTY; without even the implied warranty of
23 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 GNU General Public License for more details.
26 You should have received a copy of the GNU General Public License
27 along with this program; if not, write to the
28 Free Software Foundation, Inc.,
29 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
34 Abstract: rt2800 generic device routines.
37 #include <linux/crc-ccitt.h>
38 #include <linux/kernel.h>
39 #include <linux/module.h>
40 #include <linux/slab.h>
43 #include "rt2800lib.h"
48 * All access to the CSR registers will go through the methods
49 * rt2800_register_read and rt2800_register_write.
50 * BBP and RF register require indirect register access,
51 * and use the CSR registers BBPCSR and RFCSR to achieve this.
52 * These indirect registers work with busy bits,
53 * and we will try maximal REGISTER_BUSY_COUNT times to access
54 * the register while taking a REGISTER_BUSY_DELAY us delay
55 * between each attampt. When the busy bit is still set at that time,
56 * the access attempt is considered to have failed,
57 * and we will print an error.
58 * The _lock versions must be used if you already hold the csr_mutex
60 #define WAIT_FOR_BBP(__dev, __reg) \
61 rt2800_regbusy_read((__dev), BBP_CSR_CFG, BBP_CSR_CFG_BUSY, (__reg))
62 #define WAIT_FOR_RFCSR(__dev, __reg) \
63 rt2800_regbusy_read((__dev), RF_CSR_CFG, RF_CSR_CFG_BUSY, (__reg))
64 #define WAIT_FOR_RF(__dev, __reg) \
65 rt2800_regbusy_read((__dev), RF_CSR_CFG0, RF_CSR_CFG0_BUSY, (__reg))
66 #define WAIT_FOR_MCU(__dev, __reg) \
67 rt2800_regbusy_read((__dev), H2M_MAILBOX_CSR, \
68 H2M_MAILBOX_CSR_OWNER, (__reg))
70 static inline bool rt2800_is_305x_soc(struct rt2x00_dev *rt2x00dev)
72 /* check for rt2872 on SoC */
73 if (!rt2x00_is_soc(rt2x00dev) ||
74 !rt2x00_rt(rt2x00dev, RT2872))
77 /* we know for sure that these rf chipsets are used on rt305x boards */
78 if (rt2x00_rf(rt2x00dev, RF3020) ||
79 rt2x00_rf(rt2x00dev, RF3021) ||
80 rt2x00_rf(rt2x00dev, RF3022))
83 NOTICE(rt2x00dev, "Unknown RF chipset on rt305x\n");
87 static void rt2800_bbp_write(struct rt2x00_dev *rt2x00dev,
88 const unsigned int word, const u8 value)
92 mutex_lock(&rt2x00dev->csr_mutex);
95 * Wait until the BBP becomes available, afterwards we
96 * can safely write the new data into the register.
98 if (WAIT_FOR_BBP(rt2x00dev, ®)) {
100 rt2x00_set_field32(®, BBP_CSR_CFG_VALUE, value);
101 rt2x00_set_field32(®, BBP_CSR_CFG_REGNUM, word);
102 rt2x00_set_field32(®, BBP_CSR_CFG_BUSY, 1);
103 rt2x00_set_field32(®, BBP_CSR_CFG_READ_CONTROL, 0);
104 rt2x00_set_field32(®, BBP_CSR_CFG_BBP_RW_MODE, 1);
106 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
109 mutex_unlock(&rt2x00dev->csr_mutex);
112 static void rt2800_bbp_read(struct rt2x00_dev *rt2x00dev,
113 const unsigned int word, u8 *value)
117 mutex_lock(&rt2x00dev->csr_mutex);
120 * Wait until the BBP becomes available, afterwards we
121 * can safely write the read request into the register.
122 * After the data has been written, we wait until hardware
123 * returns the correct value, if at any time the register
124 * doesn't become available in time, reg will be 0xffffffff
125 * which means we return 0xff to the caller.
127 if (WAIT_FOR_BBP(rt2x00dev, ®)) {
129 rt2x00_set_field32(®, BBP_CSR_CFG_REGNUM, word);
130 rt2x00_set_field32(®, BBP_CSR_CFG_BUSY, 1);
131 rt2x00_set_field32(®, BBP_CSR_CFG_READ_CONTROL, 1);
132 rt2x00_set_field32(®, BBP_CSR_CFG_BBP_RW_MODE, 1);
134 rt2800_register_write_lock(rt2x00dev, BBP_CSR_CFG, reg);
136 WAIT_FOR_BBP(rt2x00dev, ®);
139 *value = rt2x00_get_field32(reg, BBP_CSR_CFG_VALUE);
141 mutex_unlock(&rt2x00dev->csr_mutex);
144 static void rt2800_rfcsr_write(struct rt2x00_dev *rt2x00dev,
145 const unsigned int word, const u8 value)
149 mutex_lock(&rt2x00dev->csr_mutex);
152 * Wait until the RFCSR becomes available, afterwards we
153 * can safely write the new data into the register.
155 if (WAIT_FOR_RFCSR(rt2x00dev, ®)) {
157 rt2x00_set_field32(®, RF_CSR_CFG_DATA, value);
158 rt2x00_set_field32(®, RF_CSR_CFG_REGNUM, word);
159 rt2x00_set_field32(®, RF_CSR_CFG_WRITE, 1);
160 rt2x00_set_field32(®, RF_CSR_CFG_BUSY, 1);
162 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
165 mutex_unlock(&rt2x00dev->csr_mutex);
168 static void rt2800_rfcsr_read(struct rt2x00_dev *rt2x00dev,
169 const unsigned int word, u8 *value)
173 mutex_lock(&rt2x00dev->csr_mutex);
176 * Wait until the RFCSR becomes available, afterwards we
177 * can safely write the read request into the register.
178 * After the data has been written, we wait until hardware
179 * returns the correct value, if at any time the register
180 * doesn't become available in time, reg will be 0xffffffff
181 * which means we return 0xff to the caller.
183 if (WAIT_FOR_RFCSR(rt2x00dev, ®)) {
185 rt2x00_set_field32(®, RF_CSR_CFG_REGNUM, word);
186 rt2x00_set_field32(®, RF_CSR_CFG_WRITE, 0);
187 rt2x00_set_field32(®, RF_CSR_CFG_BUSY, 1);
189 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG, reg);
191 WAIT_FOR_RFCSR(rt2x00dev, ®);
194 *value = rt2x00_get_field32(reg, RF_CSR_CFG_DATA);
196 mutex_unlock(&rt2x00dev->csr_mutex);
199 static void rt2800_rf_write(struct rt2x00_dev *rt2x00dev,
200 const unsigned int word, const u32 value)
204 mutex_lock(&rt2x00dev->csr_mutex);
207 * Wait until the RF becomes available, afterwards we
208 * can safely write the new data into the register.
210 if (WAIT_FOR_RF(rt2x00dev, ®)) {
212 rt2x00_set_field32(®, RF_CSR_CFG0_REG_VALUE_BW, value);
213 rt2x00_set_field32(®, RF_CSR_CFG0_STANDBYMODE, 0);
214 rt2x00_set_field32(®, RF_CSR_CFG0_SEL, 0);
215 rt2x00_set_field32(®, RF_CSR_CFG0_BUSY, 1);
217 rt2800_register_write_lock(rt2x00dev, RF_CSR_CFG0, reg);
218 rt2x00_rf_write(rt2x00dev, word, value);
221 mutex_unlock(&rt2x00dev->csr_mutex);
224 void rt2800_mcu_request(struct rt2x00_dev *rt2x00dev,
225 const u8 command, const u8 token,
226 const u8 arg0, const u8 arg1)
231 * SOC devices don't support MCU requests.
233 if (rt2x00_is_soc(rt2x00dev))
236 mutex_lock(&rt2x00dev->csr_mutex);
239 * Wait until the MCU becomes available, afterwards we
240 * can safely write the new data into the register.
242 if (WAIT_FOR_MCU(rt2x00dev, ®)) {
243 rt2x00_set_field32(®, H2M_MAILBOX_CSR_OWNER, 1);
244 rt2x00_set_field32(®, H2M_MAILBOX_CSR_CMD_TOKEN, token);
245 rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG0, arg0);
246 rt2x00_set_field32(®, H2M_MAILBOX_CSR_ARG1, arg1);
247 rt2800_register_write_lock(rt2x00dev, H2M_MAILBOX_CSR, reg);
250 rt2x00_set_field32(®, HOST_CMD_CSR_HOST_COMMAND, command);
251 rt2800_register_write_lock(rt2x00dev, HOST_CMD_CSR, reg);
254 mutex_unlock(&rt2x00dev->csr_mutex);
256 EXPORT_SYMBOL_GPL(rt2800_mcu_request);
258 int rt2800_wait_csr_ready(struct rt2x00_dev *rt2x00dev)
263 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
264 rt2800_register_read(rt2x00dev, MAC_CSR0, ®);
265 if (reg && reg != ~0)
270 ERROR(rt2x00dev, "Unstable hardware.\n");
273 EXPORT_SYMBOL_GPL(rt2800_wait_csr_ready);
275 int rt2800_wait_wpdma_ready(struct rt2x00_dev *rt2x00dev)
281 * Some devices are really slow to respond here. Wait a whole second
284 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
285 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, ®);
286 if (!rt2x00_get_field32(reg, WPDMA_GLO_CFG_TX_DMA_BUSY) &&
287 !rt2x00_get_field32(reg, WPDMA_GLO_CFG_RX_DMA_BUSY))
293 ERROR(rt2x00dev, "WPDMA TX/RX busy [0x%08x].\n", reg);
296 EXPORT_SYMBOL_GPL(rt2800_wait_wpdma_ready);
298 void rt2800_disable_wpdma(struct rt2x00_dev *rt2x00dev)
302 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, ®);
303 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
304 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
305 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
306 rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
307 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
308 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
310 EXPORT_SYMBOL_GPL(rt2800_disable_wpdma);
312 static bool rt2800_check_firmware_crc(const u8 *data, const size_t len)
318 * The last 2 bytes in the firmware array are the crc checksum itself,
319 * this means that we should never pass those 2 bytes to the crc
322 fw_crc = (data[len - 2] << 8 | data[len - 1]);
325 * Use the crc ccitt algorithm.
326 * This will return the same value as the legacy driver which
327 * used bit ordering reversion on the both the firmware bytes
328 * before input input as well as on the final output.
329 * Obviously using crc ccitt directly is much more efficient.
331 crc = crc_ccitt(~0, data, len - 2);
334 * There is a small difference between the crc-itu-t + bitrev and
335 * the crc-ccitt crc calculation. In the latter method the 2 bytes
336 * will be swapped, use swab16 to convert the crc to the correct
341 return fw_crc == crc;
344 int rt2800_check_firmware(struct rt2x00_dev *rt2x00dev,
345 const u8 *data, const size_t len)
352 * PCI(e) & SOC devices require firmware with a length
353 * of 8kb. USB devices require firmware files with a length
354 * of 4kb. Certain USB chipsets however require different firmware,
355 * which Ralink only provides attached to the original firmware
356 * file. Thus for USB devices, firmware files have a length
357 * which is a multiple of 4kb. The firmware for rt3290 chip also
358 * have a length which is a multiple of 4kb.
360 if (rt2x00_is_usb(rt2x00dev) || rt2x00_rt(rt2x00dev, RT3290))
367 * Validate the firmware length
369 if (len != fw_len && (!multiple || (len % fw_len) != 0))
370 return FW_BAD_LENGTH;
373 * Check if the chipset requires one of the upper parts
376 if (rt2x00_is_usb(rt2x00dev) &&
377 !rt2x00_rt(rt2x00dev, RT2860) &&
378 !rt2x00_rt(rt2x00dev, RT2872) &&
379 !rt2x00_rt(rt2x00dev, RT3070) &&
380 ((len / fw_len) == 1))
381 return FW_BAD_VERSION;
384 * 8kb firmware files must be checked as if it were
385 * 2 separate firmware files.
387 while (offset < len) {
388 if (!rt2800_check_firmware_crc(data + offset, fw_len))
396 EXPORT_SYMBOL_GPL(rt2800_check_firmware);
398 int rt2800_load_firmware(struct rt2x00_dev *rt2x00dev,
399 const u8 *data, const size_t len)
405 * If driver doesn't wake up firmware here,
406 * rt2800_load_firmware will hang forever when interface is up again.
408 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0x00000000);
411 * Wait for stable hardware.
413 if (rt2800_wait_csr_ready(rt2x00dev))
416 if (rt2x00_is_pci(rt2x00dev)) {
417 if (rt2x00_rt(rt2x00dev, RT3290) ||
418 rt2x00_rt(rt2x00dev, RT3572) ||
419 rt2x00_rt(rt2x00dev, RT5390) ||
420 rt2x00_rt(rt2x00dev, RT5392)) {
421 rt2800_register_read(rt2x00dev, AUX_CTRL, ®);
422 rt2x00_set_field32(®, AUX_CTRL_FORCE_PCIE_CLK, 1);
423 rt2x00_set_field32(®, AUX_CTRL_WAKE_PCIE_EN, 1);
424 rt2800_register_write(rt2x00dev, AUX_CTRL, reg);
426 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000002);
429 rt2800_disable_wpdma(rt2x00dev);
432 * Write firmware to the device.
434 rt2800_drv_write_firmware(rt2x00dev, data, len);
437 * Wait for device to stabilize.
439 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
440 rt2800_register_read(rt2x00dev, PBF_SYS_CTRL, ®);
441 if (rt2x00_get_field32(reg, PBF_SYS_CTRL_READY))
446 if (i == REGISTER_BUSY_COUNT) {
447 ERROR(rt2x00dev, "PBF system register not ready.\n");
452 * Disable DMA, will be reenabled later when enabling
455 rt2800_disable_wpdma(rt2x00dev);
458 * Initialize firmware.
460 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
461 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
462 if (rt2x00_is_usb(rt2x00dev))
463 rt2800_register_write(rt2x00dev, H2M_INT_SRC, 0);
468 EXPORT_SYMBOL_GPL(rt2800_load_firmware);
470 void rt2800_write_tx_data(struct queue_entry *entry,
471 struct txentry_desc *txdesc)
473 __le32 *txwi = rt2800_drv_get_txwi(entry);
477 * Initialize TX Info descriptor
479 rt2x00_desc_read(txwi, 0, &word);
480 rt2x00_set_field32(&word, TXWI_W0_FRAG,
481 test_bit(ENTRY_TXD_MORE_FRAG, &txdesc->flags));
482 rt2x00_set_field32(&word, TXWI_W0_MIMO_PS,
483 test_bit(ENTRY_TXD_HT_MIMO_PS, &txdesc->flags));
484 rt2x00_set_field32(&word, TXWI_W0_CF_ACK, 0);
485 rt2x00_set_field32(&word, TXWI_W0_TS,
486 test_bit(ENTRY_TXD_REQ_TIMESTAMP, &txdesc->flags));
487 rt2x00_set_field32(&word, TXWI_W0_AMPDU,
488 test_bit(ENTRY_TXD_HT_AMPDU, &txdesc->flags));
489 rt2x00_set_field32(&word, TXWI_W0_MPDU_DENSITY,
490 txdesc->u.ht.mpdu_density);
491 rt2x00_set_field32(&word, TXWI_W0_TX_OP, txdesc->u.ht.txop);
492 rt2x00_set_field32(&word, TXWI_W0_MCS, txdesc->u.ht.mcs);
493 rt2x00_set_field32(&word, TXWI_W0_BW,
494 test_bit(ENTRY_TXD_HT_BW_40, &txdesc->flags));
495 rt2x00_set_field32(&word, TXWI_W0_SHORT_GI,
496 test_bit(ENTRY_TXD_HT_SHORT_GI, &txdesc->flags));
497 rt2x00_set_field32(&word, TXWI_W0_STBC, txdesc->u.ht.stbc);
498 rt2x00_set_field32(&word, TXWI_W0_PHYMODE, txdesc->rate_mode);
499 rt2x00_desc_write(txwi, 0, word);
501 rt2x00_desc_read(txwi, 1, &word);
502 rt2x00_set_field32(&word, TXWI_W1_ACK,
503 test_bit(ENTRY_TXD_ACK, &txdesc->flags));
504 rt2x00_set_field32(&word, TXWI_W1_NSEQ,
505 test_bit(ENTRY_TXD_GENERATE_SEQ, &txdesc->flags));
506 rt2x00_set_field32(&word, TXWI_W1_BW_WIN_SIZE, txdesc->u.ht.ba_size);
507 rt2x00_set_field32(&word, TXWI_W1_WIRELESS_CLI_ID,
508 test_bit(ENTRY_TXD_ENCRYPT, &txdesc->flags) ?
509 txdesc->key_idx : txdesc->u.ht.wcid);
510 rt2x00_set_field32(&word, TXWI_W1_MPDU_TOTAL_BYTE_COUNT,
512 rt2x00_set_field32(&word, TXWI_W1_PACKETID_QUEUE, entry->queue->qid);
513 rt2x00_set_field32(&word, TXWI_W1_PACKETID_ENTRY, (entry->entry_idx % 3) + 1);
514 rt2x00_desc_write(txwi, 1, word);
517 * Always write 0 to IV/EIV fields, hardware will insert the IV
518 * from the IVEIV register when TXD_W3_WIV is set to 0.
519 * When TXD_W3_WIV is set to 1 it will use the IV data
520 * from the descriptor. The TXWI_W1_WIRELESS_CLI_ID indicates which
521 * crypto entry in the registers should be used to encrypt the frame.
523 _rt2x00_desc_write(txwi, 2, 0 /* skbdesc->iv[0] */);
524 _rt2x00_desc_write(txwi, 3, 0 /* skbdesc->iv[1] */);
526 EXPORT_SYMBOL_GPL(rt2800_write_tx_data);
528 static int rt2800_agc_to_rssi(struct rt2x00_dev *rt2x00dev, u32 rxwi_w2)
530 s8 rssi0 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI0);
531 s8 rssi1 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI1);
532 s8 rssi2 = rt2x00_get_field32(rxwi_w2, RXWI_W2_RSSI2);
538 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
539 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &eeprom);
540 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET0);
541 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG_OFFSET1);
542 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
543 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_OFFSET2);
545 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &eeprom);
546 offset0 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET0);
547 offset1 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A_OFFSET1);
548 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
549 offset2 = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_OFFSET2);
553 * Convert the value from the descriptor into the RSSI value
554 * If the value in the descriptor is 0, it is considered invalid
555 * and the default (extremely low) rssi value is assumed
557 rssi0 = (rssi0) ? (-12 - offset0 - rt2x00dev->lna_gain - rssi0) : -128;
558 rssi1 = (rssi1) ? (-12 - offset1 - rt2x00dev->lna_gain - rssi1) : -128;
559 rssi2 = (rssi2) ? (-12 - offset2 - rt2x00dev->lna_gain - rssi2) : -128;
562 * mac80211 only accepts a single RSSI value. Calculating the
563 * average doesn't deliver a fair answer either since -60:-60 would
564 * be considered equally good as -50:-70 while the second is the one
565 * which gives less energy...
567 rssi0 = max(rssi0, rssi1);
568 return (int)max(rssi0, rssi2);
571 void rt2800_process_rxwi(struct queue_entry *entry,
572 struct rxdone_entry_desc *rxdesc)
574 __le32 *rxwi = (__le32 *) entry->skb->data;
577 rt2x00_desc_read(rxwi, 0, &word);
579 rxdesc->cipher = rt2x00_get_field32(word, RXWI_W0_UDF);
580 rxdesc->size = rt2x00_get_field32(word, RXWI_W0_MPDU_TOTAL_BYTE_COUNT);
582 rt2x00_desc_read(rxwi, 1, &word);
584 if (rt2x00_get_field32(word, RXWI_W1_SHORT_GI))
585 rxdesc->flags |= RX_FLAG_SHORT_GI;
587 if (rt2x00_get_field32(word, RXWI_W1_BW))
588 rxdesc->flags |= RX_FLAG_40MHZ;
591 * Detect RX rate, always use MCS as signal type.
593 rxdesc->dev_flags |= RXDONE_SIGNAL_MCS;
594 rxdesc->signal = rt2x00_get_field32(word, RXWI_W1_MCS);
595 rxdesc->rate_mode = rt2x00_get_field32(word, RXWI_W1_PHYMODE);
598 * Mask of 0x8 bit to remove the short preamble flag.
600 if (rxdesc->rate_mode == RATE_MODE_CCK)
601 rxdesc->signal &= ~0x8;
603 rt2x00_desc_read(rxwi, 2, &word);
606 * Convert descriptor AGC value to RSSI value.
608 rxdesc->rssi = rt2800_agc_to_rssi(entry->queue->rt2x00dev, word);
611 * Remove RXWI descriptor from start of buffer.
613 skb_pull(entry->skb, RXWI_DESC_SIZE);
615 EXPORT_SYMBOL_GPL(rt2800_process_rxwi);
617 void rt2800_txdone_entry(struct queue_entry *entry, u32 status, __le32 *txwi)
619 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
620 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
621 struct txdone_entry_desc txdesc;
627 * Obtain the status about this packet.
630 rt2x00_desc_read(txwi, 0, &word);
632 mcs = rt2x00_get_field32(word, TXWI_W0_MCS);
633 ampdu = rt2x00_get_field32(word, TXWI_W0_AMPDU);
635 real_mcs = rt2x00_get_field32(status, TX_STA_FIFO_MCS);
636 aggr = rt2x00_get_field32(status, TX_STA_FIFO_TX_AGGRE);
639 * If a frame was meant to be sent as a single non-aggregated MPDU
640 * but ended up in an aggregate the used tx rate doesn't correlate
641 * with the one specified in the TXWI as the whole aggregate is sent
642 * with the same rate.
644 * For example: two frames are sent to rt2x00, the first one sets
645 * AMPDU=1 and requests MCS7 whereas the second frame sets AMDPU=0
646 * and requests MCS15. If the hw aggregates both frames into one
647 * AMDPU the tx status for both frames will contain MCS7 although
648 * the frame was sent successfully.
650 * Hence, replace the requested rate with the real tx rate to not
651 * confuse the rate control algortihm by providing clearly wrong
654 if (unlikely(aggr == 1 && ampdu == 0 && real_mcs != mcs)) {
655 skbdesc->tx_rate_idx = real_mcs;
659 if (aggr == 1 || ampdu == 1)
660 __set_bit(TXDONE_AMPDU, &txdesc.flags);
663 * Ralink has a retry mechanism using a global fallback
664 * table. We setup this fallback table to try the immediate
665 * lower rate for all rates. In the TX_STA_FIFO, the MCS field
666 * always contains the MCS used for the last transmission, be
667 * it successful or not.
669 if (rt2x00_get_field32(status, TX_STA_FIFO_TX_SUCCESS)) {
671 * Transmission succeeded. The number of retries is
674 __set_bit(TXDONE_SUCCESS, &txdesc.flags);
675 txdesc.retry = ((mcs > real_mcs) ? mcs - real_mcs : 0);
678 * Transmission failed. The number of retries is
679 * always 7 in this case (for a total number of 8
682 __set_bit(TXDONE_FAILURE, &txdesc.flags);
683 txdesc.retry = rt2x00dev->long_retry;
687 * the frame was retried at least once
688 * -> hw used fallback rates
691 __set_bit(TXDONE_FALLBACK, &txdesc.flags);
693 rt2x00lib_txdone(entry, &txdesc);
695 EXPORT_SYMBOL_GPL(rt2800_txdone_entry);
697 void rt2800_write_beacon(struct queue_entry *entry, struct txentry_desc *txdesc)
699 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
700 struct skb_frame_desc *skbdesc = get_skb_frame_desc(entry->skb);
701 unsigned int beacon_base;
702 unsigned int padding_len;
706 * Disable beaconing while we are reloading the beacon data,
707 * otherwise we might be sending out invalid data.
709 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, ®);
711 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0);
712 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
715 * Add space for the TXWI in front of the skb.
717 memset(skb_push(entry->skb, TXWI_DESC_SIZE), 0, TXWI_DESC_SIZE);
720 * Register descriptor details in skb frame descriptor.
722 skbdesc->flags |= SKBDESC_DESC_IN_SKB;
723 skbdesc->desc = entry->skb->data;
724 skbdesc->desc_len = TXWI_DESC_SIZE;
727 * Add the TXWI for the beacon to the skb.
729 rt2800_write_tx_data(entry, txdesc);
732 * Dump beacon to userspace through debugfs.
734 rt2x00debug_dump_frame(rt2x00dev, DUMP_FRAME_BEACON, entry->skb);
737 * Write entire beacon with TXWI and padding to register.
739 padding_len = roundup(entry->skb->len, 4) - entry->skb->len;
740 if (padding_len && skb_pad(entry->skb, padding_len)) {
741 ERROR(rt2x00dev, "Failure padding beacon, aborting\n");
742 /* skb freed by skb_pad() on failure */
744 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, orig_reg);
748 beacon_base = HW_BEACON_OFFSET(entry->entry_idx);
749 rt2800_register_multiwrite(rt2x00dev, beacon_base, entry->skb->data,
750 entry->skb->len + padding_len);
753 * Enable beaconing again.
755 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 1);
756 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
759 * Clean up beacon skb.
761 dev_kfree_skb_any(entry->skb);
764 EXPORT_SYMBOL_GPL(rt2800_write_beacon);
766 static inline void rt2800_clear_beacon_register(struct rt2x00_dev *rt2x00dev,
767 unsigned int beacon_base)
772 * For the Beacon base registers we only need to clear
773 * the whole TXWI which (when set to 0) will invalidate
776 for (i = 0; i < TXWI_DESC_SIZE; i += sizeof(__le32))
777 rt2800_register_write(rt2x00dev, beacon_base + i, 0);
780 void rt2800_clear_beacon(struct queue_entry *entry)
782 struct rt2x00_dev *rt2x00dev = entry->queue->rt2x00dev;
786 * Disable beaconing while we are reloading the beacon data,
787 * otherwise we might be sending out invalid data.
789 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, ®);
790 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0);
791 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
796 rt2800_clear_beacon_register(rt2x00dev,
797 HW_BEACON_OFFSET(entry->entry_idx));
800 * Enabled beaconing again.
802 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 1);
803 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
805 EXPORT_SYMBOL_GPL(rt2800_clear_beacon);
807 #ifdef CONFIG_RT2X00_LIB_DEBUGFS
808 const struct rt2x00debug rt2800_rt2x00debug = {
809 .owner = THIS_MODULE,
811 .read = rt2800_register_read,
812 .write = rt2800_register_write,
813 .flags = RT2X00DEBUGFS_OFFSET,
814 .word_base = CSR_REG_BASE,
815 .word_size = sizeof(u32),
816 .word_count = CSR_REG_SIZE / sizeof(u32),
819 .read = rt2x00_eeprom_read,
820 .write = rt2x00_eeprom_write,
821 .word_base = EEPROM_BASE,
822 .word_size = sizeof(u16),
823 .word_count = EEPROM_SIZE / sizeof(u16),
826 .read = rt2800_bbp_read,
827 .write = rt2800_bbp_write,
828 .word_base = BBP_BASE,
829 .word_size = sizeof(u8),
830 .word_count = BBP_SIZE / sizeof(u8),
833 .read = rt2x00_rf_read,
834 .write = rt2800_rf_write,
835 .word_base = RF_BASE,
836 .word_size = sizeof(u32),
837 .word_count = RF_SIZE / sizeof(u32),
840 .read = rt2800_rfcsr_read,
841 .write = rt2800_rfcsr_write,
842 .word_base = RFCSR_BASE,
843 .word_size = sizeof(u8),
844 .word_count = RFCSR_SIZE / sizeof(u8),
847 EXPORT_SYMBOL_GPL(rt2800_rt2x00debug);
848 #endif /* CONFIG_RT2X00_LIB_DEBUGFS */
850 int rt2800_rfkill_poll(struct rt2x00_dev *rt2x00dev)
854 if (rt2x00_rt(rt2x00dev, RT3290)) {
855 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, ®);
856 return rt2x00_get_field32(reg, WLAN_GPIO_IN_BIT0);
858 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, ®);
859 return rt2x00_get_field32(reg, GPIO_CTRL_CFG_BIT2);
862 EXPORT_SYMBOL_GPL(rt2800_rfkill_poll);
864 #ifdef CONFIG_RT2X00_LIB_LEDS
865 static void rt2800_brightness_set(struct led_classdev *led_cdev,
866 enum led_brightness brightness)
868 struct rt2x00_led *led =
869 container_of(led_cdev, struct rt2x00_led, led_dev);
870 unsigned int enabled = brightness != LED_OFF;
871 unsigned int bg_mode =
872 (enabled && led->rt2x00dev->curr_band == IEEE80211_BAND_2GHZ);
873 unsigned int polarity =
874 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
875 EEPROM_FREQ_LED_POLARITY);
876 unsigned int ledmode =
877 rt2x00_get_field16(led->rt2x00dev->led_mcu_reg,
878 EEPROM_FREQ_LED_MODE);
881 /* Check for SoC (SOC devices don't support MCU requests) */
882 if (rt2x00_is_soc(led->rt2x00dev)) {
883 rt2800_register_read(led->rt2x00dev, LED_CFG, ®);
885 /* Set LED Polarity */
886 rt2x00_set_field32(®, LED_CFG_LED_POLAR, polarity);
889 if (led->type == LED_TYPE_RADIO) {
890 rt2x00_set_field32(®, LED_CFG_G_LED_MODE,
892 } else if (led->type == LED_TYPE_ASSOC) {
893 rt2x00_set_field32(®, LED_CFG_Y_LED_MODE,
895 } else if (led->type == LED_TYPE_QUALITY) {
896 rt2x00_set_field32(®, LED_CFG_R_LED_MODE,
900 rt2800_register_write(led->rt2x00dev, LED_CFG, reg);
903 if (led->type == LED_TYPE_RADIO) {
904 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
906 } else if (led->type == LED_TYPE_ASSOC) {
907 rt2800_mcu_request(led->rt2x00dev, MCU_LED, 0xff, ledmode,
908 enabled ? (bg_mode ? 0x60 : 0xa0) : 0x20);
909 } else if (led->type == LED_TYPE_QUALITY) {
911 * The brightness is divided into 6 levels (0 - 5),
912 * The specs tell us the following levels:
914 * to determine the level in a simple way we can simply
915 * work with bitshifting:
918 rt2800_mcu_request(led->rt2x00dev, MCU_LED_STRENGTH, 0xff,
919 (1 << brightness / (LED_FULL / 6)) - 1,
925 static void rt2800_init_led(struct rt2x00_dev *rt2x00dev,
926 struct rt2x00_led *led, enum led_type type)
928 led->rt2x00dev = rt2x00dev;
930 led->led_dev.brightness_set = rt2800_brightness_set;
931 led->flags = LED_INITIALIZED;
933 #endif /* CONFIG_RT2X00_LIB_LEDS */
936 * Configuration handlers.
938 static void rt2800_config_wcid(struct rt2x00_dev *rt2x00dev,
942 struct mac_wcid_entry wcid_entry;
945 offset = MAC_WCID_ENTRY(wcid);
947 memset(&wcid_entry, 0xff, sizeof(wcid_entry));
949 memcpy(wcid_entry.mac, address, ETH_ALEN);
951 rt2800_register_multiwrite(rt2x00dev, offset,
952 &wcid_entry, sizeof(wcid_entry));
955 static void rt2800_delete_wcid_attr(struct rt2x00_dev *rt2x00dev, int wcid)
958 offset = MAC_WCID_ATTR_ENTRY(wcid);
959 rt2800_register_write(rt2x00dev, offset, 0);
962 static void rt2800_config_wcid_attr_bssidx(struct rt2x00_dev *rt2x00dev,
963 int wcid, u32 bssidx)
965 u32 offset = MAC_WCID_ATTR_ENTRY(wcid);
969 * The BSS Idx numbers is split in a main value of 3 bits,
970 * and a extended field for adding one additional bit to the value.
972 rt2800_register_read(rt2x00dev, offset, ®);
973 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_BSS_IDX, (bssidx & 0x7));
974 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_BSS_IDX_EXT,
975 (bssidx & 0x8) >> 3);
976 rt2800_register_write(rt2x00dev, offset, reg);
979 static void rt2800_config_wcid_attr_cipher(struct rt2x00_dev *rt2x00dev,
980 struct rt2x00lib_crypto *crypto,
981 struct ieee80211_key_conf *key)
983 struct mac_iveiv_entry iveiv_entry;
987 offset = MAC_WCID_ATTR_ENTRY(key->hw_key_idx);
989 if (crypto->cmd == SET_KEY) {
990 rt2800_register_read(rt2x00dev, offset, ®);
991 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_KEYTAB,
992 !!(key->flags & IEEE80211_KEY_FLAG_PAIRWISE));
994 * Both the cipher as the BSS Idx numbers are split in a main
995 * value of 3 bits, and a extended field for adding one additional
998 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER,
999 (crypto->cipher & 0x7));
1000 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER_EXT,
1001 (crypto->cipher & 0x8) >> 3);
1002 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_RX_WIUDF, crypto->cipher);
1003 rt2800_register_write(rt2x00dev, offset, reg);
1005 /* Delete the cipher without touching the bssidx */
1006 rt2800_register_read(rt2x00dev, offset, ®);
1007 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_KEYTAB, 0);
1008 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER, 0);
1009 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_CIPHER_EXT, 0);
1010 rt2x00_set_field32(®, MAC_WCID_ATTRIBUTE_RX_WIUDF, 0);
1011 rt2800_register_write(rt2x00dev, offset, reg);
1014 offset = MAC_IVEIV_ENTRY(key->hw_key_idx);
1016 memset(&iveiv_entry, 0, sizeof(iveiv_entry));
1017 if ((crypto->cipher == CIPHER_TKIP) ||
1018 (crypto->cipher == CIPHER_TKIP_NO_MIC) ||
1019 (crypto->cipher == CIPHER_AES))
1020 iveiv_entry.iv[3] |= 0x20;
1021 iveiv_entry.iv[3] |= key->keyidx << 6;
1022 rt2800_register_multiwrite(rt2x00dev, offset,
1023 &iveiv_entry, sizeof(iveiv_entry));
1026 int rt2800_config_shared_key(struct rt2x00_dev *rt2x00dev,
1027 struct rt2x00lib_crypto *crypto,
1028 struct ieee80211_key_conf *key)
1030 struct hw_key_entry key_entry;
1031 struct rt2x00_field32 field;
1035 if (crypto->cmd == SET_KEY) {
1036 key->hw_key_idx = (4 * crypto->bssidx) + key->keyidx;
1038 memcpy(key_entry.key, crypto->key,
1039 sizeof(key_entry.key));
1040 memcpy(key_entry.tx_mic, crypto->tx_mic,
1041 sizeof(key_entry.tx_mic));
1042 memcpy(key_entry.rx_mic, crypto->rx_mic,
1043 sizeof(key_entry.rx_mic));
1045 offset = SHARED_KEY_ENTRY(key->hw_key_idx);
1046 rt2800_register_multiwrite(rt2x00dev, offset,
1047 &key_entry, sizeof(key_entry));
1051 * The cipher types are stored over multiple registers
1052 * starting with SHARED_KEY_MODE_BASE each word will have
1053 * 32 bits and contains the cipher types for 2 bssidx each.
1054 * Using the correct defines correctly will cause overhead,
1055 * so just calculate the correct offset.
1057 field.bit_offset = 4 * (key->hw_key_idx % 8);
1058 field.bit_mask = 0x7 << field.bit_offset;
1060 offset = SHARED_KEY_MODE_ENTRY(key->hw_key_idx / 8);
1062 rt2800_register_read(rt2x00dev, offset, ®);
1063 rt2x00_set_field32(®, field,
1064 (crypto->cmd == SET_KEY) * crypto->cipher);
1065 rt2800_register_write(rt2x00dev, offset, reg);
1068 * Update WCID information
1070 rt2800_config_wcid(rt2x00dev, crypto->address, key->hw_key_idx);
1071 rt2800_config_wcid_attr_bssidx(rt2x00dev, key->hw_key_idx,
1073 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1077 EXPORT_SYMBOL_GPL(rt2800_config_shared_key);
1079 static inline int rt2800_find_wcid(struct rt2x00_dev *rt2x00dev)
1081 struct mac_wcid_entry wcid_entry;
1086 * Search for the first free WCID entry and return the corresponding
1089 * Make sure the WCID starts _after_ the last possible shared key
1092 * Since parts of the pairwise key table might be shared with
1093 * the beacon frame buffers 6 & 7 we should only write into the
1094 * first 222 entries.
1096 for (idx = 33; idx <= 222; idx++) {
1097 offset = MAC_WCID_ENTRY(idx);
1098 rt2800_register_multiread(rt2x00dev, offset, &wcid_entry,
1099 sizeof(wcid_entry));
1100 if (is_broadcast_ether_addr(wcid_entry.mac))
1105 * Use -1 to indicate that we don't have any more space in the WCID
1111 int rt2800_config_pairwise_key(struct rt2x00_dev *rt2x00dev,
1112 struct rt2x00lib_crypto *crypto,
1113 struct ieee80211_key_conf *key)
1115 struct hw_key_entry key_entry;
1118 if (crypto->cmd == SET_KEY) {
1120 * Allow key configuration only for STAs that are
1123 if (crypto->wcid < 0)
1125 key->hw_key_idx = crypto->wcid;
1127 memcpy(key_entry.key, crypto->key,
1128 sizeof(key_entry.key));
1129 memcpy(key_entry.tx_mic, crypto->tx_mic,
1130 sizeof(key_entry.tx_mic));
1131 memcpy(key_entry.rx_mic, crypto->rx_mic,
1132 sizeof(key_entry.rx_mic));
1134 offset = PAIRWISE_KEY_ENTRY(key->hw_key_idx);
1135 rt2800_register_multiwrite(rt2x00dev, offset,
1136 &key_entry, sizeof(key_entry));
1140 * Update WCID information
1142 rt2800_config_wcid_attr_cipher(rt2x00dev, crypto, key);
1146 EXPORT_SYMBOL_GPL(rt2800_config_pairwise_key);
1148 int rt2800_sta_add(struct rt2x00_dev *rt2x00dev, struct ieee80211_vif *vif,
1149 struct ieee80211_sta *sta)
1152 struct rt2x00_sta *sta_priv = sta_to_rt2x00_sta(sta);
1155 * Find next free WCID.
1157 wcid = rt2800_find_wcid(rt2x00dev);
1160 * Store selected wcid even if it is invalid so that we can
1161 * later decide if the STA is uploaded into the hw.
1163 sta_priv->wcid = wcid;
1166 * No space left in the device, however, we can still communicate
1167 * with the STA -> No error.
1173 * Clean up WCID attributes and write STA address to the device.
1175 rt2800_delete_wcid_attr(rt2x00dev, wcid);
1176 rt2800_config_wcid(rt2x00dev, sta->addr, wcid);
1177 rt2800_config_wcid_attr_bssidx(rt2x00dev, wcid,
1178 rt2x00lib_get_bssidx(rt2x00dev, vif));
1181 EXPORT_SYMBOL_GPL(rt2800_sta_add);
1183 int rt2800_sta_remove(struct rt2x00_dev *rt2x00dev, int wcid)
1186 * Remove WCID entry, no need to clean the attributes as they will
1187 * get renewed when the WCID is reused.
1189 rt2800_config_wcid(rt2x00dev, NULL, wcid);
1193 EXPORT_SYMBOL_GPL(rt2800_sta_remove);
1195 void rt2800_config_filter(struct rt2x00_dev *rt2x00dev,
1196 const unsigned int filter_flags)
1201 * Start configuration steps.
1202 * Note that the version error will always be dropped
1203 * and broadcast frames will always be accepted since
1204 * there is no filter for it at this time.
1206 rt2800_register_read(rt2x00dev, RX_FILTER_CFG, ®);
1207 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CRC_ERROR,
1208 !(filter_flags & FIF_FCSFAIL));
1209 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_PHY_ERROR,
1210 !(filter_flags & FIF_PLCPFAIL));
1211 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_NOT_TO_ME,
1212 !(filter_flags & FIF_PROMISC_IN_BSS));
1213 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_NOT_MY_BSSD, 0);
1214 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_VER_ERROR, 1);
1215 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_MULTICAST,
1216 !(filter_flags & FIF_ALLMULTI));
1217 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BROADCAST, 0);
1218 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_DUPLICATE, 1);
1219 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CF_END_ACK,
1220 !(filter_flags & FIF_CONTROL));
1221 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CF_END,
1222 !(filter_flags & FIF_CONTROL));
1223 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_ACK,
1224 !(filter_flags & FIF_CONTROL));
1225 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CTS,
1226 !(filter_flags & FIF_CONTROL));
1227 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_RTS,
1228 !(filter_flags & FIF_CONTROL));
1229 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_PSPOLL,
1230 !(filter_flags & FIF_PSPOLL));
1231 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BA,
1232 !(filter_flags & FIF_CONTROL));
1233 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_BAR,
1234 !(filter_flags & FIF_CONTROL));
1235 rt2x00_set_field32(®, RX_FILTER_CFG_DROP_CNTL,
1236 !(filter_flags & FIF_CONTROL));
1237 rt2800_register_write(rt2x00dev, RX_FILTER_CFG, reg);
1239 EXPORT_SYMBOL_GPL(rt2800_config_filter);
1241 void rt2800_config_intf(struct rt2x00_dev *rt2x00dev, struct rt2x00_intf *intf,
1242 struct rt2x00intf_conf *conf, const unsigned int flags)
1245 bool update_bssid = false;
1247 if (flags & CONFIG_UPDATE_TYPE) {
1249 * Enable synchronisation.
1251 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, ®);
1252 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_SYNC, conf->sync);
1253 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1255 if (conf->sync == TSF_SYNC_AP_NONE) {
1257 * Tune beacon queue transmit parameters for AP mode
1259 rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, ®);
1260 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_CWMIN, 0);
1261 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_AIFSN, 1);
1262 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1263 rt2x00_set_field32(®, TBTT_SYNC_CFG_TBTT_ADJUST, 0);
1264 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1266 rt2800_register_read(rt2x00dev, TBTT_SYNC_CFG, ®);
1267 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_CWMIN, 4);
1268 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_AIFSN, 2);
1269 rt2x00_set_field32(®, TBTT_SYNC_CFG_BCN_EXP_WIN, 32);
1270 rt2x00_set_field32(®, TBTT_SYNC_CFG_TBTT_ADJUST, 16);
1271 rt2800_register_write(rt2x00dev, TBTT_SYNC_CFG, reg);
1275 if (flags & CONFIG_UPDATE_MAC) {
1276 if (flags & CONFIG_UPDATE_TYPE &&
1277 conf->sync == TSF_SYNC_AP_NONE) {
1279 * The BSSID register has to be set to our own mac
1280 * address in AP mode.
1282 memcpy(conf->bssid, conf->mac, sizeof(conf->mac));
1283 update_bssid = true;
1286 if (!is_zero_ether_addr((const u8 *)conf->mac)) {
1287 reg = le32_to_cpu(conf->mac[1]);
1288 rt2x00_set_field32(®, MAC_ADDR_DW1_UNICAST_TO_ME_MASK, 0xff);
1289 conf->mac[1] = cpu_to_le32(reg);
1292 rt2800_register_multiwrite(rt2x00dev, MAC_ADDR_DW0,
1293 conf->mac, sizeof(conf->mac));
1296 if ((flags & CONFIG_UPDATE_BSSID) || update_bssid) {
1297 if (!is_zero_ether_addr((const u8 *)conf->bssid)) {
1298 reg = le32_to_cpu(conf->bssid[1]);
1299 rt2x00_set_field32(®, MAC_BSSID_DW1_BSS_ID_MASK, 3);
1300 rt2x00_set_field32(®, MAC_BSSID_DW1_BSS_BCN_NUM, 7);
1301 conf->bssid[1] = cpu_to_le32(reg);
1304 rt2800_register_multiwrite(rt2x00dev, MAC_BSSID_DW0,
1305 conf->bssid, sizeof(conf->bssid));
1308 EXPORT_SYMBOL_GPL(rt2800_config_intf);
1310 static void rt2800_config_ht_opmode(struct rt2x00_dev *rt2x00dev,
1311 struct rt2x00lib_erp *erp)
1313 bool any_sta_nongf = !!(erp->ht_opmode &
1314 IEEE80211_HT_OP_MODE_NON_GF_STA_PRSNT);
1315 u8 protection = erp->ht_opmode & IEEE80211_HT_OP_MODE_PROTECTION;
1316 u8 mm20_mode, mm40_mode, gf20_mode, gf40_mode;
1317 u16 mm20_rate, mm40_rate, gf20_rate, gf40_rate;
1320 /* default protection rate for HT20: OFDM 24M */
1321 mm20_rate = gf20_rate = 0x4004;
1323 /* default protection rate for HT40: duplicate OFDM 24M */
1324 mm40_rate = gf40_rate = 0x4084;
1326 switch (protection) {
1327 case IEEE80211_HT_OP_MODE_PROTECTION_NONE:
1329 * All STAs in this BSS are HT20/40 but there might be
1330 * STAs not supporting greenfield mode.
1331 * => Disable protection for HT transmissions.
1333 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 0;
1336 case IEEE80211_HT_OP_MODE_PROTECTION_20MHZ:
1338 * All STAs in this BSS are HT20 or HT20/40 but there
1339 * might be STAs not supporting greenfield mode.
1340 * => Protect all HT40 transmissions.
1342 mm20_mode = gf20_mode = 0;
1343 mm40_mode = gf40_mode = 2;
1346 case IEEE80211_HT_OP_MODE_PROTECTION_NONMEMBER:
1348 * Nonmember protection:
1349 * According to 802.11n we _should_ protect all
1350 * HT transmissions (but we don't have to).
1352 * But if cts_protection is enabled we _shall_ protect
1353 * all HT transmissions using a CCK rate.
1355 * And if any station is non GF we _shall_ protect
1358 * We decide to protect everything
1359 * -> fall through to mixed mode.
1361 case IEEE80211_HT_OP_MODE_PROTECTION_NONHT_MIXED:
1363 * Legacy STAs are present
1364 * => Protect all HT transmissions.
1366 mm20_mode = mm40_mode = gf20_mode = gf40_mode = 2;
1369 * If erp protection is needed we have to protect HT
1370 * transmissions with CCK 11M long preamble.
1372 if (erp->cts_protection) {
1373 /* don't duplicate RTS/CTS in CCK mode */
1374 mm20_rate = mm40_rate = 0x0003;
1375 gf20_rate = gf40_rate = 0x0003;
1380 /* check for STAs not supporting greenfield mode */
1382 gf20_mode = gf40_mode = 2;
1384 /* Update HT protection config */
1385 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, ®);
1386 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_RATE, mm20_rate);
1387 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_CTRL, mm20_mode);
1388 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
1390 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, ®);
1391 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_RATE, mm40_rate);
1392 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_CTRL, mm40_mode);
1393 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
1395 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, ®);
1396 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_RATE, gf20_rate);
1397 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_CTRL, gf20_mode);
1398 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
1400 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, ®);
1401 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_RATE, gf40_rate);
1402 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_CTRL, gf40_mode);
1403 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
1406 void rt2800_config_erp(struct rt2x00_dev *rt2x00dev, struct rt2x00lib_erp *erp,
1411 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
1412 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, ®);
1413 rt2x00_set_field32(®, AUTO_RSP_CFG_BAC_ACK_POLICY,
1414 !!erp->short_preamble);
1415 rt2x00_set_field32(®, AUTO_RSP_CFG_AR_PREAMBLE,
1416 !!erp->short_preamble);
1417 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
1420 if (changed & BSS_CHANGED_ERP_CTS_PROT) {
1421 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, ®);
1422 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_CTRL,
1423 erp->cts_protection ? 2 : 0);
1424 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
1427 if (changed & BSS_CHANGED_BASIC_RATES) {
1428 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE,
1430 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
1433 if (changed & BSS_CHANGED_ERP_SLOT) {
1434 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, ®);
1435 rt2x00_set_field32(®, BKOFF_SLOT_CFG_SLOT_TIME,
1437 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
1439 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, ®);
1440 rt2x00_set_field32(®, XIFS_TIME_CFG_EIFS, erp->eifs);
1441 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
1444 if (changed & BSS_CHANGED_BEACON_INT) {
1445 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, ®);
1446 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL,
1447 erp->beacon_int * 16);
1448 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
1451 if (changed & BSS_CHANGED_HT)
1452 rt2800_config_ht_opmode(rt2x00dev, erp);
1454 EXPORT_SYMBOL_GPL(rt2800_config_erp);
1456 static void rt2800_config_3572bt_ant(struct rt2x00_dev *rt2x00dev)
1460 u8 led_ctrl, led_g_mode, led_r_mode;
1462 rt2800_register_read(rt2x00dev, GPIO_SWITCH, ®);
1463 if (rt2x00dev->curr_band == IEEE80211_BAND_5GHZ) {
1464 rt2x00_set_field32(®, GPIO_SWITCH_0, 1);
1465 rt2x00_set_field32(®, GPIO_SWITCH_1, 1);
1467 rt2x00_set_field32(®, GPIO_SWITCH_0, 0);
1468 rt2x00_set_field32(®, GPIO_SWITCH_1, 0);
1470 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
1472 rt2800_register_read(rt2x00dev, LED_CFG, ®);
1473 led_g_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 3 : 0;
1474 led_r_mode = rt2x00_get_field32(reg, LED_CFG_LED_POLAR) ? 0 : 3;
1475 if (led_g_mode != rt2x00_get_field32(reg, LED_CFG_G_LED_MODE) ||
1476 led_r_mode != rt2x00_get_field32(reg, LED_CFG_R_LED_MODE)) {
1477 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
1478 led_ctrl = rt2x00_get_field16(eeprom, EEPROM_FREQ_LED_MODE);
1479 if (led_ctrl == 0 || led_ctrl > 0x40) {
1480 rt2x00_set_field32(®, LED_CFG_G_LED_MODE, led_g_mode);
1481 rt2x00_set_field32(®, LED_CFG_R_LED_MODE, led_r_mode);
1482 rt2800_register_write(rt2x00dev, LED_CFG, reg);
1484 rt2800_mcu_request(rt2x00dev, MCU_BAND_SELECT, 0xff,
1485 (led_g_mode << 2) | led_r_mode, 1);
1490 static void rt2800_set_ant_diversity(struct rt2x00_dev *rt2x00dev,
1494 u8 eesk_pin = (ant == ANTENNA_A) ? 1 : 0;
1495 u8 gpio_bit3 = (ant == ANTENNA_A) ? 0 : 1;
1497 if (rt2x00_is_pci(rt2x00dev)) {
1498 rt2800_register_read(rt2x00dev, E2PROM_CSR, ®);
1499 rt2x00_set_field32(®, E2PROM_CSR_DATA_CLOCK, eesk_pin);
1500 rt2800_register_write(rt2x00dev, E2PROM_CSR, reg);
1501 } else if (rt2x00_is_usb(rt2x00dev))
1502 rt2800_mcu_request(rt2x00dev, MCU_ANT_SELECT, 0xff,
1505 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, ®);
1506 rt2x00_set_field32(®, GPIO_CTRL_CFG_GPIOD_BIT3, 0);
1507 rt2x00_set_field32(®, GPIO_CTRL_CFG_BIT3, gpio_bit3);
1508 rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
1511 void rt2800_config_ant(struct rt2x00_dev *rt2x00dev, struct antenna_setup *ant)
1517 rt2800_bbp_read(rt2x00dev, 1, &r1);
1518 rt2800_bbp_read(rt2x00dev, 3, &r3);
1520 if (rt2x00_rt(rt2x00dev, RT3572) &&
1521 test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1522 rt2800_config_3572bt_ant(rt2x00dev);
1525 * Configure the TX antenna.
1527 switch (ant->tx_chain_num) {
1529 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1532 if (rt2x00_rt(rt2x00dev, RT3572) &&
1533 test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
1534 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 1);
1536 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 2);
1539 rt2x00_set_field8(&r1, BBP1_TX_ANTENNA, 0);
1544 * Configure the RX antenna.
1546 switch (ant->rx_chain_num) {
1548 if (rt2x00_rt(rt2x00dev, RT3070) ||
1549 rt2x00_rt(rt2x00dev, RT3090) ||
1550 rt2x00_rt(rt2x00dev, RT3390)) {
1551 rt2x00_eeprom_read(rt2x00dev,
1552 EEPROM_NIC_CONF1, &eeprom);
1553 if (rt2x00_get_field16(eeprom,
1554 EEPROM_NIC_CONF1_ANT_DIVERSITY))
1555 rt2800_set_ant_diversity(rt2x00dev,
1556 rt2x00dev->default_ant.rx);
1558 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 0);
1561 if (rt2x00_rt(rt2x00dev, RT3572) &&
1562 test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
1563 rt2x00_set_field8(&r3, BBP3_RX_ADC, 1);
1564 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA,
1565 rt2x00dev->curr_band == IEEE80211_BAND_5GHZ);
1566 rt2800_set_ant_diversity(rt2x00dev, ANTENNA_B);
1568 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 1);
1572 rt2x00_set_field8(&r3, BBP3_RX_ANTENNA, 2);
1576 rt2800_bbp_write(rt2x00dev, 3, r3);
1577 rt2800_bbp_write(rt2x00dev, 1, r1);
1579 EXPORT_SYMBOL_GPL(rt2800_config_ant);
1581 static void rt2800_config_lna_gain(struct rt2x00_dev *rt2x00dev,
1582 struct rt2x00lib_conf *libconf)
1587 if (libconf->rf.channel <= 14) {
1588 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1589 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_BG);
1590 } else if (libconf->rf.channel <= 64) {
1591 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &eeprom);
1592 lna_gain = rt2x00_get_field16(eeprom, EEPROM_LNA_A0);
1593 } else if (libconf->rf.channel <= 128) {
1594 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &eeprom);
1595 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_BG2_LNA_A1);
1597 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &eeprom);
1598 lna_gain = rt2x00_get_field16(eeprom, EEPROM_RSSI_A2_LNA_A2);
1601 rt2x00dev->lna_gain = lna_gain;
1604 static void rt2800_config_channel_rf2xxx(struct rt2x00_dev *rt2x00dev,
1605 struct ieee80211_conf *conf,
1606 struct rf_channel *rf,
1607 struct channel_info *info)
1609 rt2x00_set_field32(&rf->rf4, RF4_FREQ_OFFSET, rt2x00dev->freq_offset);
1611 if (rt2x00dev->default_ant.tx_chain_num == 1)
1612 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_TX1, 1);
1614 if (rt2x00dev->default_ant.rx_chain_num == 1) {
1615 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX1, 1);
1616 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1617 } else if (rt2x00dev->default_ant.rx_chain_num == 2)
1618 rt2x00_set_field32(&rf->rf2, RF2_ANTENNA_RX2, 1);
1620 if (rf->channel > 14) {
1622 * When TX power is below 0, we should increase it by 7 to
1623 * make it a positive value (Minimum value is -7).
1624 * However this means that values between 0 and 7 have
1625 * double meaning, and we should set a 7DBm boost flag.
1627 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A_7DBM_BOOST,
1628 (info->default_power1 >= 0));
1630 if (info->default_power1 < 0)
1631 info->default_power1 += 7;
1633 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_A, info->default_power1);
1635 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A_7DBM_BOOST,
1636 (info->default_power2 >= 0));
1638 if (info->default_power2 < 0)
1639 info->default_power2 += 7;
1641 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_A, info->default_power2);
1643 rt2x00_set_field32(&rf->rf3, RF3_TXPOWER_G, info->default_power1);
1644 rt2x00_set_field32(&rf->rf4, RF4_TXPOWER_G, info->default_power2);
1647 rt2x00_set_field32(&rf->rf4, RF4_HT40, conf_is_ht40(conf));
1649 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1650 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1651 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1652 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1656 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1657 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1658 rt2800_rf_write(rt2x00dev, 3, rf->rf3 | 0x00000004);
1659 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1663 rt2800_rf_write(rt2x00dev, 1, rf->rf1);
1664 rt2800_rf_write(rt2x00dev, 2, rf->rf2);
1665 rt2800_rf_write(rt2x00dev, 3, rf->rf3 & ~0x00000004);
1666 rt2800_rf_write(rt2x00dev, 4, rf->rf4);
1669 static void rt2800_config_channel_rf3xxx(struct rt2x00_dev *rt2x00dev,
1670 struct ieee80211_conf *conf,
1671 struct rf_channel *rf,
1672 struct channel_info *info)
1674 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1675 u8 rfcsr, calib_tx, calib_rx;
1677 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
1679 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
1680 rt2x00_set_field8(&rfcsr, RFCSR3_K, rf->rf3);
1681 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
1683 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1684 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
1685 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1687 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
1688 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER, info->default_power1);
1689 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1691 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
1692 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER, info->default_power2);
1693 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1695 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1696 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
1697 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
1698 if (rt2x00_rt(rt2x00dev, RT3390)) {
1699 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD,
1700 rt2x00dev->default_ant.rx_chain_num == 1);
1701 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD,
1702 rt2x00dev->default_ant.tx_chain_num == 1);
1704 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
1705 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
1706 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
1707 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
1709 switch (rt2x00dev->default_ant.tx_chain_num) {
1711 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
1714 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
1718 switch (rt2x00dev->default_ant.rx_chain_num) {
1720 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
1723 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
1727 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1729 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1730 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1731 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1733 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1734 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1736 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1737 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1738 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1740 if (rt2x00_rt(rt2x00dev, RT3390)) {
1741 calib_tx = conf_is_ht40(conf) ? 0x68 : 0x4f;
1742 calib_rx = conf_is_ht40(conf) ? 0x6f : 0x4f;
1744 if (conf_is_ht40(conf)) {
1745 calib_tx = drv_data->calibration_bw40;
1746 calib_rx = drv_data->calibration_bw40;
1748 calib_tx = drv_data->calibration_bw20;
1749 calib_rx = drv_data->calibration_bw20;
1753 rt2800_rfcsr_read(rt2x00dev, 24, &rfcsr);
1754 rt2x00_set_field8(&rfcsr, RFCSR24_TX_CALIB, calib_tx);
1755 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr);
1757 rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
1758 rt2x00_set_field8(&rfcsr, RFCSR31_RX_CALIB, calib_rx);
1759 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
1761 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1762 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
1763 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1765 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
1766 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
1767 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1769 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
1770 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
1773 static void rt2800_config_channel_rf3052(struct rt2x00_dev *rt2x00dev,
1774 struct ieee80211_conf *conf,
1775 struct rf_channel *rf,
1776 struct channel_info *info)
1778 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
1782 if (rf->channel <= 14) {
1783 rt2800_bbp_write(rt2x00dev, 25, drv_data->bbp25);
1784 rt2800_bbp_write(rt2x00dev, 26, drv_data->bbp26);
1786 rt2800_bbp_write(rt2x00dev, 25, 0x09);
1787 rt2800_bbp_write(rt2x00dev, 26, 0xff);
1790 rt2800_rfcsr_write(rt2x00dev, 2, rf->rf1);
1791 rt2800_rfcsr_write(rt2x00dev, 3, rf->rf3);
1793 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
1794 rt2x00_set_field8(&rfcsr, RFCSR6_R1, rf->rf2);
1795 if (rf->channel <= 14)
1796 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 2);
1798 rt2x00_set_field8(&rfcsr, RFCSR6_TXDIV, 1);
1799 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
1801 rt2800_rfcsr_read(rt2x00dev, 5, &rfcsr);
1802 if (rf->channel <= 14)
1803 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 1);
1805 rt2x00_set_field8(&rfcsr, RFCSR5_R1, 2);
1806 rt2800_rfcsr_write(rt2x00dev, 5, rfcsr);
1808 rt2800_rfcsr_read(rt2x00dev, 12, &rfcsr);
1809 if (rf->channel <= 14) {
1810 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 3);
1811 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
1812 info->default_power1);
1814 rt2x00_set_field8(&rfcsr, RFCSR12_DR0, 7);
1815 rt2x00_set_field8(&rfcsr, RFCSR12_TX_POWER,
1816 (info->default_power1 & 0x3) |
1817 ((info->default_power1 & 0xC) << 1));
1819 rt2800_rfcsr_write(rt2x00dev, 12, rfcsr);
1821 rt2800_rfcsr_read(rt2x00dev, 13, &rfcsr);
1822 if (rf->channel <= 14) {
1823 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 3);
1824 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
1825 info->default_power2);
1827 rt2x00_set_field8(&rfcsr, RFCSR13_DR0, 7);
1828 rt2x00_set_field8(&rfcsr, RFCSR13_TX_POWER,
1829 (info->default_power2 & 0x3) |
1830 ((info->default_power2 & 0xC) << 1));
1832 rt2800_rfcsr_write(rt2x00dev, 13, rfcsr);
1834 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
1835 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
1836 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
1837 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 0);
1838 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 0);
1839 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 0);
1840 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 0);
1841 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
1842 if (rf->channel <= 14) {
1843 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
1844 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
1846 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
1847 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
1849 switch (rt2x00dev->default_ant.tx_chain_num) {
1851 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
1853 rt2x00_set_field8(&rfcsr, RFCSR1_TX2_PD, 1);
1857 switch (rt2x00dev->default_ant.rx_chain_num) {
1859 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
1861 rt2x00_set_field8(&rfcsr, RFCSR1_RX2_PD, 1);
1865 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
1867 rt2800_rfcsr_read(rt2x00dev, 23, &rfcsr);
1868 rt2x00_set_field8(&rfcsr, RFCSR23_FREQ_OFFSET, rt2x00dev->freq_offset);
1869 rt2800_rfcsr_write(rt2x00dev, 23, rfcsr);
1871 if (conf_is_ht40(conf)) {
1872 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw40);
1873 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw40);
1875 rt2800_rfcsr_write(rt2x00dev, 24, drv_data->calibration_bw20);
1876 rt2800_rfcsr_write(rt2x00dev, 31, drv_data->calibration_bw20);
1879 if (rf->channel <= 14) {
1880 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
1881 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
1882 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
1883 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
1884 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
1886 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
1887 drv_data->txmixer_gain_24g);
1888 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
1889 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
1890 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
1891 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
1892 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
1893 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
1894 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
1895 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
1897 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1898 rt2x00_set_field8(&rfcsr, RFCSR7_BIT2, 1);
1899 rt2x00_set_field8(&rfcsr, RFCSR7_BIT3, 0);
1900 rt2x00_set_field8(&rfcsr, RFCSR7_BIT4, 1);
1901 rt2x00_set_field8(&rfcsr, RFCSR7_BITS67, 0);
1902 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1903 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
1904 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
1905 rt2800_rfcsr_write(rt2x00dev, 11, 0x00);
1906 rt2800_rfcsr_write(rt2x00dev, 15, 0x43);
1908 rt2x00_set_field8(&rfcsr, RFCSR16_TXMIXER_GAIN,
1909 drv_data->txmixer_gain_5g);
1910 rt2800_rfcsr_write(rt2x00dev, 16, rfcsr);
1911 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
1912 if (rf->channel <= 64) {
1913 rt2800_rfcsr_write(rt2x00dev, 19, 0xb7);
1914 rt2800_rfcsr_write(rt2x00dev, 20, 0xf6);
1915 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
1916 } else if (rf->channel <= 128) {
1917 rt2800_rfcsr_write(rt2x00dev, 19, 0x74);
1918 rt2800_rfcsr_write(rt2x00dev, 20, 0xf4);
1919 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1921 rt2800_rfcsr_write(rt2x00dev, 19, 0x72);
1922 rt2800_rfcsr_write(rt2x00dev, 20, 0xf3);
1923 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
1925 rt2800_rfcsr_write(rt2x00dev, 26, 0x87);
1926 rt2800_rfcsr_write(rt2x00dev, 27, 0x01);
1927 rt2800_rfcsr_write(rt2x00dev, 29, 0x9f);
1930 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, ®);
1931 rt2x00_set_field32(®, GPIO_CTRL_CFG_GPIOD_BIT7, 0);
1932 if (rf->channel <= 14)
1933 rt2x00_set_field32(®, GPIO_CTRL_CFG_BIT7, 1);
1935 rt2x00_set_field32(®, GPIO_CTRL_CFG_BIT7, 0);
1936 rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
1938 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
1939 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
1940 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
1943 #define POWER_BOUND 0x27
1944 #define FREQ_OFFSET_BOUND 0x5f
1946 static void rt2800_config_channel_rf3290(struct rt2x00_dev *rt2x00dev,
1947 struct ieee80211_conf *conf,
1948 struct rf_channel *rf,
1949 struct channel_info *info)
1953 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
1954 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
1955 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
1956 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
1957 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
1959 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
1960 if (info->default_power1 > POWER_BOUND)
1961 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
1963 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
1964 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
1966 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
1967 if (rt2x00dev->freq_offset > FREQ_OFFSET_BOUND)
1968 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, FREQ_OFFSET_BOUND);
1970 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, rt2x00dev->freq_offset);
1971 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
1973 if (rf->channel <= 14) {
1974 if (rf->channel == 6)
1975 rt2800_bbp_write(rt2x00dev, 68, 0x0c);
1977 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
1979 if (rf->channel >= 1 && rf->channel <= 6)
1980 rt2800_bbp_write(rt2x00dev, 59, 0x0f);
1981 else if (rf->channel >= 7 && rf->channel <= 11)
1982 rt2800_bbp_write(rt2x00dev, 59, 0x0e);
1983 else if (rf->channel >= 12 && rf->channel <= 14)
1984 rt2800_bbp_write(rt2x00dev, 59, 0x0d);
1988 static void rt2800_config_channel_rf53xx(struct rt2x00_dev *rt2x00dev,
1989 struct ieee80211_conf *conf,
1990 struct rf_channel *rf,
1991 struct channel_info *info)
1995 rt2800_rfcsr_write(rt2x00dev, 8, rf->rf1);
1996 rt2800_rfcsr_write(rt2x00dev, 9, rf->rf3);
1997 rt2800_rfcsr_read(rt2x00dev, 11, &rfcsr);
1998 rt2x00_set_field8(&rfcsr, RFCSR11_R, rf->rf2);
1999 rt2800_rfcsr_write(rt2x00dev, 11, rfcsr);
2001 rt2800_rfcsr_read(rt2x00dev, 49, &rfcsr);
2002 if (info->default_power1 > POWER_BOUND)
2003 rt2x00_set_field8(&rfcsr, RFCSR49_TX, POWER_BOUND);
2005 rt2x00_set_field8(&rfcsr, RFCSR49_TX, info->default_power1);
2006 rt2800_rfcsr_write(rt2x00dev, 49, rfcsr);
2008 if (rt2x00_rt(rt2x00dev, RT5392)) {
2009 rt2800_rfcsr_read(rt2x00dev, 50, &rfcsr);
2010 if (info->default_power1 > POWER_BOUND)
2011 rt2x00_set_field8(&rfcsr, RFCSR50_TX, POWER_BOUND);
2013 rt2x00_set_field8(&rfcsr, RFCSR50_TX,
2014 info->default_power2);
2015 rt2800_rfcsr_write(rt2x00dev, 50, rfcsr);
2018 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
2019 if (rt2x00_rt(rt2x00dev, RT5392)) {
2020 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
2021 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
2023 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
2024 rt2x00_set_field8(&rfcsr, RFCSR1_PLL_PD, 1);
2025 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 1);
2026 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 1);
2027 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
2029 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
2030 if (rt2x00dev->freq_offset > FREQ_OFFSET_BOUND)
2031 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, FREQ_OFFSET_BOUND);
2033 rt2x00_set_field8(&rfcsr, RFCSR17_CODE, rt2x00dev->freq_offset);
2034 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
2036 if (rf->channel <= 14) {
2037 int idx = rf->channel-1;
2039 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
2040 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
2041 /* r55/r59 value array of channel 1~14 */
2042 static const char r55_bt_rev[] = {0x83, 0x83,
2043 0x83, 0x73, 0x73, 0x63, 0x53, 0x53,
2044 0x53, 0x43, 0x43, 0x43, 0x43, 0x43};
2045 static const char r59_bt_rev[] = {0x0e, 0x0e,
2046 0x0e, 0x0e, 0x0e, 0x0b, 0x0a, 0x09,
2047 0x07, 0x07, 0x07, 0x07, 0x07, 0x07};
2049 rt2800_rfcsr_write(rt2x00dev, 55,
2051 rt2800_rfcsr_write(rt2x00dev, 59,
2054 static const char r59_bt[] = {0x8b, 0x8b, 0x8b,
2055 0x8b, 0x8b, 0x8b, 0x8b, 0x8a, 0x89,
2056 0x88, 0x88, 0x86, 0x85, 0x84};
2058 rt2800_rfcsr_write(rt2x00dev, 59, r59_bt[idx]);
2061 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F)) {
2062 static const char r55_nonbt_rev[] = {0x23, 0x23,
2063 0x23, 0x23, 0x13, 0x13, 0x03, 0x03,
2064 0x03, 0x03, 0x03, 0x03, 0x03, 0x03};
2065 static const char r59_nonbt_rev[] = {0x07, 0x07,
2066 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
2067 0x07, 0x07, 0x06, 0x05, 0x04, 0x04};
2069 rt2800_rfcsr_write(rt2x00dev, 55,
2070 r55_nonbt_rev[idx]);
2071 rt2800_rfcsr_write(rt2x00dev, 59,
2072 r59_nonbt_rev[idx]);
2073 } else if (rt2x00_rt(rt2x00dev, RT5390) ||
2074 rt2x00_rt(rt2x00dev, RT5392)) {
2075 static const char r59_non_bt[] = {0x8f, 0x8f,
2076 0x8f, 0x8f, 0x8f, 0x8f, 0x8f, 0x8d,
2077 0x8a, 0x88, 0x88, 0x87, 0x87, 0x86};
2079 rt2800_rfcsr_write(rt2x00dev, 59,
2086 static void rt2800_config_channel(struct rt2x00_dev *rt2x00dev,
2087 struct ieee80211_conf *conf,
2088 struct rf_channel *rf,
2089 struct channel_info *info)
2092 unsigned int tx_pin;
2095 if (rf->channel <= 14) {
2096 info->default_power1 = TXPOWER_G_TO_DEV(info->default_power1);
2097 info->default_power2 = TXPOWER_G_TO_DEV(info->default_power2);
2099 info->default_power1 = TXPOWER_A_TO_DEV(info->default_power1);
2100 info->default_power2 = TXPOWER_A_TO_DEV(info->default_power2);
2103 switch (rt2x00dev->chip.rf) {
2109 rt2800_config_channel_rf3xxx(rt2x00dev, conf, rf, info);
2112 rt2800_config_channel_rf3052(rt2x00dev, conf, rf, info);
2115 rt2800_config_channel_rf3290(rt2x00dev, conf, rf, info);
2122 rt2800_config_channel_rf53xx(rt2x00dev, conf, rf, info);
2125 rt2800_config_channel_rf2xxx(rt2x00dev, conf, rf, info);
2128 if (rt2x00_rf(rt2x00dev, RF3290) ||
2129 rt2x00_rf(rt2x00dev, RF5360) ||
2130 rt2x00_rf(rt2x00dev, RF5370) ||
2131 rt2x00_rf(rt2x00dev, RF5372) ||
2132 rt2x00_rf(rt2x00dev, RF5390) ||
2133 rt2x00_rf(rt2x00dev, RF5392)) {
2134 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
2135 rt2x00_set_field8(&rfcsr, RFCSR30_TX_H20M, 0);
2136 rt2x00_set_field8(&rfcsr, RFCSR30_RX_H20M, 0);
2137 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
2139 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2140 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
2141 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2145 * Change BBP settings
2147 rt2800_bbp_write(rt2x00dev, 62, 0x37 - rt2x00dev->lna_gain);
2148 rt2800_bbp_write(rt2x00dev, 63, 0x37 - rt2x00dev->lna_gain);
2149 rt2800_bbp_write(rt2x00dev, 64, 0x37 - rt2x00dev->lna_gain);
2150 rt2800_bbp_write(rt2x00dev, 86, 0);
2152 if (rf->channel <= 14) {
2153 if (!rt2x00_rt(rt2x00dev, RT5390) &&
2154 !rt2x00_rt(rt2x00dev, RT5392)) {
2155 if (test_bit(CAPABILITY_EXTERNAL_LNA_BG,
2156 &rt2x00dev->cap_flags)) {
2157 rt2800_bbp_write(rt2x00dev, 82, 0x62);
2158 rt2800_bbp_write(rt2x00dev, 75, 0x46);
2160 rt2800_bbp_write(rt2x00dev, 82, 0x84);
2161 rt2800_bbp_write(rt2x00dev, 75, 0x50);
2165 if (rt2x00_rt(rt2x00dev, RT3572))
2166 rt2800_bbp_write(rt2x00dev, 82, 0x94);
2168 rt2800_bbp_write(rt2x00dev, 82, 0xf2);
2170 if (test_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags))
2171 rt2800_bbp_write(rt2x00dev, 75, 0x46);
2173 rt2800_bbp_write(rt2x00dev, 75, 0x50);
2176 rt2800_register_read(rt2x00dev, TX_BAND_CFG, ®);
2177 rt2x00_set_field32(®, TX_BAND_CFG_HT40_MINUS, conf_is_ht40_minus(conf));
2178 rt2x00_set_field32(®, TX_BAND_CFG_A, rf->channel > 14);
2179 rt2x00_set_field32(®, TX_BAND_CFG_BG, rf->channel <= 14);
2180 rt2800_register_write(rt2x00dev, TX_BAND_CFG, reg);
2182 if (rt2x00_rt(rt2x00dev, RT3572))
2183 rt2800_rfcsr_write(rt2x00dev, 8, 0);
2187 /* Turn on unused PA or LNA when not using 1T or 1R */
2188 if (rt2x00dev->default_ant.tx_chain_num == 2) {
2189 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN,
2191 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN,
2195 /* Turn on unused PA or LNA when not using 1T or 1R */
2196 if (rt2x00dev->default_ant.rx_chain_num == 2) {
2197 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A1_EN, 1);
2198 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G1_EN, 1);
2201 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_A0_EN, 1);
2202 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_LNA_PE_G0_EN, 1);
2203 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_RFTR_EN, 1);
2204 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_TRSW_EN, 1);
2205 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags))
2206 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
2208 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN,
2210 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, rf->channel > 14);
2212 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
2214 if (rt2x00_rt(rt2x00dev, RT3572))
2215 rt2800_rfcsr_write(rt2x00dev, 8, 0x80);
2217 rt2800_bbp_read(rt2x00dev, 4, &bbp);
2218 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * conf_is_ht40(conf));
2219 rt2800_bbp_write(rt2x00dev, 4, bbp);
2221 rt2800_bbp_read(rt2x00dev, 3, &bbp);
2222 rt2x00_set_field8(&bbp, BBP3_HT40_MINUS, conf_is_ht40_minus(conf));
2223 rt2800_bbp_write(rt2x00dev, 3, bbp);
2225 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
2226 if (conf_is_ht40(conf)) {
2227 rt2800_bbp_write(rt2x00dev, 69, 0x1a);
2228 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
2229 rt2800_bbp_write(rt2x00dev, 73, 0x16);
2231 rt2800_bbp_write(rt2x00dev, 69, 0x16);
2232 rt2800_bbp_write(rt2x00dev, 70, 0x08);
2233 rt2800_bbp_write(rt2x00dev, 73, 0x11);
2240 * Clear channel statistic counters
2242 rt2800_register_read(rt2x00dev, CH_IDLE_STA, ®);
2243 rt2800_register_read(rt2x00dev, CH_BUSY_STA, ®);
2244 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, ®);
2247 static int rt2800_get_gain_calibration_delta(struct rt2x00_dev *rt2x00dev)
2256 * Read TSSI boundaries for temperature compensation from
2259 * Array idx 0 1 2 3 4 5 6 7 8
2260 * Matching Delta value -4 -3 -2 -1 0 +1 +2 +3 +4
2261 * Example TSSI bounds 0xF0 0xD0 0xB5 0xA0 0x88 0x45 0x25 0x15 0x00
2263 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
2264 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG1, &eeprom);
2265 tssi_bounds[0] = rt2x00_get_field16(eeprom,
2266 EEPROM_TSSI_BOUND_BG1_MINUS4);
2267 tssi_bounds[1] = rt2x00_get_field16(eeprom,
2268 EEPROM_TSSI_BOUND_BG1_MINUS3);
2270 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG2, &eeprom);
2271 tssi_bounds[2] = rt2x00_get_field16(eeprom,
2272 EEPROM_TSSI_BOUND_BG2_MINUS2);
2273 tssi_bounds[3] = rt2x00_get_field16(eeprom,
2274 EEPROM_TSSI_BOUND_BG2_MINUS1);
2276 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG3, &eeprom);
2277 tssi_bounds[4] = rt2x00_get_field16(eeprom,
2278 EEPROM_TSSI_BOUND_BG3_REF);
2279 tssi_bounds[5] = rt2x00_get_field16(eeprom,
2280 EEPROM_TSSI_BOUND_BG3_PLUS1);
2282 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG4, &eeprom);
2283 tssi_bounds[6] = rt2x00_get_field16(eeprom,
2284 EEPROM_TSSI_BOUND_BG4_PLUS2);
2285 tssi_bounds[7] = rt2x00_get_field16(eeprom,
2286 EEPROM_TSSI_BOUND_BG4_PLUS3);
2288 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_BG5, &eeprom);
2289 tssi_bounds[8] = rt2x00_get_field16(eeprom,
2290 EEPROM_TSSI_BOUND_BG5_PLUS4);
2292 step = rt2x00_get_field16(eeprom,
2293 EEPROM_TSSI_BOUND_BG5_AGC_STEP);
2295 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A1, &eeprom);
2296 tssi_bounds[0] = rt2x00_get_field16(eeprom,
2297 EEPROM_TSSI_BOUND_A1_MINUS4);
2298 tssi_bounds[1] = rt2x00_get_field16(eeprom,
2299 EEPROM_TSSI_BOUND_A1_MINUS3);
2301 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A2, &eeprom);
2302 tssi_bounds[2] = rt2x00_get_field16(eeprom,
2303 EEPROM_TSSI_BOUND_A2_MINUS2);
2304 tssi_bounds[3] = rt2x00_get_field16(eeprom,
2305 EEPROM_TSSI_BOUND_A2_MINUS1);
2307 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A3, &eeprom);
2308 tssi_bounds[4] = rt2x00_get_field16(eeprom,
2309 EEPROM_TSSI_BOUND_A3_REF);
2310 tssi_bounds[5] = rt2x00_get_field16(eeprom,
2311 EEPROM_TSSI_BOUND_A3_PLUS1);
2313 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A4, &eeprom);
2314 tssi_bounds[6] = rt2x00_get_field16(eeprom,
2315 EEPROM_TSSI_BOUND_A4_PLUS2);
2316 tssi_bounds[7] = rt2x00_get_field16(eeprom,
2317 EEPROM_TSSI_BOUND_A4_PLUS3);
2319 rt2x00_eeprom_read(rt2x00dev, EEPROM_TSSI_BOUND_A5, &eeprom);
2320 tssi_bounds[8] = rt2x00_get_field16(eeprom,
2321 EEPROM_TSSI_BOUND_A5_PLUS4);
2323 step = rt2x00_get_field16(eeprom,
2324 EEPROM_TSSI_BOUND_A5_AGC_STEP);
2328 * Check if temperature compensation is supported.
2330 if (tssi_bounds[4] == 0xff)
2334 * Read current TSSI (BBP 49).
2336 rt2800_bbp_read(rt2x00dev, 49, ¤t_tssi);
2339 * Compare TSSI value (BBP49) with the compensation boundaries
2340 * from the EEPROM and increase or decrease tx power.
2342 for (i = 0; i <= 3; i++) {
2343 if (current_tssi > tssi_bounds[i])
2348 for (i = 8; i >= 5; i--) {
2349 if (current_tssi < tssi_bounds[i])
2354 return (i - 4) * step;
2357 static int rt2800_get_txpower_bw_comp(struct rt2x00_dev *rt2x00dev,
2358 enum ieee80211_band band)
2365 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_DELTA, &eeprom);
2368 * HT40 compensation not required.
2370 if (eeprom == 0xffff ||
2371 !test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
2374 if (band == IEEE80211_BAND_2GHZ) {
2375 comp_en = rt2x00_get_field16(eeprom,
2376 EEPROM_TXPOWER_DELTA_ENABLE_2G);
2378 comp_type = rt2x00_get_field16(eeprom,
2379 EEPROM_TXPOWER_DELTA_TYPE_2G);
2380 comp_value = rt2x00_get_field16(eeprom,
2381 EEPROM_TXPOWER_DELTA_VALUE_2G);
2383 comp_value = -comp_value;
2386 comp_en = rt2x00_get_field16(eeprom,
2387 EEPROM_TXPOWER_DELTA_ENABLE_5G);
2389 comp_type = rt2x00_get_field16(eeprom,
2390 EEPROM_TXPOWER_DELTA_TYPE_5G);
2391 comp_value = rt2x00_get_field16(eeprom,
2392 EEPROM_TXPOWER_DELTA_VALUE_5G);
2394 comp_value = -comp_value;
2401 static u8 rt2800_compensate_txpower(struct rt2x00_dev *rt2x00dev, int is_rate_b,
2402 enum ieee80211_band band, int power_level,
2403 u8 txpower, int delta)
2409 u8 eirp_txpower_criterion;
2412 if (!((band == IEEE80211_BAND_5GHZ) && is_rate_b))
2415 if (test_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags)) {
2417 * Check if eirp txpower exceed txpower_limit.
2418 * We use OFDM 6M as criterion and its eirp txpower
2419 * is stored at EEPROM_EIRP_MAX_TX_POWER.
2420 * .11b data rate need add additional 4dbm
2421 * when calculating eirp txpower.
2423 rt2800_register_read(rt2x00dev, TX_PWR_CFG_0, ®);
2424 criterion = rt2x00_get_field32(reg, TX_PWR_CFG_0_6MBS);
2426 rt2x00_eeprom_read(rt2x00dev,
2427 EEPROM_EIRP_MAX_TX_POWER, &eeprom);
2429 if (band == IEEE80211_BAND_2GHZ)
2430 eirp_txpower_criterion = rt2x00_get_field16(eeprom,
2431 EEPROM_EIRP_MAX_TX_POWER_2GHZ);
2433 eirp_txpower_criterion = rt2x00_get_field16(eeprom,
2434 EEPROM_EIRP_MAX_TX_POWER_5GHZ);
2436 eirp_txpower = eirp_txpower_criterion + (txpower - criterion) +
2437 (is_rate_b ? 4 : 0) + delta;
2439 reg_limit = (eirp_txpower > power_level) ?
2440 (eirp_txpower - power_level) : 0;
2444 return txpower + delta - reg_limit;
2447 static void rt2800_config_txpower(struct rt2x00_dev *rt2x00dev,
2448 enum ieee80211_band band,
2460 * Calculate HT40 compensation delta
2462 delta = rt2800_get_txpower_bw_comp(rt2x00dev, band);
2465 * calculate temperature compensation delta
2467 delta += rt2800_get_gain_calibration_delta(rt2x00dev);
2470 * set to normal bbp tx power control mode: +/- 0dBm
2472 rt2800_bbp_read(rt2x00dev, 1, &r1);
2473 rt2x00_set_field8(&r1, BBP1_TX_POWER_CTRL, 0);
2474 rt2800_bbp_write(rt2x00dev, 1, r1);
2475 offset = TX_PWR_CFG_0;
2477 for (i = 0; i < EEPROM_TXPOWER_BYRATE_SIZE; i += 2) {
2478 /* just to be safe */
2479 if (offset > TX_PWR_CFG_4)
2482 rt2800_register_read(rt2x00dev, offset, ®);
2484 /* read the next four txpower values */
2485 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i,
2488 is_rate_b = i ? 0 : 1;
2490 * TX_PWR_CFG_0: 1MBS, TX_PWR_CFG_1: 24MBS,
2491 * TX_PWR_CFG_2: MCS4, TX_PWR_CFG_3: MCS12,
2492 * TX_PWR_CFG_4: unknown
2494 txpower = rt2x00_get_field16(eeprom,
2495 EEPROM_TXPOWER_BYRATE_RATE0);
2496 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2497 power_level, txpower, delta);
2498 rt2x00_set_field32(®, TX_PWR_CFG_RATE0, txpower);
2501 * TX_PWR_CFG_0: 2MBS, TX_PWR_CFG_1: 36MBS,
2502 * TX_PWR_CFG_2: MCS5, TX_PWR_CFG_3: MCS13,
2503 * TX_PWR_CFG_4: unknown
2505 txpower = rt2x00_get_field16(eeprom,
2506 EEPROM_TXPOWER_BYRATE_RATE1);
2507 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2508 power_level, txpower, delta);
2509 rt2x00_set_field32(®, TX_PWR_CFG_RATE1, txpower);
2512 * TX_PWR_CFG_0: 5.5MBS, TX_PWR_CFG_1: 48MBS,
2513 * TX_PWR_CFG_2: MCS6, TX_PWR_CFG_3: MCS14,
2514 * TX_PWR_CFG_4: unknown
2516 txpower = rt2x00_get_field16(eeprom,
2517 EEPROM_TXPOWER_BYRATE_RATE2);
2518 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2519 power_level, txpower, delta);
2520 rt2x00_set_field32(®, TX_PWR_CFG_RATE2, txpower);
2523 * TX_PWR_CFG_0: 11MBS, TX_PWR_CFG_1: 54MBS,
2524 * TX_PWR_CFG_2: MCS7, TX_PWR_CFG_3: MCS15,
2525 * TX_PWR_CFG_4: unknown
2527 txpower = rt2x00_get_field16(eeprom,
2528 EEPROM_TXPOWER_BYRATE_RATE3);
2529 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2530 power_level, txpower, delta);
2531 rt2x00_set_field32(®, TX_PWR_CFG_RATE3, txpower);
2533 /* read the next four txpower values */
2534 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXPOWER_BYRATE + i + 1,
2539 * TX_PWR_CFG_0: 6MBS, TX_PWR_CFG_1: MCS0,
2540 * TX_PWR_CFG_2: MCS8, TX_PWR_CFG_3: unknown,
2541 * TX_PWR_CFG_4: unknown
2543 txpower = rt2x00_get_field16(eeprom,
2544 EEPROM_TXPOWER_BYRATE_RATE0);
2545 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2546 power_level, txpower, delta);
2547 rt2x00_set_field32(®, TX_PWR_CFG_RATE4, txpower);
2550 * TX_PWR_CFG_0: 9MBS, TX_PWR_CFG_1: MCS1,
2551 * TX_PWR_CFG_2: MCS9, TX_PWR_CFG_3: unknown,
2552 * TX_PWR_CFG_4: unknown
2554 txpower = rt2x00_get_field16(eeprom,
2555 EEPROM_TXPOWER_BYRATE_RATE1);
2556 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2557 power_level, txpower, delta);
2558 rt2x00_set_field32(®, TX_PWR_CFG_RATE5, txpower);
2561 * TX_PWR_CFG_0: 12MBS, TX_PWR_CFG_1: MCS2,
2562 * TX_PWR_CFG_2: MCS10, TX_PWR_CFG_3: unknown,
2563 * TX_PWR_CFG_4: unknown
2565 txpower = rt2x00_get_field16(eeprom,
2566 EEPROM_TXPOWER_BYRATE_RATE2);
2567 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2568 power_level, txpower, delta);
2569 rt2x00_set_field32(®, TX_PWR_CFG_RATE6, txpower);
2572 * TX_PWR_CFG_0: 18MBS, TX_PWR_CFG_1: MCS3,
2573 * TX_PWR_CFG_2: MCS11, TX_PWR_CFG_3: unknown,
2574 * TX_PWR_CFG_4: unknown
2576 txpower = rt2x00_get_field16(eeprom,
2577 EEPROM_TXPOWER_BYRATE_RATE3);
2578 txpower = rt2800_compensate_txpower(rt2x00dev, is_rate_b, band,
2579 power_level, txpower, delta);
2580 rt2x00_set_field32(®, TX_PWR_CFG_RATE7, txpower);
2582 rt2800_register_write(rt2x00dev, offset, reg);
2584 /* next TX_PWR_CFG register */
2589 void rt2800_gain_calibration(struct rt2x00_dev *rt2x00dev)
2591 rt2800_config_txpower(rt2x00dev, rt2x00dev->curr_band,
2592 rt2x00dev->tx_power);
2594 EXPORT_SYMBOL_GPL(rt2800_gain_calibration);
2596 void rt2800_vco_calibration(struct rt2x00_dev *rt2x00dev)
2602 * A voltage-controlled oscillator(VCO) is an electronic oscillator
2603 * designed to be controlled in oscillation frequency by a voltage
2604 * input. Maybe the temperature will affect the frequency of
2605 * oscillation to be shifted. The VCO calibration will be called
2606 * periodically to adjust the frequency to be precision.
2609 rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
2610 tx_pin &= TX_PIN_CFG_PA_PE_DISABLE;
2611 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
2613 switch (rt2x00dev->chip.rf) {
2620 rt2800_rfcsr_read(rt2x00dev, 7, &rfcsr);
2621 rt2x00_set_field8(&rfcsr, RFCSR7_RF_TUNING, 1);
2622 rt2800_rfcsr_write(rt2x00dev, 7, rfcsr);
2630 rt2800_rfcsr_read(rt2x00dev, 3, &rfcsr);
2631 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
2632 rt2800_rfcsr_write(rt2x00dev, 3, rfcsr);
2640 rt2800_register_read(rt2x00dev, TX_PIN_CFG, &tx_pin);
2641 if (rt2x00dev->rf_channel <= 14) {
2642 switch (rt2x00dev->default_ant.tx_chain_num) {
2644 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G2_EN, 1);
2647 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G1_EN, 1);
2651 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_G0_EN, 1);
2655 switch (rt2x00dev->default_ant.tx_chain_num) {
2657 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A2_EN, 1);
2660 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A1_EN, 1);
2664 rt2x00_set_field32(&tx_pin, TX_PIN_CFG_PA_PE_A0_EN, 1);
2668 rt2800_register_write(rt2x00dev, TX_PIN_CFG, tx_pin);
2671 EXPORT_SYMBOL_GPL(rt2800_vco_calibration);
2673 static void rt2800_config_retry_limit(struct rt2x00_dev *rt2x00dev,
2674 struct rt2x00lib_conf *libconf)
2678 rt2800_register_read(rt2x00dev, TX_RTY_CFG, ®);
2679 rt2x00_set_field32(®, TX_RTY_CFG_SHORT_RTY_LIMIT,
2680 libconf->conf->short_frame_max_tx_count);
2681 rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_LIMIT,
2682 libconf->conf->long_frame_max_tx_count);
2683 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
2686 static void rt2800_config_ps(struct rt2x00_dev *rt2x00dev,
2687 struct rt2x00lib_conf *libconf)
2689 enum dev_state state =
2690 (libconf->conf->flags & IEEE80211_CONF_PS) ?
2691 STATE_SLEEP : STATE_AWAKE;
2694 if (state == STATE_SLEEP) {
2695 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, 0);
2697 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, ®);
2698 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 5);
2699 rt2x00_set_field32(®, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE,
2700 libconf->conf->listen_interval - 1);
2701 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTOWAKE, 1);
2702 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
2704 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
2706 rt2800_register_read(rt2x00dev, AUTOWAKEUP_CFG, ®);
2707 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTO_LEAD_TIME, 0);
2708 rt2x00_set_field32(®, AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE, 0);
2709 rt2x00_set_field32(®, AUTOWAKEUP_CFG_AUTOWAKE, 0);
2710 rt2800_register_write(rt2x00dev, AUTOWAKEUP_CFG, reg);
2712 rt2x00dev->ops->lib->set_device_state(rt2x00dev, state);
2716 void rt2800_config(struct rt2x00_dev *rt2x00dev,
2717 struct rt2x00lib_conf *libconf,
2718 const unsigned int flags)
2720 /* Always recalculate LNA gain before changing configuration */
2721 rt2800_config_lna_gain(rt2x00dev, libconf);
2723 if (flags & IEEE80211_CONF_CHANGE_CHANNEL) {
2724 rt2800_config_channel(rt2x00dev, libconf->conf,
2725 &libconf->rf, &libconf->channel);
2726 rt2800_config_txpower(rt2x00dev, libconf->conf->channel->band,
2727 libconf->conf->power_level);
2729 if (flags & IEEE80211_CONF_CHANGE_POWER)
2730 rt2800_config_txpower(rt2x00dev, libconf->conf->channel->band,
2731 libconf->conf->power_level);
2732 if (flags & IEEE80211_CONF_CHANGE_RETRY_LIMITS)
2733 rt2800_config_retry_limit(rt2x00dev, libconf);
2734 if (flags & IEEE80211_CONF_CHANGE_PS)
2735 rt2800_config_ps(rt2x00dev, libconf);
2737 EXPORT_SYMBOL_GPL(rt2800_config);
2742 void rt2800_link_stats(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
2747 * Update FCS error count from register.
2749 rt2800_register_read(rt2x00dev, RX_STA_CNT0, ®);
2750 qual->rx_failed = rt2x00_get_field32(reg, RX_STA_CNT0_CRC_ERR);
2752 EXPORT_SYMBOL_GPL(rt2800_link_stats);
2754 static u8 rt2800_get_default_vgc(struct rt2x00_dev *rt2x00dev)
2756 if (rt2x00dev->curr_band == IEEE80211_BAND_2GHZ) {
2757 if (rt2x00_rt(rt2x00dev, RT3070) ||
2758 rt2x00_rt(rt2x00dev, RT3071) ||
2759 rt2x00_rt(rt2x00dev, RT3090) ||
2760 rt2x00_rt(rt2x00dev, RT3290) ||
2761 rt2x00_rt(rt2x00dev, RT3390) ||
2762 rt2x00_rt(rt2x00dev, RT5390) ||
2763 rt2x00_rt(rt2x00dev, RT5392))
2764 return 0x1c + (2 * rt2x00dev->lna_gain);
2766 return 0x2e + rt2x00dev->lna_gain;
2769 if (!test_bit(CONFIG_CHANNEL_HT40, &rt2x00dev->flags))
2770 return 0x32 + (rt2x00dev->lna_gain * 5) / 3;
2772 return 0x3a + (rt2x00dev->lna_gain * 5) / 3;
2775 static inline void rt2800_set_vgc(struct rt2x00_dev *rt2x00dev,
2776 struct link_qual *qual, u8 vgc_level)
2778 if (qual->vgc_level != vgc_level) {
2779 rt2800_bbp_write(rt2x00dev, 66, vgc_level);
2780 qual->vgc_level = vgc_level;
2781 qual->vgc_level_reg = vgc_level;
2785 void rt2800_reset_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual)
2787 rt2800_set_vgc(rt2x00dev, qual, rt2800_get_default_vgc(rt2x00dev));
2789 EXPORT_SYMBOL_GPL(rt2800_reset_tuner);
2791 void rt2800_link_tuner(struct rt2x00_dev *rt2x00dev, struct link_qual *qual,
2794 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C))
2798 * When RSSI is better then -80 increase VGC level with 0x10
2800 rt2800_set_vgc(rt2x00dev, qual,
2801 rt2800_get_default_vgc(rt2x00dev) +
2802 ((qual->rssi > -80) * 0x10));
2804 EXPORT_SYMBOL_GPL(rt2800_link_tuner);
2807 * Initialization functions.
2809 static int rt2800_init_registers(struct rt2x00_dev *rt2x00dev)
2816 rt2800_disable_wpdma(rt2x00dev);
2818 ret = rt2800_drv_init_registers(rt2x00dev);
2822 rt2800_register_read(rt2x00dev, BCN_OFFSET0, ®);
2823 rt2x00_set_field32(®, BCN_OFFSET0_BCN0, 0xe0); /* 0x3800 */
2824 rt2x00_set_field32(®, BCN_OFFSET0_BCN1, 0xe8); /* 0x3a00 */
2825 rt2x00_set_field32(®, BCN_OFFSET0_BCN2, 0xf0); /* 0x3c00 */
2826 rt2x00_set_field32(®, BCN_OFFSET0_BCN3, 0xf8); /* 0x3e00 */
2827 rt2800_register_write(rt2x00dev, BCN_OFFSET0, reg);
2829 rt2800_register_read(rt2x00dev, BCN_OFFSET1, ®);
2830 rt2x00_set_field32(®, BCN_OFFSET1_BCN4, 0xc8); /* 0x3200 */
2831 rt2x00_set_field32(®, BCN_OFFSET1_BCN5, 0xd0); /* 0x3400 */
2832 rt2x00_set_field32(®, BCN_OFFSET1_BCN6, 0x77); /* 0x1dc0 */
2833 rt2x00_set_field32(®, BCN_OFFSET1_BCN7, 0x6f); /* 0x1bc0 */
2834 rt2800_register_write(rt2x00dev, BCN_OFFSET1, reg);
2836 rt2800_register_write(rt2x00dev, LEGACY_BASIC_RATE, 0x0000013f);
2837 rt2800_register_write(rt2x00dev, HT_BASIC_RATE, 0x00008003);
2839 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, 0x00000000);
2841 rt2800_register_read(rt2x00dev, BCN_TIME_CFG, ®);
2842 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_INTERVAL, 1600);
2843 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_TICKING, 0);
2844 rt2x00_set_field32(®, BCN_TIME_CFG_TSF_SYNC, 0);
2845 rt2x00_set_field32(®, BCN_TIME_CFG_TBTT_ENABLE, 0);
2846 rt2x00_set_field32(®, BCN_TIME_CFG_BEACON_GEN, 0);
2847 rt2x00_set_field32(®, BCN_TIME_CFG_TX_TIME_COMPENSATE, 0);
2848 rt2800_register_write(rt2x00dev, BCN_TIME_CFG, reg);
2850 rt2800_config_filter(rt2x00dev, FIF_ALLMULTI);
2852 rt2800_register_read(rt2x00dev, BKOFF_SLOT_CFG, ®);
2853 rt2x00_set_field32(®, BKOFF_SLOT_CFG_SLOT_TIME, 9);
2854 rt2x00_set_field32(®, BKOFF_SLOT_CFG_CC_DELAY_TIME, 2);
2855 rt2800_register_write(rt2x00dev, BKOFF_SLOT_CFG, reg);
2857 if (rt2x00_rt(rt2x00dev, RT3290)) {
2858 rt2800_register_read(rt2x00dev, WLAN_FUN_CTRL, ®);
2859 if (rt2x00_get_field32(reg, WLAN_EN) == 1) {
2860 rt2x00_set_field32(®, PCIE_APP0_CLK_REQ, 1);
2861 rt2800_register_write(rt2x00dev, WLAN_FUN_CTRL, reg);
2864 rt2800_register_read(rt2x00dev, CMB_CTRL, ®);
2865 if (!(rt2x00_get_field32(reg, LDO0_EN) == 1)) {
2866 rt2x00_set_field32(®, LDO0_EN, 1);
2867 rt2x00_set_field32(®, LDO_BGSEL, 3);
2868 rt2800_register_write(rt2x00dev, CMB_CTRL, reg);
2871 rt2800_register_read(rt2x00dev, OSC_CTRL, ®);
2872 rt2x00_set_field32(®, OSC_ROSC_EN, 1);
2873 rt2x00_set_field32(®, OSC_CAL_REQ, 1);
2874 rt2x00_set_field32(®, OSC_REF_CYCLE, 0x27);
2875 rt2800_register_write(rt2x00dev, OSC_CTRL, reg);
2877 rt2800_register_read(rt2x00dev, COEX_CFG0, ®);
2878 rt2x00_set_field32(®, COEX_CFG_ANT, 0x5e);
2879 rt2800_register_write(rt2x00dev, COEX_CFG0, reg);
2881 rt2800_register_read(rt2x00dev, COEX_CFG2, ®);
2882 rt2x00_set_field32(®, BT_COEX_CFG1, 0x00);
2883 rt2x00_set_field32(®, BT_COEX_CFG0, 0x17);
2884 rt2x00_set_field32(®, WL_COEX_CFG1, 0x93);
2885 rt2x00_set_field32(®, WL_COEX_CFG0, 0x7f);
2886 rt2800_register_write(rt2x00dev, COEX_CFG2, reg);
2888 rt2800_register_read(rt2x00dev, PLL_CTRL, ®);
2889 rt2x00_set_field32(®, PLL_CONTROL, 1);
2890 rt2800_register_write(rt2x00dev, PLL_CTRL, reg);
2893 if (rt2x00_rt(rt2x00dev, RT3071) ||
2894 rt2x00_rt(rt2x00dev, RT3090) ||
2895 rt2x00_rt(rt2x00dev, RT3290) ||
2896 rt2x00_rt(rt2x00dev, RT3390)) {
2898 if (rt2x00_rt(rt2x00dev, RT3290))
2899 rt2800_register_write(rt2x00dev, TX_SW_CFG0,
2902 rt2800_register_write(rt2x00dev, TX_SW_CFG0,
2905 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
2906 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
2907 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
2908 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
2909 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
2910 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
2911 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
2914 rt2800_register_write(rt2x00dev, TX_SW_CFG2,
2917 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
2919 } else if (rt2x00_rt(rt2x00dev, RT3070)) {
2920 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2922 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
2923 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
2924 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x0000002c);
2926 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2927 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
2929 } else if (rt2800_is_305x_soc(rt2x00dev)) {
2930 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2931 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00000000);
2932 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000030);
2933 } else if (rt2x00_rt(rt2x00dev, RT3572)) {
2934 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000400);
2935 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2936 } else if (rt2x00_rt(rt2x00dev, RT5390) ||
2937 rt2x00_rt(rt2x00dev, RT5392)) {
2938 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000404);
2939 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2940 rt2800_register_write(rt2x00dev, TX_SW_CFG2, 0x00000000);
2942 rt2800_register_write(rt2x00dev, TX_SW_CFG0, 0x00000000);
2943 rt2800_register_write(rt2x00dev, TX_SW_CFG1, 0x00080606);
2946 rt2800_register_read(rt2x00dev, TX_LINK_CFG, ®);
2947 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFB_LIFETIME, 32);
2948 rt2x00_set_field32(®, TX_LINK_CFG_MFB_ENABLE, 0);
2949 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_UMFS_ENABLE, 0);
2950 rt2x00_set_field32(®, TX_LINK_CFG_TX_MRQ_EN, 0);
2951 rt2x00_set_field32(®, TX_LINK_CFG_TX_RDG_EN, 0);
2952 rt2x00_set_field32(®, TX_LINK_CFG_TX_CF_ACK_EN, 1);
2953 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFB, 0);
2954 rt2x00_set_field32(®, TX_LINK_CFG_REMOTE_MFS, 0);
2955 rt2800_register_write(rt2x00dev, TX_LINK_CFG, reg);
2957 rt2800_register_read(rt2x00dev, TX_TIMEOUT_CFG, ®);
2958 rt2x00_set_field32(®, TX_TIMEOUT_CFG_MPDU_LIFETIME, 9);
2959 rt2x00_set_field32(®, TX_TIMEOUT_CFG_RX_ACK_TIMEOUT, 32);
2960 rt2x00_set_field32(®, TX_TIMEOUT_CFG_TX_OP_TIMEOUT, 10);
2961 rt2800_register_write(rt2x00dev, TX_TIMEOUT_CFG, reg);
2963 rt2800_register_read(rt2x00dev, MAX_LEN_CFG, ®);
2964 rt2x00_set_field32(®, MAX_LEN_CFG_MAX_MPDU, AGGREGATION_SIZE);
2965 if (rt2x00_rt_rev_gte(rt2x00dev, RT2872, REV_RT2872E) ||
2966 rt2x00_rt(rt2x00dev, RT2883) ||
2967 rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070E))
2968 rt2x00_set_field32(®, MAX_LEN_CFG_MAX_PSDU, 2);
2970 rt2x00_set_field32(®, MAX_LEN_CFG_MAX_PSDU, 1);
2971 rt2x00_set_field32(®, MAX_LEN_CFG_MIN_PSDU, 0);
2972 rt2x00_set_field32(®, MAX_LEN_CFG_MIN_MPDU, 0);
2973 rt2800_register_write(rt2x00dev, MAX_LEN_CFG, reg);
2975 rt2800_register_read(rt2x00dev, LED_CFG, ®);
2976 rt2x00_set_field32(®, LED_CFG_ON_PERIOD, 70);
2977 rt2x00_set_field32(®, LED_CFG_OFF_PERIOD, 30);
2978 rt2x00_set_field32(®, LED_CFG_SLOW_BLINK_PERIOD, 3);
2979 rt2x00_set_field32(®, LED_CFG_R_LED_MODE, 3);
2980 rt2x00_set_field32(®, LED_CFG_G_LED_MODE, 3);
2981 rt2x00_set_field32(®, LED_CFG_Y_LED_MODE, 3);
2982 rt2x00_set_field32(®, LED_CFG_LED_POLAR, 1);
2983 rt2800_register_write(rt2x00dev, LED_CFG, reg);
2985 rt2800_register_write(rt2x00dev, PBF_MAX_PCNT, 0x1f3fbf9f);
2987 rt2800_register_read(rt2x00dev, TX_RTY_CFG, ®);
2988 rt2x00_set_field32(®, TX_RTY_CFG_SHORT_RTY_LIMIT, 15);
2989 rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_LIMIT, 31);
2990 rt2x00_set_field32(®, TX_RTY_CFG_LONG_RTY_THRE, 2000);
2991 rt2x00_set_field32(®, TX_RTY_CFG_NON_AGG_RTY_MODE, 0);
2992 rt2x00_set_field32(®, TX_RTY_CFG_AGG_RTY_MODE, 0);
2993 rt2x00_set_field32(®, TX_RTY_CFG_TX_AUTO_FB_ENABLE, 1);
2994 rt2800_register_write(rt2x00dev, TX_RTY_CFG, reg);
2996 rt2800_register_read(rt2x00dev, AUTO_RSP_CFG, ®);
2997 rt2x00_set_field32(®, AUTO_RSP_CFG_AUTORESPONDER, 1);
2998 rt2x00_set_field32(®, AUTO_RSP_CFG_BAC_ACK_POLICY, 1);
2999 rt2x00_set_field32(®, AUTO_RSP_CFG_CTS_40_MMODE, 0);
3000 rt2x00_set_field32(®, AUTO_RSP_CFG_CTS_40_MREF, 0);
3001 rt2x00_set_field32(®, AUTO_RSP_CFG_AR_PREAMBLE, 1);
3002 rt2x00_set_field32(®, AUTO_RSP_CFG_DUAL_CTS_EN, 0);
3003 rt2x00_set_field32(®, AUTO_RSP_CFG_ACK_CTS_PSM_BIT, 0);
3004 rt2800_register_write(rt2x00dev, AUTO_RSP_CFG, reg);
3006 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, ®);
3007 rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_RATE, 3);
3008 rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_CTRL, 0);
3009 rt2x00_set_field32(®, CCK_PROT_CFG_PROTECT_NAV_SHORT, 1);
3010 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3011 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3012 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3013 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_MM40, 0);
3014 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3015 rt2x00_set_field32(®, CCK_PROT_CFG_TX_OP_ALLOW_GF40, 0);
3016 rt2x00_set_field32(®, CCK_PROT_CFG_RTS_TH_EN, 1);
3017 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
3019 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, ®);
3020 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_RATE, 3);
3021 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_CTRL, 0);
3022 rt2x00_set_field32(®, OFDM_PROT_CFG_PROTECT_NAV_SHORT, 1);
3023 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3024 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3025 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3026 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_MM40, 0);
3027 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3028 rt2x00_set_field32(®, OFDM_PROT_CFG_TX_OP_ALLOW_GF40, 0);
3029 rt2x00_set_field32(®, OFDM_PROT_CFG_RTS_TH_EN, 1);
3030 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
3032 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, ®);
3033 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_RATE, 0x4004);
3034 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_CTRL, 0);
3035 rt2x00_set_field32(®, MM20_PROT_CFG_PROTECT_NAV_SHORT, 1);
3036 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3037 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3038 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3039 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
3040 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3041 rt2x00_set_field32(®, MM20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
3042 rt2x00_set_field32(®, MM20_PROT_CFG_RTS_TH_EN, 0);
3043 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
3045 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, ®);
3046 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_RATE, 0x4084);
3047 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_CTRL, 0);
3048 rt2x00_set_field32(®, MM40_PROT_CFG_PROTECT_NAV_SHORT, 1);
3049 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3050 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3051 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3052 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
3053 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3054 rt2x00_set_field32(®, MM40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
3055 rt2x00_set_field32(®, MM40_PROT_CFG_RTS_TH_EN, 0);
3056 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
3058 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, ®);
3059 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_RATE, 0x4004);
3060 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_CTRL, 0);
3061 rt2x00_set_field32(®, GF20_PROT_CFG_PROTECT_NAV_SHORT, 1);
3062 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3063 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3064 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3065 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_MM40, 0);
3066 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3067 rt2x00_set_field32(®, GF20_PROT_CFG_TX_OP_ALLOW_GF40, 0);
3068 rt2x00_set_field32(®, GF20_PROT_CFG_RTS_TH_EN, 0);
3069 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
3071 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, ®);
3072 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_RATE, 0x4084);
3073 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_CTRL, 0);
3074 rt2x00_set_field32(®, GF40_PROT_CFG_PROTECT_NAV_SHORT, 1);
3075 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_CCK, 1);
3076 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_OFDM, 1);
3077 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_MM20, 1);
3078 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_MM40, 1);
3079 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_GF20, 1);
3080 rt2x00_set_field32(®, GF40_PROT_CFG_TX_OP_ALLOW_GF40, 1);
3081 rt2x00_set_field32(®, GF40_PROT_CFG_RTS_TH_EN, 0);
3082 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
3084 if (rt2x00_is_usb(rt2x00dev)) {
3085 rt2800_register_write(rt2x00dev, PBF_CFG, 0xf40006);
3087 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, ®);
3088 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 0);
3089 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_DMA_BUSY, 0);
3090 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 0);
3091 rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_DMA_BUSY, 0);
3092 rt2x00_set_field32(®, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 3);
3093 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 0);
3094 rt2x00_set_field32(®, WPDMA_GLO_CFG_BIG_ENDIAN, 0);
3095 rt2x00_set_field32(®, WPDMA_GLO_CFG_RX_HDR_SCATTER, 0);
3096 rt2x00_set_field32(®, WPDMA_GLO_CFG_HDR_SEG_LEN, 0);
3097 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
3101 * The legacy driver also sets TXOP_CTRL_CFG_RESERVED_TRUN_EN to 1
3102 * although it is reserved.
3104 rt2800_register_read(rt2x00dev, TXOP_CTRL_CFG, ®);
3105 rt2x00_set_field32(®, TXOP_CTRL_CFG_TIMEOUT_TRUN_EN, 1);
3106 rt2x00_set_field32(®, TXOP_CTRL_CFG_AC_TRUN_EN, 1);
3107 rt2x00_set_field32(®, TXOP_CTRL_CFG_TXRATEGRP_TRUN_EN, 1);
3108 rt2x00_set_field32(®, TXOP_CTRL_CFG_USER_MODE_TRUN_EN, 1);
3109 rt2x00_set_field32(®, TXOP_CTRL_CFG_MIMO_PS_TRUN_EN, 1);
3110 rt2x00_set_field32(®, TXOP_CTRL_CFG_RESERVED_TRUN_EN, 1);
3111 rt2x00_set_field32(®, TXOP_CTRL_CFG_LSIG_TXOP_EN, 0);
3112 rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CCA_EN, 0);
3113 rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CCA_DLY, 88);
3114 rt2x00_set_field32(®, TXOP_CTRL_CFG_EXT_CWMIN, 0);
3115 rt2800_register_write(rt2x00dev, TXOP_CTRL_CFG, reg);
3117 rt2800_register_write(rt2x00dev, TXOP_HLDR_ET, 0x00000002);
3119 rt2800_register_read(rt2x00dev, TX_RTS_CFG, ®);
3120 rt2x00_set_field32(®, TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT, 32);
3121 rt2x00_set_field32(®, TX_RTS_CFG_RTS_THRES,
3122 IEEE80211_MAX_RTS_THRESHOLD);
3123 rt2x00_set_field32(®, TX_RTS_CFG_RTS_FBK_EN, 0);
3124 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
3126 rt2800_register_write(rt2x00dev, EXP_ACK_TIME, 0x002400ca);
3129 * Usually the CCK SIFS time should be set to 10 and the OFDM SIFS
3130 * time should be set to 16. However, the original Ralink driver uses
3131 * 16 for both and indeed using a value of 10 for CCK SIFS results in
3132 * connection problems with 11g + CTS protection. Hence, use the same
3133 * defaults as the Ralink driver: 16 for both, CCK and OFDM SIFS.
3135 rt2800_register_read(rt2x00dev, XIFS_TIME_CFG, ®);
3136 rt2x00_set_field32(®, XIFS_TIME_CFG_CCKM_SIFS_TIME, 16);
3137 rt2x00_set_field32(®, XIFS_TIME_CFG_OFDM_SIFS_TIME, 16);
3138 rt2x00_set_field32(®, XIFS_TIME_CFG_OFDM_XIFS_TIME, 4);
3139 rt2x00_set_field32(®, XIFS_TIME_CFG_EIFS, 314);
3140 rt2x00_set_field32(®, XIFS_TIME_CFG_BB_RXEND_ENABLE, 1);
3141 rt2800_register_write(rt2x00dev, XIFS_TIME_CFG, reg);
3143 rt2800_register_write(rt2x00dev, PWR_PIN_CFG, 0x00000003);
3146 * ASIC will keep garbage value after boot, clear encryption keys.
3148 for (i = 0; i < 4; i++)
3149 rt2800_register_write(rt2x00dev,
3150 SHARED_KEY_MODE_ENTRY(i), 0);
3152 for (i = 0; i < 256; i++) {
3153 rt2800_config_wcid(rt2x00dev, NULL, i);
3154 rt2800_delete_wcid_attr(rt2x00dev, i);
3155 rt2800_register_write(rt2x00dev, MAC_IVEIV_ENTRY(i), 0);
3161 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE0);
3162 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE1);
3163 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE2);
3164 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE3);
3165 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE4);
3166 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE5);
3167 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE6);
3168 rt2800_clear_beacon_register(rt2x00dev, HW_BEACON_BASE7);
3170 if (rt2x00_is_usb(rt2x00dev)) {
3171 rt2800_register_read(rt2x00dev, US_CYC_CNT, ®);
3172 rt2x00_set_field32(®, US_CYC_CNT_CLOCK_CYCLE, 30);
3173 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
3174 } else if (rt2x00_is_pcie(rt2x00dev)) {
3175 rt2800_register_read(rt2x00dev, US_CYC_CNT, ®);
3176 rt2x00_set_field32(®, US_CYC_CNT_CLOCK_CYCLE, 125);
3177 rt2800_register_write(rt2x00dev, US_CYC_CNT, reg);
3180 rt2800_register_read(rt2x00dev, HT_FBK_CFG0, ®);
3181 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS0FBK, 0);
3182 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS1FBK, 0);
3183 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS2FBK, 1);
3184 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS3FBK, 2);
3185 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS4FBK, 3);
3186 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS5FBK, 4);
3187 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS6FBK, 5);
3188 rt2x00_set_field32(®, HT_FBK_CFG0_HTMCS7FBK, 6);
3189 rt2800_register_write(rt2x00dev, HT_FBK_CFG0, reg);
3191 rt2800_register_read(rt2x00dev, HT_FBK_CFG1, ®);
3192 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS8FBK, 8);
3193 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS9FBK, 8);
3194 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS10FBK, 9);
3195 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS11FBK, 10);
3196 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS12FBK, 11);
3197 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS13FBK, 12);
3198 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS14FBK, 13);
3199 rt2x00_set_field32(®, HT_FBK_CFG1_HTMCS15FBK, 14);
3200 rt2800_register_write(rt2x00dev, HT_FBK_CFG1, reg);
3202 rt2800_register_read(rt2x00dev, LG_FBK_CFG0, ®);
3203 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS0FBK, 8);
3204 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS1FBK, 8);
3205 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS2FBK, 9);
3206 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS3FBK, 10);
3207 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS4FBK, 11);
3208 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS5FBK, 12);
3209 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS6FBK, 13);
3210 rt2x00_set_field32(®, LG_FBK_CFG0_OFDMMCS7FBK, 14);
3211 rt2800_register_write(rt2x00dev, LG_FBK_CFG0, reg);
3213 rt2800_register_read(rt2x00dev, LG_FBK_CFG1, ®);
3214 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS0FBK, 0);
3215 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS1FBK, 0);
3216 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS2FBK, 1);
3217 rt2x00_set_field32(®, LG_FBK_CFG0_CCKMCS3FBK, 2);
3218 rt2800_register_write(rt2x00dev, LG_FBK_CFG1, reg);
3221 * Do not force the BA window size, we use the TXWI to set it
3223 rt2800_register_read(rt2x00dev, AMPDU_BA_WINSIZE, ®);
3224 rt2x00_set_field32(®, AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE, 0);
3225 rt2x00_set_field32(®, AMPDU_BA_WINSIZE_FORCE_WINSIZE, 0);
3226 rt2800_register_write(rt2x00dev, AMPDU_BA_WINSIZE, reg);
3229 * We must clear the error counters.
3230 * These registers are cleared on read,
3231 * so we may pass a useless variable to store the value.
3233 rt2800_register_read(rt2x00dev, RX_STA_CNT0, ®);
3234 rt2800_register_read(rt2x00dev, RX_STA_CNT1, ®);
3235 rt2800_register_read(rt2x00dev, RX_STA_CNT2, ®);
3236 rt2800_register_read(rt2x00dev, TX_STA_CNT0, ®);
3237 rt2800_register_read(rt2x00dev, TX_STA_CNT1, ®);
3238 rt2800_register_read(rt2x00dev, TX_STA_CNT2, ®);
3241 * Setup leadtime for pre tbtt interrupt to 6ms
3243 rt2800_register_read(rt2x00dev, INT_TIMER_CFG, ®);
3244 rt2x00_set_field32(®, INT_TIMER_CFG_PRE_TBTT_TIMER, 6 << 4);
3245 rt2800_register_write(rt2x00dev, INT_TIMER_CFG, reg);
3248 * Set up channel statistics timer
3250 rt2800_register_read(rt2x00dev, CH_TIME_CFG, ®);
3251 rt2x00_set_field32(®, CH_TIME_CFG_EIFS_BUSY, 1);
3252 rt2x00_set_field32(®, CH_TIME_CFG_NAV_BUSY, 1);
3253 rt2x00_set_field32(®, CH_TIME_CFG_RX_BUSY, 1);
3254 rt2x00_set_field32(®, CH_TIME_CFG_TX_BUSY, 1);
3255 rt2x00_set_field32(®, CH_TIME_CFG_TMR_EN, 1);
3256 rt2800_register_write(rt2x00dev, CH_TIME_CFG, reg);
3261 static int rt2800_wait_bbp_rf_ready(struct rt2x00_dev *rt2x00dev)
3266 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
3267 rt2800_register_read(rt2x00dev, MAC_STATUS_CFG, ®);
3268 if (!rt2x00_get_field32(reg, MAC_STATUS_CFG_BBP_RF_BUSY))
3271 udelay(REGISTER_BUSY_DELAY);
3274 ERROR(rt2x00dev, "BBP/RF register access failed, aborting.\n");
3278 static int rt2800_wait_bbp_ready(struct rt2x00_dev *rt2x00dev)
3284 * BBP was enabled after firmware was loaded,
3285 * but we need to reactivate it now.
3287 rt2800_register_write(rt2x00dev, H2M_BBP_AGENT, 0);
3288 rt2800_register_write(rt2x00dev, H2M_MAILBOX_CSR, 0);
3291 for (i = 0; i < REGISTER_BUSY_COUNT; i++) {
3292 rt2800_bbp_read(rt2x00dev, 0, &value);
3293 if ((value != 0xff) && (value != 0x00))
3295 udelay(REGISTER_BUSY_DELAY);
3298 ERROR(rt2x00dev, "BBP register access failed, aborting.\n");
3302 static int rt2800_init_bbp(struct rt2x00_dev *rt2x00dev)
3309 if (unlikely(rt2800_wait_bbp_rf_ready(rt2x00dev) ||
3310 rt2800_wait_bbp_ready(rt2x00dev)))
3313 if (rt2x00_rt(rt2x00dev, RT3290) ||
3314 rt2x00_rt(rt2x00dev, RT5390) ||
3315 rt2x00_rt(rt2x00dev, RT5392)) {
3316 rt2800_bbp_read(rt2x00dev, 4, &value);
3317 rt2x00_set_field8(&value, BBP4_MAC_IF_CTRL, 1);
3318 rt2800_bbp_write(rt2x00dev, 4, value);
3321 if (rt2800_is_305x_soc(rt2x00dev) ||
3322 rt2x00_rt(rt2x00dev, RT3290) ||
3323 rt2x00_rt(rt2x00dev, RT3572) ||
3324 rt2x00_rt(rt2x00dev, RT5390) ||
3325 rt2x00_rt(rt2x00dev, RT5392))
3326 rt2800_bbp_write(rt2x00dev, 31, 0x08);
3328 rt2800_bbp_write(rt2x00dev, 65, 0x2c);
3329 rt2800_bbp_write(rt2x00dev, 66, 0x38);
3331 if (rt2x00_rt(rt2x00dev, RT3290) ||
3332 rt2x00_rt(rt2x00dev, RT5390) ||
3333 rt2x00_rt(rt2x00dev, RT5392))
3334 rt2800_bbp_write(rt2x00dev, 68, 0x0b);
3336 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860C)) {
3337 rt2800_bbp_write(rt2x00dev, 69, 0x16);
3338 rt2800_bbp_write(rt2x00dev, 73, 0x12);
3339 } else if (rt2x00_rt(rt2x00dev, RT3290) ||
3340 rt2x00_rt(rt2x00dev, RT5390) ||
3341 rt2x00_rt(rt2x00dev, RT5392)) {
3342 rt2800_bbp_write(rt2x00dev, 69, 0x12);
3343 rt2800_bbp_write(rt2x00dev, 73, 0x13);
3344 rt2800_bbp_write(rt2x00dev, 75, 0x46);
3345 rt2800_bbp_write(rt2x00dev, 76, 0x28);
3347 if (rt2x00_rt(rt2x00dev, RT3290))
3348 rt2800_bbp_write(rt2x00dev, 77, 0x58);
3350 rt2800_bbp_write(rt2x00dev, 77, 0x59);
3352 rt2800_bbp_write(rt2x00dev, 69, 0x12);
3353 rt2800_bbp_write(rt2x00dev, 73, 0x10);
3356 rt2800_bbp_write(rt2x00dev, 70, 0x0a);
3358 if (rt2x00_rt(rt2x00dev, RT3070) ||
3359 rt2x00_rt(rt2x00dev, RT3071) ||
3360 rt2x00_rt(rt2x00dev, RT3090) ||
3361 rt2x00_rt(rt2x00dev, RT3390) ||
3362 rt2x00_rt(rt2x00dev, RT3572) ||
3363 rt2x00_rt(rt2x00dev, RT5390) ||
3364 rt2x00_rt(rt2x00dev, RT5392)) {
3365 rt2800_bbp_write(rt2x00dev, 79, 0x13);
3366 rt2800_bbp_write(rt2x00dev, 80, 0x05);
3367 rt2800_bbp_write(rt2x00dev, 81, 0x33);
3368 } else if (rt2800_is_305x_soc(rt2x00dev)) {
3369 rt2800_bbp_write(rt2x00dev, 78, 0x0e);
3370 rt2800_bbp_write(rt2x00dev, 80, 0x08);
3372 rt2800_bbp_write(rt2x00dev, 81, 0x37);
3375 if (rt2x00_rt(rt2x00dev, RT3290)) {
3376 rt2800_bbp_write(rt2x00dev, 74, 0x0b);
3377 rt2800_bbp_write(rt2x00dev, 79, 0x18);
3378 rt2800_bbp_write(rt2x00dev, 80, 0x09);
3379 rt2800_bbp_write(rt2x00dev, 81, 0x33);
3382 rt2800_bbp_write(rt2x00dev, 82, 0x62);
3383 if (rt2x00_rt(rt2x00dev, RT3290) ||
3384 rt2x00_rt(rt2x00dev, RT5390) ||
3385 rt2x00_rt(rt2x00dev, RT5392))
3386 rt2800_bbp_write(rt2x00dev, 83, 0x7a);
3388 rt2800_bbp_write(rt2x00dev, 83, 0x6a);
3390 if (rt2x00_rt_rev(rt2x00dev, RT2860, REV_RT2860D))
3391 rt2800_bbp_write(rt2x00dev, 84, 0x19);
3392 else if (rt2x00_rt(rt2x00dev, RT3290) ||
3393 rt2x00_rt(rt2x00dev, RT5390) ||
3394 rt2x00_rt(rt2x00dev, RT5392))
3395 rt2800_bbp_write(rt2x00dev, 84, 0x9a);
3397 rt2800_bbp_write(rt2x00dev, 84, 0x99);
3399 if (rt2x00_rt(rt2x00dev, RT3290) ||
3400 rt2x00_rt(rt2x00dev, RT5390) ||
3401 rt2x00_rt(rt2x00dev, RT5392))
3402 rt2800_bbp_write(rt2x00dev, 86, 0x38);
3404 rt2800_bbp_write(rt2x00dev, 86, 0x00);
3406 if (rt2x00_rt(rt2x00dev, RT5392))
3407 rt2800_bbp_write(rt2x00dev, 88, 0x90);
3409 rt2800_bbp_write(rt2x00dev, 91, 0x04);
3411 if (rt2x00_rt(rt2x00dev, RT3290) ||
3412 rt2x00_rt(rt2x00dev, RT5390) ||
3413 rt2x00_rt(rt2x00dev, RT5392))
3414 rt2800_bbp_write(rt2x00dev, 92, 0x02);
3416 rt2800_bbp_write(rt2x00dev, 92, 0x00);
3418 if (rt2x00_rt(rt2x00dev, RT5392)) {
3419 rt2800_bbp_write(rt2x00dev, 95, 0x9a);
3420 rt2800_bbp_write(rt2x00dev, 98, 0x12);
3423 if (rt2x00_rt_rev_gte(rt2x00dev, RT3070, REV_RT3070F) ||
3424 rt2x00_rt_rev_gte(rt2x00dev, RT3071, REV_RT3071E) ||
3425 rt2x00_rt_rev_gte(rt2x00dev, RT3090, REV_RT3090E) ||
3426 rt2x00_rt_rev_gte(rt2x00dev, RT3390, REV_RT3390E) ||
3427 rt2x00_rt(rt2x00dev, RT3290) ||
3428 rt2x00_rt(rt2x00dev, RT3572) ||
3429 rt2x00_rt(rt2x00dev, RT5390) ||
3430 rt2x00_rt(rt2x00dev, RT5392) ||
3431 rt2800_is_305x_soc(rt2x00dev))
3432 rt2800_bbp_write(rt2x00dev, 103, 0xc0);
3434 rt2800_bbp_write(rt2x00dev, 103, 0x00);
3436 if (rt2x00_rt(rt2x00dev, RT3290) ||
3437 rt2x00_rt(rt2x00dev, RT5390) ||
3438 rt2x00_rt(rt2x00dev, RT5392))
3439 rt2800_bbp_write(rt2x00dev, 104, 0x92);
3441 if (rt2800_is_305x_soc(rt2x00dev))
3442 rt2800_bbp_write(rt2x00dev, 105, 0x01);
3443 else if (rt2x00_rt(rt2x00dev, RT3290))
3444 rt2800_bbp_write(rt2x00dev, 105, 0x1c);
3445 else if (rt2x00_rt(rt2x00dev, RT5390) ||
3446 rt2x00_rt(rt2x00dev, RT5392))
3447 rt2800_bbp_write(rt2x00dev, 105, 0x3c);
3449 rt2800_bbp_write(rt2x00dev, 105, 0x05);
3451 if (rt2x00_rt(rt2x00dev, RT3290) ||
3452 rt2x00_rt(rt2x00dev, RT5390))
3453 rt2800_bbp_write(rt2x00dev, 106, 0x03);
3454 else if (rt2x00_rt(rt2x00dev, RT5392))
3455 rt2800_bbp_write(rt2x00dev, 106, 0x12);
3457 rt2800_bbp_write(rt2x00dev, 106, 0x35);
3459 if (rt2x00_rt(rt2x00dev, RT3290) ||
3460 rt2x00_rt(rt2x00dev, RT5390) ||
3461 rt2x00_rt(rt2x00dev, RT5392))
3462 rt2800_bbp_write(rt2x00dev, 128, 0x12);
3464 if (rt2x00_rt(rt2x00dev, RT5392)) {
3465 rt2800_bbp_write(rt2x00dev, 134, 0xd0);
3466 rt2800_bbp_write(rt2x00dev, 135, 0xf6);
3469 if (rt2x00_rt(rt2x00dev, RT3071) ||
3470 rt2x00_rt(rt2x00dev, RT3090) ||
3471 rt2x00_rt(rt2x00dev, RT3390) ||
3472 rt2x00_rt(rt2x00dev, RT3572) ||
3473 rt2x00_rt(rt2x00dev, RT5390) ||
3474 rt2x00_rt(rt2x00dev, RT5392)) {
3475 rt2800_bbp_read(rt2x00dev, 138, &value);
3477 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
3478 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
3480 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
3483 rt2800_bbp_write(rt2x00dev, 138, value);
3486 if (rt2x00_rt(rt2x00dev, RT3290)) {
3487 rt2800_bbp_write(rt2x00dev, 67, 0x24);
3488 rt2800_bbp_write(rt2x00dev, 143, 0x04);
3489 rt2800_bbp_write(rt2x00dev, 142, 0x99);
3490 rt2800_bbp_write(rt2x00dev, 150, 0x30);
3491 rt2800_bbp_write(rt2x00dev, 151, 0x2e);
3492 rt2800_bbp_write(rt2x00dev, 152, 0x20);
3493 rt2800_bbp_write(rt2x00dev, 153, 0x34);
3494 rt2800_bbp_write(rt2x00dev, 154, 0x40);
3495 rt2800_bbp_write(rt2x00dev, 155, 0x3b);
3496 rt2800_bbp_write(rt2x00dev, 253, 0x04);
3498 rt2800_bbp_read(rt2x00dev, 47, &value);
3499 rt2x00_set_field8(&value, BBP47_TSSI_ADC6, 1);
3500 rt2800_bbp_write(rt2x00dev, 47, value);
3502 /* Use 5-bit ADC for Acquisition and 8-bit ADC for data */
3503 rt2800_bbp_read(rt2x00dev, 3, &value);
3504 rt2x00_set_field8(&value, BBP3_ADC_MODE_SWITCH, 1);
3505 rt2x00_set_field8(&value, BBP3_ADC_INIT_MODE, 1);
3506 rt2800_bbp_write(rt2x00dev, 3, value);
3509 if (rt2x00_rt(rt2x00dev, RT5390) ||
3510 rt2x00_rt(rt2x00dev, RT5392)) {
3513 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3514 div_mode = rt2x00_get_field16(eeprom,
3515 EEPROM_NIC_CONF1_ANT_DIVERSITY);
3516 ant = (div_mode == 3) ? 1 : 0;
3518 /* check if this is a Bluetooth combo card */
3519 if (test_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags)) {
3522 rt2800_register_read(rt2x00dev, GPIO_CTRL_CFG, ®);
3523 rt2x00_set_field32(®, GPIO_CTRL_CFG_GPIOD_BIT3, 0);
3524 rt2x00_set_field32(®, GPIO_CTRL_CFG_GPIOD_BIT6, 0);
3525 rt2x00_set_field32(®, GPIO_CTRL_CFG_BIT3, 0);
3526 rt2x00_set_field32(®, GPIO_CTRL_CFG_BIT6, 0);
3528 rt2x00_set_field32(®, GPIO_CTRL_CFG_BIT3, 1);
3530 rt2x00_set_field32(®, GPIO_CTRL_CFG_BIT6, 1);
3531 rt2800_register_write(rt2x00dev, GPIO_CTRL_CFG, reg);
3534 /* This chip has hardware antenna diversity*/
3535 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) {
3536 rt2800_bbp_write(rt2x00dev, 150, 0); /* Disable Antenna Software OFDM */
3537 rt2800_bbp_write(rt2x00dev, 151, 0); /* Disable Antenna Software CCK */
3538 rt2800_bbp_write(rt2x00dev, 154, 0); /* Clear previously selected antenna */
3541 rt2800_bbp_read(rt2x00dev, 152, &value);
3543 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 1);
3545 rt2x00_set_field8(&value, BBP152_RX_DEFAULT_ANT, 0);
3546 rt2800_bbp_write(rt2x00dev, 152, value);
3548 /* Init frequency calibration */
3549 rt2800_bbp_write(rt2x00dev, 142, 1);
3550 rt2800_bbp_write(rt2x00dev, 143, 57);
3553 for (i = 0; i < EEPROM_BBP_SIZE; i++) {
3554 rt2x00_eeprom_read(rt2x00dev, EEPROM_BBP_START + i, &eeprom);
3556 if (eeprom != 0xffff && eeprom != 0x0000) {
3557 reg_id = rt2x00_get_field16(eeprom, EEPROM_BBP_REG_ID);
3558 value = rt2x00_get_field16(eeprom, EEPROM_BBP_VALUE);
3559 rt2800_bbp_write(rt2x00dev, reg_id, value);
3566 static u8 rt2800_init_rx_filter(struct rt2x00_dev *rt2x00dev,
3567 bool bw40, u8 rfcsr24, u8 filter_target)
3576 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
3578 rt2800_bbp_read(rt2x00dev, 4, &bbp);
3579 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 2 * bw40);
3580 rt2800_bbp_write(rt2x00dev, 4, bbp);
3582 rt2800_rfcsr_read(rt2x00dev, 31, &rfcsr);
3583 rt2x00_set_field8(&rfcsr, RFCSR31_RX_H20M, bw40);
3584 rt2800_rfcsr_write(rt2x00dev, 31, rfcsr);
3586 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
3587 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 1);
3588 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
3591 * Set power & frequency of passband test tone
3593 rt2800_bbp_write(rt2x00dev, 24, 0);
3595 for (i = 0; i < 100; i++) {
3596 rt2800_bbp_write(rt2x00dev, 25, 0x90);
3599 rt2800_bbp_read(rt2x00dev, 55, &passband);
3605 * Set power & frequency of stopband test tone
3607 rt2800_bbp_write(rt2x00dev, 24, 0x06);
3609 for (i = 0; i < 100; i++) {
3610 rt2800_bbp_write(rt2x00dev, 25, 0x90);
3613 rt2800_bbp_read(rt2x00dev, 55, &stopband);
3615 if ((passband - stopband) <= filter_target) {
3617 overtuned += ((passband - stopband) == filter_target);
3621 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
3624 rfcsr24 -= !!overtuned;
3626 rt2800_rfcsr_write(rt2x00dev, 24, rfcsr24);
3630 static int rt2800_init_rfcsr(struct rt2x00_dev *rt2x00dev)
3632 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
3638 if (!rt2x00_rt(rt2x00dev, RT3070) &&
3639 !rt2x00_rt(rt2x00dev, RT3071) &&
3640 !rt2x00_rt(rt2x00dev, RT3090) &&
3641 !rt2x00_rt(rt2x00dev, RT3290) &&
3642 !rt2x00_rt(rt2x00dev, RT3390) &&
3643 !rt2x00_rt(rt2x00dev, RT3572) &&
3644 !rt2x00_rt(rt2x00dev, RT5390) &&
3645 !rt2x00_rt(rt2x00dev, RT5392) &&
3646 !rt2800_is_305x_soc(rt2x00dev))
3650 * Init RF calibration.
3652 if (rt2x00_rt(rt2x00dev, RT3290) ||
3653 rt2x00_rt(rt2x00dev, RT5390) ||
3654 rt2x00_rt(rt2x00dev, RT5392)) {
3655 rt2800_rfcsr_read(rt2x00dev, 2, &rfcsr);
3656 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 1);
3657 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
3659 rt2x00_set_field8(&rfcsr, RFCSR2_RESCAL_EN, 0);
3660 rt2800_rfcsr_write(rt2x00dev, 2, rfcsr);
3662 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
3663 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 1);
3664 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3666 rt2x00_set_field8(&rfcsr, RFCSR30_RF_CALIBRATION, 0);
3667 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
3670 if (rt2x00_rt(rt2x00dev, RT3070) ||
3671 rt2x00_rt(rt2x00dev, RT3071) ||
3672 rt2x00_rt(rt2x00dev, RT3090)) {
3673 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
3674 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
3675 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
3676 rt2800_rfcsr_write(rt2x00dev, 7, 0x60);
3677 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
3678 rt2800_rfcsr_write(rt2x00dev, 10, 0x41);
3679 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
3680 rt2800_rfcsr_write(rt2x00dev, 12, 0x7b);
3681 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
3682 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
3683 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
3684 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
3685 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
3686 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
3687 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
3688 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
3689 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
3690 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
3691 rt2800_rfcsr_write(rt2x00dev, 29, 0x1f);
3692 } else if (rt2x00_rt(rt2x00dev, RT3290)) {
3693 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
3694 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
3695 rt2800_rfcsr_write(rt2x00dev, 3, 0x08);
3696 rt2800_rfcsr_write(rt2x00dev, 4, 0x00);
3697 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
3698 rt2800_rfcsr_write(rt2x00dev, 8, 0xf3);
3699 rt2800_rfcsr_write(rt2x00dev, 9, 0x02);
3700 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
3701 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
3702 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
3703 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
3704 rt2800_rfcsr_write(rt2x00dev, 18, 0x02);
3705 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
3706 rt2800_rfcsr_write(rt2x00dev, 25, 0x83);
3707 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
3708 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
3709 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
3710 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
3711 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
3712 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
3713 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
3714 rt2800_rfcsr_write(rt2x00dev, 34, 0x05);
3715 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
3716 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
3717 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
3718 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
3719 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
3720 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
3721 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
3722 rt2800_rfcsr_write(rt2x00dev, 43, 0x7b);
3723 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
3724 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
3725 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
3726 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
3727 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
3728 rt2800_rfcsr_write(rt2x00dev, 49, 0x98);
3729 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
3730 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
3731 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
3732 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
3733 rt2800_rfcsr_write(rt2x00dev, 56, 0x02);
3734 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
3735 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
3736 rt2800_rfcsr_write(rt2x00dev, 59, 0x09);
3737 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
3738 rt2800_rfcsr_write(rt2x00dev, 61, 0xc1);
3739 } else if (rt2x00_rt(rt2x00dev, RT3390)) {
3740 rt2800_rfcsr_write(rt2x00dev, 0, 0xa0);
3741 rt2800_rfcsr_write(rt2x00dev, 1, 0xe1);
3742 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
3743 rt2800_rfcsr_write(rt2x00dev, 3, 0x62);
3744 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
3745 rt2800_rfcsr_write(rt2x00dev, 5, 0x8b);
3746 rt2800_rfcsr_write(rt2x00dev, 6, 0x42);
3747 rt2800_rfcsr_write(rt2x00dev, 7, 0x34);
3748 rt2800_rfcsr_write(rt2x00dev, 8, 0x00);
3749 rt2800_rfcsr_write(rt2x00dev, 9, 0xc0);
3750 rt2800_rfcsr_write(rt2x00dev, 10, 0x61);
3751 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
3752 rt2800_rfcsr_write(rt2x00dev, 12, 0x3b);
3753 rt2800_rfcsr_write(rt2x00dev, 13, 0xe0);
3754 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
3755 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
3756 rt2800_rfcsr_write(rt2x00dev, 16, 0xe0);
3757 rt2800_rfcsr_write(rt2x00dev, 17, 0x94);
3758 rt2800_rfcsr_write(rt2x00dev, 18, 0x5c);
3759 rt2800_rfcsr_write(rt2x00dev, 19, 0x4a);
3760 rt2800_rfcsr_write(rt2x00dev, 20, 0xb2);
3761 rt2800_rfcsr_write(rt2x00dev, 21, 0xf6);
3762 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
3763 rt2800_rfcsr_write(rt2x00dev, 23, 0x14);
3764 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
3765 rt2800_rfcsr_write(rt2x00dev, 25, 0x3d);
3766 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
3767 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
3768 rt2800_rfcsr_write(rt2x00dev, 28, 0x41);
3769 rt2800_rfcsr_write(rt2x00dev, 29, 0x8f);
3770 rt2800_rfcsr_write(rt2x00dev, 30, 0x20);
3771 rt2800_rfcsr_write(rt2x00dev, 31, 0x0f);
3772 } else if (rt2x00_rt(rt2x00dev, RT3572)) {
3773 rt2800_rfcsr_write(rt2x00dev, 0, 0x70);
3774 rt2800_rfcsr_write(rt2x00dev, 1, 0x81);
3775 rt2800_rfcsr_write(rt2x00dev, 2, 0xf1);
3776 rt2800_rfcsr_write(rt2x00dev, 3, 0x02);
3777 rt2800_rfcsr_write(rt2x00dev, 4, 0x4c);
3778 rt2800_rfcsr_write(rt2x00dev, 5, 0x05);
3779 rt2800_rfcsr_write(rt2x00dev, 6, 0x4a);
3780 rt2800_rfcsr_write(rt2x00dev, 7, 0xd8);
3781 rt2800_rfcsr_write(rt2x00dev, 9, 0xc3);
3782 rt2800_rfcsr_write(rt2x00dev, 10, 0xf1);
3783 rt2800_rfcsr_write(rt2x00dev, 11, 0xb9);
3784 rt2800_rfcsr_write(rt2x00dev, 12, 0x70);
3785 rt2800_rfcsr_write(rt2x00dev, 13, 0x65);
3786 rt2800_rfcsr_write(rt2x00dev, 14, 0xa0);
3787 rt2800_rfcsr_write(rt2x00dev, 15, 0x53);
3788 rt2800_rfcsr_write(rt2x00dev, 16, 0x4c);
3789 rt2800_rfcsr_write(rt2x00dev, 17, 0x23);
3790 rt2800_rfcsr_write(rt2x00dev, 18, 0xac);
3791 rt2800_rfcsr_write(rt2x00dev, 19, 0x93);
3792 rt2800_rfcsr_write(rt2x00dev, 20, 0xb3);
3793 rt2800_rfcsr_write(rt2x00dev, 21, 0xd0);
3794 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
3795 rt2800_rfcsr_write(rt2x00dev, 23, 0x3c);
3796 rt2800_rfcsr_write(rt2x00dev, 24, 0x16);
3797 rt2800_rfcsr_write(rt2x00dev, 25, 0x15);
3798 rt2800_rfcsr_write(rt2x00dev, 26, 0x85);
3799 rt2800_rfcsr_write(rt2x00dev, 27, 0x00);
3800 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
3801 rt2800_rfcsr_write(rt2x00dev, 29, 0x9b);
3802 rt2800_rfcsr_write(rt2x00dev, 30, 0x09);
3803 rt2800_rfcsr_write(rt2x00dev, 31, 0x10);
3804 } else if (rt2800_is_305x_soc(rt2x00dev)) {
3805 rt2800_rfcsr_write(rt2x00dev, 0, 0x50);
3806 rt2800_rfcsr_write(rt2x00dev, 1, 0x01);
3807 rt2800_rfcsr_write(rt2x00dev, 2, 0xf7);
3808 rt2800_rfcsr_write(rt2x00dev, 3, 0x75);
3809 rt2800_rfcsr_write(rt2x00dev, 4, 0x40);
3810 rt2800_rfcsr_write(rt2x00dev, 5, 0x03);
3811 rt2800_rfcsr_write(rt2x00dev, 6, 0x02);
3812 rt2800_rfcsr_write(rt2x00dev, 7, 0x50);
3813 rt2800_rfcsr_write(rt2x00dev, 8, 0x39);
3814 rt2800_rfcsr_write(rt2x00dev, 9, 0x0f);
3815 rt2800_rfcsr_write(rt2x00dev, 10, 0x60);
3816 rt2800_rfcsr_write(rt2x00dev, 11, 0x21);
3817 rt2800_rfcsr_write(rt2x00dev, 12, 0x75);
3818 rt2800_rfcsr_write(rt2x00dev, 13, 0x75);
3819 rt2800_rfcsr_write(rt2x00dev, 14, 0x90);
3820 rt2800_rfcsr_write(rt2x00dev, 15, 0x58);
3821 rt2800_rfcsr_write(rt2x00dev, 16, 0xb3);
3822 rt2800_rfcsr_write(rt2x00dev, 17, 0x92);
3823 rt2800_rfcsr_write(rt2x00dev, 18, 0x2c);
3824 rt2800_rfcsr_write(rt2x00dev, 19, 0x02);
3825 rt2800_rfcsr_write(rt2x00dev, 20, 0xba);
3826 rt2800_rfcsr_write(rt2x00dev, 21, 0xdb);
3827 rt2800_rfcsr_write(rt2x00dev, 22, 0x00);
3828 rt2800_rfcsr_write(rt2x00dev, 23, 0x31);
3829 rt2800_rfcsr_write(rt2x00dev, 24, 0x08);
3830 rt2800_rfcsr_write(rt2x00dev, 25, 0x01);
3831 rt2800_rfcsr_write(rt2x00dev, 26, 0x25);
3832 rt2800_rfcsr_write(rt2x00dev, 27, 0x23);
3833 rt2800_rfcsr_write(rt2x00dev, 28, 0x13);
3834 rt2800_rfcsr_write(rt2x00dev, 29, 0x83);
3835 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
3836 rt2800_rfcsr_write(rt2x00dev, 31, 0x00);
3838 } else if (rt2x00_rt(rt2x00dev, RT5390)) {
3839 rt2800_rfcsr_write(rt2x00dev, 1, 0x0f);
3840 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
3841 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
3842 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
3843 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3844 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
3846 rt2800_rfcsr_write(rt2x00dev, 6, 0xa0);
3847 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
3848 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
3849 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
3850 rt2800_rfcsr_write(rt2x00dev, 12, 0xc6);
3851 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
3852 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
3853 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
3854 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
3855 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
3856 rt2800_rfcsr_write(rt2x00dev, 19, 0x00);
3858 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
3859 rt2800_rfcsr_write(rt2x00dev, 21, 0x00);
3860 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
3861 rt2800_rfcsr_write(rt2x00dev, 23, 0x00);
3862 rt2800_rfcsr_write(rt2x00dev, 24, 0x00);
3863 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3864 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
3866 rt2800_rfcsr_write(rt2x00dev, 25, 0xc0);
3867 rt2800_rfcsr_write(rt2x00dev, 26, 0x00);
3868 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
3869 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
3870 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
3872 rt2800_rfcsr_write(rt2x00dev, 30, 0x00);
3873 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
3874 rt2800_rfcsr_write(rt2x00dev, 32, 0x80);
3875 rt2800_rfcsr_write(rt2x00dev, 33, 0x00);
3876 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
3877 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
3878 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
3879 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
3880 rt2800_rfcsr_write(rt2x00dev, 38, 0x85);
3881 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
3883 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3884 rt2800_rfcsr_write(rt2x00dev, 40, 0x0b);
3886 rt2800_rfcsr_write(rt2x00dev, 40, 0x4b);
3887 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
3888 rt2800_rfcsr_write(rt2x00dev, 42, 0xd2);
3889 rt2800_rfcsr_write(rt2x00dev, 43, 0x9a);
3890 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
3891 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
3892 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3893 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
3895 rt2800_rfcsr_write(rt2x00dev, 46, 0x7b);
3896 rt2800_rfcsr_write(rt2x00dev, 47, 0x00);
3897 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
3898 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
3900 rt2800_rfcsr_write(rt2x00dev, 52, 0x38);
3901 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3902 rt2800_rfcsr_write(rt2x00dev, 53, 0x00);
3904 rt2800_rfcsr_write(rt2x00dev, 53, 0x84);
3905 rt2800_rfcsr_write(rt2x00dev, 54, 0x78);
3906 rt2800_rfcsr_write(rt2x00dev, 55, 0x44);
3907 rt2800_rfcsr_write(rt2x00dev, 56, 0x22);
3908 rt2800_rfcsr_write(rt2x00dev, 57, 0x80);
3909 rt2800_rfcsr_write(rt2x00dev, 58, 0x7f);
3910 rt2800_rfcsr_write(rt2x00dev, 59, 0x63);
3912 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
3913 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390F))
3914 rt2800_rfcsr_write(rt2x00dev, 61, 0xd1);
3916 rt2800_rfcsr_write(rt2x00dev, 61, 0xdd);
3917 rt2800_rfcsr_write(rt2x00dev, 62, 0x00);
3918 rt2800_rfcsr_write(rt2x00dev, 63, 0x00);
3919 } else if (rt2x00_rt(rt2x00dev, RT5392)) {
3920 rt2800_rfcsr_write(rt2x00dev, 1, 0x17);
3921 rt2800_rfcsr_write(rt2x00dev, 2, 0x80);
3922 rt2800_rfcsr_write(rt2x00dev, 3, 0x88);
3923 rt2800_rfcsr_write(rt2x00dev, 5, 0x10);
3924 rt2800_rfcsr_write(rt2x00dev, 6, 0xe0);
3925 rt2800_rfcsr_write(rt2x00dev, 7, 0x00);
3926 rt2800_rfcsr_write(rt2x00dev, 10, 0x53);
3927 rt2800_rfcsr_write(rt2x00dev, 11, 0x4a);
3928 rt2800_rfcsr_write(rt2x00dev, 12, 0x46);
3929 rt2800_rfcsr_write(rt2x00dev, 13, 0x9f);
3930 rt2800_rfcsr_write(rt2x00dev, 14, 0x00);
3931 rt2800_rfcsr_write(rt2x00dev, 15, 0x00);
3932 rt2800_rfcsr_write(rt2x00dev, 16, 0x00);
3933 rt2800_rfcsr_write(rt2x00dev, 18, 0x03);
3934 rt2800_rfcsr_write(rt2x00dev, 19, 0x4d);
3935 rt2800_rfcsr_write(rt2x00dev, 20, 0x00);
3936 rt2800_rfcsr_write(rt2x00dev, 21, 0x8d);
3937 rt2800_rfcsr_write(rt2x00dev, 22, 0x20);
3938 rt2800_rfcsr_write(rt2x00dev, 23, 0x0b);
3939 rt2800_rfcsr_write(rt2x00dev, 24, 0x44);
3940 rt2800_rfcsr_write(rt2x00dev, 25, 0x80);
3941 rt2800_rfcsr_write(rt2x00dev, 26, 0x82);
3942 rt2800_rfcsr_write(rt2x00dev, 27, 0x09);
3943 rt2800_rfcsr_write(rt2x00dev, 28, 0x00);
3944 rt2800_rfcsr_write(rt2x00dev, 29, 0x10);
3945 rt2800_rfcsr_write(rt2x00dev, 30, 0x10);
3946 rt2800_rfcsr_write(rt2x00dev, 31, 0x80);
3947 rt2800_rfcsr_write(rt2x00dev, 32, 0x20);
3948 rt2800_rfcsr_write(rt2x00dev, 33, 0xC0);
3949 rt2800_rfcsr_write(rt2x00dev, 34, 0x07);
3950 rt2800_rfcsr_write(rt2x00dev, 35, 0x12);
3951 rt2800_rfcsr_write(rt2x00dev, 36, 0x00);
3952 rt2800_rfcsr_write(rt2x00dev, 37, 0x08);
3953 rt2800_rfcsr_write(rt2x00dev, 38, 0x89);
3954 rt2800_rfcsr_write(rt2x00dev, 39, 0x1b);
3955 rt2800_rfcsr_write(rt2x00dev, 40, 0x0f);
3956 rt2800_rfcsr_write(rt2x00dev, 41, 0xbb);
3957 rt2800_rfcsr_write(rt2x00dev, 42, 0xd5);
3958 rt2800_rfcsr_write(rt2x00dev, 43, 0x9b);
3959 rt2800_rfcsr_write(rt2x00dev, 44, 0x0e);
3960 rt2800_rfcsr_write(rt2x00dev, 45, 0xa2);
3961 rt2800_rfcsr_write(rt2x00dev, 46, 0x73);
3962 rt2800_rfcsr_write(rt2x00dev, 47, 0x0c);
3963 rt2800_rfcsr_write(rt2x00dev, 48, 0x10);
3964 rt2800_rfcsr_write(rt2x00dev, 49, 0x94);
3965 rt2800_rfcsr_write(rt2x00dev, 50, 0x94);
3966 rt2800_rfcsr_write(rt2x00dev, 51, 0x3a);
3967 rt2800_rfcsr_write(rt2x00dev, 52, 0x48);
3968 rt2800_rfcsr_write(rt2x00dev, 53, 0x44);
3969 rt2800_rfcsr_write(rt2x00dev, 54, 0x38);
3970 rt2800_rfcsr_write(rt2x00dev, 55, 0x43);
3971 rt2800_rfcsr_write(rt2x00dev, 56, 0xa1);
3972 rt2800_rfcsr_write(rt2x00dev, 57, 0x00);
3973 rt2800_rfcsr_write(rt2x00dev, 58, 0x39);
3974 rt2800_rfcsr_write(rt2x00dev, 59, 0x07);
3975 rt2800_rfcsr_write(rt2x00dev, 60, 0x45);
3976 rt2800_rfcsr_write(rt2x00dev, 61, 0x91);
3977 rt2800_rfcsr_write(rt2x00dev, 62, 0x39);
3978 rt2800_rfcsr_write(rt2x00dev, 63, 0x07);
3981 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F)) {
3982 rt2800_register_read(rt2x00dev, LDO_CFG0, ®);
3983 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1);
3984 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3);
3985 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
3986 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
3987 rt2x00_rt(rt2x00dev, RT3090)) {
3988 rt2800_rfcsr_write(rt2x00dev, 31, 0x14);
3990 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
3991 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
3992 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
3994 rt2800_register_read(rt2x00dev, LDO_CFG0, ®);
3995 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1);
3996 if (rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
3997 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E)) {
3998 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
3999 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_DAC_TEST))
4000 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3);
4002 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 0);
4004 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
4006 rt2800_register_read(rt2x00dev, GPIO_SWITCH, ®);
4007 rt2x00_set_field32(®, GPIO_SWITCH_5, 0);
4008 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
4009 } else if (rt2x00_rt(rt2x00dev, RT3390)) {
4010 rt2800_register_read(rt2x00dev, GPIO_SWITCH, ®);
4011 rt2x00_set_field32(®, GPIO_SWITCH_5, 0);
4012 rt2800_register_write(rt2x00dev, GPIO_SWITCH, reg);
4013 } else if (rt2x00_rt(rt2x00dev, RT3572)) {
4014 rt2800_rfcsr_read(rt2x00dev, 6, &rfcsr);
4015 rt2x00_set_field8(&rfcsr, RFCSR6_R2, 1);
4016 rt2800_rfcsr_write(rt2x00dev, 6, rfcsr);
4018 rt2800_register_read(rt2x00dev, LDO_CFG0, ®);
4019 rt2x00_set_field32(®, LDO_CFG0_LDO_CORE_VLEVEL, 3);
4020 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1);
4021 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
4023 rt2800_register_read(rt2x00dev, LDO_CFG0, ®);
4024 rt2x00_set_field32(®, LDO_CFG0_BGSEL, 1);
4025 rt2800_register_write(rt2x00dev, LDO_CFG0, reg);
4029 * Set RX Filter calibration for 20MHz and 40MHz
4031 if (rt2x00_rt(rt2x00dev, RT3070)) {
4032 drv_data->calibration_bw20 =
4033 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x16);
4034 drv_data->calibration_bw40 =
4035 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x19);
4036 } else if (rt2x00_rt(rt2x00dev, RT3071) ||
4037 rt2x00_rt(rt2x00dev, RT3090) ||
4038 rt2x00_rt(rt2x00dev, RT3390) ||
4039 rt2x00_rt(rt2x00dev, RT3572)) {
4040 drv_data->calibration_bw20 =
4041 rt2800_init_rx_filter(rt2x00dev, false, 0x07, 0x13);
4042 drv_data->calibration_bw40 =
4043 rt2800_init_rx_filter(rt2x00dev, true, 0x27, 0x15);
4047 * Save BBP 25 & 26 values for later use in channel switching
4049 rt2800_bbp_read(rt2x00dev, 25, &drv_data->bbp25);
4050 rt2800_bbp_read(rt2x00dev, 26, &drv_data->bbp26);
4052 if (!rt2x00_rt(rt2x00dev, RT5390) &&
4053 !rt2x00_rt(rt2x00dev, RT5392)) {
4055 * Set back to initial state
4057 rt2800_bbp_write(rt2x00dev, 24, 0);
4059 rt2800_rfcsr_read(rt2x00dev, 22, &rfcsr);
4060 rt2x00_set_field8(&rfcsr, RFCSR22_BASEBAND_LOOPBACK, 0);
4061 rt2800_rfcsr_write(rt2x00dev, 22, rfcsr);
4064 * Set BBP back to BW20
4066 rt2800_bbp_read(rt2x00dev, 4, &bbp);
4067 rt2x00_set_field8(&bbp, BBP4_BANDWIDTH, 0);
4068 rt2800_bbp_write(rt2x00dev, 4, bbp);
4071 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F) ||
4072 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
4073 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
4074 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E))
4075 rt2800_rfcsr_write(rt2x00dev, 27, 0x03);
4077 rt2800_register_read(rt2x00dev, OPT_14_CSR, ®);
4078 rt2x00_set_field32(®, OPT_14_CSR_BIT0, 1);
4079 rt2800_register_write(rt2x00dev, OPT_14_CSR, reg);
4081 if (!rt2x00_rt(rt2x00dev, RT5390) &&
4082 !rt2x00_rt(rt2x00dev, RT5392)) {
4083 rt2800_rfcsr_read(rt2x00dev, 17, &rfcsr);
4084 rt2x00_set_field8(&rfcsr, RFCSR17_TX_LO1_EN, 0);
4085 if (rt2x00_rt(rt2x00dev, RT3070) ||
4086 rt2x00_rt_rev_lt(rt2x00dev, RT3071, REV_RT3071E) ||
4087 rt2x00_rt_rev_lt(rt2x00dev, RT3090, REV_RT3090E) ||
4088 rt2x00_rt_rev_lt(rt2x00dev, RT3390, REV_RT3390E)) {
4089 if (!test_bit(CAPABILITY_EXTERNAL_LNA_BG,
4090 &rt2x00dev->cap_flags))
4091 rt2x00_set_field8(&rfcsr, RFCSR17_R, 1);
4093 rt2x00_set_field8(&rfcsr, RFCSR17_TXMIXER_GAIN,
4094 drv_data->txmixer_gain_24g);
4095 rt2800_rfcsr_write(rt2x00dev, 17, rfcsr);
4098 if (rt2x00_rt(rt2x00dev, RT3090)) {
4099 rt2800_bbp_read(rt2x00dev, 138, &bbp);
4101 /* Turn off unused DAC1 and ADC1 to reduce power consumption */
4102 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
4103 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) == 1)
4104 rt2x00_set_field8(&bbp, BBP138_RX_ADC1, 0);
4105 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) == 1)
4106 rt2x00_set_field8(&bbp, BBP138_TX_DAC1, 1);
4108 rt2800_bbp_write(rt2x00dev, 138, bbp);
4111 if (rt2x00_rt(rt2x00dev, RT3071) ||
4112 rt2x00_rt(rt2x00dev, RT3090) ||
4113 rt2x00_rt(rt2x00dev, RT3390)) {
4114 rt2800_rfcsr_read(rt2x00dev, 1, &rfcsr);
4115 rt2x00_set_field8(&rfcsr, RFCSR1_RF_BLOCK_EN, 1);
4116 rt2x00_set_field8(&rfcsr, RFCSR1_RX0_PD, 0);
4117 rt2x00_set_field8(&rfcsr, RFCSR1_TX0_PD, 0);
4118 rt2x00_set_field8(&rfcsr, RFCSR1_RX1_PD, 1);
4119 rt2x00_set_field8(&rfcsr, RFCSR1_TX1_PD, 1);
4120 rt2800_rfcsr_write(rt2x00dev, 1, rfcsr);
4122 rt2800_rfcsr_read(rt2x00dev, 15, &rfcsr);
4123 rt2x00_set_field8(&rfcsr, RFCSR15_TX_LO2_EN, 0);
4124 rt2800_rfcsr_write(rt2x00dev, 15, rfcsr);
4126 rt2800_rfcsr_read(rt2x00dev, 20, &rfcsr);
4127 rt2x00_set_field8(&rfcsr, RFCSR20_RX_LO1_EN, 0);
4128 rt2800_rfcsr_write(rt2x00dev, 20, rfcsr);
4130 rt2800_rfcsr_read(rt2x00dev, 21, &rfcsr);
4131 rt2x00_set_field8(&rfcsr, RFCSR21_RX_LO2_EN, 0);
4132 rt2800_rfcsr_write(rt2x00dev, 21, rfcsr);
4135 if (rt2x00_rt(rt2x00dev, RT3070)) {
4136 rt2800_rfcsr_read(rt2x00dev, 27, &rfcsr);
4137 if (rt2x00_rt_rev_lt(rt2x00dev, RT3070, REV_RT3070F))
4138 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 3);
4140 rt2x00_set_field8(&rfcsr, RFCSR27_R1, 0);
4141 rt2x00_set_field8(&rfcsr, RFCSR27_R2, 0);
4142 rt2x00_set_field8(&rfcsr, RFCSR27_R3, 0);
4143 rt2x00_set_field8(&rfcsr, RFCSR27_R4, 0);
4144 rt2800_rfcsr_write(rt2x00dev, 27, rfcsr);
4147 if (rt2x00_rt(rt2x00dev, RT3290)) {
4148 rt2800_rfcsr_read(rt2x00dev, 29, &rfcsr);
4149 rt2x00_set_field8(&rfcsr, RFCSR29_RSSI_GAIN, 3);
4150 rt2800_rfcsr_write(rt2x00dev, 29, rfcsr);
4153 if (rt2x00_rt(rt2x00dev, RT5390) ||
4154 rt2x00_rt(rt2x00dev, RT5392)) {
4155 rt2800_rfcsr_read(rt2x00dev, 38, &rfcsr);
4156 rt2x00_set_field8(&rfcsr, RFCSR38_RX_LO1_EN, 0);
4157 rt2800_rfcsr_write(rt2x00dev, 38, rfcsr);
4159 rt2800_rfcsr_read(rt2x00dev, 39, &rfcsr);
4160 rt2x00_set_field8(&rfcsr, RFCSR39_RX_LO2_EN, 0);
4161 rt2800_rfcsr_write(rt2x00dev, 39, rfcsr);
4163 rt2800_rfcsr_read(rt2x00dev, 30, &rfcsr);
4164 rt2x00_set_field8(&rfcsr, RFCSR30_RX_VCM, 2);
4165 rt2800_rfcsr_write(rt2x00dev, 30, rfcsr);
4171 int rt2800_enable_radio(struct rt2x00_dev *rt2x00dev)
4177 * Initialize all registers.
4179 if (unlikely(rt2800_wait_wpdma_ready(rt2x00dev) ||
4180 rt2800_init_registers(rt2x00dev) ||
4181 rt2800_init_bbp(rt2x00dev) ||
4182 rt2800_init_rfcsr(rt2x00dev)))
4186 * Send signal to firmware during boot time.
4188 rt2800_mcu_request(rt2x00dev, MCU_BOOT_SIGNAL, 0, 0, 0);
4190 if (rt2x00_is_usb(rt2x00dev) &&
4191 (rt2x00_rt(rt2x00dev, RT3070) ||
4192 rt2x00_rt(rt2x00dev, RT3071) ||
4193 rt2x00_rt(rt2x00dev, RT3572))) {
4195 rt2800_mcu_request(rt2x00dev, MCU_CURRENT, 0, 0, 0);
4202 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, ®);
4203 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 1);
4204 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 0);
4205 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
4209 rt2800_register_read(rt2x00dev, WPDMA_GLO_CFG, ®);
4210 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_TX_DMA, 1);
4211 rt2x00_set_field32(®, WPDMA_GLO_CFG_ENABLE_RX_DMA, 1);
4212 rt2x00_set_field32(®, WPDMA_GLO_CFG_WP_DMA_BURST_SIZE, 2);
4213 rt2x00_set_field32(®, WPDMA_GLO_CFG_TX_WRITEBACK_DONE, 1);
4214 rt2800_register_write(rt2x00dev, WPDMA_GLO_CFG, reg);
4216 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, ®);
4217 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 1);
4218 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 1);
4219 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
4222 * Initialize LED control
4224 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_AG_CONF, &word);
4225 rt2800_mcu_request(rt2x00dev, MCU_LED_AG_CONF, 0xff,
4226 word & 0xff, (word >> 8) & 0xff);
4228 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_ACT_CONF, &word);
4229 rt2800_mcu_request(rt2x00dev, MCU_LED_ACT_CONF, 0xff,
4230 word & 0xff, (word >> 8) & 0xff);
4232 rt2x00_eeprom_read(rt2x00dev, EEPROM_LED_POLARITY, &word);
4233 rt2800_mcu_request(rt2x00dev, MCU_LED_LED_POLARITY, 0xff,
4234 word & 0xff, (word >> 8) & 0xff);
4238 EXPORT_SYMBOL_GPL(rt2800_enable_radio);
4240 void rt2800_disable_radio(struct rt2x00_dev *rt2x00dev)
4244 rt2800_disable_wpdma(rt2x00dev);
4246 /* Wait for DMA, ignore error */
4247 rt2800_wait_wpdma_ready(rt2x00dev);
4249 rt2800_register_read(rt2x00dev, MAC_SYS_CTRL, ®);
4250 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_TX, 0);
4251 rt2x00_set_field32(®, MAC_SYS_CTRL_ENABLE_RX, 0);
4252 rt2800_register_write(rt2x00dev, MAC_SYS_CTRL, reg);
4254 EXPORT_SYMBOL_GPL(rt2800_disable_radio);
4256 int rt2800_efuse_detect(struct rt2x00_dev *rt2x00dev)
4261 if (rt2x00_rt(rt2x00dev, RT3290))
4262 efuse_ctrl_reg = EFUSE_CTRL_3290;
4264 efuse_ctrl_reg = EFUSE_CTRL;
4266 rt2800_register_read(rt2x00dev, efuse_ctrl_reg, ®);
4267 return rt2x00_get_field32(reg, EFUSE_CTRL_PRESENT);
4269 EXPORT_SYMBOL_GPL(rt2800_efuse_detect);
4271 static void rt2800_efuse_read(struct rt2x00_dev *rt2x00dev, unsigned int i)
4275 u16 efuse_data0_reg;
4276 u16 efuse_data1_reg;
4277 u16 efuse_data2_reg;
4278 u16 efuse_data3_reg;
4280 if (rt2x00_rt(rt2x00dev, RT3290)) {
4281 efuse_ctrl_reg = EFUSE_CTRL_3290;
4282 efuse_data0_reg = EFUSE_DATA0_3290;
4283 efuse_data1_reg = EFUSE_DATA1_3290;
4284 efuse_data2_reg = EFUSE_DATA2_3290;
4285 efuse_data3_reg = EFUSE_DATA3_3290;
4287 efuse_ctrl_reg = EFUSE_CTRL;
4288 efuse_data0_reg = EFUSE_DATA0;
4289 efuse_data1_reg = EFUSE_DATA1;
4290 efuse_data2_reg = EFUSE_DATA2;
4291 efuse_data3_reg = EFUSE_DATA3;
4293 mutex_lock(&rt2x00dev->csr_mutex);
4295 rt2800_register_read_lock(rt2x00dev, efuse_ctrl_reg, ®);
4296 rt2x00_set_field32(®, EFUSE_CTRL_ADDRESS_IN, i);
4297 rt2x00_set_field32(®, EFUSE_CTRL_MODE, 0);
4298 rt2x00_set_field32(®, EFUSE_CTRL_KICK, 1);
4299 rt2800_register_write_lock(rt2x00dev, efuse_ctrl_reg, reg);
4301 /* Wait until the EEPROM has been loaded */
4302 rt2800_regbusy_read(rt2x00dev, efuse_ctrl_reg, EFUSE_CTRL_KICK, ®);
4303 /* Apparently the data is read from end to start */
4304 rt2800_register_read_lock(rt2x00dev, efuse_data3_reg, ®);
4305 /* The returned value is in CPU order, but eeprom is le */
4306 *(u32 *)&rt2x00dev->eeprom[i] = cpu_to_le32(reg);
4307 rt2800_register_read_lock(rt2x00dev, efuse_data2_reg, ®);
4308 *(u32 *)&rt2x00dev->eeprom[i + 2] = cpu_to_le32(reg);
4309 rt2800_register_read_lock(rt2x00dev, efuse_data1_reg, ®);
4310 *(u32 *)&rt2x00dev->eeprom[i + 4] = cpu_to_le32(reg);
4311 rt2800_register_read_lock(rt2x00dev, efuse_data0_reg, ®);
4312 *(u32 *)&rt2x00dev->eeprom[i + 6] = cpu_to_le32(reg);
4314 mutex_unlock(&rt2x00dev->csr_mutex);
4317 void rt2800_read_eeprom_efuse(struct rt2x00_dev *rt2x00dev)
4321 for (i = 0; i < EEPROM_SIZE / sizeof(u16); i += 8)
4322 rt2800_efuse_read(rt2x00dev, i);
4324 EXPORT_SYMBOL_GPL(rt2800_read_eeprom_efuse);
4326 int rt2800_validate_eeprom(struct rt2x00_dev *rt2x00dev)
4328 struct rt2800_drv_data *drv_data = rt2x00dev->drv_data;
4331 u8 default_lna_gain;
4334 * Start validation of the data that has been read.
4336 mac = rt2x00_eeprom_addr(rt2x00dev, EEPROM_MAC_ADDR_0);
4337 if (!is_valid_ether_addr(mac)) {
4338 eth_random_addr(mac);
4339 EEPROM(rt2x00dev, "MAC: %pM\n", mac);
4342 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &word);
4343 if (word == 0xffff) {
4344 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
4345 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_TXPATH, 1);
4346 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RF_TYPE, RF2820);
4347 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
4348 EEPROM(rt2x00dev, "Antenna: 0x%04x\n", word);
4349 } else if (rt2x00_rt(rt2x00dev, RT2860) ||
4350 rt2x00_rt(rt2x00dev, RT2872)) {
4352 * There is a max of 2 RX streams for RT28x0 series
4354 if (rt2x00_get_field16(word, EEPROM_NIC_CONF0_RXPATH) > 2)
4355 rt2x00_set_field16(&word, EEPROM_NIC_CONF0_RXPATH, 2);
4356 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF0, word);
4359 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &word);
4360 if (word == 0xffff) {
4361 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_HW_RADIO, 0);
4362 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_TX_ALC, 0);
4363 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G, 0);
4364 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G, 0);
4365 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_CARDBUS_ACCEL, 0);
4366 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_2G, 0);
4367 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_SB_5G, 0);
4368 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_WPS_PBC, 0);
4369 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_2G, 0);
4370 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BW40M_5G, 0);
4371 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BROADBAND_EXT_LNA, 0);
4372 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_ANT_DIVERSITY, 0);
4373 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_INTERNAL_TX_ALC, 0);
4374 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_BT_COEXIST, 0);
4375 rt2x00_set_field16(&word, EEPROM_NIC_CONF1_DAC_TEST, 0);
4376 rt2x00_eeprom_write(rt2x00dev, EEPROM_NIC_CONF1, word);
4377 EEPROM(rt2x00dev, "NIC: 0x%04x\n", word);
4380 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &word);
4381 if ((word & 0x00ff) == 0x00ff) {
4382 rt2x00_set_field16(&word, EEPROM_FREQ_OFFSET, 0);
4383 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
4384 EEPROM(rt2x00dev, "Freq: 0x%04x\n", word);
4386 if ((word & 0xff00) == 0xff00) {
4387 rt2x00_set_field16(&word, EEPROM_FREQ_LED_MODE,
4388 LED_MODE_TXRX_ACTIVITY);
4389 rt2x00_set_field16(&word, EEPROM_FREQ_LED_POLARITY, 0);
4390 rt2x00_eeprom_write(rt2x00dev, EEPROM_FREQ, word);
4391 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_AG_CONF, 0x5555);
4392 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_ACT_CONF, 0x2221);
4393 rt2x00_eeprom_write(rt2x00dev, EEPROM_LED_POLARITY, 0xa9f8);
4394 EEPROM(rt2x00dev, "Led Mode: 0x%04x\n", word);
4398 * During the LNA validation we are going to use
4399 * lna0 as correct value. Note that EEPROM_LNA
4400 * is never validated.
4402 rt2x00_eeprom_read(rt2x00dev, EEPROM_LNA, &word);
4403 default_lna_gain = rt2x00_get_field16(word, EEPROM_LNA_A0);
4405 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG, &word);
4406 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET0)) > 10)
4407 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET0, 0);
4408 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG_OFFSET1)) > 10)
4409 rt2x00_set_field16(&word, EEPROM_RSSI_BG_OFFSET1, 0);
4410 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG, word);
4412 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_BG, &word);
4413 if ((word & 0x00ff) != 0x00ff) {
4414 drv_data->txmixer_gain_24g =
4415 rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_BG_VAL);
4417 drv_data->txmixer_gain_24g = 0;
4420 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_BG2, &word);
4421 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_BG2_OFFSET2)) > 10)
4422 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_OFFSET2, 0);
4423 if (rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0x00 ||
4424 rt2x00_get_field16(word, EEPROM_RSSI_BG2_LNA_A1) == 0xff)
4425 rt2x00_set_field16(&word, EEPROM_RSSI_BG2_LNA_A1,
4427 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_BG2, word);
4429 rt2x00_eeprom_read(rt2x00dev, EEPROM_TXMIXER_GAIN_A, &word);
4430 if ((word & 0x00ff) != 0x00ff) {
4431 drv_data->txmixer_gain_5g =
4432 rt2x00_get_field16(word, EEPROM_TXMIXER_GAIN_A_VAL);
4434 drv_data->txmixer_gain_5g = 0;
4437 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A, &word);
4438 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET0)) > 10)
4439 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET0, 0);
4440 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A_OFFSET1)) > 10)
4441 rt2x00_set_field16(&word, EEPROM_RSSI_A_OFFSET1, 0);
4442 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A, word);
4444 rt2x00_eeprom_read(rt2x00dev, EEPROM_RSSI_A2, &word);
4445 if (abs(rt2x00_get_field16(word, EEPROM_RSSI_A2_OFFSET2)) > 10)
4446 rt2x00_set_field16(&word, EEPROM_RSSI_A2_OFFSET2, 0);
4447 if (rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0x00 ||
4448 rt2x00_get_field16(word, EEPROM_RSSI_A2_LNA_A2) == 0xff)
4449 rt2x00_set_field16(&word, EEPROM_RSSI_A2_LNA_A2,
4451 rt2x00_eeprom_write(rt2x00dev, EEPROM_RSSI_A2, word);
4455 EXPORT_SYMBOL_GPL(rt2800_validate_eeprom);
4457 int rt2800_init_eeprom(struct rt2x00_dev *rt2x00dev)
4464 * Read EEPROM word for configuration.
4466 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
4469 * Identify RF chipset by EEPROM value
4470 * RT28xx/RT30xx: defined in "EEPROM_NIC_CONF0_RF_TYPE" field
4471 * RT53xx: defined in "EEPROM_CHIP_ID" field
4473 if (rt2x00_rt(rt2x00dev, RT3290))
4474 rt2800_register_read(rt2x00dev, MAC_CSR0_3290, ®);
4476 rt2800_register_read(rt2x00dev, MAC_CSR0, ®);
4478 if (rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT3290 ||
4479 rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT5390 ||
4480 rt2x00_get_field32(reg, MAC_CSR0_CHIPSET) == RT5392)
4481 rt2x00_eeprom_read(rt2x00dev, EEPROM_CHIP_ID, &value);
4483 value = rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RF_TYPE);
4485 rt2x00_set_chip(rt2x00dev, rt2x00_get_field32(reg, MAC_CSR0_CHIPSET),
4486 value, rt2x00_get_field32(reg, MAC_CSR0_REVISION));
4488 switch (rt2x00dev->chip.rt) {
4502 ERROR(rt2x00dev, "Invalid RT chipset 0x%04x detected.\n", rt2x00dev->chip.rt);
4506 switch (rt2x00dev->chip.rf) {
4525 ERROR(rt2x00dev, "Invalid RF chipset 0x%04x detected.\n",
4526 rt2x00dev->chip.rf);
4531 * Identify default antenna configuration.
4533 rt2x00dev->default_ant.tx_chain_num =
4534 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH);
4535 rt2x00dev->default_ant.rx_chain_num =
4536 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH);
4538 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF1, &eeprom);
4540 if (rt2x00_rt(rt2x00dev, RT3070) ||
4541 rt2x00_rt(rt2x00dev, RT3090) ||
4542 rt2x00_rt(rt2x00dev, RT3390)) {
4543 value = rt2x00_get_field16(eeprom,
4544 EEPROM_NIC_CONF1_ANT_DIVERSITY);
4549 rt2x00dev->default_ant.tx = ANTENNA_A;
4550 rt2x00dev->default_ant.rx = ANTENNA_A;
4553 rt2x00dev->default_ant.tx = ANTENNA_A;
4554 rt2x00dev->default_ant.rx = ANTENNA_B;
4558 rt2x00dev->default_ant.tx = ANTENNA_A;
4559 rt2x00dev->default_ant.rx = ANTENNA_A;
4562 if (rt2x00_rt_rev_gte(rt2x00dev, RT5390, REV_RT5390R)) {
4563 rt2x00dev->default_ant.tx = ANTENNA_HW_DIVERSITY; /* Unused */
4564 rt2x00dev->default_ant.rx = ANTENNA_HW_DIVERSITY; /* Unused */
4568 * Determine external LNA informations.
4570 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_5G))
4571 __set_bit(CAPABILITY_EXTERNAL_LNA_A, &rt2x00dev->cap_flags);
4572 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_EXTERNAL_LNA_2G))
4573 __set_bit(CAPABILITY_EXTERNAL_LNA_BG, &rt2x00dev->cap_flags);
4576 * Detect if this device has an hardware controlled radio.
4578 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_HW_RADIO))
4579 __set_bit(CAPABILITY_HW_BUTTON, &rt2x00dev->cap_flags);
4582 * Detect if this device has Bluetooth co-existence.
4584 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF1_BT_COEXIST))
4585 __set_bit(CAPABILITY_BT_COEXIST, &rt2x00dev->cap_flags);
4588 * Read frequency offset and RF programming sequence.
4590 rt2x00_eeprom_read(rt2x00dev, EEPROM_FREQ, &eeprom);
4591 rt2x00dev->freq_offset = rt2x00_get_field16(eeprom, EEPROM_FREQ_OFFSET);
4594 * Store led settings, for correct led behaviour.
4596 #ifdef CONFIG_RT2X00_LIB_LEDS
4597 rt2800_init_led(rt2x00dev, &rt2x00dev->led_radio, LED_TYPE_RADIO);
4598 rt2800_init_led(rt2x00dev, &rt2x00dev->led_assoc, LED_TYPE_ASSOC);
4599 rt2800_init_led(rt2x00dev, &rt2x00dev->led_qual, LED_TYPE_QUALITY);
4601 rt2x00dev->led_mcu_reg = eeprom;
4602 #endif /* CONFIG_RT2X00_LIB_LEDS */
4605 * Check if support EIRP tx power limit feature.
4607 rt2x00_eeprom_read(rt2x00dev, EEPROM_EIRP_MAX_TX_POWER, &eeprom);
4609 if (rt2x00_get_field16(eeprom, EEPROM_EIRP_MAX_TX_POWER_2GHZ) <
4610 EIRP_MAX_TX_POWER_LIMIT)
4611 __set_bit(CAPABILITY_POWER_LIMIT, &rt2x00dev->cap_flags);
4615 EXPORT_SYMBOL_GPL(rt2800_init_eeprom);
4618 * RF value list for rt28xx
4619 * Supports: 2.4 GHz (all) & 5.2 GHz (RF2850 & RF2750)
4621 static const struct rf_channel rf_vals[] = {
4622 { 1, 0x18402ecc, 0x184c0786, 0x1816b455, 0x1800510b },
4623 { 2, 0x18402ecc, 0x184c0786, 0x18168a55, 0x1800519f },
4624 { 3, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800518b },
4625 { 4, 0x18402ecc, 0x184c078a, 0x18168a55, 0x1800519f },
4626 { 5, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800518b },
4627 { 6, 0x18402ecc, 0x184c078e, 0x18168a55, 0x1800519f },
4628 { 7, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800518b },
4629 { 8, 0x18402ecc, 0x184c0792, 0x18168a55, 0x1800519f },
4630 { 9, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800518b },
4631 { 10, 0x18402ecc, 0x184c0796, 0x18168a55, 0x1800519f },
4632 { 11, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800518b },
4633 { 12, 0x18402ecc, 0x184c079a, 0x18168a55, 0x1800519f },
4634 { 13, 0x18402ecc, 0x184c079e, 0x18168a55, 0x1800518b },
4635 { 14, 0x18402ecc, 0x184c07a2, 0x18168a55, 0x18005193 },
4637 /* 802.11 UNI / HyperLan 2 */
4638 { 36, 0x18402ecc, 0x184c099a, 0x18158a55, 0x180ed1a3 },
4639 { 38, 0x18402ecc, 0x184c099e, 0x18158a55, 0x180ed193 },
4640 { 40, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed183 },
4641 { 44, 0x18402ec8, 0x184c0682, 0x18158a55, 0x180ed1a3 },
4642 { 46, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed18b },
4643 { 48, 0x18402ec8, 0x184c0686, 0x18158a55, 0x180ed19b },
4644 { 52, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed193 },
4645 { 54, 0x18402ec8, 0x184c068a, 0x18158a55, 0x180ed1a3 },
4646 { 56, 0x18402ec8, 0x184c068e, 0x18158a55, 0x180ed18b },
4647 { 60, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed183 },
4648 { 62, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed193 },
4649 { 64, 0x18402ec8, 0x184c0692, 0x18158a55, 0x180ed1a3 },
4651 /* 802.11 HyperLan 2 */
4652 { 100, 0x18402ec8, 0x184c06b2, 0x18178a55, 0x180ed783 },
4653 { 102, 0x18402ec8, 0x184c06b2, 0x18578a55, 0x180ed793 },
4654 { 104, 0x18402ec8, 0x185c06b2, 0x18578a55, 0x180ed1a3 },
4655 { 108, 0x18402ecc, 0x185c0a32, 0x18578a55, 0x180ed193 },
4656 { 110, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed183 },
4657 { 112, 0x18402ecc, 0x184c0a36, 0x18178a55, 0x180ed19b },
4658 { 116, 0x18402ecc, 0x184c0a3a, 0x18178a55, 0x180ed1a3 },
4659 { 118, 0x18402ecc, 0x184c0a3e, 0x18178a55, 0x180ed193 },
4660 { 120, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed183 },
4661 { 124, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed193 },
4662 { 126, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed15b },
4663 { 128, 0x18402ec4, 0x184c0382, 0x18178a55, 0x180ed1a3 },
4664 { 132, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed18b },
4665 { 134, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed193 },
4666 { 136, 0x18402ec4, 0x184c0386, 0x18178a55, 0x180ed19b },
4667 { 140, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed183 },
4670 { 149, 0x18402ec4, 0x184c038a, 0x18178a55, 0x180ed1a7 },
4671 { 151, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed187 },
4672 { 153, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed18f },
4673 { 157, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed19f },
4674 { 159, 0x18402ec4, 0x184c038e, 0x18178a55, 0x180ed1a7 },
4675 { 161, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed187 },
4676 { 165, 0x18402ec4, 0x184c0392, 0x18178a55, 0x180ed197 },
4677 { 167, 0x18402ec4, 0x184c03d2, 0x18179855, 0x1815531f },
4678 { 169, 0x18402ec4, 0x184c03d2, 0x18179855, 0x18155327 },
4679 { 171, 0x18402ec4, 0x184c03d6, 0x18179855, 0x18155307 },
4680 { 173, 0x18402ec4, 0x184c03d6, 0x18179855, 0x1815530f },
4683 { 184, 0x15002ccc, 0x1500491e, 0x1509be55, 0x150c0a0b },
4684 { 188, 0x15002ccc, 0x15004922, 0x1509be55, 0x150c0a13 },
4685 { 192, 0x15002ccc, 0x15004926, 0x1509be55, 0x150c0a1b },
4686 { 196, 0x15002ccc, 0x1500492a, 0x1509be55, 0x150c0a23 },
4687 { 208, 0x15002ccc, 0x1500493a, 0x1509be55, 0x150c0a13 },
4688 { 212, 0x15002ccc, 0x1500493e, 0x1509be55, 0x150c0a1b },
4689 { 216, 0x15002ccc, 0x15004982, 0x1509be55, 0x150c0a23 },
4693 * RF value list for rt3xxx
4694 * Supports: 2.4 GHz (all) & 5.2 GHz (RF3052)
4696 static const struct rf_channel rf_vals_3x[] = {
4712 /* 802.11 UNI / HyperLan 2 */
4726 /* 802.11 HyperLan 2 */
4758 int rt2800_probe_hw_mode(struct rt2x00_dev *rt2x00dev)
4760 struct hw_mode_spec *spec = &rt2x00dev->spec;
4761 struct channel_info *info;
4762 char *default_power1;
4763 char *default_power2;
4768 * Disable powersaving as default on PCI devices.
4770 if (rt2x00_is_pci(rt2x00dev) || rt2x00_is_soc(rt2x00dev))
4771 rt2x00dev->hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
4774 * Initialize all hw fields.
4776 rt2x00dev->hw->flags =
4777 IEEE80211_HW_SIGNAL_DBM |
4778 IEEE80211_HW_SUPPORTS_PS |
4779 IEEE80211_HW_PS_NULLFUNC_STACK |
4780 IEEE80211_HW_AMPDU_AGGREGATION |
4781 IEEE80211_HW_REPORTS_TX_ACK_STATUS;
4784 * Don't set IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING for USB devices
4785 * unless we are capable of sending the buffered frames out after the
4786 * DTIM transmission using rt2x00lib_beacondone. This will send out
4787 * multicast and broadcast traffic immediately instead of buffering it
4788 * infinitly and thus dropping it after some time.
4790 if (!rt2x00_is_usb(rt2x00dev))
4791 rt2x00dev->hw->flags |=
4792 IEEE80211_HW_HOST_BROADCAST_PS_BUFFERING;
4794 SET_IEEE80211_DEV(rt2x00dev->hw, rt2x00dev->dev);
4795 SET_IEEE80211_PERM_ADDR(rt2x00dev->hw,
4796 rt2x00_eeprom_addr(rt2x00dev,
4797 EEPROM_MAC_ADDR_0));
4800 * As rt2800 has a global fallback table we cannot specify
4801 * more then one tx rate per frame but since the hw will
4802 * try several rates (based on the fallback table) we should
4803 * initialize max_report_rates to the maximum number of rates
4804 * we are going to try. Otherwise mac80211 will truncate our
4805 * reported tx rates and the rc algortihm will end up with
4808 rt2x00dev->hw->max_rates = 1;
4809 rt2x00dev->hw->max_report_rates = 7;
4810 rt2x00dev->hw->max_rate_tries = 1;
4812 rt2x00_eeprom_read(rt2x00dev, EEPROM_NIC_CONF0, &eeprom);
4815 * Initialize hw_mode information.
4817 spec->supported_bands = SUPPORT_BAND_2GHZ;
4818 spec->supported_rates = SUPPORT_RATE_CCK | SUPPORT_RATE_OFDM;
4820 if (rt2x00_rf(rt2x00dev, RF2820) ||
4821 rt2x00_rf(rt2x00dev, RF2720)) {
4822 spec->num_channels = 14;
4823 spec->channels = rf_vals;
4824 } else if (rt2x00_rf(rt2x00dev, RF2850) ||
4825 rt2x00_rf(rt2x00dev, RF2750)) {
4826 spec->supported_bands |= SUPPORT_BAND_5GHZ;
4827 spec->num_channels = ARRAY_SIZE(rf_vals);
4828 spec->channels = rf_vals;
4829 } else if (rt2x00_rf(rt2x00dev, RF3020) ||
4830 rt2x00_rf(rt2x00dev, RF2020) ||
4831 rt2x00_rf(rt2x00dev, RF3021) ||
4832 rt2x00_rf(rt2x00dev, RF3022) ||
4833 rt2x00_rf(rt2x00dev, RF3290) ||
4834 rt2x00_rf(rt2x00dev, RF3320) ||
4835 rt2x00_rf(rt2x00dev, RF5360) ||
4836 rt2x00_rf(rt2x00dev, RF5370) ||
4837 rt2x00_rf(rt2x00dev, RF5372) ||
4838 rt2x00_rf(rt2x00dev, RF5390) ||
4839 rt2x00_rf(rt2x00dev, RF5392)) {
4840 spec->num_channels = 14;
4841 spec->channels = rf_vals_3x;
4842 } else if (rt2x00_rf(rt2x00dev, RF3052)) {
4843 spec->supported_bands |= SUPPORT_BAND_5GHZ;
4844 spec->num_channels = ARRAY_SIZE(rf_vals_3x);
4845 spec->channels = rf_vals_3x;
4849 * Initialize HT information.
4851 if (!rt2x00_rf(rt2x00dev, RF2020))
4852 spec->ht.ht_supported = true;
4854 spec->ht.ht_supported = false;
4857 IEEE80211_HT_CAP_SUP_WIDTH_20_40 |
4858 IEEE80211_HT_CAP_GRN_FLD |
4859 IEEE80211_HT_CAP_SGI_20 |
4860 IEEE80211_HT_CAP_SGI_40;
4862 if (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) >= 2)
4863 spec->ht.cap |= IEEE80211_HT_CAP_TX_STBC;
4866 rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH) <<
4867 IEEE80211_HT_CAP_RX_STBC_SHIFT;
4869 spec->ht.ampdu_factor = 3;
4870 spec->ht.ampdu_density = 4;
4871 spec->ht.mcs.tx_params =
4872 IEEE80211_HT_MCS_TX_DEFINED |
4873 IEEE80211_HT_MCS_TX_RX_DIFF |
4874 ((rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_TXPATH) - 1) <<
4875 IEEE80211_HT_MCS_TX_MAX_STREAMS_SHIFT);
4877 switch (rt2x00_get_field16(eeprom, EEPROM_NIC_CONF0_RXPATH)) {
4879 spec->ht.mcs.rx_mask[2] = 0xff;
4881 spec->ht.mcs.rx_mask[1] = 0xff;
4883 spec->ht.mcs.rx_mask[0] = 0xff;
4884 spec->ht.mcs.rx_mask[4] = 0x1; /* MCS32 */
4889 * Create channel information array
4891 info = kcalloc(spec->num_channels, sizeof(*info), GFP_KERNEL);
4895 spec->channels_info = info;
4897 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG1);
4898 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_BG2);
4900 for (i = 0; i < 14; i++) {
4901 info[i].default_power1 = default_power1[i];
4902 info[i].default_power2 = default_power2[i];
4905 if (spec->num_channels > 14) {
4906 default_power1 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A1);
4907 default_power2 = rt2x00_eeprom_addr(rt2x00dev, EEPROM_TXPOWER_A2);
4909 for (i = 14; i < spec->num_channels; i++) {
4910 info[i].default_power1 = default_power1[i];
4911 info[i].default_power2 = default_power2[i];
4915 switch (rt2x00dev->chip.rf) {
4928 __set_bit(CAPABILITY_VCO_RECALIBRATION, &rt2x00dev->cap_flags);
4934 EXPORT_SYMBOL_GPL(rt2800_probe_hw_mode);
4937 * IEEE80211 stack callback functions.
4939 void rt2800_get_tkip_seq(struct ieee80211_hw *hw, u8 hw_key_idx, u32 *iv32,
4942 struct rt2x00_dev *rt2x00dev = hw->priv;
4943 struct mac_iveiv_entry iveiv_entry;
4946 offset = MAC_IVEIV_ENTRY(hw_key_idx);
4947 rt2800_register_multiread(rt2x00dev, offset,
4948 &iveiv_entry, sizeof(iveiv_entry));
4950 memcpy(iv16, &iveiv_entry.iv[0], sizeof(*iv16));
4951 memcpy(iv32, &iveiv_entry.iv[4], sizeof(*iv32));
4953 EXPORT_SYMBOL_GPL(rt2800_get_tkip_seq);
4955 int rt2800_set_rts_threshold(struct ieee80211_hw *hw, u32 value)
4957 struct rt2x00_dev *rt2x00dev = hw->priv;
4959 bool enabled = (value < IEEE80211_MAX_RTS_THRESHOLD);
4961 rt2800_register_read(rt2x00dev, TX_RTS_CFG, ®);
4962 rt2x00_set_field32(®, TX_RTS_CFG_RTS_THRES, value);
4963 rt2800_register_write(rt2x00dev, TX_RTS_CFG, reg);
4965 rt2800_register_read(rt2x00dev, CCK_PROT_CFG, ®);
4966 rt2x00_set_field32(®, CCK_PROT_CFG_RTS_TH_EN, enabled);
4967 rt2800_register_write(rt2x00dev, CCK_PROT_CFG, reg);
4969 rt2800_register_read(rt2x00dev, OFDM_PROT_CFG, ®);
4970 rt2x00_set_field32(®, OFDM_PROT_CFG_RTS_TH_EN, enabled);
4971 rt2800_register_write(rt2x00dev, OFDM_PROT_CFG, reg);
4973 rt2800_register_read(rt2x00dev, MM20_PROT_CFG, ®);
4974 rt2x00_set_field32(®, MM20_PROT_CFG_RTS_TH_EN, enabled);
4975 rt2800_register_write(rt2x00dev, MM20_PROT_CFG, reg);
4977 rt2800_register_read(rt2x00dev, MM40_PROT_CFG, ®);
4978 rt2x00_set_field32(®, MM40_PROT_CFG_RTS_TH_EN, enabled);
4979 rt2800_register_write(rt2x00dev, MM40_PROT_CFG, reg);
4981 rt2800_register_read(rt2x00dev, GF20_PROT_CFG, ®);
4982 rt2x00_set_field32(®, GF20_PROT_CFG_RTS_TH_EN, enabled);
4983 rt2800_register_write(rt2x00dev, GF20_PROT_CFG, reg);
4985 rt2800_register_read(rt2x00dev, GF40_PROT_CFG, ®);
4986 rt2x00_set_field32(®, GF40_PROT_CFG_RTS_TH_EN, enabled);
4987 rt2800_register_write(rt2x00dev, GF40_PROT_CFG, reg);
4991 EXPORT_SYMBOL_GPL(rt2800_set_rts_threshold);
4993 int rt2800_conf_tx(struct ieee80211_hw *hw,
4994 struct ieee80211_vif *vif, u16 queue_idx,
4995 const struct ieee80211_tx_queue_params *params)
4997 struct rt2x00_dev *rt2x00dev = hw->priv;
4998 struct data_queue *queue;
4999 struct rt2x00_field32 field;
5005 * First pass the configuration through rt2x00lib, that will
5006 * update the queue settings and validate the input. After that
5007 * we are free to update the registers based on the value
5008 * in the queue parameter.
5010 retval = rt2x00mac_conf_tx(hw, vif, queue_idx, params);
5015 * We only need to perform additional register initialization
5021 queue = rt2x00queue_get_tx_queue(rt2x00dev, queue_idx);
5023 /* Update WMM TXOP register */
5024 offset = WMM_TXOP0_CFG + (sizeof(u32) * (!!(queue_idx & 2)));
5025 field.bit_offset = (queue_idx & 1) * 16;
5026 field.bit_mask = 0xffff << field.bit_offset;
5028 rt2800_register_read(rt2x00dev, offset, ®);
5029 rt2x00_set_field32(®, field, queue->txop);
5030 rt2800_register_write(rt2x00dev, offset, reg);
5032 /* Update WMM registers */
5033 field.bit_offset = queue_idx * 4;
5034 field.bit_mask = 0xf << field.bit_offset;
5036 rt2800_register_read(rt2x00dev, WMM_AIFSN_CFG, ®);
5037 rt2x00_set_field32(®, field, queue->aifs);
5038 rt2800_register_write(rt2x00dev, WMM_AIFSN_CFG, reg);
5040 rt2800_register_read(rt2x00dev, WMM_CWMIN_CFG, ®);
5041 rt2x00_set_field32(®, field, queue->cw_min);
5042 rt2800_register_write(rt2x00dev, WMM_CWMIN_CFG, reg);
5044 rt2800_register_read(rt2x00dev, WMM_CWMAX_CFG, ®);
5045 rt2x00_set_field32(®, field, queue->cw_max);
5046 rt2800_register_write(rt2x00dev, WMM_CWMAX_CFG, reg);
5048 /* Update EDCA registers */
5049 offset = EDCA_AC0_CFG + (sizeof(u32) * queue_idx);
5051 rt2800_register_read(rt2x00dev, offset, ®);
5052 rt2x00_set_field32(®, EDCA_AC0_CFG_TX_OP, queue->txop);
5053 rt2x00_set_field32(®, EDCA_AC0_CFG_AIFSN, queue->aifs);
5054 rt2x00_set_field32(®, EDCA_AC0_CFG_CWMIN, queue->cw_min);
5055 rt2x00_set_field32(®, EDCA_AC0_CFG_CWMAX, queue->cw_max);
5056 rt2800_register_write(rt2x00dev, offset, reg);
5060 EXPORT_SYMBOL_GPL(rt2800_conf_tx);
5062 u64 rt2800_get_tsf(struct ieee80211_hw *hw, struct ieee80211_vif *vif)
5064 struct rt2x00_dev *rt2x00dev = hw->priv;
5068 rt2800_register_read(rt2x00dev, TSF_TIMER_DW1, ®);
5069 tsf = (u64) rt2x00_get_field32(reg, TSF_TIMER_DW1_HIGH_WORD) << 32;
5070 rt2800_register_read(rt2x00dev, TSF_TIMER_DW0, ®);
5071 tsf |= rt2x00_get_field32(reg, TSF_TIMER_DW0_LOW_WORD);
5075 EXPORT_SYMBOL_GPL(rt2800_get_tsf);
5077 int rt2800_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
5078 enum ieee80211_ampdu_mlme_action action,
5079 struct ieee80211_sta *sta, u16 tid, u16 *ssn,
5082 struct rt2x00_sta *sta_priv = (struct rt2x00_sta *)sta->drv_priv;
5086 * Don't allow aggregation for stations the hardware isn't aware
5087 * of because tx status reports for frames to an unknown station
5088 * always contain wcid=255 and thus we can't distinguish between
5089 * multiple stations which leads to unwanted situations when the
5090 * hw reorders frames due to aggregation.
5092 if (sta_priv->wcid < 0)
5096 case IEEE80211_AMPDU_RX_START:
5097 case IEEE80211_AMPDU_RX_STOP:
5099 * The hw itself takes care of setting up BlockAck mechanisms.
5100 * So, we only have to allow mac80211 to nagotiate a BlockAck
5101 * agreement. Once that is done, the hw will BlockAck incoming
5102 * AMPDUs without further setup.
5105 case IEEE80211_AMPDU_TX_START:
5106 ieee80211_start_tx_ba_cb_irqsafe(vif, sta->addr, tid);
5108 case IEEE80211_AMPDU_TX_STOP:
5109 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid);
5111 case IEEE80211_AMPDU_TX_OPERATIONAL:
5114 WARNING((struct rt2x00_dev *)hw->priv, "Unknown AMPDU action\n");
5119 EXPORT_SYMBOL_GPL(rt2800_ampdu_action);
5121 int rt2800_get_survey(struct ieee80211_hw *hw, int idx,
5122 struct survey_info *survey)
5124 struct rt2x00_dev *rt2x00dev = hw->priv;
5125 struct ieee80211_conf *conf = &hw->conf;
5126 u32 idle, busy, busy_ext;
5131 survey->channel = conf->channel;
5133 rt2800_register_read(rt2x00dev, CH_IDLE_STA, &idle);
5134 rt2800_register_read(rt2x00dev, CH_BUSY_STA, &busy);
5135 rt2800_register_read(rt2x00dev, CH_BUSY_STA_SEC, &busy_ext);
5138 survey->filled = SURVEY_INFO_CHANNEL_TIME |
5139 SURVEY_INFO_CHANNEL_TIME_BUSY |
5140 SURVEY_INFO_CHANNEL_TIME_EXT_BUSY;
5142 survey->channel_time = (idle + busy) / 1000;
5143 survey->channel_time_busy = busy / 1000;
5144 survey->channel_time_ext_busy = busy_ext / 1000;
5147 if (!(hw->conf.flags & IEEE80211_CONF_OFFCHANNEL))
5148 survey->filled |= SURVEY_INFO_IN_USE;
5153 EXPORT_SYMBOL_GPL(rt2800_get_survey);
5155 MODULE_AUTHOR(DRV_PROJECT ", Bartlomiej Zolnierkiewicz");
5156 MODULE_VERSION(DRV_VERSION);
5157 MODULE_DESCRIPTION("Ralink RT2800 library");
5158 MODULE_LICENSE("GPL");