2 Copyright (C) 2004 - 2010 Ivo van Doorn <IvDoorn@gmail.com>
3 Copyright (C) 2010 Willow Garage <http://www.willowgarage.com>
4 Copyright (C) 2009 Alban Browaeys <prahal@yahoo.com>
5 Copyright (C) 2009 Felix Fietkau <nbd@openwrt.org>
6 Copyright (C) 2009 Luis Correia <luis.f.correia@gmail.com>
7 Copyright (C) 2009 Mattias Nissler <mattias.nissler@gmx.de>
8 Copyright (C) 2009 Mark Asselstine <asselsm@gmail.com>
9 Copyright (C) 2009 Xose Vazquez Perez <xose.vazquez@gmail.com>
10 Copyright (C) 2009 Bart Zolnierkiewicz <bzolnier@gmail.com>
11 <http://rt2x00.serialmonkey.com>
13 This program is free software; you can redistribute it and/or modify
14 it under the terms of the GNU General Public License as published by
15 the Free Software Foundation; either version 2 of the License, or
16 (at your option) any later version.
18 This program is distributed in the hope that it will be useful,
19 but WITHOUT ANY WARRANTY; without even the implied warranty of
20 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
21 GNU General Public License for more details.
23 You should have received a copy of the GNU General Public License
24 along with this program; if not, write to the
25 Free Software Foundation, Inc.,
26 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
31 Abstract: Data structures and registers for the rt2800 modules.
32 Supported chipsets: RT2800E, RT2800ED & RT2800U.
65 #define REV_RT2860C 0x0100
66 #define REV_RT2860D 0x0101
67 #define REV_RT2872E 0x0200
68 #define REV_RT3070E 0x0200
69 #define REV_RT3070F 0x0201
70 #define REV_RT3071E 0x0211
71 #define REV_RT3090E 0x0211
72 #define REV_RT3390E 0x0211
76 * Default offset is required for RSSI <-> dBm conversion.
78 #define DEFAULT_RSSI_OFFSET 120
81 * Register layout information.
83 #define CSR_REG_BASE 0x1000
84 #define CSR_REG_SIZE 0x0800
85 #define EEPROM_BASE 0x0000
86 #define EEPROM_SIZE 0x0110
87 #define BBP_BASE 0x0000
88 #define BBP_SIZE 0x0080
89 #define RF_BASE 0x0004
90 #define RF_SIZE 0x0010
93 * Number of TX queues.
95 #define NUM_TX_QUEUES 4
102 * E2PROM_CSR: PCI EEPROM control register.
103 * RELOAD: Write 1 to reload eeprom content.
104 * TYPE: 0: 93c46, 1:93c66.
105 * LOAD_STATUS: 1:loading, 0:done.
107 #define E2PROM_CSR 0x0004
108 #define E2PROM_CSR_DATA_CLOCK FIELD32(0x00000001)
109 #define E2PROM_CSR_CHIP_SELECT FIELD32(0x00000002)
110 #define E2PROM_CSR_DATA_IN FIELD32(0x00000004)
111 #define E2PROM_CSR_DATA_OUT FIELD32(0x00000008)
112 #define E2PROM_CSR_TYPE FIELD32(0x00000030)
113 #define E2PROM_CSR_LOAD_STATUS FIELD32(0x00000040)
114 #define E2PROM_CSR_RELOAD FIELD32(0x00000080)
117 * OPT_14: Unknown register used by rt3xxx devices.
119 #define OPT_14_CSR 0x0114
120 #define OPT_14_CSR_BIT0 FIELD32(0x00000001)
123 * INT_SOURCE_CSR: Interrupt source register.
124 * Write one to clear corresponding bit.
125 * TX_FIFO_STATUS: FIFO Statistics is full, sw should read TX_STA_FIFO
127 #define INT_SOURCE_CSR 0x0200
128 #define INT_SOURCE_CSR_RXDELAYINT FIELD32(0x00000001)
129 #define INT_SOURCE_CSR_TXDELAYINT FIELD32(0x00000002)
130 #define INT_SOURCE_CSR_RX_DONE FIELD32(0x00000004)
131 #define INT_SOURCE_CSR_AC0_DMA_DONE FIELD32(0x00000008)
132 #define INT_SOURCE_CSR_AC1_DMA_DONE FIELD32(0x00000010)
133 #define INT_SOURCE_CSR_AC2_DMA_DONE FIELD32(0x00000020)
134 #define INT_SOURCE_CSR_AC3_DMA_DONE FIELD32(0x00000040)
135 #define INT_SOURCE_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
136 #define INT_SOURCE_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
137 #define INT_SOURCE_CSR_MCU_COMMAND FIELD32(0x00000200)
138 #define INT_SOURCE_CSR_RXTX_COHERENT FIELD32(0x00000400)
139 #define INT_SOURCE_CSR_TBTT FIELD32(0x00000800)
140 #define INT_SOURCE_CSR_PRE_TBTT FIELD32(0x00001000)
141 #define INT_SOURCE_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
142 #define INT_SOURCE_CSR_AUTO_WAKEUP FIELD32(0x00004000)
143 #define INT_SOURCE_CSR_GPTIMER FIELD32(0x00008000)
144 #define INT_SOURCE_CSR_RX_COHERENT FIELD32(0x00010000)
145 #define INT_SOURCE_CSR_TX_COHERENT FIELD32(0x00020000)
148 * INT_MASK_CSR: Interrupt MASK register. 1: the interrupt is mask OFF.
150 #define INT_MASK_CSR 0x0204
151 #define INT_MASK_CSR_RXDELAYINT FIELD32(0x00000001)
152 #define INT_MASK_CSR_TXDELAYINT FIELD32(0x00000002)
153 #define INT_MASK_CSR_RX_DONE FIELD32(0x00000004)
154 #define INT_MASK_CSR_AC0_DMA_DONE FIELD32(0x00000008)
155 #define INT_MASK_CSR_AC1_DMA_DONE FIELD32(0x00000010)
156 #define INT_MASK_CSR_AC2_DMA_DONE FIELD32(0x00000020)
157 #define INT_MASK_CSR_AC3_DMA_DONE FIELD32(0x00000040)
158 #define INT_MASK_CSR_HCCA_DMA_DONE FIELD32(0x00000080)
159 #define INT_MASK_CSR_MGMT_DMA_DONE FIELD32(0x00000100)
160 #define INT_MASK_CSR_MCU_COMMAND FIELD32(0x00000200)
161 #define INT_MASK_CSR_RXTX_COHERENT FIELD32(0x00000400)
162 #define INT_MASK_CSR_TBTT FIELD32(0x00000800)
163 #define INT_MASK_CSR_PRE_TBTT FIELD32(0x00001000)
164 #define INT_MASK_CSR_TX_FIFO_STATUS FIELD32(0x00002000)
165 #define INT_MASK_CSR_AUTO_WAKEUP FIELD32(0x00004000)
166 #define INT_MASK_CSR_GPTIMER FIELD32(0x00008000)
167 #define INT_MASK_CSR_RX_COHERENT FIELD32(0x00010000)
168 #define INT_MASK_CSR_TX_COHERENT FIELD32(0x00020000)
173 #define WPDMA_GLO_CFG 0x0208
174 #define WPDMA_GLO_CFG_ENABLE_TX_DMA FIELD32(0x00000001)
175 #define WPDMA_GLO_CFG_TX_DMA_BUSY FIELD32(0x00000002)
176 #define WPDMA_GLO_CFG_ENABLE_RX_DMA FIELD32(0x00000004)
177 #define WPDMA_GLO_CFG_RX_DMA_BUSY FIELD32(0x00000008)
178 #define WPDMA_GLO_CFG_WP_DMA_BURST_SIZE FIELD32(0x00000030)
179 #define WPDMA_GLO_CFG_TX_WRITEBACK_DONE FIELD32(0x00000040)
180 #define WPDMA_GLO_CFG_BIG_ENDIAN FIELD32(0x00000080)
181 #define WPDMA_GLO_CFG_RX_HDR_SCATTER FIELD32(0x0000ff00)
182 #define WPDMA_GLO_CFG_HDR_SEG_LEN FIELD32(0xffff0000)
187 #define WPDMA_RST_IDX 0x020c
188 #define WPDMA_RST_IDX_DTX_IDX0 FIELD32(0x00000001)
189 #define WPDMA_RST_IDX_DTX_IDX1 FIELD32(0x00000002)
190 #define WPDMA_RST_IDX_DTX_IDX2 FIELD32(0x00000004)
191 #define WPDMA_RST_IDX_DTX_IDX3 FIELD32(0x00000008)
192 #define WPDMA_RST_IDX_DTX_IDX4 FIELD32(0x00000010)
193 #define WPDMA_RST_IDX_DTX_IDX5 FIELD32(0x00000020)
194 #define WPDMA_RST_IDX_DRX_IDX0 FIELD32(0x00010000)
199 #define DELAY_INT_CFG 0x0210
200 #define DELAY_INT_CFG_RXMAX_PTIME FIELD32(0x000000ff)
201 #define DELAY_INT_CFG_RXMAX_PINT FIELD32(0x00007f00)
202 #define DELAY_INT_CFG_RXDLY_INT_EN FIELD32(0x00008000)
203 #define DELAY_INT_CFG_TXMAX_PTIME FIELD32(0x00ff0000)
204 #define DELAY_INT_CFG_TXMAX_PINT FIELD32(0x7f000000)
205 #define DELAY_INT_CFG_TXDLY_INT_EN FIELD32(0x80000000)
208 * WMM_AIFSN_CFG: Aifsn for each EDCA AC
214 #define WMM_AIFSN_CFG 0x0214
215 #define WMM_AIFSN_CFG_AIFSN0 FIELD32(0x0000000f)
216 #define WMM_AIFSN_CFG_AIFSN1 FIELD32(0x000000f0)
217 #define WMM_AIFSN_CFG_AIFSN2 FIELD32(0x00000f00)
218 #define WMM_AIFSN_CFG_AIFSN3 FIELD32(0x0000f000)
221 * WMM_CWMIN_CSR: CWmin for each EDCA AC
227 #define WMM_CWMIN_CFG 0x0218
228 #define WMM_CWMIN_CFG_CWMIN0 FIELD32(0x0000000f)
229 #define WMM_CWMIN_CFG_CWMIN1 FIELD32(0x000000f0)
230 #define WMM_CWMIN_CFG_CWMIN2 FIELD32(0x00000f00)
231 #define WMM_CWMIN_CFG_CWMIN3 FIELD32(0x0000f000)
234 * WMM_CWMAX_CSR: CWmax for each EDCA AC
240 #define WMM_CWMAX_CFG 0x021c
241 #define WMM_CWMAX_CFG_CWMAX0 FIELD32(0x0000000f)
242 #define WMM_CWMAX_CFG_CWMAX1 FIELD32(0x000000f0)
243 #define WMM_CWMAX_CFG_CWMAX2 FIELD32(0x00000f00)
244 #define WMM_CWMAX_CFG_CWMAX3 FIELD32(0x0000f000)
247 * AC_TXOP0: AC_BK/AC_BE TXOP register
248 * AC0TXOP: AC_BK in unit of 32us
249 * AC1TXOP: AC_BE in unit of 32us
251 #define WMM_TXOP0_CFG 0x0220
252 #define WMM_TXOP0_CFG_AC0TXOP FIELD32(0x0000ffff)
253 #define WMM_TXOP0_CFG_AC1TXOP FIELD32(0xffff0000)
256 * AC_TXOP1: AC_VO/AC_VI TXOP register
257 * AC2TXOP: AC_VI in unit of 32us
258 * AC3TXOP: AC_VO in unit of 32us
260 #define WMM_TXOP1_CFG 0x0224
261 #define WMM_TXOP1_CFG_AC2TXOP FIELD32(0x0000ffff)
262 #define WMM_TXOP1_CFG_AC3TXOP FIELD32(0xffff0000)
267 #define GPIO_CTRL_CFG 0x0228
268 #define GPIO_CTRL_CFG_BIT0 FIELD32(0x00000001)
269 #define GPIO_CTRL_CFG_BIT1 FIELD32(0x00000002)
270 #define GPIO_CTRL_CFG_BIT2 FIELD32(0x00000004)
271 #define GPIO_CTRL_CFG_BIT3 FIELD32(0x00000008)
272 #define GPIO_CTRL_CFG_BIT4 FIELD32(0x00000010)
273 #define GPIO_CTRL_CFG_BIT5 FIELD32(0x00000020)
274 #define GPIO_CTRL_CFG_BIT6 FIELD32(0x00000040)
275 #define GPIO_CTRL_CFG_BIT7 FIELD32(0x00000080)
276 #define GPIO_CTRL_CFG_BIT8 FIELD32(0x00000100)
281 #define MCU_CMD_CFG 0x022c
284 * AC_BK register offsets
286 #define TX_BASE_PTR0 0x0230
287 #define TX_MAX_CNT0 0x0234
288 #define TX_CTX_IDX0 0x0238
289 #define TX_DTX_IDX0 0x023c
292 * AC_BE register offsets
294 #define TX_BASE_PTR1 0x0240
295 #define TX_MAX_CNT1 0x0244
296 #define TX_CTX_IDX1 0x0248
297 #define TX_DTX_IDX1 0x024c
300 * AC_VI register offsets
302 #define TX_BASE_PTR2 0x0250
303 #define TX_MAX_CNT2 0x0254
304 #define TX_CTX_IDX2 0x0258
305 #define TX_DTX_IDX2 0x025c
308 * AC_VO register offsets
310 #define TX_BASE_PTR3 0x0260
311 #define TX_MAX_CNT3 0x0264
312 #define TX_CTX_IDX3 0x0268
313 #define TX_DTX_IDX3 0x026c
316 * HCCA register offsets
318 #define TX_BASE_PTR4 0x0270
319 #define TX_MAX_CNT4 0x0274
320 #define TX_CTX_IDX4 0x0278
321 #define TX_DTX_IDX4 0x027c
324 * MGMT register offsets
326 #define TX_BASE_PTR5 0x0280
327 #define TX_MAX_CNT5 0x0284
328 #define TX_CTX_IDX5 0x0288
329 #define TX_DTX_IDX5 0x028c
332 * RX register offsets
334 #define RX_BASE_PTR 0x0290
335 #define RX_MAX_CNT 0x0294
336 #define RX_CRX_IDX 0x0298
337 #define RX_DRX_IDX 0x029c
341 * RX_BULK_AGG_TIMEOUT: Rx Bulk Aggregation TimeOut in unit of 33ns.
342 * RX_BULK_AGG_LIMIT: Rx Bulk Aggregation Limit in unit of 256 bytes.
343 * PHY_CLEAR: phy watch dog enable.
344 * TX_CLEAR: Clear USB DMA TX path.
345 * TXOP_HALT: Halt TXOP count down when TX buffer is full.
346 * RX_BULK_AGG_EN: Enable Rx Bulk Aggregation.
347 * RX_BULK_EN: Enable USB DMA Rx.
348 * TX_BULK_EN: Enable USB DMA Tx.
349 * EP_OUT_VALID: OUT endpoint data valid.
350 * RX_BUSY: USB DMA RX FSM busy.
351 * TX_BUSY: USB DMA TX FSM busy.
353 #define USB_DMA_CFG 0x02a0
354 #define USB_DMA_CFG_RX_BULK_AGG_TIMEOUT FIELD32(0x000000ff)
355 #define USB_DMA_CFG_RX_BULK_AGG_LIMIT FIELD32(0x0000ff00)
356 #define USB_DMA_CFG_PHY_CLEAR FIELD32(0x00010000)
357 #define USB_DMA_CFG_TX_CLEAR FIELD32(0x00080000)
358 #define USB_DMA_CFG_TXOP_HALT FIELD32(0x00100000)
359 #define USB_DMA_CFG_RX_BULK_AGG_EN FIELD32(0x00200000)
360 #define USB_DMA_CFG_RX_BULK_EN FIELD32(0x00400000)
361 #define USB_DMA_CFG_TX_BULK_EN FIELD32(0x00800000)
362 #define USB_DMA_CFG_EP_OUT_VALID FIELD32(0x3f000000)
363 #define USB_DMA_CFG_RX_BUSY FIELD32(0x40000000)
364 #define USB_DMA_CFG_TX_BUSY FIELD32(0x80000000)
369 #define US_CYC_CNT 0x02a4
370 #define US_CYC_CNT_CLOCK_CYCLE FIELD32(0x000000ff)
374 * HOST_RAM_WRITE: enable Host program ram write selection
376 #define PBF_SYS_CTRL 0x0400
377 #define PBF_SYS_CTRL_READY FIELD32(0x00000080)
378 #define PBF_SYS_CTRL_HOST_RAM_WRITE FIELD32(0x00010000)
381 * HOST-MCU shared memory
383 #define HOST_CMD_CSR 0x0404
384 #define HOST_CMD_CSR_HOST_COMMAND FIELD32(0x000000ff)
388 * Most are for debug. Driver doesn't touch PBF register.
390 #define PBF_CFG 0x0408
391 #define PBF_MAX_PCNT 0x040c
392 #define PBF_CTRL 0x0410
393 #define PBF_INT_STA 0x0414
394 #define PBF_INT_ENA 0x0418
399 #define BCN_OFFSET0 0x042c
400 #define BCN_OFFSET0_BCN0 FIELD32(0x000000ff)
401 #define BCN_OFFSET0_BCN1 FIELD32(0x0000ff00)
402 #define BCN_OFFSET0_BCN2 FIELD32(0x00ff0000)
403 #define BCN_OFFSET0_BCN3 FIELD32(0xff000000)
408 #define BCN_OFFSET1 0x0430
409 #define BCN_OFFSET1_BCN4 FIELD32(0x000000ff)
410 #define BCN_OFFSET1_BCN5 FIELD32(0x0000ff00)
411 #define BCN_OFFSET1_BCN6 FIELD32(0x00ff0000)
412 #define BCN_OFFSET1_BCN7 FIELD32(0xff000000)
416 * Most are for debug. Driver doesn't touch PBF register.
418 #define TXRXQ_PCNT 0x0438
419 #define PBF_DBG 0x043c
424 #define RF_CSR_CFG 0x0500
425 #define RF_CSR_CFG_DATA FIELD32(0x000000ff)
426 #define RF_CSR_CFG_REGNUM FIELD32(0x00001f00)
427 #define RF_CSR_CFG_WRITE FIELD32(0x00010000)
428 #define RF_CSR_CFG_BUSY FIELD32(0x00020000)
431 * EFUSE_CSR: RT30x0 EEPROM
433 #define EFUSE_CTRL 0x0580
434 #define EFUSE_CTRL_ADDRESS_IN FIELD32(0x03fe0000)
435 #define EFUSE_CTRL_MODE FIELD32(0x000000c0)
436 #define EFUSE_CTRL_KICK FIELD32(0x40000000)
437 #define EFUSE_CTRL_PRESENT FIELD32(0x80000000)
442 #define EFUSE_DATA0 0x0590
447 #define EFUSE_DATA1 0x0594
452 #define EFUSE_DATA2 0x0598
457 #define EFUSE_DATA3 0x059c
462 #define LDO_CFG0 0x05d4
463 #define LDO_CFG0_DELAY3 FIELD32(0x000000ff)
464 #define LDO_CFG0_DELAY2 FIELD32(0x0000ff00)
465 #define LDO_CFG0_DELAY1 FIELD32(0x00ff0000)
466 #define LDO_CFG0_BGSEL FIELD32(0x03000000)
467 #define LDO_CFG0_LDO_CORE_VLEVEL FIELD32(0x1c000000)
468 #define LD0_CFG0_LDO25_LEVEL FIELD32(0x60000000)
469 #define LDO_CFG0_LDO25_LARGEA FIELD32(0x80000000)
474 #define GPIO_SWITCH 0x05dc
475 #define GPIO_SWITCH_0 FIELD32(0x00000001)
476 #define GPIO_SWITCH_1 FIELD32(0x00000002)
477 #define GPIO_SWITCH_2 FIELD32(0x00000004)
478 #define GPIO_SWITCH_3 FIELD32(0x00000008)
479 #define GPIO_SWITCH_4 FIELD32(0x00000010)
480 #define GPIO_SWITCH_5 FIELD32(0x00000020)
481 #define GPIO_SWITCH_6 FIELD32(0x00000040)
482 #define GPIO_SWITCH_7 FIELD32(0x00000080)
485 * MAC Control/Status Registers(CSR).
486 * Some values are set in TU, whereas 1 TU == 1024 us.
490 * MAC_CSR0: ASIC revision number.
492 * ASIC_VER: 2860 or 2870
494 #define MAC_CSR0 0x1000
495 #define MAC_CSR0_REVISION FIELD32(0x0000ffff)
496 #define MAC_CSR0_CHIPSET FIELD32(0xffff0000)
501 #define MAC_SYS_CTRL 0x1004
502 #define MAC_SYS_CTRL_RESET_CSR FIELD32(0x00000001)
503 #define MAC_SYS_CTRL_RESET_BBP FIELD32(0x00000002)
504 #define MAC_SYS_CTRL_ENABLE_TX FIELD32(0x00000004)
505 #define MAC_SYS_CTRL_ENABLE_RX FIELD32(0x00000008)
506 #define MAC_SYS_CTRL_CONTINUOUS_TX FIELD32(0x00000010)
507 #define MAC_SYS_CTRL_LOOPBACK FIELD32(0x00000020)
508 #define MAC_SYS_CTRL_WLAN_HALT FIELD32(0x00000040)
509 #define MAC_SYS_CTRL_RX_TIMESTAMP FIELD32(0x00000080)
512 * MAC_ADDR_DW0: STA MAC register 0
514 #define MAC_ADDR_DW0 0x1008
515 #define MAC_ADDR_DW0_BYTE0 FIELD32(0x000000ff)
516 #define MAC_ADDR_DW0_BYTE1 FIELD32(0x0000ff00)
517 #define MAC_ADDR_DW0_BYTE2 FIELD32(0x00ff0000)
518 #define MAC_ADDR_DW0_BYTE3 FIELD32(0xff000000)
521 * MAC_ADDR_DW1: STA MAC register 1
522 * UNICAST_TO_ME_MASK:
523 * Used to mask off bits from byte 5 of the MAC address
524 * to determine the UNICAST_TO_ME bit for RX frames.
525 * The full mask is complemented by BSS_ID_MASK:
526 * MASK = BSS_ID_MASK & UNICAST_TO_ME_MASK
528 #define MAC_ADDR_DW1 0x100c
529 #define MAC_ADDR_DW1_BYTE4 FIELD32(0x000000ff)
530 #define MAC_ADDR_DW1_BYTE5 FIELD32(0x0000ff00)
531 #define MAC_ADDR_DW1_UNICAST_TO_ME_MASK FIELD32(0x00ff0000)
534 * MAC_BSSID_DW0: BSSID register 0
536 #define MAC_BSSID_DW0 0x1010
537 #define MAC_BSSID_DW0_BYTE0 FIELD32(0x000000ff)
538 #define MAC_BSSID_DW0_BYTE1 FIELD32(0x0000ff00)
539 #define MAC_BSSID_DW0_BYTE2 FIELD32(0x00ff0000)
540 #define MAC_BSSID_DW0_BYTE3 FIELD32(0xff000000)
543 * MAC_BSSID_DW1: BSSID register 1
545 * 0: 1-BSSID mode (BSS index = 0)
546 * 1: 2-BSSID mode (BSS index: Byte5, bit 0)
547 * 2: 4-BSSID mode (BSS index: byte5, bit 0 - 1)
548 * 3: 8-BSSID mode (BSS index: byte5, bit 0 - 2)
549 * This mask is used to mask off bits 0, 1 and 2 of byte 5 of the
550 * BSSID. This will make sure that those bits will be ignored
551 * when determining the MY_BSS of RX frames.
553 #define MAC_BSSID_DW1 0x1014
554 #define MAC_BSSID_DW1_BYTE4 FIELD32(0x000000ff)
555 #define MAC_BSSID_DW1_BYTE5 FIELD32(0x0000ff00)
556 #define MAC_BSSID_DW1_BSS_ID_MASK FIELD32(0x00030000)
557 #define MAC_BSSID_DW1_BSS_BCN_NUM FIELD32(0x001c0000)
560 * MAX_LEN_CFG: Maximum frame length register.
561 * MAX_MPDU: rt2860b max 16k bytes
562 * MAX_PSDU: Maximum PSDU length
563 * (power factor) 0:2^13, 1:2^14, 2:2^15, 3:2^16
565 #define MAX_LEN_CFG 0x1018
566 #define MAX_LEN_CFG_MAX_MPDU FIELD32(0x00000fff)
567 #define MAX_LEN_CFG_MAX_PSDU FIELD32(0x00003000)
568 #define MAX_LEN_CFG_MIN_PSDU FIELD32(0x0000c000)
569 #define MAX_LEN_CFG_MIN_MPDU FIELD32(0x000f0000)
572 * BBP_CSR_CFG: BBP serial control register
573 * VALUE: Register value to program into BBP
574 * REG_NUM: Selected BBP register
575 * READ_CONTROL: 0 write BBP, 1 read BBP
576 * BUSY: ASIC is busy executing BBP commands
577 * BBP_PAR_DUR: 0 4 MAC clocks, 1 8 MAC clocks
578 * BBP_RW_MODE: 0 serial, 1 paralell
580 #define BBP_CSR_CFG 0x101c
581 #define BBP_CSR_CFG_VALUE FIELD32(0x000000ff)
582 #define BBP_CSR_CFG_REGNUM FIELD32(0x0000ff00)
583 #define BBP_CSR_CFG_READ_CONTROL FIELD32(0x00010000)
584 #define BBP_CSR_CFG_BUSY FIELD32(0x00020000)
585 #define BBP_CSR_CFG_BBP_PAR_DUR FIELD32(0x00040000)
586 #define BBP_CSR_CFG_BBP_RW_MODE FIELD32(0x00080000)
589 * RF_CSR_CFG0: RF control register
590 * REGID_AND_VALUE: Register value to program into RF
591 * BITWIDTH: Selected RF register
592 * STANDBYMODE: 0 high when standby, 1 low when standby
593 * SEL: 0 RF_LE0 activate, 1 RF_LE1 activate
594 * BUSY: ASIC is busy executing RF commands
596 #define RF_CSR_CFG0 0x1020
597 #define RF_CSR_CFG0_REGID_AND_VALUE FIELD32(0x00ffffff)
598 #define RF_CSR_CFG0_BITWIDTH FIELD32(0x1f000000)
599 #define RF_CSR_CFG0_REG_VALUE_BW FIELD32(0x1fffffff)
600 #define RF_CSR_CFG0_STANDBYMODE FIELD32(0x20000000)
601 #define RF_CSR_CFG0_SEL FIELD32(0x40000000)
602 #define RF_CSR_CFG0_BUSY FIELD32(0x80000000)
605 * RF_CSR_CFG1: RF control register
606 * REGID_AND_VALUE: Register value to program into RF
607 * RFGAP: Gap between BB_CONTROL_RF and RF_LE
608 * 0: 3 system clock cycle (37.5usec)
609 * 1: 5 system clock cycle (62.5usec)
611 #define RF_CSR_CFG1 0x1024
612 #define RF_CSR_CFG1_REGID_AND_VALUE FIELD32(0x00ffffff)
613 #define RF_CSR_CFG1_RFGAP FIELD32(0x1f000000)
616 * RF_CSR_CFG2: RF control register
617 * VALUE: Register value to program into RF
619 #define RF_CSR_CFG2 0x1028
620 #define RF_CSR_CFG2_VALUE FIELD32(0x00ffffff)
623 * LED_CFG: LED control
626 * 1: blinking upon TX2
627 * 2: periodic slow blinking
633 #define LED_CFG 0x102c
634 #define LED_CFG_ON_PERIOD FIELD32(0x000000ff)
635 #define LED_CFG_OFF_PERIOD FIELD32(0x0000ff00)
636 #define LED_CFG_SLOW_BLINK_PERIOD FIELD32(0x003f0000)
637 #define LED_CFG_R_LED_MODE FIELD32(0x03000000)
638 #define LED_CFG_G_LED_MODE FIELD32(0x0c000000)
639 #define LED_CFG_Y_LED_MODE FIELD32(0x30000000)
640 #define LED_CFG_LED_POLAR FIELD32(0x40000000)
643 * AMPDU_BA_WINSIZE: Force BlockAck window size
644 * FORCE_WINSIZE_ENABLE:
645 * 0: Disable forcing of BlockAck window size
646 * 1: Enable forcing of BlockAck window size, overwrites values BlockAck
647 * window size values in the TXWI
648 * FORCE_WINSIZE: BlockAck window size
650 #define AMPDU_BA_WINSIZE 0x1040
651 #define AMPDU_BA_WINSIZE_FORCE_WINSIZE_ENABLE FIELD32(0x00000020)
652 #define AMPDU_BA_WINSIZE_FORCE_WINSIZE FIELD32(0x0000001f)
655 * XIFS_TIME_CFG: MAC timing
656 * CCKM_SIFS_TIME: unit 1us. Applied after CCK RX/TX
657 * OFDM_SIFS_TIME: unit 1us. Applied after OFDM RX/TX
658 * OFDM_XIFS_TIME: unit 1us. Applied after OFDM RX
659 * when MAC doesn't reference BBP signal BBRXEND
661 * BB_RXEND_ENABLE: reference RXEND signal to begin XIFS defer
664 #define XIFS_TIME_CFG 0x1100
665 #define XIFS_TIME_CFG_CCKM_SIFS_TIME FIELD32(0x000000ff)
666 #define XIFS_TIME_CFG_OFDM_SIFS_TIME FIELD32(0x0000ff00)
667 #define XIFS_TIME_CFG_OFDM_XIFS_TIME FIELD32(0x000f0000)
668 #define XIFS_TIME_CFG_EIFS FIELD32(0x1ff00000)
669 #define XIFS_TIME_CFG_BB_RXEND_ENABLE FIELD32(0x20000000)
674 #define BKOFF_SLOT_CFG 0x1104
675 #define BKOFF_SLOT_CFG_SLOT_TIME FIELD32(0x000000ff)
676 #define BKOFF_SLOT_CFG_CC_DELAY_TIME FIELD32(0x0000ff00)
681 #define NAV_TIME_CFG 0x1108
682 #define NAV_TIME_CFG_SIFS FIELD32(0x000000ff)
683 #define NAV_TIME_CFG_SLOT_TIME FIELD32(0x0000ff00)
684 #define NAV_TIME_CFG_EIFS FIELD32(0x01ff0000)
685 #define NAV_TIME_ZERO_SIFS FIELD32(0x02000000)
688 * CH_TIME_CFG: count as channel busy
690 #define CH_TIME_CFG 0x110c
693 * PBF_LIFE_TIMER: TX/RX MPDU timestamp timer (free run) Unit: 1us
695 #define PBF_LIFE_TIMER 0x1110
699 * BEACON_INTERVAL: in unit of 1/16 TU
700 * TSF_TICKING: Enable TSF auto counting
701 * TSF_SYNC: Enable TSF sync, 00: disable, 01: infra mode, 10: ad-hoc mode
702 * BEACON_GEN: Enable beacon generator
704 #define BCN_TIME_CFG 0x1114
705 #define BCN_TIME_CFG_BEACON_INTERVAL FIELD32(0x0000ffff)
706 #define BCN_TIME_CFG_TSF_TICKING FIELD32(0x00010000)
707 #define BCN_TIME_CFG_TSF_SYNC FIELD32(0x00060000)
708 #define BCN_TIME_CFG_TBTT_ENABLE FIELD32(0x00080000)
709 #define BCN_TIME_CFG_BEACON_GEN FIELD32(0x00100000)
710 #define BCN_TIME_CFG_TX_TIME_COMPENSATE FIELD32(0xf0000000)
714 * BCN_AIFSN: Beacon AIFSN after TBTT interrupt in slots
715 * BCN_CWMIN: Beacon CWMin after TBTT interrupt in slots
717 #define TBTT_SYNC_CFG 0x1118
718 #define TBTT_SYNC_CFG_TBTT_ADJUST FIELD32(0x000000ff)
719 #define TBTT_SYNC_CFG_BCN_EXP_WIN FIELD32(0x0000ff00)
720 #define TBTT_SYNC_CFG_BCN_AIFSN FIELD32(0x000f0000)
721 #define TBTT_SYNC_CFG_BCN_CWMIN FIELD32(0x00f00000)
724 * TSF_TIMER_DW0: Local lsb TSF timer, read-only
726 #define TSF_TIMER_DW0 0x111c
727 #define TSF_TIMER_DW0_LOW_WORD FIELD32(0xffffffff)
730 * TSF_TIMER_DW1: Local msb TSF timer, read-only
732 #define TSF_TIMER_DW1 0x1120
733 #define TSF_TIMER_DW1_HIGH_WORD FIELD32(0xffffffff)
736 * TBTT_TIMER: TImer remains till next TBTT, read-only
738 #define TBTT_TIMER 0x1124
741 * INT_TIMER_CFG: timer configuration
742 * PRE_TBTT_TIMER: leadtime to tbtt for pretbtt interrupt in units of 1/16 TU
743 * GP_TIMER: period of general purpose timer in units of 1/16 TU
745 #define INT_TIMER_CFG 0x1128
746 #define INT_TIMER_CFG_PRE_TBTT_TIMER FIELD32(0x0000ffff)
747 #define INT_TIMER_CFG_GP_TIMER FIELD32(0xffff0000)
750 * INT_TIMER_EN: GP-timer and pre-tbtt Int enable
752 #define INT_TIMER_EN 0x112c
753 #define INT_TIMER_EN_PRE_TBTT_TIMER FIELD32(0x00000001)
754 #define INT_TIMER_EN_GP_TIMER FIELD32(0x00000002)
757 * CH_IDLE_STA: channel idle time (in us)
759 #define CH_IDLE_STA 0x1130
762 * CH_BUSY_STA: channel busy time on primary channel (in us)
764 #define CH_BUSY_STA 0x1134
767 * CH_BUSY_STA_SEC: channel busy time on secondary channel in HT40 mode (in us)
769 #define CH_BUSY_STA_SEC 0x1138
773 * BBP_RF_BUSY: When set to 0, BBP and RF are stable.
774 * if 1 or higher one of the 2 registers is busy.
776 #define MAC_STATUS_CFG 0x1200
777 #define MAC_STATUS_CFG_BBP_RF_BUSY FIELD32(0x00000003)
782 #define PWR_PIN_CFG 0x1204
785 * AUTOWAKEUP_CFG: Manual power control / status register
786 * TBCN_BEFORE_WAKE: ForceWake has high privilege than PutToSleep when both set
787 * AUTOWAKE: 0:sleep, 1:awake
789 #define AUTOWAKEUP_CFG 0x1208
790 #define AUTOWAKEUP_CFG_AUTO_LEAD_TIME FIELD32(0x000000ff)
791 #define AUTOWAKEUP_CFG_TBCN_BEFORE_WAKE FIELD32(0x00007f00)
792 #define AUTOWAKEUP_CFG_AUTOWAKE FIELD32(0x00008000)
797 #define EDCA_AC0_CFG 0x1300
798 #define EDCA_AC0_CFG_TX_OP FIELD32(0x000000ff)
799 #define EDCA_AC0_CFG_AIFSN FIELD32(0x00000f00)
800 #define EDCA_AC0_CFG_CWMIN FIELD32(0x0000f000)
801 #define EDCA_AC0_CFG_CWMAX FIELD32(0x000f0000)
806 #define EDCA_AC1_CFG 0x1304
807 #define EDCA_AC1_CFG_TX_OP FIELD32(0x000000ff)
808 #define EDCA_AC1_CFG_AIFSN FIELD32(0x00000f00)
809 #define EDCA_AC1_CFG_CWMIN FIELD32(0x0000f000)
810 #define EDCA_AC1_CFG_CWMAX FIELD32(0x000f0000)
815 #define EDCA_AC2_CFG 0x1308
816 #define EDCA_AC2_CFG_TX_OP FIELD32(0x000000ff)
817 #define EDCA_AC2_CFG_AIFSN FIELD32(0x00000f00)
818 #define EDCA_AC2_CFG_CWMIN FIELD32(0x0000f000)
819 #define EDCA_AC2_CFG_CWMAX FIELD32(0x000f0000)
824 #define EDCA_AC3_CFG 0x130c
825 #define EDCA_AC3_CFG_TX_OP FIELD32(0x000000ff)
826 #define EDCA_AC3_CFG_AIFSN FIELD32(0x00000f00)
827 #define EDCA_AC3_CFG_CWMIN FIELD32(0x0000f000)
828 #define EDCA_AC3_CFG_CWMAX FIELD32(0x000f0000)
833 #define EDCA_TID_AC_MAP 0x1310
838 #define TX_PWR_CFG_RATE0 FIELD32(0x0000000f)
839 #define TX_PWR_CFG_RATE1 FIELD32(0x000000f0)
840 #define TX_PWR_CFG_RATE2 FIELD32(0x00000f00)
841 #define TX_PWR_CFG_RATE3 FIELD32(0x0000f000)
842 #define TX_PWR_CFG_RATE4 FIELD32(0x000f0000)
843 #define TX_PWR_CFG_RATE5 FIELD32(0x00f00000)
844 #define TX_PWR_CFG_RATE6 FIELD32(0x0f000000)
845 #define TX_PWR_CFG_RATE7 FIELD32(0xf0000000)
850 #define TX_PWR_CFG_0 0x1314
851 #define TX_PWR_CFG_0_1MBS FIELD32(0x0000000f)
852 #define TX_PWR_CFG_0_2MBS FIELD32(0x000000f0)
853 #define TX_PWR_CFG_0_55MBS FIELD32(0x00000f00)
854 #define TX_PWR_CFG_0_11MBS FIELD32(0x0000f000)
855 #define TX_PWR_CFG_0_6MBS FIELD32(0x000f0000)
856 #define TX_PWR_CFG_0_9MBS FIELD32(0x00f00000)
857 #define TX_PWR_CFG_0_12MBS FIELD32(0x0f000000)
858 #define TX_PWR_CFG_0_18MBS FIELD32(0xf0000000)
863 #define TX_PWR_CFG_1 0x1318
864 #define TX_PWR_CFG_1_24MBS FIELD32(0x0000000f)
865 #define TX_PWR_CFG_1_36MBS FIELD32(0x000000f0)
866 #define TX_PWR_CFG_1_48MBS FIELD32(0x00000f00)
867 #define TX_PWR_CFG_1_54MBS FIELD32(0x0000f000)
868 #define TX_PWR_CFG_1_MCS0 FIELD32(0x000f0000)
869 #define TX_PWR_CFG_1_MCS1 FIELD32(0x00f00000)
870 #define TX_PWR_CFG_1_MCS2 FIELD32(0x0f000000)
871 #define TX_PWR_CFG_1_MCS3 FIELD32(0xf0000000)
876 #define TX_PWR_CFG_2 0x131c
877 #define TX_PWR_CFG_2_MCS4 FIELD32(0x0000000f)
878 #define TX_PWR_CFG_2_MCS5 FIELD32(0x000000f0)
879 #define TX_PWR_CFG_2_MCS6 FIELD32(0x00000f00)
880 #define TX_PWR_CFG_2_MCS7 FIELD32(0x0000f000)
881 #define TX_PWR_CFG_2_MCS8 FIELD32(0x000f0000)
882 #define TX_PWR_CFG_2_MCS9 FIELD32(0x00f00000)
883 #define TX_PWR_CFG_2_MCS10 FIELD32(0x0f000000)
884 #define TX_PWR_CFG_2_MCS11 FIELD32(0xf0000000)
889 #define TX_PWR_CFG_3 0x1320
890 #define TX_PWR_CFG_3_MCS12 FIELD32(0x0000000f)
891 #define TX_PWR_CFG_3_MCS13 FIELD32(0x000000f0)
892 #define TX_PWR_CFG_3_MCS14 FIELD32(0x00000f00)
893 #define TX_PWR_CFG_3_MCS15 FIELD32(0x0000f000)
894 #define TX_PWR_CFG_3_UKNOWN1 FIELD32(0x000f0000)
895 #define TX_PWR_CFG_3_UKNOWN2 FIELD32(0x00f00000)
896 #define TX_PWR_CFG_3_UKNOWN3 FIELD32(0x0f000000)
897 #define TX_PWR_CFG_3_UKNOWN4 FIELD32(0xf0000000)
902 #define TX_PWR_CFG_4 0x1324
903 #define TX_PWR_CFG_4_UKNOWN5 FIELD32(0x0000000f)
904 #define TX_PWR_CFG_4_UKNOWN6 FIELD32(0x000000f0)
905 #define TX_PWR_CFG_4_UKNOWN7 FIELD32(0x00000f00)
906 #define TX_PWR_CFG_4_UKNOWN8 FIELD32(0x0000f000)
911 #define TX_PIN_CFG 0x1328
912 #define TX_PIN_CFG_PA_PE_A0_EN FIELD32(0x00000001)
913 #define TX_PIN_CFG_PA_PE_G0_EN FIELD32(0x00000002)
914 #define TX_PIN_CFG_PA_PE_A1_EN FIELD32(0x00000004)
915 #define TX_PIN_CFG_PA_PE_G1_EN FIELD32(0x00000008)
916 #define TX_PIN_CFG_PA_PE_A0_POL FIELD32(0x00000010)
917 #define TX_PIN_CFG_PA_PE_G0_POL FIELD32(0x00000020)
918 #define TX_PIN_CFG_PA_PE_A1_POL FIELD32(0x00000040)
919 #define TX_PIN_CFG_PA_PE_G1_POL FIELD32(0x00000080)
920 #define TX_PIN_CFG_LNA_PE_A0_EN FIELD32(0x00000100)
921 #define TX_PIN_CFG_LNA_PE_G0_EN FIELD32(0x00000200)
922 #define TX_PIN_CFG_LNA_PE_A1_EN FIELD32(0x00000400)
923 #define TX_PIN_CFG_LNA_PE_G1_EN FIELD32(0x00000800)
924 #define TX_PIN_CFG_LNA_PE_A0_POL FIELD32(0x00001000)
925 #define TX_PIN_CFG_LNA_PE_G0_POL FIELD32(0x00002000)
926 #define TX_PIN_CFG_LNA_PE_A1_POL FIELD32(0x00004000)
927 #define TX_PIN_CFG_LNA_PE_G1_POL FIELD32(0x00008000)
928 #define TX_PIN_CFG_RFTR_EN FIELD32(0x00010000)
929 #define TX_PIN_CFG_RFTR_POL FIELD32(0x00020000)
930 #define TX_PIN_CFG_TRSW_EN FIELD32(0x00040000)
931 #define TX_PIN_CFG_TRSW_POL FIELD32(0x00080000)
934 * TX_BAND_CFG: 0x1 use upper 20MHz, 0x0 use lower 20MHz
936 #define TX_BAND_CFG 0x132c
937 #define TX_BAND_CFG_HT40_MINUS FIELD32(0x00000001)
938 #define TX_BAND_CFG_A FIELD32(0x00000002)
939 #define TX_BAND_CFG_BG FIELD32(0x00000004)
944 #define TX_SW_CFG0 0x1330
949 #define TX_SW_CFG1 0x1334
954 #define TX_SW_CFG2 0x1338
959 #define TXOP_THRES_CFG 0x133c
964 #define TXOP_CTRL_CFG 0x1340
968 * RTS_THRES: unit:byte
969 * RTS_FBK_EN: enable rts rate fallback
971 #define TX_RTS_CFG 0x1344
972 #define TX_RTS_CFG_AUTO_RTS_RETRY_LIMIT FIELD32(0x000000ff)
973 #define TX_RTS_CFG_RTS_THRES FIELD32(0x00ffff00)
974 #define TX_RTS_CFG_RTS_FBK_EN FIELD32(0x01000000)
978 * MPDU_LIFETIME: expiration time = 2^(9+MPDU LIFE TIME) us
979 * RX_ACK_TIMEOUT: unit:slot. Used for TX procedure
980 * TX_OP_TIMEOUT: TXOP timeout value for TXOP truncation.
981 * it is recommended that:
982 * (SLOT_TIME) > (TX_OP_TIMEOUT) > (RX_ACK_TIMEOUT)
984 #define TX_TIMEOUT_CFG 0x1348
985 #define TX_TIMEOUT_CFG_MPDU_LIFETIME FIELD32(0x000000f0)
986 #define TX_TIMEOUT_CFG_RX_ACK_TIMEOUT FIELD32(0x0000ff00)
987 #define TX_TIMEOUT_CFG_TX_OP_TIMEOUT FIELD32(0x00ff0000)
991 * SHORT_RTY_LIMIT: short retry limit
992 * LONG_RTY_LIMIT: long retry limit
993 * LONG_RTY_THRE: Long retry threshoold
994 * NON_AGG_RTY_MODE: Non-Aggregate MPDU retry mode
995 * 0:expired by retry limit, 1: expired by mpdu life timer
996 * AGG_RTY_MODE: Aggregate MPDU retry mode
997 * 0:expired by retry limit, 1: expired by mpdu life timer
998 * TX_AUTO_FB_ENABLE: Tx retry PHY rate auto fallback enable
1000 #define TX_RTY_CFG 0x134c
1001 #define TX_RTY_CFG_SHORT_RTY_LIMIT FIELD32(0x000000ff)
1002 #define TX_RTY_CFG_LONG_RTY_LIMIT FIELD32(0x0000ff00)
1003 #define TX_RTY_CFG_LONG_RTY_THRE FIELD32(0x0fff0000)
1004 #define TX_RTY_CFG_NON_AGG_RTY_MODE FIELD32(0x10000000)
1005 #define TX_RTY_CFG_AGG_RTY_MODE FIELD32(0x20000000)
1006 #define TX_RTY_CFG_TX_AUTO_FB_ENABLE FIELD32(0x40000000)
1010 * REMOTE_MFB_LIFETIME: remote MFB life time. unit: 32us
1011 * MFB_ENABLE: TX apply remote MFB 1:enable
1012 * REMOTE_UMFS_ENABLE: remote unsolicit MFB enable
1013 * 0: not apply remote remote unsolicit (MFS=7)
1014 * TX_MRQ_EN: MCS request TX enable
1015 * TX_RDG_EN: RDG TX enable
1016 * TX_CF_ACK_EN: Piggyback CF-ACK enable
1017 * REMOTE_MFB: remote MCS feedback
1018 * REMOTE_MFS: remote MCS feedback sequence number
1020 #define TX_LINK_CFG 0x1350
1021 #define TX_LINK_CFG_REMOTE_MFB_LIFETIME FIELD32(0x000000ff)
1022 #define TX_LINK_CFG_MFB_ENABLE FIELD32(0x00000100)
1023 #define TX_LINK_CFG_REMOTE_UMFS_ENABLE FIELD32(0x00000200)
1024 #define TX_LINK_CFG_TX_MRQ_EN FIELD32(0x00000400)
1025 #define TX_LINK_CFG_TX_RDG_EN FIELD32(0x00000800)
1026 #define TX_LINK_CFG_TX_CF_ACK_EN FIELD32(0x00001000)
1027 #define TX_LINK_CFG_REMOTE_MFB FIELD32(0x00ff0000)
1028 #define TX_LINK_CFG_REMOTE_MFS FIELD32(0xff000000)
1033 #define HT_FBK_CFG0 0x1354
1034 #define HT_FBK_CFG0_HTMCS0FBK FIELD32(0x0000000f)
1035 #define HT_FBK_CFG0_HTMCS1FBK FIELD32(0x000000f0)
1036 #define HT_FBK_CFG0_HTMCS2FBK FIELD32(0x00000f00)
1037 #define HT_FBK_CFG0_HTMCS3FBK FIELD32(0x0000f000)
1038 #define HT_FBK_CFG0_HTMCS4FBK FIELD32(0x000f0000)
1039 #define HT_FBK_CFG0_HTMCS5FBK FIELD32(0x00f00000)
1040 #define HT_FBK_CFG0_HTMCS6FBK FIELD32(0x0f000000)
1041 #define HT_FBK_CFG0_HTMCS7FBK FIELD32(0xf0000000)
1046 #define HT_FBK_CFG1 0x1358
1047 #define HT_FBK_CFG1_HTMCS8FBK FIELD32(0x0000000f)
1048 #define HT_FBK_CFG1_HTMCS9FBK FIELD32(0x000000f0)
1049 #define HT_FBK_CFG1_HTMCS10FBK FIELD32(0x00000f00)
1050 #define HT_FBK_CFG1_HTMCS11FBK FIELD32(0x0000f000)
1051 #define HT_FBK_CFG1_HTMCS12FBK FIELD32(0x000f0000)
1052 #define HT_FBK_CFG1_HTMCS13FBK FIELD32(0x00f00000)
1053 #define HT_FBK_CFG1_HTMCS14FBK FIELD32(0x0f000000)
1054 #define HT_FBK_CFG1_HTMCS15FBK FIELD32(0xf0000000)
1059 #define LG_FBK_CFG0 0x135c
1060 #define LG_FBK_CFG0_OFDMMCS0FBK FIELD32(0x0000000f)
1061 #define LG_FBK_CFG0_OFDMMCS1FBK FIELD32(0x000000f0)
1062 #define LG_FBK_CFG0_OFDMMCS2FBK FIELD32(0x00000f00)
1063 #define LG_FBK_CFG0_OFDMMCS3FBK FIELD32(0x0000f000)
1064 #define LG_FBK_CFG0_OFDMMCS4FBK FIELD32(0x000f0000)
1065 #define LG_FBK_CFG0_OFDMMCS5FBK FIELD32(0x00f00000)
1066 #define LG_FBK_CFG0_OFDMMCS6FBK FIELD32(0x0f000000)
1067 #define LG_FBK_CFG0_OFDMMCS7FBK FIELD32(0xf0000000)
1072 #define LG_FBK_CFG1 0x1360
1073 #define LG_FBK_CFG0_CCKMCS0FBK FIELD32(0x0000000f)
1074 #define LG_FBK_CFG0_CCKMCS1FBK FIELD32(0x000000f0)
1075 #define LG_FBK_CFG0_CCKMCS2FBK FIELD32(0x00000f00)
1076 #define LG_FBK_CFG0_CCKMCS3FBK FIELD32(0x0000f000)
1079 * CCK_PROT_CFG: CCK Protection
1080 * PROTECT_RATE: Protection control frame rate for CCK TX(RTS/CTS/CFEnd)
1081 * PROTECT_CTRL: Protection control frame type for CCK TX
1082 * 0:none, 1:RTS/CTS, 2:CTS-to-self
1083 * PROTECT_NAV: TXOP protection type for CCK TX
1084 * 0:none, 1:ShortNAVprotect, 2:LongNAVProtect
1085 * TX_OP_ALLOW_CCK: CCK TXOP allowance, 0:disallow
1086 * TX_OP_ALLOW_OFDM: CCK TXOP allowance, 0:disallow
1087 * TX_OP_ALLOW_MM20: CCK TXOP allowance, 0:disallow
1088 * TX_OP_ALLOW_MM40: CCK TXOP allowance, 0:disallow
1089 * TX_OP_ALLOW_GF20: CCK TXOP allowance, 0:disallow
1090 * TX_OP_ALLOW_GF40: CCK TXOP allowance, 0:disallow
1091 * RTS_TH_EN: RTS threshold enable on CCK TX
1093 #define CCK_PROT_CFG 0x1364
1094 #define CCK_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1095 #define CCK_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1096 #define CCK_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
1097 #define CCK_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1098 #define CCK_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1099 #define CCK_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1100 #define CCK_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1101 #define CCK_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1102 #define CCK_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1103 #define CCK_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1106 * OFDM_PROT_CFG: OFDM Protection
1108 #define OFDM_PROT_CFG 0x1368
1109 #define OFDM_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1110 #define OFDM_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1111 #define OFDM_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
1112 #define OFDM_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1113 #define OFDM_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1114 #define OFDM_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1115 #define OFDM_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1116 #define OFDM_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1117 #define OFDM_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1118 #define OFDM_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1121 * MM20_PROT_CFG: MM20 Protection
1123 #define MM20_PROT_CFG 0x136c
1124 #define MM20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1125 #define MM20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1126 #define MM20_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
1127 #define MM20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1128 #define MM20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1129 #define MM20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1130 #define MM20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1131 #define MM20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1132 #define MM20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1133 #define MM20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1136 * MM40_PROT_CFG: MM40 Protection
1138 #define MM40_PROT_CFG 0x1370
1139 #define MM40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1140 #define MM40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1141 #define MM40_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
1142 #define MM40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1143 #define MM40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1144 #define MM40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1145 #define MM40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1146 #define MM40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1147 #define MM40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1148 #define MM40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1151 * GF20_PROT_CFG: GF20 Protection
1153 #define GF20_PROT_CFG 0x1374
1154 #define GF20_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1155 #define GF20_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1156 #define GF20_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
1157 #define GF20_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1158 #define GF20_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1159 #define GF20_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1160 #define GF20_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1161 #define GF20_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1162 #define GF20_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1163 #define GF20_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1166 * GF40_PROT_CFG: GF40 Protection
1168 #define GF40_PROT_CFG 0x1378
1169 #define GF40_PROT_CFG_PROTECT_RATE FIELD32(0x0000ffff)
1170 #define GF40_PROT_CFG_PROTECT_CTRL FIELD32(0x00030000)
1171 #define GF40_PROT_CFG_PROTECT_NAV FIELD32(0x000c0000)
1172 #define GF40_PROT_CFG_TX_OP_ALLOW_CCK FIELD32(0x00100000)
1173 #define GF40_PROT_CFG_TX_OP_ALLOW_OFDM FIELD32(0x00200000)
1174 #define GF40_PROT_CFG_TX_OP_ALLOW_MM20 FIELD32(0x00400000)
1175 #define GF40_PROT_CFG_TX_OP_ALLOW_MM40 FIELD32(0x00800000)
1176 #define GF40_PROT_CFG_TX_OP_ALLOW_GF20 FIELD32(0x01000000)
1177 #define GF40_PROT_CFG_TX_OP_ALLOW_GF40 FIELD32(0x02000000)
1178 #define GF40_PROT_CFG_RTS_TH_EN FIELD32(0x04000000)
1183 #define EXP_CTS_TIME 0x137c
1188 #define EXP_ACK_TIME 0x1380
1191 * RX_FILTER_CFG: RX configuration register.
1193 #define RX_FILTER_CFG 0x1400
1194 #define RX_FILTER_CFG_DROP_CRC_ERROR FIELD32(0x00000001)
1195 #define RX_FILTER_CFG_DROP_PHY_ERROR FIELD32(0x00000002)
1196 #define RX_FILTER_CFG_DROP_NOT_TO_ME FIELD32(0x00000004)
1197 #define RX_FILTER_CFG_DROP_NOT_MY_BSSD FIELD32(0x00000008)
1198 #define RX_FILTER_CFG_DROP_VER_ERROR FIELD32(0x00000010)
1199 #define RX_FILTER_CFG_DROP_MULTICAST FIELD32(0x00000020)
1200 #define RX_FILTER_CFG_DROP_BROADCAST FIELD32(0x00000040)
1201 #define RX_FILTER_CFG_DROP_DUPLICATE FIELD32(0x00000080)
1202 #define RX_FILTER_CFG_DROP_CF_END_ACK FIELD32(0x00000100)
1203 #define RX_FILTER_CFG_DROP_CF_END FIELD32(0x00000200)
1204 #define RX_FILTER_CFG_DROP_ACK FIELD32(0x00000400)
1205 #define RX_FILTER_CFG_DROP_CTS FIELD32(0x00000800)
1206 #define RX_FILTER_CFG_DROP_RTS FIELD32(0x00001000)
1207 #define RX_FILTER_CFG_DROP_PSPOLL FIELD32(0x00002000)
1208 #define RX_FILTER_CFG_DROP_BA FIELD32(0x00004000)
1209 #define RX_FILTER_CFG_DROP_BAR FIELD32(0x00008000)
1210 #define RX_FILTER_CFG_DROP_CNTL FIELD32(0x00010000)
1214 * AUTORESPONDER: 0: disable, 1: enable
1215 * BAC_ACK_POLICY: 0:long, 1:short preamble
1216 * CTS_40_MMODE: Response CTS 40MHz duplicate mode
1217 * CTS_40_MREF: Response CTS 40MHz duplicate mode
1218 * AR_PREAMBLE: Auto responder preamble 0:long, 1:short preamble
1219 * DUAL_CTS_EN: Power bit value in control frame
1220 * ACK_CTS_PSM_BIT:Power bit value in control frame
1222 #define AUTO_RSP_CFG 0x1404
1223 #define AUTO_RSP_CFG_AUTORESPONDER FIELD32(0x00000001)
1224 #define AUTO_RSP_CFG_BAC_ACK_POLICY FIELD32(0x00000002)
1225 #define AUTO_RSP_CFG_CTS_40_MMODE FIELD32(0x00000004)
1226 #define AUTO_RSP_CFG_CTS_40_MREF FIELD32(0x00000008)
1227 #define AUTO_RSP_CFG_AR_PREAMBLE FIELD32(0x00000010)
1228 #define AUTO_RSP_CFG_DUAL_CTS_EN FIELD32(0x00000040)
1229 #define AUTO_RSP_CFG_ACK_CTS_PSM_BIT FIELD32(0x00000080)
1232 * LEGACY_BASIC_RATE:
1234 #define LEGACY_BASIC_RATE 0x1408
1239 #define HT_BASIC_RATE 0x140c
1244 #define HT_CTRL_CFG 0x1410
1249 #define SIFS_COST_CFG 0x1414
1253 * Set NAV for all received frames
1255 #define RX_PARSER_CFG 0x1418
1260 #define TX_SEC_CNT0 0x1500
1265 #define RX_SEC_CNT0 0x1504
1270 #define CCMP_FC_MUTE 0x1508
1275 #define TXOP_HLDR_ADDR0 0x1600
1280 #define TXOP_HLDR_ADDR1 0x1604
1285 #define TXOP_HLDR_ET 0x1608
1288 * QOS_CFPOLL_RA_DW0:
1290 #define QOS_CFPOLL_RA_DW0 0x160c
1293 * QOS_CFPOLL_RA_DW1:
1295 #define QOS_CFPOLL_RA_DW1 0x1610
1300 #define QOS_CFPOLL_QC 0x1614
1303 * RX_STA_CNT0: RX PLCP error count & RX CRC error count
1305 #define RX_STA_CNT0 0x1700
1306 #define RX_STA_CNT0_CRC_ERR FIELD32(0x0000ffff)
1307 #define RX_STA_CNT0_PHY_ERR FIELD32(0xffff0000)
1310 * RX_STA_CNT1: RX False CCA count & RX LONG frame count
1312 #define RX_STA_CNT1 0x1704
1313 #define RX_STA_CNT1_FALSE_CCA FIELD32(0x0000ffff)
1314 #define RX_STA_CNT1_PLCP_ERR FIELD32(0xffff0000)
1319 #define RX_STA_CNT2 0x1708
1320 #define RX_STA_CNT2_RX_DUPLI_COUNT FIELD32(0x0000ffff)
1321 #define RX_STA_CNT2_RX_FIFO_OVERFLOW FIELD32(0xffff0000)
1324 * TX_STA_CNT0: TX Beacon count
1326 #define TX_STA_CNT0 0x170c
1327 #define TX_STA_CNT0_TX_FAIL_COUNT FIELD32(0x0000ffff)
1328 #define TX_STA_CNT0_TX_BEACON_COUNT FIELD32(0xffff0000)
1331 * TX_STA_CNT1: TX tx count
1333 #define TX_STA_CNT1 0x1710
1334 #define TX_STA_CNT1_TX_SUCCESS FIELD32(0x0000ffff)
1335 #define TX_STA_CNT1_TX_RETRANSMIT FIELD32(0xffff0000)
1338 * TX_STA_CNT2: TX tx count
1340 #define TX_STA_CNT2 0x1714
1341 #define TX_STA_CNT2_TX_ZERO_LEN_COUNT FIELD32(0x0000ffff)
1342 #define TX_STA_CNT2_TX_UNDER_FLOW_COUNT FIELD32(0xffff0000)
1345 * TX_STA_FIFO: TX Result for specific PID status fifo register.
1347 * This register is implemented as FIFO with 16 entries in the HW. Each
1348 * register read fetches the next tx result. If the FIFO is full because
1349 * it wasn't read fast enough after the according interrupt (TX_FIFO_STATUS)
1350 * triggered, the hw seems to simply drop further tx results.
1352 * VALID: 1: this tx result is valid
1353 * 0: no valid tx result -> driver should stop reading
1354 * PID_TYPE: The PID latched from the PID field in the TXWI, can be used
1355 * to match a frame with its tx result (even though the PID is
1356 * only 4 bits wide).
1357 * PID_QUEUE: Part of PID_TYPE, this is the queue index number (0-3)
1358 * PID_ENTRY: Part of PID_TYPE, this is the queue entry index number (1-3)
1359 * This identification number is calculated by ((idx % 3) + 1).
1360 * TX_SUCCESS: Indicates tx success (1) or failure (0)
1361 * TX_AGGRE: Indicates if the frame was part of an aggregate (1) or not (0)
1362 * TX_ACK_REQUIRED: Indicates if the frame needed to get ack'ed (1) or not (0)
1363 * WCID: The wireless client ID.
1364 * MCS: The tx rate used during the last transmission of this frame, be it
1365 * successful or not.
1366 * PHYMODE: The phymode used for the transmission.
1368 #define TX_STA_FIFO 0x1718
1369 #define TX_STA_FIFO_VALID FIELD32(0x00000001)
1370 #define TX_STA_FIFO_PID_TYPE FIELD32(0x0000001e)
1371 #define TX_STA_FIFO_PID_QUEUE FIELD32(0x00000006)
1372 #define TX_STA_FIFO_PID_ENTRY FIELD32(0x00000018)
1373 #define TX_STA_FIFO_TX_SUCCESS FIELD32(0x00000020)
1374 #define TX_STA_FIFO_TX_AGGRE FIELD32(0x00000040)
1375 #define TX_STA_FIFO_TX_ACK_REQUIRED FIELD32(0x00000080)
1376 #define TX_STA_FIFO_WCID FIELD32(0x0000ff00)
1377 #define TX_STA_FIFO_SUCCESS_RATE FIELD32(0xffff0000)
1378 #define TX_STA_FIFO_MCS FIELD32(0x007f0000)
1379 #define TX_STA_FIFO_PHYMODE FIELD32(0xc0000000)
1382 * TX_AGG_CNT: Debug counter
1384 #define TX_AGG_CNT 0x171c
1385 #define TX_AGG_CNT_NON_AGG_TX_COUNT FIELD32(0x0000ffff)
1386 #define TX_AGG_CNT_AGG_TX_COUNT FIELD32(0xffff0000)
1391 #define TX_AGG_CNT0 0x1720
1392 #define TX_AGG_CNT0_AGG_SIZE_1_COUNT FIELD32(0x0000ffff)
1393 #define TX_AGG_CNT0_AGG_SIZE_2_COUNT FIELD32(0xffff0000)
1398 #define TX_AGG_CNT1 0x1724
1399 #define TX_AGG_CNT1_AGG_SIZE_3_COUNT FIELD32(0x0000ffff)
1400 #define TX_AGG_CNT1_AGG_SIZE_4_COUNT FIELD32(0xffff0000)
1405 #define TX_AGG_CNT2 0x1728
1406 #define TX_AGG_CNT2_AGG_SIZE_5_COUNT FIELD32(0x0000ffff)
1407 #define TX_AGG_CNT2_AGG_SIZE_6_COUNT FIELD32(0xffff0000)
1412 #define TX_AGG_CNT3 0x172c
1413 #define TX_AGG_CNT3_AGG_SIZE_7_COUNT FIELD32(0x0000ffff)
1414 #define TX_AGG_CNT3_AGG_SIZE_8_COUNT FIELD32(0xffff0000)
1419 #define TX_AGG_CNT4 0x1730
1420 #define TX_AGG_CNT4_AGG_SIZE_9_COUNT FIELD32(0x0000ffff)
1421 #define TX_AGG_CNT4_AGG_SIZE_10_COUNT FIELD32(0xffff0000)
1426 #define TX_AGG_CNT5 0x1734
1427 #define TX_AGG_CNT5_AGG_SIZE_11_COUNT FIELD32(0x0000ffff)
1428 #define TX_AGG_CNT5_AGG_SIZE_12_COUNT FIELD32(0xffff0000)
1433 #define TX_AGG_CNT6 0x1738
1434 #define TX_AGG_CNT6_AGG_SIZE_13_COUNT FIELD32(0x0000ffff)
1435 #define TX_AGG_CNT6_AGG_SIZE_14_COUNT FIELD32(0xffff0000)
1440 #define TX_AGG_CNT7 0x173c
1441 #define TX_AGG_CNT7_AGG_SIZE_15_COUNT FIELD32(0x0000ffff)
1442 #define TX_AGG_CNT7_AGG_SIZE_16_COUNT FIELD32(0xffff0000)
1446 * TX_ZERO_DEL: TX zero length delimiter count
1447 * RX_ZERO_DEL: RX zero length delimiter count
1449 #define MPDU_DENSITY_CNT 0x1740
1450 #define MPDU_DENSITY_CNT_TX_ZERO_DEL FIELD32(0x0000ffff)
1451 #define MPDU_DENSITY_CNT_RX_ZERO_DEL FIELD32(0xffff0000)
1454 * Security key table memory.
1456 * The pairwise key table shares some memory with the beacon frame
1457 * buffers 6 and 7. That basically means that when beacon 6 & 7
1458 * are used we should only use the reduced pairwise key table which
1459 * has a maximum of 222 entries.
1461 * ---------------------------------------------
1462 * |0x4000 | Pairwise Key | Reduced Pairwise |
1463 * | | Table | Key Table |
1464 * | | Size: 256 * 32 | Size: 222 * 32 |
1465 * |0x5BC0 | |-------------------
1467 * |0x5DC0 | |-------------------
1469 * |0x5FC0 | |-------------------
1471 * --------------------------
1473 * MAC_WCID_BASE: 8-bytes (use only 6 bytes) * 256 entry
1474 * PAIRWISE_KEY_TABLE_BASE: 32-byte * 256 entry
1475 * MAC_IVEIV_TABLE_BASE: 8-byte * 256-entry
1476 * MAC_WCID_ATTRIBUTE_BASE: 4-byte * 256-entry
1477 * SHARED_KEY_TABLE_BASE: 32-byte * 16-entry
1478 * SHARED_KEY_MODE_BASE: 4-byte * 16-entry
1480 #define MAC_WCID_BASE 0x1800
1481 #define PAIRWISE_KEY_TABLE_BASE 0x4000
1482 #define MAC_IVEIV_TABLE_BASE 0x6000
1483 #define MAC_WCID_ATTRIBUTE_BASE 0x6800
1484 #define SHARED_KEY_TABLE_BASE 0x6c00
1485 #define SHARED_KEY_MODE_BASE 0x7000
1487 #define MAC_WCID_ENTRY(__idx) \
1488 ( MAC_WCID_BASE + ((__idx) * sizeof(struct mac_wcid_entry)) )
1489 #define PAIRWISE_KEY_ENTRY(__idx) \
1490 ( PAIRWISE_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)) )
1491 #define MAC_IVEIV_ENTRY(__idx) \
1492 ( MAC_IVEIV_TABLE_BASE + ((__idx) * sizeof(struct mac_iveiv_entry)) )
1493 #define MAC_WCID_ATTR_ENTRY(__idx) \
1494 ( MAC_WCID_ATTRIBUTE_BASE + ((__idx) * sizeof(u32)) )
1495 #define SHARED_KEY_ENTRY(__idx) \
1496 ( SHARED_KEY_TABLE_BASE + ((__idx) * sizeof(struct hw_key_entry)) )
1497 #define SHARED_KEY_MODE_ENTRY(__idx) \
1498 ( SHARED_KEY_MODE_BASE + ((__idx) * sizeof(u32)) )
1500 struct mac_wcid_entry {
1505 struct hw_key_entry {
1511 struct mac_iveiv_entry {
1516 * MAC_WCID_ATTRIBUTE:
1518 #define MAC_WCID_ATTRIBUTE_KEYTAB FIELD32(0x00000001)
1519 #define MAC_WCID_ATTRIBUTE_CIPHER FIELD32(0x0000000e)
1520 #define MAC_WCID_ATTRIBUTE_BSS_IDX FIELD32(0x00000070)
1521 #define MAC_WCID_ATTRIBUTE_RX_WIUDF FIELD32(0x00000380)
1522 #define MAC_WCID_ATTRIBUTE_CIPHER_EXT FIELD32(0x00000400)
1523 #define MAC_WCID_ATTRIBUTE_BSS_IDX_EXT FIELD32(0x00000800)
1524 #define MAC_WCID_ATTRIBUTE_WAPI_MCBC FIELD32(0x00008000)
1525 #define MAC_WCID_ATTRIBUTE_WAPI_KEY_IDX FIELD32(0xff000000)
1530 #define SHARED_KEY_MODE_BSS0_KEY0 FIELD32(0x00000007)
1531 #define SHARED_KEY_MODE_BSS0_KEY1 FIELD32(0x00000070)
1532 #define SHARED_KEY_MODE_BSS0_KEY2 FIELD32(0x00000700)
1533 #define SHARED_KEY_MODE_BSS0_KEY3 FIELD32(0x00007000)
1534 #define SHARED_KEY_MODE_BSS1_KEY0 FIELD32(0x00070000)
1535 #define SHARED_KEY_MODE_BSS1_KEY1 FIELD32(0x00700000)
1536 #define SHARED_KEY_MODE_BSS1_KEY2 FIELD32(0x07000000)
1537 #define SHARED_KEY_MODE_BSS1_KEY3 FIELD32(0x70000000)
1540 * HOST-MCU communication
1544 * H2M_MAILBOX_CSR: Host-to-MCU Mailbox.
1546 #define H2M_MAILBOX_CSR 0x7010
1547 #define H2M_MAILBOX_CSR_ARG0 FIELD32(0x000000ff)
1548 #define H2M_MAILBOX_CSR_ARG1 FIELD32(0x0000ff00)
1549 #define H2M_MAILBOX_CSR_CMD_TOKEN FIELD32(0x00ff0000)
1550 #define H2M_MAILBOX_CSR_OWNER FIELD32(0xff000000)
1555 #define H2M_MAILBOX_CID 0x7014
1556 #define H2M_MAILBOX_CID_CMD0 FIELD32(0x000000ff)
1557 #define H2M_MAILBOX_CID_CMD1 FIELD32(0x0000ff00)
1558 #define H2M_MAILBOX_CID_CMD2 FIELD32(0x00ff0000)
1559 #define H2M_MAILBOX_CID_CMD3 FIELD32(0xff000000)
1562 * H2M_MAILBOX_STATUS:
1564 #define H2M_MAILBOX_STATUS 0x701c
1569 #define H2M_INT_SRC 0x7024
1574 #define H2M_BBP_AGENT 0x7028
1577 * MCU_LEDCS: LED control for MCU Mailbox.
1579 #define MCU_LEDCS_LED_MODE FIELD8(0x1f)
1580 #define MCU_LEDCS_POLARITY FIELD8(0x01)
1584 * Carrier-sense CTS frame base address.
1585 * It's where mac stores carrier-sense frame for carrier-sense function.
1587 #define HW_CS_CTS_BASE 0x7700
1591 * DFS CTS frame base address. It's where mac stores CTS frame for DFS.
1593 #define HW_DFS_CTS_BASE 0x7780
1596 * TXRX control registers - base address 0x3000
1601 * rt2860b UNKNOWN reg use R/O Reg Addr 0x77d0 first..
1603 #define TXRX_CSR1 0x77d0
1606 * HW_DEBUG_SETTING_BASE:
1607 * since NULL frame won't be that long (256 byte)
1608 * We steal 16 tail bytes to save debugging settings
1610 #define HW_DEBUG_SETTING_BASE 0x77f0
1611 #define HW_DEBUG_SETTING_BASE2 0x7770
1615 * In order to support maximum 8 MBSS and its maximum length
1616 * is 512 bytes for each beacon
1617 * Three section discontinue memory segments will be used.
1618 * 1. The original region for BCN 0~3
1619 * 2. Extract memory from FCE table for BCN 4~5
1620 * 3. Extract memory from Pair-wise key table for BCN 6~7
1621 * It occupied those memory of wcid 238~253 for BCN 6
1622 * and wcid 222~237 for BCN 7 (see Security key table memory
1625 * IMPORTANT NOTE: Not sure why legacy driver does this,
1626 * but HW_BEACON_BASE7 is 0x0200 bytes below HW_BEACON_BASE6.
1628 #define HW_BEACON_BASE0 0x7800
1629 #define HW_BEACON_BASE1 0x7a00
1630 #define HW_BEACON_BASE2 0x7c00
1631 #define HW_BEACON_BASE3 0x7e00
1632 #define HW_BEACON_BASE4 0x7200
1633 #define HW_BEACON_BASE5 0x7400
1634 #define HW_BEACON_BASE6 0x5dc0
1635 #define HW_BEACON_BASE7 0x5bc0
1637 #define HW_BEACON_OFFSET(__index) \
1638 ( ((__index) < 4) ? ( HW_BEACON_BASE0 + (__index * 0x0200) ) : \
1639 (((__index) < 6) ? ( HW_BEACON_BASE4 + ((__index - 4) * 0x0200) ) : \
1640 (HW_BEACON_BASE6 - ((__index - 6) * 0x0200))) )
1644 * The wordsize of the BBP is 8 bits.
1648 * BBP 1: TX Antenna & Power
1649 * POWER: 0 - normal, 1 - drop tx power by 6dBm, 2 - drop tx power by 12dBm,
1650 * 3 - increase tx power by 6dBm
1652 #define BBP1_TX_POWER FIELD8(0x07)
1653 #define BBP1_TX_ANTENNA FIELD8(0x18)
1658 #define BBP3_RX_ANTENNA FIELD8(0x18)
1659 #define BBP3_HT40_MINUS FIELD8(0x20)
1664 #define BBP4_TX_BF FIELD8(0x01)
1665 #define BBP4_BANDWIDTH FIELD8(0x18)
1670 #define BBP138_RX_ADC1 FIELD8(0x02)
1671 #define BBP138_RX_ADC2 FIELD8(0x04)
1672 #define BBP138_TX_DAC1 FIELD8(0x20)
1673 #define BBP138_TX_DAC2 FIELD8(0x40)
1677 * The wordsize of the RFCSR is 8 bits.
1683 #define RFCSR1_RF_BLOCK_EN FIELD8(0x01)
1684 #define RFCSR1_RX0_PD FIELD8(0x04)
1685 #define RFCSR1_TX0_PD FIELD8(0x08)
1686 #define RFCSR1_RX1_PD FIELD8(0x10)
1687 #define RFCSR1_TX1_PD FIELD8(0x20)
1692 #define RFCSR6_R1 FIELD8(0x03)
1693 #define RFCSR6_R2 FIELD8(0x40)
1698 #define RFCSR7_RF_TUNING FIELD8(0x01)
1703 #define RFCSR12_TX_POWER FIELD8(0x1f)
1708 #define RFCSR13_TX_POWER FIELD8(0x1f)
1713 #define RFCSR15_TX_LO2_EN FIELD8(0x08)
1718 #define RFCSR17_TXMIXER_GAIN FIELD8(0x07)
1719 #define RFCSR17_TX_LO1_EN FIELD8(0x08)
1720 #define RFCSR17_R FIELD8(0x20)
1725 #define RFCSR20_RX_LO1_EN FIELD8(0x08)
1730 #define RFCSR21_RX_LO2_EN FIELD8(0x08)
1735 #define RFCSR22_BASEBAND_LOOPBACK FIELD8(0x01)
1740 #define RFCSR23_FREQ_OFFSET FIELD8(0x7f)
1745 #define RFCSR27_R1 FIELD8(0x03)
1746 #define RFCSR27_R2 FIELD8(0x04)
1747 #define RFCSR27_R3 FIELD8(0x30)
1748 #define RFCSR27_R4 FIELD8(0x40)
1753 #define RFCSR30_RF_CALIBRATION FIELD8(0x80)
1762 #define RF2_ANTENNA_RX2 FIELD32(0x00000040)
1763 #define RF2_ANTENNA_TX1 FIELD32(0x00004000)
1764 #define RF2_ANTENNA_RX1 FIELD32(0x00020000)
1769 #define RF3_TXPOWER_G FIELD32(0x00003e00)
1770 #define RF3_TXPOWER_A_7DBM_BOOST FIELD32(0x00000200)
1771 #define RF3_TXPOWER_A FIELD32(0x00003c00)
1776 #define RF4_TXPOWER_G FIELD32(0x000007c0)
1777 #define RF4_TXPOWER_A_7DBM_BOOST FIELD32(0x00000040)
1778 #define RF4_TXPOWER_A FIELD32(0x00000780)
1779 #define RF4_FREQ_OFFSET FIELD32(0x001f8000)
1780 #define RF4_HT40 FIELD32(0x00200000)
1784 * The wordsize of the EEPROM is 16 bits.
1790 #define EEPROM_VERSION 0x0001
1791 #define EEPROM_VERSION_FAE FIELD16(0x00ff)
1792 #define EEPROM_VERSION_VERSION FIELD16(0xff00)
1797 #define EEPROM_MAC_ADDR_0 0x0002
1798 #define EEPROM_MAC_ADDR_BYTE0 FIELD16(0x00ff)
1799 #define EEPROM_MAC_ADDR_BYTE1 FIELD16(0xff00)
1800 #define EEPROM_MAC_ADDR_1 0x0003
1801 #define EEPROM_MAC_ADDR_BYTE2 FIELD16(0x00ff)
1802 #define EEPROM_MAC_ADDR_BYTE3 FIELD16(0xff00)
1803 #define EEPROM_MAC_ADDR_2 0x0004
1804 #define EEPROM_MAC_ADDR_BYTE4 FIELD16(0x00ff)
1805 #define EEPROM_MAC_ADDR_BYTE5 FIELD16(0xff00)
1808 * EEPROM ANTENNA config
1809 * RXPATH: 1: 1R, 2: 2R, 3: 3R
1810 * TXPATH: 1: 1T, 2: 2T
1812 #define EEPROM_ANTENNA 0x001a
1813 #define EEPROM_ANTENNA_RXPATH FIELD16(0x000f)
1814 #define EEPROM_ANTENNA_TXPATH FIELD16(0x00f0)
1815 #define EEPROM_ANTENNA_RF_TYPE FIELD16(0x0f00)
1819 * CARDBUS_ACCEL: 0 - enable, 1 - disable
1821 #define EEPROM_NIC 0x001b
1822 #define EEPROM_NIC_HW_RADIO FIELD16(0x0001)
1823 #define EEPROM_NIC_DYNAMIC_TX_AGC FIELD16(0x0002)
1824 #define EEPROM_NIC_EXTERNAL_LNA_BG FIELD16(0x0004)
1825 #define EEPROM_NIC_EXTERNAL_LNA_A FIELD16(0x0008)
1826 #define EEPROM_NIC_CARDBUS_ACCEL FIELD16(0x0010)
1827 #define EEPROM_NIC_BW40M_SB_BG FIELD16(0x0020)
1828 #define EEPROM_NIC_BW40M_SB_A FIELD16(0x0040)
1829 #define EEPROM_NIC_WPS_PBC FIELD16(0x0080)
1830 #define EEPROM_NIC_BW40M_BG FIELD16(0x0100)
1831 #define EEPROM_NIC_BW40M_A FIELD16(0x0200)
1832 #define EEPROM_NIC_ANT_DIVERSITY FIELD16(0x0800)
1833 #define EEPROM_NIC_DAC_TEST FIELD16(0x8000)
1838 #define EEPROM_FREQ 0x001d
1839 #define EEPROM_FREQ_OFFSET FIELD16(0x00ff)
1840 #define EEPROM_FREQ_LED_MODE FIELD16(0x7f00)
1841 #define EEPROM_FREQ_LED_POLARITY FIELD16(0x1000)
1845 * POLARITY_RDY_G: Polarity RDY_G setting.
1846 * POLARITY_RDY_A: Polarity RDY_A setting.
1847 * POLARITY_ACT: Polarity ACT setting.
1848 * POLARITY_GPIO_0: Polarity GPIO0 setting.
1849 * POLARITY_GPIO_1: Polarity GPIO1 setting.
1850 * POLARITY_GPIO_2: Polarity GPIO2 setting.
1851 * POLARITY_GPIO_3: Polarity GPIO3 setting.
1852 * POLARITY_GPIO_4: Polarity GPIO4 setting.
1853 * LED_MODE: Led mode.
1855 #define EEPROM_LED1 0x001e
1856 #define EEPROM_LED2 0x001f
1857 #define EEPROM_LED3 0x0020
1858 #define EEPROM_LED_POLARITY_RDY_BG FIELD16(0x0001)
1859 #define EEPROM_LED_POLARITY_RDY_A FIELD16(0x0002)
1860 #define EEPROM_LED_POLARITY_ACT FIELD16(0x0004)
1861 #define EEPROM_LED_POLARITY_GPIO_0 FIELD16(0x0008)
1862 #define EEPROM_LED_POLARITY_GPIO_1 FIELD16(0x0010)
1863 #define EEPROM_LED_POLARITY_GPIO_2 FIELD16(0x0020)
1864 #define EEPROM_LED_POLARITY_GPIO_3 FIELD16(0x0040)
1865 #define EEPROM_LED_POLARITY_GPIO_4 FIELD16(0x0080)
1866 #define EEPROM_LED_LED_MODE FIELD16(0x1f00)
1871 #define EEPROM_LNA 0x0022
1872 #define EEPROM_LNA_BG FIELD16(0x00ff)
1873 #define EEPROM_LNA_A0 FIELD16(0xff00)
1876 * EEPROM RSSI BG offset
1878 #define EEPROM_RSSI_BG 0x0023
1879 #define EEPROM_RSSI_BG_OFFSET0 FIELD16(0x00ff)
1880 #define EEPROM_RSSI_BG_OFFSET1 FIELD16(0xff00)
1883 * EEPROM RSSI BG2 offset
1885 #define EEPROM_RSSI_BG2 0x0024
1886 #define EEPROM_RSSI_BG2_OFFSET2 FIELD16(0x00ff)
1887 #define EEPROM_RSSI_BG2_LNA_A1 FIELD16(0xff00)
1890 * EEPROM TXMIXER GAIN BG offset (note overlaps with EEPROM RSSI BG2).
1892 #define EEPROM_TXMIXER_GAIN_BG 0x0024
1893 #define EEPROM_TXMIXER_GAIN_BG_VAL FIELD16(0x0007)
1896 * EEPROM RSSI A offset
1898 #define EEPROM_RSSI_A 0x0025
1899 #define EEPROM_RSSI_A_OFFSET0 FIELD16(0x00ff)
1900 #define EEPROM_RSSI_A_OFFSET1 FIELD16(0xff00)
1903 * EEPROM RSSI A2 offset
1905 #define EEPROM_RSSI_A2 0x0026
1906 #define EEPROM_RSSI_A2_OFFSET2 FIELD16(0x00ff)
1907 #define EEPROM_RSSI_A2_LNA_A2 FIELD16(0xff00)
1910 * EEPROM Maximum TX power values
1912 #define EEPROM_MAX_TX_POWER 0x0027
1913 #define EEPROM_MAX_TX_POWER_24GHZ FIELD16(0x00ff)
1914 #define EEPROM_MAX_TX_POWER_5GHZ FIELD16(0xff00)
1917 * EEPROM TXpower delta: 20MHZ AND 40 MHZ use different power.
1918 * This is delta in 40MHZ.
1919 * VALUE: Tx Power dalta value (MAX=4)
1920 * TYPE: 1: Plus the delta value, 0: minus the delta value
1923 #define EEPROM_TXPOWER_DELTA 0x0028
1924 #define EEPROM_TXPOWER_DELTA_VALUE FIELD16(0x003f)
1925 #define EEPROM_TXPOWER_DELTA_TYPE FIELD16(0x0040)
1926 #define EEPROM_TXPOWER_DELTA_TXPOWER FIELD16(0x0080)
1929 * EEPROM TXPOWER 802.11BG
1931 #define EEPROM_TXPOWER_BG1 0x0029
1932 #define EEPROM_TXPOWER_BG2 0x0030
1933 #define EEPROM_TXPOWER_BG_SIZE 7
1934 #define EEPROM_TXPOWER_BG_1 FIELD16(0x00ff)
1935 #define EEPROM_TXPOWER_BG_2 FIELD16(0xff00)
1938 * EEPROM TXPOWER 802.11A
1940 #define EEPROM_TXPOWER_A1 0x003c
1941 #define EEPROM_TXPOWER_A2 0x0053
1942 #define EEPROM_TXPOWER_A_SIZE 6
1943 #define EEPROM_TXPOWER_A_1 FIELD16(0x00ff)
1944 #define EEPROM_TXPOWER_A_2 FIELD16(0xff00)
1947 * EEPROM TXPOWER by rate: tx power per tx rate for HT20 mode
1949 #define EEPROM_TXPOWER_BYRATE 0x006f
1950 #define EEPROM_TXPOWER_BYRATE_SIZE 9
1952 #define EEPROM_TXPOWER_BYRATE_RATE0 FIELD16(0x000f)
1953 #define EEPROM_TXPOWER_BYRATE_RATE1 FIELD16(0x00f0)
1954 #define EEPROM_TXPOWER_BYRATE_RATE2 FIELD16(0x0f00)
1955 #define EEPROM_TXPOWER_BYRATE_RATE3 FIELD16(0xf000)
1960 #define EEPROM_BBP_START 0x0078
1961 #define EEPROM_BBP_SIZE 16
1962 #define EEPROM_BBP_VALUE FIELD16(0x00ff)
1963 #define EEPROM_BBP_REG_ID FIELD16(0xff00)
1966 * MCU mailbox commands.
1968 #define MCU_SLEEP 0x30
1969 #define MCU_WAKEUP 0x31
1970 #define MCU_RADIO_OFF 0x35
1971 #define MCU_CURRENT 0x36
1972 #define MCU_LED 0x50
1973 #define MCU_LED_STRENGTH 0x51
1974 #define MCU_LED_1 0x52
1975 #define MCU_LED_2 0x53
1976 #define MCU_LED_3 0x54
1977 #define MCU_RADAR 0x60
1978 #define MCU_BOOT_SIGNAL 0x72
1979 #define MCU_BBP_SIGNAL 0x80
1980 #define MCU_POWER_SAVE 0x83
1983 * MCU mailbox tokens
1985 #define TOKEN_WAKUP 3
1988 * DMA descriptor defines.
1990 #define TXWI_DESC_SIZE ( 4 * sizeof(__le32) )
1991 #define RXWI_DESC_SIZE ( 4 * sizeof(__le32) )
1999 * FRAG: 1 To inform TKIP engine this is a fragment.
2000 * MIMO_PS: The remote peer is in dynamic MIMO-PS mode
2001 * TX_OP: 0:HT TXOP rule , 1:PIFS TX ,2:Backoff, 3:sifs
2002 * BW: Channel bandwidth 0:20MHz, 1:40 MHz (for legacy rates this will
2003 * duplicate the frame to both channels).
2004 * STBC: 1: STBC support MCS =0-7, 2,3 : RESERVED
2005 * AMPDU: 1: this frame is eligible for AMPDU aggregation, the hw will
2006 * aggregate consecutive frames with the same RA and QoS TID. If
2007 * a frame A with the same RA and QoS TID but AMPDU=0 is queued
2008 * directly after a frame B with AMPDU=1, frame A might still
2009 * get aggregated into the AMPDU started by frame B. So, setting
2010 * AMPDU to 0 does _not_ necessarily mean the frame is sent as
2011 * MPDU, it can still end up in an AMPDU if the previous frame
2012 * was tagged as AMPDU.
2014 #define TXWI_W0_FRAG FIELD32(0x00000001)
2015 #define TXWI_W0_MIMO_PS FIELD32(0x00000002)
2016 #define TXWI_W0_CF_ACK FIELD32(0x00000004)
2017 #define TXWI_W0_TS FIELD32(0x00000008)
2018 #define TXWI_W0_AMPDU FIELD32(0x00000010)
2019 #define TXWI_W0_MPDU_DENSITY FIELD32(0x000000e0)
2020 #define TXWI_W0_TX_OP FIELD32(0x00000300)
2021 #define TXWI_W0_MCS FIELD32(0x007f0000)
2022 #define TXWI_W0_BW FIELD32(0x00800000)
2023 #define TXWI_W0_SHORT_GI FIELD32(0x01000000)
2024 #define TXWI_W0_STBC FIELD32(0x06000000)
2025 #define TXWI_W0_IFS FIELD32(0x08000000)
2026 #define TXWI_W0_PHYMODE FIELD32(0xc0000000)
2030 * ACK: 0: No Ack needed, 1: Ack needed
2031 * NSEQ: 0: Don't assign hw sequence number, 1: Assign hw sequence number
2032 * BW_WIN_SIZE: BA windows size of the recipient
2033 * WIRELESS_CLI_ID: Client ID for WCID table access
2034 * MPDU_TOTAL_BYTE_COUNT: Length of 802.11 frame
2035 * PACKETID: Will be latched into the TX_STA_FIFO register once the according
2036 * frame was processed. If multiple frames are aggregated together
2037 * (AMPDU==1) the reported tx status will always contain the packet
2038 * id of the first frame. 0: Don't report tx status for this frame.
2039 * PACKETID_QUEUE: Part of PACKETID, This is the queue index (0-3)
2040 * PACKETID_ENTRY: Part of PACKETID, THis is the queue entry index (1-3)
2041 * This identification number is calculated by ((idx % 3) + 1).
2042 * The (+1) is required to prevent PACKETID to become 0.
2044 #define TXWI_W1_ACK FIELD32(0x00000001)
2045 #define TXWI_W1_NSEQ FIELD32(0x00000002)
2046 #define TXWI_W1_BW_WIN_SIZE FIELD32(0x000000fc)
2047 #define TXWI_W1_WIRELESS_CLI_ID FIELD32(0x0000ff00)
2048 #define TXWI_W1_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
2049 #define TXWI_W1_PACKETID FIELD32(0xf0000000)
2050 #define TXWI_W1_PACKETID_QUEUE FIELD32(0x30000000)
2051 #define TXWI_W1_PACKETID_ENTRY FIELD32(0xc0000000)
2056 #define TXWI_W2_IV FIELD32(0xffffffff)
2061 #define TXWI_W3_EIV FIELD32(0xffffffff)
2070 #define RXWI_W0_WIRELESS_CLI_ID FIELD32(0x000000ff)
2071 #define RXWI_W0_KEY_INDEX FIELD32(0x00000300)
2072 #define RXWI_W0_BSSID FIELD32(0x00001c00)
2073 #define RXWI_W0_UDF FIELD32(0x0000e000)
2074 #define RXWI_W0_MPDU_TOTAL_BYTE_COUNT FIELD32(0x0fff0000)
2075 #define RXWI_W0_TID FIELD32(0xf0000000)
2080 #define RXWI_W1_FRAG FIELD32(0x0000000f)
2081 #define RXWI_W1_SEQUENCE FIELD32(0x0000fff0)
2082 #define RXWI_W1_MCS FIELD32(0x007f0000)
2083 #define RXWI_W1_BW FIELD32(0x00800000)
2084 #define RXWI_W1_SHORT_GI FIELD32(0x01000000)
2085 #define RXWI_W1_STBC FIELD32(0x06000000)
2086 #define RXWI_W1_PHYMODE FIELD32(0xc0000000)
2091 #define RXWI_W2_RSSI0 FIELD32(0x000000ff)
2092 #define RXWI_W2_RSSI1 FIELD32(0x0000ff00)
2093 #define RXWI_W2_RSSI2 FIELD32(0x00ff0000)
2098 #define RXWI_W3_SNR0 FIELD32(0x000000ff)
2099 #define RXWI_W3_SNR1 FIELD32(0x0000ff00)
2102 * Macros for converting txpower from EEPROM to mac80211 value
2103 * and from mac80211 value to register value.
2105 #define MIN_G_TXPOWER 0
2106 #define MIN_A_TXPOWER -7
2107 #define MAX_G_TXPOWER 31
2108 #define MAX_A_TXPOWER 15
2109 #define DEFAULT_TXPOWER 5
2111 #define TXPOWER_G_FROM_DEV(__txpower) \
2112 ((__txpower) > MAX_G_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
2114 #define TXPOWER_G_TO_DEV(__txpower) \
2115 clamp_t(char, __txpower, MIN_G_TXPOWER, MAX_G_TXPOWER)
2117 #define TXPOWER_A_FROM_DEV(__txpower) \
2118 ((__txpower) > MAX_A_TXPOWER) ? DEFAULT_TXPOWER : (__txpower)
2120 #define TXPOWER_A_TO_DEV(__txpower) \
2121 clamp_t(char, __txpower, MIN_A_TXPOWER, MAX_A_TXPOWER)
2123 #endif /* RT2800_H */