1 /******************************************************************************
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
18 *******************************************************************************/
19 #ifndef __RTL8188F_SPEC_H__
20 #define __RTL8188F_SPEC_H__
25 #define HAL_NAV_UPPER_UNIT_8188F 128 /* micro-second */
27 /* -----------------------------------------------------
29 * 0x0000h ~ 0x00FFh System Configuration
31 * ----------------------------------------------------- */
32 #define REG_RSV_CTRL_8188F 0x001C /* 3 Byte */
33 #define REG_BT_WIFI_ANTENNA_SWITCH_8188F 0x0038
34 #define REG_HSISR_8188F 0x005c
35 #define REG_PAD_CTRL1_8188F 0x0064
36 #define REG_AFE_CTRL_4_8188F 0x0078
37 #define REG_HMEBOX_DBG_0_8188F 0x0088
38 #define REG_HMEBOX_DBG_1_8188F 0x008A
39 #define REG_HMEBOX_DBG_2_8188F 0x008C
40 #define REG_HMEBOX_DBG_3_8188F 0x008E
41 #define REG_HIMR0_8188F 0x00B0
42 #define REG_HISR0_8188F 0x00B4
43 #define REG_HIMR1_8188F 0x00B8
44 #define REG_HISR1_8188F 0x00BC
45 #define REG_PMC_DBG_CTRL2_8188F 0x00CC
47 /* -----------------------------------------------------
49 * 0x0100h ~ 0x01FFh MACTOP General Configuration
51 * ----------------------------------------------------- */
52 #define REG_C2HEVT_CMD_ID_8188F 0x01A0
53 #define REG_C2HEVT_CMD_LEN_8188F 0x01AE
54 #define REG_WOWLAN_WAKE_REASON 0x01C7
55 #define REG_WOWLAN_GTK_DBG1 0x630
56 #define REG_WOWLAN_GTK_DBG2 0x634
58 #define REG_HMEBOX_EXT0_8188F 0x01F0
59 #define REG_HMEBOX_EXT1_8188F 0x01F4
60 #define REG_HMEBOX_EXT2_8188F 0x01F8
61 #define REG_HMEBOX_EXT3_8188F 0x01FC
63 /* -----------------------------------------------------
65 * 0x0200h ~ 0x027Fh TXDMA Configuration
67 * ----------------------------------------------------- */
69 /* -----------------------------------------------------
71 * 0x0280h ~ 0x02FFh RXDMA Configuration
73 * ----------------------------------------------------- */
74 #define REG_RXDMA_CONTROL_8188F 0x0286 /* Control the RX DMA. */
75 #define REG_RXDMA_MODE_CTRL_8188F 0x0290
77 /* -----------------------------------------------------
79 * 0x0300h ~ 0x03FFh PCIe
81 * ----------------------------------------------------- */
82 #define REG_PCIE_CTRL_REG_8188F 0x0300
83 #define REG_INT_MIG_8188F 0x0304 /* Interrupt Migration */
84 #define REG_BCNQ_DESA_8188F 0x0308 /* TX Beacon Descriptor Address */
85 #define REG_HQ_DESA_8188F 0x0310 /* TX High Queue Descriptor Address */
86 #define REG_MGQ_DESA_8188F 0x0318 /* TX Manage Queue Descriptor Address */
87 #define REG_VOQ_DESA_8188F 0x0320 /* TX VO Queue Descriptor Address */
88 #define REG_VIQ_DESA_8188F 0x0328 /* TX VI Queue Descriptor Address */
89 #define REG_BEQ_DESA_8188F 0x0330 /* TX BE Queue Descriptor Address */
90 #define REG_BKQ_DESA_8188F 0x0338 /* TX BK Queue Descriptor Address */
91 #define REG_RX_DESA_8188F 0x0340 /* RX Queue Descriptor Address */
92 #define REG_DBI_WDATA_8188F 0x0348 /* DBI Write Data */
93 #define REG_DBI_RDATA_8188F 0x034C /* DBI Read Data */
94 #define REG_DBI_ADDR_8188F 0x0350 /* DBI Address */
95 #define REG_DBI_FLAG_8188F 0x0352 /* DBI Read/Write Flag */
96 #define REG_MDIO_WDATA_8188F 0x0354 /* MDIO for Write PCIE PHY */
97 #define REG_MDIO_RDATA_8188F 0x0356 /* MDIO for Reads PCIE PHY */
98 #define REG_MDIO_CTL_8188F 0x0358 /* MDIO for Control */
99 #define REG_DBG_SEL_8188F 0x0360 /* Debug Selection Register */
100 #define REG_PCIE_HRPWM_8188F 0x0361 /* PCIe RPWM */
101 #define REG_PCIE_HCPWM_8188F 0x0363 /* PCIe CPWM */
102 #define REG_PCIE_MULTIFET_CTRL_8188F 0x036A /* PCIE Multi-Fethc Control */
104 /* -----------------------------------------------------
106 * 0x0400h ~ 0x047Fh Protocol Configuration
108 * ----------------------------------------------------- */
109 #define REG_TXPKTBUF_BCNQ_BDNY_8188F 0x0424
110 #define REG_TXPKTBUF_MGQ_BDNY_8188F 0x0425
111 #define REG_TXPKTBUF_WMAC_LBK_BF_HD_8188F 0x045D
113 #define REG_TXPKTBUF_IV_LOW 0x0484
114 #define REG_TXPKTBUF_IV_HIGH 0x0488
116 #define REG_AMPDU_BURST_MODE_8188F 0x04BC
118 /* -----------------------------------------------------
120 * 0x0500h ~ 0x05FFh EDCA Configuration
122 * ----------------------------------------------------- */
123 #define REG_SECONDARY_CCA_CTRL_8188F 0x0577
125 /* -----------------------------------------------------
127 * 0x0600h ~ 0x07FFh WMAC Configuration
129 * ----------------------------------------------------- */
132 /* ************************************************************
133 * SDIO Bus Specification
134 * ************************************************************ */
136 /* -----------------------------------------------------
137 * SDIO CMD Address Mapping
138 * ----------------------------------------------------- */
140 /* -----------------------------------------------------
141 * I/O bus domain (Host)
142 * ----------------------------------------------------- */
144 /* -----------------------------------------------------
146 * ----------------------------------------------------- */
147 #define SDIO_REG_HIQ_FREEPG_8188F 0x0020
148 #define SDIO_REG_MID_FREEPG_8188F 0x0022
149 #define SDIO_REG_LOW_FREEPG_8188F 0x0024
150 #define SDIO_REG_PUB_FREEPG_8188F 0x0026
151 #define SDIO_REG_EXQ_FREEPG_8188F 0x0028
152 #define SDIO_REG_AC_OQT_FREEPG_8188F 0x002A
153 #define SDIO_REG_NOAC_OQT_FREEPG_8188F 0x002B
155 #define SDIO_REG_HCPWM1_8188F 0x0038
157 /* indirect access */
158 #define SDIO_REG_INDIRECT_REG_CFG_8188F 0x40
159 #define SET_INDIRECT_REG_ADDR(_cmd, _addr) SET_BITS_TO_LE_2BYTE(((u8 *)(_cmd)) + 0, 0, 16, (_addr))
160 #define SET_INDIRECT_REG_SIZE_1BYTE(_cmd) SET_BITS_TO_LE_1BYTE(((u8 *)(_cmd)) + 2, 0, 2, 0)
161 #define SET_INDIRECT_REG_SIZE_2BYTE(_cmd) SET_BITS_TO_LE_1BYTE(((u8 *)(_cmd)) + 2, 0, 2, 1)
162 #define SET_INDIRECT_REG_SIZE_4BYTE(_cmd) SET_BITS_TO_LE_1BYTE(((u8 *)(_cmd)) + 2, 0, 2, 2)
163 #define SET_INDIRECT_REG_WRITE(_cmd) SET_BITS_TO_LE_1BYTE(((u8 *)(_cmd)) + 2, 2, 1, 1)
164 #define SET_INDIRECT_REG_READ(_cmd) SET_BITS_TO_LE_1BYTE(((u8 *)(_cmd)) + 2, 3, 1, 1)
165 #define GET_INDIRECT_REG_RDY(_cmd) LE_BITS_TO_1BYTE(((u8 *)(_cmd)) + 2, 4, 1)
167 #define SDIO_REG_INDIRECT_REG_DATA_8188F 0x44
169 /* ****************************************************************************
170 * 8188 Regsiter Bit and Content definition
171 * **************************************************************************** */
174 * interrupt mask which needs to clear */
175 #define MASK_HSISR_CLEAR (HSISR_GPIO12_0_INT |\
181 /* -----------------------------------------------------
183 * 0x0100h ~ 0x01FFh MACTOP General Configuration
185 * ----------------------------------------------------- */
188 /* -----------------------------------------------------
190 * 0x0200h ~ 0x027Fh TXDMA Configuration
192 * ----------------------------------------------------- */
194 /* -----------------------------------------------------
196 * 0x0280h ~ 0x02FFh RXDMA Configuration
198 * ----------------------------------------------------- */
199 #define BIT_USB_RXDMA_AGG_EN BIT(31)
200 #define RXDMA_AGG_MODE_EN BIT(1)
203 #define RXPKT_RELEASE_POLL BIT(16)
204 #define RXDMA_IDLE BIT(17)
205 #define RW_RELEASE_EN BIT(18)
208 /* -----------------------------------------------------
210 * 0x0400h ~ 0x047Fh Protocol Configuration
212 * ----------------------------------------------------- */
214 /* ----------------------------------------------------------------------------
215 * 8188F REG_CCK_CHECK (offset 0x454)
216 * ---------------------------------------------------------------------------- */
217 #define BIT_BCN_PORT_SEL BIT5
219 /* -----------------------------------------------------
221 * 0x0500h ~ 0x05FFh EDCA Configuration
223 * ----------------------------------------------------- */
225 /* -----------------------------------------------------
227 * 0x0600h ~ 0x07FFh WMAC Configuration
229 * ----------------------------------------------------- */
231 /* ----------------------------------------------------------------------------
232 * 8195 IMR/ISR bits (offset 0xB0, 8bits)
233 * ---------------------------------------------------------------------------- */
234 #define IMR_DISABLED_8188F 0
235 /* IMR DW0(0x00B0-00B3) Bit 0-31 */
236 #define IMR_TIMER2_8188F BIT31 /* Timeout interrupt 2 */
237 #define IMR_TIMER1_8188F BIT30 /* Timeout interrupt 1 */
238 #define IMR_PSTIMEOUT_8188F BIT29 /* Power Save Time Out Interrupt */
239 #define IMR_GTINT4_8188F BIT28 /* When GTIMER4 expires, this bit is set to 1 */
240 #define IMR_GTINT3_8188F BIT27 /* When GTIMER3 expires, this bit is set to 1 */
241 #define IMR_TXBCN0ERR_8188F BIT26 /* Transmit Beacon0 Error */
242 #define IMR_TXBCN0OK_8188F BIT25 /* Transmit Beacon0 OK */
243 #define IMR_TSF_BIT32_TOGGLE_8188F BIT24 /* TSF Timer BIT32 toggle indication interrupt */
244 #define IMR_BCNDMAINT0_8188F BIT20 /* Beacon DMA Interrupt 0 */
245 #define IMR_BCNDERR0_8188F BIT16 /* Beacon Queue DMA OK0 */
246 #define IMR_HSISR_IND_ON_INT_8188F BIT15 /* HSISR Indicator (HSIMR & HSISR is true, this bit is set to 1) */
247 #define IMR_BCNDMAINT_E_8188F BIT14 /* Beacon DMA Interrupt Extension for Win7 */
248 #define IMR_ATIMEND_8188F BIT12 /* CTWidnow End or ATIM Window End */
249 #define IMR_C2HCMD_8188F BIT10 /* CPU to Host Command INT Status, Write 1 clear */
250 #define IMR_CPWM2_8188F BIT9 /* CPU power Mode exchange INT Status, Write 1 clear */
251 #define IMR_CPWM_8188F BIT8 /* CPU power Mode exchange INT Status, Write 1 clear */
252 #define IMR_HIGHDOK_8188F BIT7 /* High Queue DMA OK */
253 #define IMR_MGNTDOK_8188F BIT6 /* Management Queue DMA OK */
254 #define IMR_BKDOK_8188F BIT5 /* AC_BK DMA OK */
255 #define IMR_BEDOK_8188F BIT4 /* AC_BE DMA OK */
256 #define IMR_VIDOK_8188F BIT3 /* AC_VI DMA OK */
257 #define IMR_VODOK_8188F BIT2 /* AC_VO DMA OK */
258 #define IMR_RDU_8188F BIT1 /* Rx Descriptor Unavailable */
259 #define IMR_ROK_8188F BIT0 /* Receive DMA OK */
261 /* IMR DW1(0x00B4-00B7) Bit 0-31 */
262 #define IMR_BCNDMAINT7_8188F BIT27 /* Beacon DMA Interrupt 7 */
263 #define IMR_BCNDMAINT6_8188F BIT26 /* Beacon DMA Interrupt 6 */
264 #define IMR_BCNDMAINT5_8188F BIT25 /* Beacon DMA Interrupt 5 */
265 #define IMR_BCNDMAINT4_8188F BIT24 /* Beacon DMA Interrupt 4 */
266 #define IMR_BCNDMAINT3_8188F BIT23 /* Beacon DMA Interrupt 3 */
267 #define IMR_BCNDMAINT2_8188F BIT22 /* Beacon DMA Interrupt 2 */
268 #define IMR_BCNDMAINT1_8188F BIT21 /* Beacon DMA Interrupt 1 */
269 #define IMR_BCNDOK7_8188F BIT20 /* Beacon Queue DMA OK Interrup 7 */
270 #define IMR_BCNDOK6_8188F BIT19 /* Beacon Queue DMA OK Interrup 6 */
271 #define IMR_BCNDOK5_8188F BIT18 /* Beacon Queue DMA OK Interrup 5 */
272 #define IMR_BCNDOK4_8188F BIT17 /* Beacon Queue DMA OK Interrup 4 */
273 #define IMR_BCNDOK3_8188F BIT16 /* Beacon Queue DMA OK Interrup 3 */
274 #define IMR_BCNDOK2_8188F BIT15 /* Beacon Queue DMA OK Interrup 2 */
275 #define IMR_BCNDOK1_8188F BIT14 /* Beacon Queue DMA OK Interrup 1 */
276 #define IMR_ATIMEND_E_8188F BIT13 /* ATIM Window End Extension for Win7 */
277 #define IMR_TXERR_8188F BIT11 /* Tx Error Flag Interrupt Status, write 1 clear. */
278 #define IMR_RXERR_8188F BIT10 /* Rx Error Flag INT Status, Write 1 clear */
279 #define IMR_TXFOVW_8188F BIT9 /* Transmit FIFO Overflow */
280 #define IMR_RXFOVW_8188F BIT8 /* Receive FIFO Overflow */
282 #ifdef CONFIG_PCI_HCI
283 /* #define IMR_RX_MASK (IMR_ROK_8188F|IMR_RDU_8188F|IMR_RXFOVW_8188F) */
284 #define IMR_TX_MASK (IMR_VODOK_8188F | IMR_VIDOK_8188F | IMR_BEDOK_8188F | IMR_BKDOK_8188F | IMR_MGNTDOK_8188F | IMR_HIGHDOK_8188F)
286 #define RT_BCN_INT_MASKS (IMR_BCNDMAINT0_8188F | IMR_TXBCN0OK_8188F | IMR_TXBCN0ERR_8188F | IMR_BCNDERR0_8188F)
288 #define RT_AC_INT_MASKS (IMR_VIDOK_8188F | IMR_VODOK_8188F | IMR_BEDOK_8188F | IMR_BKDOK_8188F)
291 /* ********************************************************
292 * General definitions
293 * ******************************************************** */
295 #define MACID_NUM_8188F 16
296 #define SEC_CAM_ENT_NUM_8188F 16
297 #define HW_PORT_NUM_8188F 2
298 #define NSS_NUM_8188F 1
299 #define BAND_CAP_8188F (BAND_CAP_2G)
300 #define BW_CAP_8188F (BW_CAP_20M | BW_CAP_40M)
301 #define PROTO_CAP_8188F (PROTO_CAP_11B | PROTO_CAP_11G | PROTO_CAP_11N)
303 #endif /* __RTL8188F_SPEC_H__ */