1 /******************************************************************************
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
18 *******************************************************************************/
19 #ifndef __RTL8188E_SPEC_H__
20 #define __RTL8188E_SPEC_H__
23 /* ************************************************************
24 * 8188E Regsiter offset definition
25 * ************************************************************ */
28 /* ************************************************************
30 * ************************************************************ */
32 /* -----------------------------------------------------
34 * 0x0000h ~ 0x00FFh System Configuration
36 * ----------------------------------------------------- */
37 #define REG_BB_PAD_CTRL 0x0064
38 #define REG_HMEBOX_E0 0x0088
39 #define REG_HMEBOX_E1 0x008A
40 #define REG_HMEBOX_E2 0x008C
41 #define REG_HMEBOX_E3 0x008E
42 #define REG_HMEBOX_EXT_0 0x01F0
43 #define REG_HMEBOX_EXT_1 0x01F4
44 #define REG_HMEBOX_EXT_2 0x01F8
45 #define REG_HMEBOX_EXT_3 0x01FC
46 #define REG_HIMR_88E 0x00B0 /* RTL8188E */
47 #define REG_HISR_88E 0x00B4 /* RTL8188E */
48 #define REG_HIMRE_88E 0x00B8 /* RTL8188E */
49 #define REG_HISRE_88E 0x00BC /* RTL8188E */
50 #define REG_MACID_NO_LINK_0 0x0484
51 #define REG_MACID_NO_LINK_1 0x0488
52 #define REG_MACID_PAUSE_0 0x048c
53 #define REG_MACID_PAUSE_1 0x0490
55 /* -----------------------------------------------------
57 * 0x0100h ~ 0x01FFh MACTOP General Configuration
59 * ----------------------------------------------------- */
60 #define REG_PKTBUF_DBG_ADDR (REG_PKTBUF_DBG_CTRL)
61 #define REG_RXPKTBUF_DBG (REG_PKTBUF_DBG_CTRL+2)
62 #define REG_TXPKTBUF_DBG (REG_PKTBUF_DBG_CTRL+3)
63 #define REG_WOWLAN_WAKE_REASON REG_MCUTST_WOWLAN
65 /* -----------------------------------------------------
67 * 0x0200h ~ 0x027Fh TXDMA Configuration
69 * ----------------------------------------------------- */
71 /* -----------------------------------------------------
73 * 0x0280h ~ 0x02FFh RXDMA Configuration
75 * ----------------------------------------------------- */
77 /* -----------------------------------------------------
79 * 0x0300h ~ 0x03FFh PCIe
81 * ----------------------------------------------------- */
83 /* -----------------------------------------------------
85 * 0x0400h ~ 0x047Fh Protocol Configuration
87 * ----------------------------------------------------- */
89 #define REG_TXPKTBUF_IV_LOW 0x01a4
90 #define REG_TXPKTBUF_IV_HIGH 0x01a8
93 /* -----------------------------------------------------
95 * 0x0500h ~ 0x05FFh EDCA Configuration
97 * ----------------------------------------------------- */
99 /* -----------------------------------------------------
101 * 0x0600h ~ 0x07FFh WMAC Configuration
103 * ----------------------------------------------------- */
104 #ifdef CONFIG_RF_POWER_TRIM
105 #define EEPROM_RF_GAIN_OFFSET 0xC1
106 #define EEPROM_RF_GAIN_VAL 0xF6
107 #define EEPROM_THERMAL_OFFSET 0xF5
108 #endif /*CONFIG_RF_POWER_TRIM*/
109 /* ----------------------------------------------------------------------------
110 * 88E Driver Initialization Offload REG_FDHM0(Offset 0x88, 8 bits)
111 * ----------------------------------------------------------------------------
112 * IOL config for REG_FDHM0(Reg0x88) */
113 #define CMD_INIT_LLT BIT0
114 #define CMD_READ_EFUSE_MAP BIT1
115 #define CMD_EFUSE_PATCH BIT2
116 #define CMD_IOCONFIG BIT3
117 #define CMD_INIT_LLT_ERR BIT4
118 #define CMD_READ_EFUSE_MAP_ERR BIT5
119 #define CMD_EFUSE_PATCH_ERR BIT6
120 #define CMD_IOCONFIG_ERR BIT7
122 /* -----------------------------------------------------
124 * Redifine register definition for compatibility
126 * ----------------------------------------------------- */
128 /* TODO: use these definition when using REG_xxx naming rule.
129 * NOTE: DO NOT Remove these definition. Use later. */
130 #define ISR_88E REG_HISR_88E
132 #ifdef CONFIG_PCI_HCI
133 /* #define IMR_RX_MASK (IMR_ROK_88E|IMR_RDU_88E|IMR_RXFOVW_88E) */
134 #define IMR_TX_MASK (IMR_VODOK_88E | IMR_VIDOK_88E | IMR_BEDOK_88E | IMR_BKDOK_88E | IMR_MGNTDOK_88E | IMR_HIGHDOK_88E | IMR_BCNDERR0_88E)
136 #ifdef CONFIG_CONCURRENT_MODE
137 #define RT_BCN_INT_MASKS (IMR_BCNDMAINT0_88E | IMR_TBDOK_88E | IMR_TBDER_88E | IMR_BCNDMAINT_E_88E)
139 #define RT_BCN_INT_MASKS (IMR_BCNDMAINT0_88E | IMR_TBDOK_88E | IMR_TBDER_88E)
142 #define RT_AC_INT_MASKS (IMR_VIDOK_88E | IMR_VODOK_88E | IMR_BEDOK_88E | IMR_BKDOK_88E)
146 /* ********************************************************
147 * General definitions
148 * ******************************************************** */
150 #define MACID_NUM_88E 64
151 #define SEC_CAM_ENT_NUM_88E 32
152 #define HW_PORT_NUM_88E 2
153 #define NSS_NUM_88E 1
154 #define BAND_CAP_88E (BAND_CAP_2G)
155 #define BW_CAP_88E (BW_CAP_20M | BW_CAP_40M)
156 #define PROTO_CAP_88E (PROTO_CAP_11B | PROTO_CAP_11G | PROTO_CAP_11N)
158 /* ----------------------------------------------------------------------------
159 * 8192C EEPROM/EFUSE share register definition.
160 * ---------------------------------------------------------------------------- */
162 #define EFUSE_ACCESS_ON 0x69 /* For RTL8723 only. */
163 #define EFUSE_ACCESS_OFF 0x00 /* For RTL8723 only. */
165 #endif /* __RTL8188E_SPEC_H__ */