drivers/net/wireless/rockchip_wlan/rtl8822be/include/drv_types_pci.h

   1 /******************************************************************************
   2  *
   3  * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of version 2 of the GNU General Public License as
   7  * published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17  *
  18  *
  19  ******************************************************************************/
  20 #ifndef __DRV_TYPES_PCI_H__
  21 #define __DRV_TYPES_PCI_H__
  22
  23
  24 #ifdef PLATFORM_LINUX
  25         #include <linux/pci.h>
  26 #endif
  27
  28
  29 #define INTEL_VENDOR_ID                         0x8086
  30 #define SIS_VENDOR_ID                                   0x1039
  31 #define ATI_VENDOR_ID                                   0x1002
  32 #define AMD_VENDOR_ID                                   0x1022
  33 #define NVI_VENDOR_ID                                   0x10de
  34
  35 #define ATI_DEVICE_ID                                   0x7914
  36
  37 #define PCI_MAX_BRIDGE_NUMBER                   255
  38 #define PCI_MAX_DEVICES                         32
  39 #define PCI_MAX_FUNCTION                                8
  40
  41 #define PCI_CONF_ADDRESS                                0x0CF8   /* PCI Configuration Space Address */
  42 #define PCI_CONF_DATA                                   0x0CFC   /* PCI Configuration Space Data */
  43
  44 #define PCI_CLASS_BRIDGE_DEV                    0x06
  45 #define PCI_SUBCLASS_BR_PCI_TO_PCI      0x04
  46
  47 #define PCI_CAPABILITY_ID_PCI_EXPRESS   0x10
  48
  49 #define U1DONTCARE                                      0xFF
  50 #define U2DONTCARE                                      0xFFFF
  51 #define U4DONTCARE                                      0xFFFFFFFF
  52
  53 #define PCI_VENDER_ID_REALTEK           0x10ec
  54
  55 #define HAL_HW_PCI_8180_DEVICE_ID       0x8180
  56 #define HAL_HW_PCI_8185_DEVICE_ID               0x8185  /* 8185 or 8185b */
  57 #define HAL_HW_PCI_8188_DEVICE_ID               0x8188  /* 8185b                 */
  58 #define HAL_HW_PCI_8198_DEVICE_ID               0x8198  /* 8185b                 */
  59 #define HAL_HW_PCI_8190_DEVICE_ID               0x8190  /* 8190 */
  60 #define HAL_HW_PCI_8723E_DEVICE_ID              0x8723  /* 8723E */
  61 #define HAL_HW_PCI_8192_DEVICE_ID               0x8192  /* 8192 PCI-E */
  62 #define HAL_HW_PCI_8192SE_DEVICE_ID             0x8192  /* 8192 SE */
  63 #define HAL_HW_PCI_8174_DEVICE_ID               0x8174  /* 8192 SE */
  64 #define HAL_HW_PCI_8173_DEVICE_ID               0x8173  /* 8191 SE Crab */
  65 #define HAL_HW_PCI_8172_DEVICE_ID               0x8172  /* 8191 SE RE */
  66 #define HAL_HW_PCI_8171_DEVICE_ID               0x8171  /* 8191 SE Unicron */
  67 #define HAL_HW_PCI_0045_DEVICE_ID                       0x0045  /* 8190 PCI for Ceraga */
  68 #define HAL_HW_PCI_0046_DEVICE_ID                       0x0046  /* 8190 Cardbus for Ceraga */
  69 #define HAL_HW_PCI_0044_DEVICE_ID                       0x0044  /* 8192e PCIE for Ceraga */
  70 #define HAL_HW_PCI_0047_DEVICE_ID                       0x0047  /* 8192e Express Card for Ceraga */
  71 #define HAL_HW_PCI_700F_DEVICE_ID                       0x700F
  72 #define HAL_HW_PCI_701F_DEVICE_ID                       0x701F
  73 #define HAL_HW_PCI_DLINK_DEVICE_ID              0x3304
  74 #define HAL_HW_PCI_8188EE_DEVICE_ID             0x8179
  75
  76 #define HAL_MEMORY_MAPPED_IO_RANGE_8190PCI              0x1000     /* 8190 support 16 pages of IO registers */
  77 #define HAL_HW_PCI_REVISION_ID_8190PCI                  0x00
  78 #define HAL_MEMORY_MAPPED_IO_RANGE_8192PCIE     0x4000  /* 8192 support 16 pages of IO registers */
  79 #define HAL_HW_PCI_REVISION_ID_8192PCIE                 0x01
  80 #define HAL_MEMORY_MAPPED_IO_RANGE_8192SE               0x4000  /* 8192 support 16 pages of IO registers */
  81 #define HAL_HW_PCI_REVISION_ID_8192SE                   0x10
  82 #define HAL_HW_PCI_REVISION_ID_8192CE                   0x1
  83 #define HAL_MEMORY_MAPPED_IO_RANGE_8192CE               0x4000  /* 8192 support 16 pages of IO registers */
  84 #define HAL_HW_PCI_REVISION_ID_8192DE                   0x0
  85 #define HAL_MEMORY_MAPPED_IO_RANGE_8192DE               0x4000  /* 8192 support 16 pages of IO registers */
  86
  87 enum pci_bridge_vendor {
  88         PCI_BRIDGE_VENDOR_INTEL = 0x0,/* 0b'0000,0001 */
  89         PCI_BRIDGE_VENDOR_ATI, /* = 0x02, */ /* 0b'0000,0010 */
  90         PCI_BRIDGE_VENDOR_AMD, /* = 0x04, */ /* 0b'0000,0100 */
  91         PCI_BRIDGE_VENDOR_SIS ,/* = 0x08, */ /* 0b'0000,1000 */
  92         PCI_BRIDGE_VENDOR_NVI ,/* = 0x10, */ /* 0b'0001,0000 */
  93         PCI_BRIDGE_VENDOR_UNKNOWN, /* = 0x40, */ /* 0b'0100,0000 */
  94         PCI_BRIDGE_VENDOR_MAX ,/* = 0x80 */
  95 } ;
  96
  97 /* copy this data structor defination from MSDN SDK */
  98 typedef struct _PCI_COMMON_CONFIG {
  99         u16     VendorID;
 100         u16     DeviceID;
 101         u16     Command;
 102         u16     Status;
 103         u8      RevisionID;
 104         u8      ProgIf;
 105         u8      SubClass;
 106         u8      BaseClass;
 107         u8      CacheLineSize;
 108         u8      LatencyTimer;
 109         u8      HeaderType;
 110         u8      BIST;
 111
 112         union {
 113                 struct _PCI_HEADER_TYPE_0 {
 114                         u32     BaseAddresses[6];
 115                         u32     CIS;
 116                         u16     SubVendorID;
 117                         u16     SubSystemID;
 118                         u32     ROMBaseAddress;
 119                         u8      CapabilitiesPtr;
 120                         u8      Reserved1[3];
 121                         u32     Reserved2;
 122
 123                         u8      InterruptLine;
 124                         u8      InterruptPin;
 125                         u8      MinimumGrant;
 126                         u8      MaximumLatency;
 127                 } type0;
 128 #if 0
 129                 struct _PCI_HEADER_TYPE_1 {
 130                         ULONG BaseAddresses[PCI_TYPE1_ADDRESSES];
 131                         UCHAR PrimaryBusNumber;
 132                         UCHAR SecondaryBusNumber;
 133                         UCHAR SubordinateBusNumber;
 134                         UCHAR SecondaryLatencyTimer;
 135                         UCHAR IOBase;
 136                         UCHAR IOLimit;
 137                         USHORT SecondaryStatus;
 138                         USHORT MemoryBase;
 139                         USHORT MemoryLimit;
 140                         USHORT PrefetchableMemoryBase;
 141                         USHORT PrefetchableMemoryLimit;
 142                         ULONG PrefetchableMemoryBaseUpper32;
 143                         ULONG PrefetchableMemoryLimitUpper32;
 144                         USHORT IOBaseUpper;
 145                         USHORT IOLimitUpper;
 146                         ULONG Reserved2;
 147                         ULONG ExpansionROMBase;
 148                         UCHAR InterruptLine;
 149                         UCHAR InterruptPin;
 150                         USHORT BridgeControl;
 151                 } type1;
 152
 153                 struct _PCI_HEADER_TYPE_2 {
 154                         ULONG BaseAddress;
 155                         UCHAR CapabilitiesPtr;
 156                         UCHAR Reserved2;
 157                         USHORT SecondaryStatus;
 158                         UCHAR PrimaryBusNumber;
 159                         UCHAR CardbusBusNumber;
 160                         UCHAR SubordinateBusNumber;
 161                         UCHAR CardbusLatencyTimer;
 162                         ULONG MemoryBase0;
 163                         ULONG MemoryLimit0;
 164                         ULONG MemoryBase1;
 165                         ULONG MemoryLimit1;
 166                         USHORT IOBase0_LO;
 167                         USHORT IOBase0_HI;
 168                         USHORT IOLimit0_LO;
 169                         USHORT IOLimit0_HI;
 170                         USHORT IOBase1_LO;
 171                         USHORT IOBase1_HI;
 172                         USHORT IOLimit1_LO;
 173                         USHORT IOLimit1_HI;
 174                         UCHAR InterruptLine;
 175                         UCHAR InterruptPin;
 176                         USHORT BridgeControl;
 177                         USHORT SubVendorID;
 178                         USHORT SubSystemID;
 179                         ULONG LegacyBaseAddress;
 180                         UCHAR Reserved3[56];
 181                         ULONG SystemControl;
 182                         UCHAR MultiMediaControl;
 183                         UCHAR GeneralStatus;
 184                         UCHAR Reserved4[2];
 185                         UCHAR GPIO0Control;
 186                         UCHAR GPIO1Control;
 187                         UCHAR GPIO2Control;
 188                         UCHAR GPIO3Control;
 189                         ULONG IRQMuxRouting;
 190                         UCHAR RetryStatus;
 191                         UCHAR CardControl;
 192                         UCHAR DeviceControl;
 193                         UCHAR Diagnostic;
 194                 } type2;
 195 #endif
 196         } u;
 197
 198         u8      DeviceSpecific[108];
 199 } PCI_COMMON_CONFIG , *PPCI_COMMON_CONFIG;
 200
 201 typedef struct _RT_PCI_CAPABILITIES_HEADER {
 202         u8   CapabilityID;
 203         u8   Next;
 204 } RT_PCI_CAPABILITIES_HEADER, *PRT_PCI_CAPABILITIES_HEADER;
 205
 206 struct pci_priv {
 207         BOOLEAN         pci_clk_req;
 208
 209         u8      pciehdr_offset;
 210         /* PCIeCap is only differece between B-cut and C-cut. */
 211         /* Configuration Space offset 72[7:4] */
 212         /* 0: A/B cut */
 213         /* 1: C cut and later. */
 214         u8      pcie_cap;
 215         u8      linkctrl_reg;
 216
 217         u8      busnumber;
 218         u8      devnumber;
 219         u8      funcnumber;
 220
 221         u8      pcibridge_busnum;
 222         u8      pcibridge_devnum;
 223         u8      pcibridge_funcnum;
 224         u8      pcibridge_vendor;
 225         u16     pcibridge_vendorid;
 226         u16     pcibridge_deviceid;
 227         u8      pcibridge_pciehdr_offset;
 228         u8      pcibridge_linkctrlreg;
 229
 230         u8      amd_l1_patch;
 231 };
 232
 233 typedef struct _RT_ISR_CONTENT {
 234         union {
 235                 u32                     IntArray[2];
 236                 u32                     IntReg4Byte;
 237                 u16                     IntReg2Byte;
 238         };
 239 } RT_ISR_CONTENT, *PRT_ISR_CONTENT;
 240
 241 /* #define RegAddr(addr)           (addr + 0xB2000000UL) */
 242 /* some platform macros will def here */
 243 static inline void NdisRawWritePortUlong(u32 port,  u32 val)
 244 {
 245         outl(val, port);
 246         /* writel(val, (u8 *)RegAddr(port));     */
 247 }
 248
 249 static inline void NdisRawWritePortUchar(u32 port,  u8 val)
 250 {
 251         outb(val, port);
 252         /* writeb(val, (u8 *)RegAddr(port)); */
 253 }
 254
 255 static inline void NdisRawReadPortUchar(u32 port, u8 *pval)
 256 {
 257         *pval = inb(port);
 258         /* *pval = readb((u8 *)RegAddr(port)); */
 259 }
 260
 261 static inline void NdisRawReadPortUshort(u32 port, u16 *pval)
 262 {
 263         *pval = inw(port);
 264         /* *pval = readw((u8 *)RegAddr(port)); */
 265 }
 266
 267 static inline void NdisRawReadPortUlong(u32 port, u32 *pval)
 268 {
 269         *pval = inl(port);
 270         /* *pval = readl((u8 *)RegAddr(port)); */
 271 }
 272
 273
 274 #endif