1 /******************************************************************************
3 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of version 2 of the GNU General Public License as
7 * published by the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
19 ******************************************************************************/
20 #ifndef __INC_HAL8814PHYREG_H__
21 #define __INC_HAL8814PHYREG_H__
22 /*--------------------------Define Parameters-------------------------------*/
24 * BB-PHY register PMAC 0x100 PHY 0x800 - 0xEFF
25 * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
26 * 2. 0x800/0x900/0xA00/0xC00/0xD00/0xE00
27 * 3. RF register 0x00-2E
28 * 4. Bit Mask for BB/RF register
29 * 5. Other defintion for BB/RF R/W
33 /* BB Register Definition */
35 #define rCCAonSec_Jaguar 0x838
36 #define rPwed_TH_Jaguar 0x830
37 #define rL1_Weight_Jaguar 0x840
38 #define r_L1_SBD_start_time 0x844
40 /* BW and sideband setting */
41 #define rBWIndication_Jaguar 0x834
42 #define rL1PeakTH_Jaguar 0x848
43 #define rRFMOD_Jaguar 0x8ac /* RF mode */
44 #define rADC_Buf_Clk_Jaguar 0x8c4
45 #define rADC_Buf_40_Clk_Jaguar2 0x8c8
46 #define rRFECTRL_Jaguar 0x900
47 #define bRFMOD_Jaguar 0xc3
48 #define rCCK_System_Jaguar 0xa00 /* for cck sideband */
49 #define bCCK_System_Jaguar 0x10
51 /* Block & Path enable */
52 #define rOFDMCCKEN_Jaguar 0x808 /* OFDM/CCK block enable */
53 #define bOFDMEN_Jaguar 0x20000000
54 #define bCCKEN_Jaguar 0x10000000
55 #define rRxPath_Jaguar 0x808 /* Rx antenna */
56 #define bRxPath_Jaguar 0xff
57 #define rTxPath_Jaguar 0x80c /* Tx antenna */
58 #define bTxPath_Jaguar 0x0fffffff
59 #define rCCK_RX_Jaguar 0xa04 /* for cck rx path selection */
60 #define bCCK_RX_Jaguar 0x0c000000
61 #define rVhtlen_Use_Lsig_Jaguar 0x8c3 /* Use LSIG for VHT length */
63 #define rRxPath_Jaguar2 0xa04 /* Rx antenna */
64 #define rTxAnt_1Nsts_Jaguar2 0x93c /* Tx antenna for 1Nsts */
65 #define rTxAnt_23Nsts_Jaguar2 0x940 /* Tx antenna for 2Nsts and 3Nsts */
68 /* RF read/write-related */
69 #define rHSSIRead_Jaguar 0x8b0 /* RF read addr */
70 #define bHSSIRead_addr_Jaguar 0xff
71 #define bHSSIRead_trigger_Jaguar 0x100
72 #define rA_PIRead_Jaguar 0xd04 /* RF readback with PI */
73 #define rB_PIRead_Jaguar 0xd44 /* RF readback with PI */
74 #define rA_SIRead_Jaguar 0xd08 /* RF readback with SI */
75 #define rB_SIRead_Jaguar 0xd48 /* RF readback with SI */
76 #define rRead_data_Jaguar 0xfffff
77 #define rA_LSSIWrite_Jaguar 0xc90 /* RF write addr */
78 #define rB_LSSIWrite_Jaguar 0xe90 /* RF write addr */
79 #define bLSSIWrite_data_Jaguar 0x000fffff
80 #define bLSSIWrite_addr_Jaguar 0x0ff00000
82 #define rC_PIRead_Jaguar2 0xd84 /* RF readback with PI */
83 #define rD_PIRead_Jaguar2 0xdC4 /* RF readback with PI */
84 #define rC_SIRead_Jaguar2 0xd88 /* RF readback with SI */
85 #define rD_SIRead_Jaguar2 0xdC8 /* RF readback with SI */
86 #define rC_LSSIWrite_Jaguar2 0x1890 /* RF write addr */
87 #define rD_LSSIWrite_Jaguar2 0x1A90 /* RF write addr */
90 /* YN: mask the following register definition temporarily */
91 #define rFPGA0_XA_RFInterfaceOE 0x860 /* RF Channel switch */
92 #define rFPGA0_XB_RFInterfaceOE 0x864
94 #define rFPGA0_XAB_RFInterfaceSW 0x870 /* RF Interface Software Control */
95 #define rFPGA0_XCD_RFInterfaceSW 0x874
97 /* #define rFPGA0_XAB_RFParameter 0x878 */ /* RF Parameter
98 * #define rFPGA0_XCD_RFParameter 0x87c */
100 /* #define rFPGA0_AnalogParameter1 0x880 */ /* Crystal cap setting RF-R/W protection for parameter4??
101 * #define rFPGA0_AnalogParameter2 0x884
102 * #define rFPGA0_AnalogParameter3 0x888
103 * #define rFPGA0_AdDaClockEn 0x888 */ /* enable ad/da clock1 for dual-phy
104 * #define rFPGA0_AnalogParameter4 0x88c */
108 #define rCCK_TxFilter1_Jaguar 0xa20
109 #define bCCK_TxFilter1_C0_Jaguar 0x00ff0000
110 #define bCCK_TxFilter1_C1_Jaguar 0xff000000
111 #define rCCK_TxFilter2_Jaguar 0xa24
112 #define bCCK_TxFilter2_C2_Jaguar 0x000000ff
113 #define bCCK_TxFilter2_C3_Jaguar 0x0000ff00
114 #define bCCK_TxFilter2_C4_Jaguar 0x00ff0000
115 #define bCCK_TxFilter2_C5_Jaguar 0xff000000
116 #define rCCK_TxFilter3_Jaguar 0xa28
117 #define bCCK_TxFilter3_C6_Jaguar 0x000000ff
118 #define bCCK_TxFilter3_C7_Jaguar 0x0000ff00
119 /* NBI & CSI Mask setting */
120 #define rCSI_Mask_Setting1_Jaguar 0x874
121 #define rCSI_Fix_Mask0_Jaguar 0x880
122 #define rCSI_Fix_Mask1_Jaguar 0x884
123 #define rCSI_Fix_Mask2_Jaguar 0x888
124 #define rCSI_Fix_Mask3_Jaguar 0x88c
125 #define rCSI_Fix_Mask4_Jaguar 0x890
126 #define rCSI_Fix_Mask5_Jaguar 0x894
127 #define rCSI_Fix_Mask6_Jaguar 0x898
128 #define rCSI_Fix_Mask7_Jaguar 0x89c
129 #define rNBI_Setting_Jaguar 0x87c
132 /* YN: mask the following register definition temporarily
133 * #define rPdp_AntA 0xb00
134 * #define rPdp_AntA_4 0xb04
135 * #define rConfig_Pmpd_AntA 0xb28
136 * #define rConfig_AntA 0xb68
137 * #define rConfig_AntB 0xb6c
138 * #define rPdp_AntB 0xb70
139 * #define rPdp_AntB_4 0xb74
140 * #define rConfig_Pmpd_AntB 0xb98
141 * #define rAPK 0xbd8 */
144 #define rA_RxIQC_AB_Jaguar 0xc10 /* RxIQ imblance matrix coeff. A & B */
145 #define rA_RxIQC_CD_Jaguar 0xc14 /* RxIQ imblance matrix coeff. C & D */
146 #define rA_TxScale_Jaguar 0xc1c /* Pah_A TX scaling factor */
147 #define rB_TxScale_Jaguar 0xe1c /* Path_B TX scaling factor */
148 #define rB_RxIQC_AB_Jaguar 0xe10 /* RxIQ imblance matrix coeff. A & B */
149 #define rB_RxIQC_CD_Jaguar 0xe14 /* RxIQ imblance matrix coeff. C & D */
150 #define b_RxIQC_AC_Jaguar 0x02ff /* bit mask for IQC matrix element A & C */
151 #define b_RxIQC_BD_Jaguar 0x02ff0000 /* bit mask for IQC matrix element A & C */
153 #define rC_TxScale_Jaguar2 0x181c /* Pah_C TX scaling factor */
154 #define rD_TxScale_Jaguar2 0x1A1c /* Path_D TX scaling factor */
155 #define rRF_TxGainOffset 0x55
158 #define rA_IGI_Jaguar 0xc50 /* Initial Gain for path-A */
159 #define rB_IGI_Jaguar 0xe50 /* Initial Gain for path-B */
160 #define rC_IGI_Jaguar2 0x1850 /* Initial Gain for path-C */
161 #define rD_IGI_Jaguar2 0x1A50 /* Initial Gain for path-D */
163 #define rOFDM_FalseAlarm1_Jaguar 0xf48 /* counter for break */
164 #define rOFDM_FalseAlarm2_Jaguar 0xf4c /* counter for spoofing */
165 #define rCCK_FalseAlarm_Jaguar 0xa5c /* counter for cck false alarm */
166 #define b_FalseAlarm_Jaguar 0xffff
167 #define rCCK_CCA_Jaguar 0xa08 /* cca threshold */
168 #define bCCK_CCA_Jaguar 0x00ff0000
170 /* Tx Power Ttraining-related */
171 #define rA_TxPwrTraing_Jaguar 0xc54
172 #define rB_TxPwrTraing_Jaguar 0xe54
175 #define rOFDM_ShortCFOAB_Jaguar 0xf60
176 #define rOFDM_LongCFOAB_Jaguar 0xf64
177 #define rOFDM_EndCFOAB_Jaguar 0xf70
178 #define rOFDM_AGCReport_Jaguar 0xf84
179 #define rOFDM_RxSNR_Jaguar 0xf88
180 #define rOFDM_RxEVMCSI_Jaguar 0xf8c
181 #define rOFDM_SIGReport_Jaguar 0xf90
184 #define rEDCCA_Jaguar 0x8a4 /* EDCCA */
185 #define bEDCCA_Jaguar 0xffff
186 #define rAGC_table_Jaguar 0x82c /* AGC tabel select */
187 #define bAGC_table_Jaguar 0x3
188 #define b_sel5g_Jaguar 0x1000 /* sel5g */
189 #define b_LNA_sw_Jaguar 0x8000 /* HW/WS control for LNA */
190 #define rFc_area_Jaguar 0x860 /* fc_area */
191 #define bFc_area_Jaguar 0x1ffe000
192 #define rSingleTone_ContTx_Jaguar 0x914
194 #define rAGC_table_Jaguar2 0x958 /* AGC tabel select */
195 #define rDMA_trigger_Jaguar2 0x95C /* ADC sample mode */
199 #define rA_RFE_Pinmux_Jaguar 0xcb0 /* Path_A RFE cotrol pinmux */
200 #define rB_RFE_Pinmux_Jaguar 0xeb0 /* Path_B RFE control pinmux */
201 #define rA_RFE_Inv_Jaguar 0xcb4 /* Path_A RFE cotrol */
202 #define rB_RFE_Inv_Jaguar 0xeb4 /* Path_B RFE control */
203 #define rA_RFE_Jaguar 0xcb8 /* Path_A RFE cotrol */
204 #define rB_RFE_Jaguar 0xeb8 /* Path_B RFE control */
205 #define r_ANTSEL_SW_Jaguar 0x900 /* ANTSEL SW Control */
206 #define bMask_RFEInv_Jaguar 0x3ff00000
207 #define bMask_AntselPathFollow_Jaguar 0x00030000
209 #define rC_RFE_Pinmux_Jaguar 0x18B4 /* Path_C RFE cotrol pinmux */
210 #define rD_RFE_Pinmux_Jaguar 0x1AB4 /* Path_D RFE cotrol pinmux */
211 #define rA_RFE_Sel_Jaguar2 0x1990
216 #define rTxAGC_A_CCK11_CCK1_JAguar 0xc20
217 #define rTxAGC_A_Ofdm18_Ofdm6_JAguar 0xc24
218 #define rTxAGC_A_Ofdm54_Ofdm24_JAguar 0xc28
219 #define rTxAGC_A_MCS3_MCS0_JAguar 0xc2c
220 #define rTxAGC_A_MCS7_MCS4_JAguar 0xc30
221 #define rTxAGC_A_MCS11_MCS8_JAguar 0xc34
222 #define rTxAGC_A_MCS15_MCS12_JAguar 0xc38
223 #define rTxAGC_A_Nss1Index3_Nss1Index0_JAguar 0xc3c
224 #define rTxAGC_A_Nss1Index7_Nss1Index4_JAguar 0xc40
225 #define rTxAGC_A_Nss2Index1_Nss1Index8_JAguar 0xc44
226 #define rTxAGC_A_Nss2Index5_Nss2Index2_JAguar 0xc48
227 #define rTxAGC_A_Nss2Index9_Nss2Index6_JAguar 0xc4c
228 #define rTxAGC_B_CCK11_CCK1_JAguar 0xe20
229 #define rTxAGC_B_Ofdm18_Ofdm6_JAguar 0xe24
230 #define rTxAGC_B_Ofdm54_Ofdm24_JAguar 0xe28
231 #define rTxAGC_B_MCS3_MCS0_JAguar 0xe2c
232 #define rTxAGC_B_MCS7_MCS4_JAguar 0xe30
233 #define rTxAGC_B_MCS11_MCS8_JAguar 0xe34
234 #define rTxAGC_B_MCS15_MCS12_JAguar 0xe38
235 #define rTxAGC_B_Nss1Index3_Nss1Index0_JAguar 0xe3c
236 #define rTxAGC_B_Nss1Index7_Nss1Index4_JAguar 0xe40
237 #define rTxAGC_B_Nss2Index1_Nss1Index8_JAguar 0xe44
238 #define rTxAGC_B_Nss2Index5_Nss2Index2_JAguar 0xe48
239 #define rTxAGC_B_Nss2Index9_Nss2Index6_JAguar 0xe4c
240 #define bTxAGC_byte0_Jaguar 0xff
241 #define bTxAGC_byte1_Jaguar 0xff00
242 #define bTxAGC_byte2_Jaguar 0xff0000
243 #define bTxAGC_byte3_Jaguar 0xff000000
247 #define rTxAGC_A_CCK11_CCK1_Jaguar2 0xc20
248 #define rTxAGC_A_Ofdm18_Ofdm6_Jaguar2 0xc24
249 #define rTxAGC_A_Ofdm54_Ofdm24_Jaguar2 0xc28
250 #define rTxAGC_A_MCS3_MCS0_Jaguar2 0xc2c
251 #define rTxAGC_A_MCS7_MCS4_Jaguar2 0xc30
252 #define rTxAGC_A_MCS11_MCS8_Jaguar2 0xc34
253 #define rTxAGC_A_MCS15_MCS12_Jaguar2 0xc38
254 #define rTxAGC_A_MCS19_MCS16_Jaguar2 0xcd8
255 #define rTxAGC_A_MCS23_MCS20_Jaguar2 0xcdc
256 #define rTxAGC_A_Nss1Index3_Nss1Index0_Jaguar2 0xc3c
257 #define rTxAGC_A_Nss1Index7_Nss1Index4_Jaguar2 0xc40
258 #define rTxAGC_A_Nss2Index1_Nss1Index8_Jaguar2 0xc44
259 #define rTxAGC_A_Nss2Index5_Nss2Index2_Jaguar2 0xc48
260 #define rTxAGC_A_Nss2Index9_Nss2Index6_Jaguar2 0xc4c
261 #define rTxAGC_A_Nss3Index3_Nss3Index0_Jaguar2 0xce0
262 #define rTxAGC_A_Nss3Index7_Nss3Index4_Jaguar2 0xce4
263 #define rTxAGC_A_Nss3Index9_Nss3Index8_Jaguar2 0xce8
264 #define rTxAGC_B_CCK11_CCK1_Jaguar2 0xe20
265 #define rTxAGC_B_Ofdm18_Ofdm6_Jaguar2 0xe24
266 #define rTxAGC_B_Ofdm54_Ofdm24_Jaguar2 0xe28
267 #define rTxAGC_B_MCS3_MCS0_Jaguar2 0xe2c
268 #define rTxAGC_B_MCS7_MCS4_Jaguar2 0xe30
269 #define rTxAGC_B_MCS11_MCS8_Jaguar2 0xe34
270 #define rTxAGC_B_MCS15_MCS12_Jaguar2 0xe38
271 #define rTxAGC_B_MCS19_MCS16_Jaguar2 0xed8
272 #define rTxAGC_B_MCS23_MCS20_Jaguar2 0xedc
273 #define rTxAGC_B_Nss1Index3_Nss1Index0_Jaguar2 0xe3c
274 #define rTxAGC_B_Nss1Index7_Nss1Index4_Jaguar2 0xe40
275 #define rTxAGC_B_Nss2Index1_Nss1Index8_Jaguar2 0xe44
276 #define rTxAGC_B_Nss2Index5_Nss2Index2_Jaguar2 0xe48
277 #define rTxAGC_B_Nss2Index9_Nss2Index6_Jaguar2 0xe4c
278 #define rTxAGC_B_Nss3Index3_Nss3Index0_Jaguar2 0xee0
279 #define rTxAGC_B_Nss3Index7_Nss3Index4_Jaguar2 0xee4
280 #define rTxAGC_B_Nss3Index9_Nss3Index8_Jaguar2 0xee8
281 #define rTxAGC_C_CCK11_CCK1_Jaguar2 0x1820
282 #define rTxAGC_C_Ofdm18_Ofdm6_Jaguar2 0x1824
283 #define rTxAGC_C_Ofdm54_Ofdm24_Jaguar2 0x1828
284 #define rTxAGC_C_MCS3_MCS0_Jaguar2 0x182c
285 #define rTxAGC_C_MCS7_MCS4_Jaguar2 0x1830
286 #define rTxAGC_C_MCS11_MCS8_Jaguar2 0x1834
287 #define rTxAGC_C_MCS15_MCS12_Jaguar2 0x1838
288 #define rTxAGC_C_MCS19_MCS16_Jaguar2 0x18d8
289 #define rTxAGC_C_MCS23_MCS20_Jaguar2 0x18dc
290 #define rTxAGC_C_Nss1Index3_Nss1Index0_Jaguar2 0x183c
291 #define rTxAGC_C_Nss1Index7_Nss1Index4_Jaguar2 0x1840
292 #define rTxAGC_C_Nss2Index1_Nss1Index8_Jaguar2 0x1844
293 #define rTxAGC_C_Nss2Index5_Nss2Index2_Jaguar2 0x1848
294 #define rTxAGC_C_Nss2Index9_Nss2Index6_Jaguar2 0x184c
295 #define rTxAGC_C_Nss3Index3_Nss3Index0_Jaguar2 0x18e0
296 #define rTxAGC_C_Nss3Index7_Nss3Index4_Jaguar2 0x18e4
297 #define rTxAGC_C_Nss3Index9_Nss3Index8_Jaguar2 0x18e8
298 #define rTxAGC_D_CCK11_CCK1_Jaguar2 0x1a20
299 #define rTxAGC_D_Ofdm18_Ofdm6_Jaguar2 0x1a24
300 #define rTxAGC_D_Ofdm54_Ofdm24_Jaguar2 0x1a28
301 #define rTxAGC_D_MCS3_MCS0_Jaguar2 0x1a2c
302 #define rTxAGC_D_MCS7_MCS4_Jaguar2 0x1a30
303 #define rTxAGC_D_MCS11_MCS8_Jaguar2 0x1a34
304 #define rTxAGC_D_MCS15_MCS12_Jaguar2 0x1a38
305 #define rTxAGC_D_MCS19_MCS16_Jaguar2 0x1ad8
306 #define rTxAGC_D_MCS23_MCS20_Jaguar2 0x1adc
307 #define rTxAGC_D_Nss1Index3_Nss1Index0_Jaguar2 0x1a3c
308 #define rTxAGC_D_Nss1Index7_Nss1Index4_Jaguar2 0x1a40
309 #define rTxAGC_D_Nss2Index1_Nss1Index8_Jaguar2 0x1a44
310 #define rTxAGC_D_Nss2Index5_Nss2Index2_Jaguar2 0x1a48
311 #define rTxAGC_D_Nss2Index9_Nss2Index6_Jaguar2 0x1a4c
312 #define rTxAGC_D_Nss3Index3_Nss3Index0_Jaguar2 0x1ae0
313 #define rTxAGC_D_Nss3Index7_Nss3Index4_Jaguar2 0x1ae4
314 #define rTxAGC_D_Nss3Index9_Nss3Index8_Jaguar2 0x1ae8
315 /* IQK YN: temporaily mask this part
316 * #define rFPGA0_IQK 0xe28
317 * #define rTx_IQK_Tone_A 0xe30
318 * #define rRx_IQK_Tone_A 0xe34
319 * #define rTx_IQK_PI_A 0xe38
320 * #define rRx_IQK_PI_A 0xe3c */
322 /* #define rTx_IQK 0xe40 */
323 /* #define rRx_IQK 0xe44 */
324 /* #define rIQK_AGC_Pts 0xe48 */
325 /* #define rIQK_AGC_Rsp 0xe4c */
326 /* #define rTx_IQK_Tone_B 0xe50 */
327 /* #define rRx_IQK_Tone_B 0xe54 */
328 /* #define rTx_IQK_PI_B 0xe58 */
329 /* #define rRx_IQK_PI_B 0xe5c */
330 /* #define rIQK_AGC_Cont 0xe60 */
334 #define rA_AFEPwr1_Jaguar 0xc60 /* dynamic AFE power control */
335 #define rA_AFEPwr2_Jaguar 0xc64 /* dynamic AFE power control */
336 #define rA_Rx_WaitCCA_Tx_CCKRFON_Jaguar 0xc68
337 #define rA_Tx_CCKBBON_OFDMRFON_Jaguar 0xc6c
338 #define rA_Tx_OFDMBBON_Tx2Rx_Jaguar 0xc70
339 #define rA_Tx2Tx_RXCCK_Jaguar 0xc74
340 #define rA_Rx_OFDM_WaitRIFS_Jaguar 0xc78
341 #define rA_Rx2Rx_BT_Jaguar 0xc7c
342 #define rA_sleep_nav_Jaguar 0xc80
343 #define rA_pmpd_Jaguar 0xc84
344 #define rB_AFEPwr1_Jaguar 0xe60 /* dynamic AFE power control */
345 #define rB_AFEPwr2_Jaguar 0xe64 /* dynamic AFE power control */
346 #define rB_Rx_WaitCCA_Tx_CCKRFON_Jaguar 0xe68
347 #define rB_Tx_CCKBBON_OFDMRFON_Jaguar 0xe6c
348 #define rB_Tx_OFDMBBON_Tx2Rx_Jaguar 0xe70
349 #define rB_Tx2Tx_RXCCK_Jaguar 0xe74
350 #define rB_Rx_OFDM_WaitRIFS_Jaguar 0xe78
351 #define rB_Rx2Rx_BT_Jaguar 0xe7c
352 #define rB_sleep_nav_Jaguar 0xe80
353 #define rB_pmpd_Jaguar 0xe84
356 /* YN: mask these registers temporaily
357 * #define rTx_Power_Before_IQK_A 0xe94
358 * #define rTx_Power_After_IQK_A 0xe9c */
360 /* #define rRx_Power_Before_IQK_A 0xea0 */
361 /* #define rRx_Power_Before_IQK_A_2 0xea4 */
362 /* #define rRx_Power_After_IQK_A 0xea8 */
363 /* #define rRx_Power_After_IQK_A_2 0xeac */
365 /* #define rTx_Power_Before_IQK_B 0xeb4 */
366 /* #define rTx_Power_After_IQK_B 0xebc */
368 /* #define rRx_Power_Before_IQK_B 0xec0 */
369 /* #define rRx_Power_Before_IQK_B_2 0xec4 */
370 /* #define rRx_Power_After_IQK_B 0xec8 */
371 /* #define rRx_Power_After_IQK_B_2 0xecc */
375 #define rA_RSSIDump_Jaguar 0xBF0
376 #define rB_RSSIDump_Jaguar 0xBF1
377 #define rS1_RXevmDump_Jaguar 0xBF4
378 #define rS2_RXevmDump_Jaguar 0xBF5
379 #define rA_RXsnrDump_Jaguar 0xBF6
380 #define rB_RXsnrDump_Jaguar 0xBF7
381 #define rA_CfoShortDump_Jaguar 0xBF8
382 #define rB_CfoShortDump_Jaguar 0xBFA
383 #define rA_CfoLongDump_Jaguar 0xBEC
384 #define rB_CfoLongDump_Jaguar 0xBEE
389 #define RF_AC_Jaguar 0x00 /* */
390 #define RF_RF_Top_Jaguar 0x07 /* */
391 #define RF_TXLOK_Jaguar 0x08 /* */
392 #define RF_TXAPK_Jaguar 0x0B
393 #define RF_CHNLBW_Jaguar 0x18 /* RF channel and BW switch */
394 #define RF_RCK1_Jaguar 0x1c /* */
395 #define RF_RCK2_Jaguar 0x1d
396 #define RF_RCK3_Jaguar 0x1e
397 #define RF_ModeTableAddr 0x30
398 #define RF_ModeTableData0 0x31
399 #define RF_ModeTableData1 0x32
400 #define RF_TxLCTank_Jaguar 0x54
401 #define RF_APK_Jaguar 0x63
403 #define RF_WeLut_Jaguar 0xEF
405 #define bRF_CHNLBW_MOD_AG_Jaguar 0x70300
406 #define bRF_CHNLBW_BW 0xc00
410 * RL6052 Register definition
412 #define RF_AC 0x00 /* */
413 #define RF_IPA_A 0x0C /* */
414 #define RF_TXBIAS_A 0x0D
415 #define RF_BS_PA_APSET_G9_G11 0x0E
416 #define RF_MODE1 0x10 /* */
417 #define RF_MODE2 0x11 /* */
418 #define RF_CHNLBW 0x18 /* RF channel and BW switch */
419 #define RF_RCK_OS 0x30 /* RF TX PA control */
420 #define RF_TXPA_G1 0x31 /* RF TX PA control */
421 #define RF_TXPA_G2 0x32 /* RF TX PA control */
422 #define RF_TXPA_G3 0x33 /* RF TX PA control */
424 #define RF_WE_LUT 0xEF
430 #define bBBResetB 0x100 /* Useless now? */
431 #define bGlobalResetB 0x200
432 #define bOFDMTxStart 0x4
433 #define bCCKTxStart 0x8
434 #define bCRC32Debug 0x100
435 #define bPMACLoopback 0x10
436 #define bTxLSIG 0xffffff
437 #define bOFDMTxRate 0xf
438 #define bOFDMTxReserved 0x10
439 #define bOFDMTxLength 0x1ffe0
440 #define bOFDMTxParity 0x20000
441 #define bTxHTSIG1 0xffffff
442 #define bTxHTMCSRate 0x7f
444 #define bTxHTLength 0xffff00
445 #define bTxHTSIG2 0xffffff
446 #define bTxHTSmoothing 0x1
447 #define bTxHTSounding 0x2
448 #define bTxHTReserved 0x4
449 #define bTxHTAggreation 0x8
450 #define bTxHTSTBC 0x30
451 #define bTxHTAdvanceCoding 0x40
452 #define bTxHTShortGI 0x80
453 #define bTxHTNumberHT_LTF 0x300
454 #define bTxHTCRC8 0x3fc00
455 #define bCounterReset 0x10000
456 #define bNumOfOFDMTx 0xffff
457 #define bNumOfCCKTx 0xffff0000
458 #define bTxIdleInterval 0xffff
459 #define bOFDMService 0xffff0000
460 #define bTxMACHeader 0xffffffff
461 #define bTxDataInit 0xff
462 #define bTxHTMode 0x100
463 #define bTxDataType 0x30000
464 #define bTxRandomSeed 0xffffffff
465 #define bCCKTxPreamble 0x1
466 #define bCCKTxSFD 0xffff0000
467 #define bCCKTxSIG 0xff
468 #define bCCKTxService 0xff00
469 #define bCCKLengthExt 0x8000
470 #define bCCKTxLength 0xffff0000
471 #define bCCKTxCRC16 0xffff
472 #define bCCKTxStatus 0x1
473 #define bOFDMTxStatus 0x2
477 * 1. PMAC duplicate register due to connection: RF_Mode, TRxRN, NumOf L-STF
480 #define rPMAC_Reset 0x100
481 #define rPMAC_TxStart 0x104
482 #define rPMAC_TxLegacySIG 0x108
483 #define rPMAC_TxHTSIG1 0x10c
484 #define rPMAC_TxHTSIG2 0x110
485 #define rPMAC_PHYDebug 0x114
486 #define rPMAC_TxPacketNum 0x118
487 #define rPMAC_TxIdle 0x11c
488 #define rPMAC_TxMACHeader0 0x120
489 #define rPMAC_TxMACHeader1 0x124
490 #define rPMAC_TxMACHeader2 0x128
491 #define rPMAC_TxMACHeader3 0x12c
492 #define rPMAC_TxMACHeader4 0x130
493 #define rPMAC_TxMACHeader5 0x134
494 #define rPMAC_TxDataType 0x138
495 #define rPMAC_TxRandomSeed 0x13c
496 #define rPMAC_CCKPLCPPreamble 0x140
497 #define rPMAC_CCKPLCPHeader 0x144
498 #define rPMAC_CCKCRC16 0x148
499 #define rPMAC_OFDMRxCRC32OK 0x170
500 #define rPMAC_OFDMRxCRC32Er 0x174
501 #define rPMAC_OFDMRxParityEr 0x178
502 #define rPMAC_OFDMRxCRC8Er 0x17c
503 #define rPMAC_CCKCRxRC16Er 0x180
504 #define rPMAC_CCKCRxRC32Er 0x184
505 #define rPMAC_CCKCRxRC32OK 0x188
506 #define rPMAC_TxStatus 0x18c
511 #define rFPGA0_RFMOD 0x800 /* RF mode & CCK TxSC */ /* RF BW Setting?? */
513 #define rFPGA0_TxInfo 0x804 /* Status report?? */
514 #define rFPGA0_PSDFunction 0x808
515 #define rFPGA0_TxGainStage 0x80c /* Set TX PWR init gain? */
517 #define rFPGA0_XA_HSSIParameter1 0x820 /* RF 3 wire register */
518 #define rFPGA0_XA_HSSIParameter2 0x824
519 #define rFPGA0_XB_HSSIParameter1 0x828
520 #define rFPGA0_XB_HSSIParameter2 0x82c
522 #define rFPGA0_XA_LSSIParameter 0x840
523 #define rFPGA0_XB_LSSIParameter 0x844
525 #define rFPGA0_XAB_SwitchControl 0x858 /* RF Channel switch */
526 #define rFPGA0_XCD_SwitchControl 0x85c
528 #define rFPGA0_XAB_RFParameter 0x878 /* RF Parameter */
529 #define rFPGA0_XCD_RFParameter 0x87c
531 #define rFPGA0_AnalogParameter1 0x880 /* Crystal cap setting RF-R/W protection for parameter4?? */
532 #define rFPGA0_AnalogParameter2 0x884
533 #define rFPGA0_AnalogParameter3 0x888
534 #define rFPGA0_AdDaClockEn 0x888 /* enable ad/da clock1 for dual-phy */
535 #define rFPGA0_AnalogParameter4 0x88c
537 #define rFPGA0_XA_LSSIReadBack 0x8a0 /* Tranceiver LSSI Readback */
538 #define rFPGA0_XB_LSSIReadBack 0x8a4
539 #define rFPGA0_XC_LSSIReadBack 0x8a8
540 #define rFPGA0_XD_LSSIReadBack 0x8ac
542 #define rFPGA0_XCD_RFPara 0x8b4
543 #define rFPGA0_PSDReport 0x8b4 /* Useless now */
544 #define TransceiverA_HSPI_Readback 0x8b8 /* Transceiver A HSPI Readback */
545 #define TransceiverB_HSPI_Readback 0x8bc /* Transceiver B HSPI Readback */
546 #define rFPGA0_XAB_RFInterfaceRB 0x8e0 /* Useless now */ /* RF Interface Readback Value */
547 #define rFPGA0_XCD_RFInterfaceRB 0x8e4 /* Useless now */
552 #define rFPGA1_RFMOD 0x900 /* RF mode & OFDM TxSC */ /* RF BW Setting?? */
553 #define REG_BB_TX_PATH_SEL_1_8814A 0x93c
554 #define REG_BB_TX_PATH_SEL_2_8814A 0x940
555 #define rFPGA1_TxBlock 0x904 /* Useless now */
556 #define rFPGA1_DebugSelect 0x908 /* Useless now */
557 #define rFPGA1_TxInfo 0x90c /* Useless now */ /* Status report?? */
559 #define REG_BB_TXBF_ANT_SET_BF1_8814A 0x19ac
560 #define REG_BB_TXBF_ANT_SET_BF0_8814A 0x19b4
564 #define rCCK0_System 0xa00
565 #define rCCK0_AFESetting 0xa04 /* Disable init gain now */ /* Select RX path by RSSI */
566 #define rCCK0_DSPParameter2 0xa1c /* SQ threshold */
567 #define rCCK0_TxFilter1 0xa20
568 #define rCCK0_TxFilter2 0xa24
569 #define rCCK0_DebugPort 0xa28 /* debug port and Tx filter3 */
570 #define rCCK0_FalseAlarmReport 0xa2c /* 0xa2d useless now 0xa30-a4f channel report */
575 #define rPdp_AntA 0xb00
576 #define rPdp_AntA_4 0xb04
577 #define rConfig_Pmpd_AntA 0xb28
578 #define rConfig_AntA 0xb68
579 #define rConfig_AntB 0xb6c
580 #define rPdp_AntB 0xb70
581 #define rPdp_AntB_4 0xb74
582 #define rConfig_Pmpd_AntB 0xb98
588 #define rOFDM0_LSTF 0xc00
590 #define rOFDM0_TRxPathEnable 0xc04
591 #define rOFDM0_TRMuxPar 0xc08
592 #define rOFDM0_TRSWIsolation 0xc0c
594 #define rOFDM0_XARxAFE 0xc10 /* RxIQ DC offset, Rx digital filter, DC notch filter */
595 #define rOFDM0_XARxIQImbalance 0xc14 /* RxIQ imblance matrix */
596 #define rOFDM0_XBRxAFE 0xc18
597 #define rOFDM0_XBRxIQImbalance 0xc1c
598 #define rOFDM0_XCRxAFE 0xc20
599 #define rOFDM0_XCRxIQImbalance 0xc24
600 #define rOFDM0_XDRxAFE 0xc28
601 #define rOFDM0_XDRxIQImbalance 0xc2c
603 #define rOFDM0_RxDetector1 0xc30 /* PD, BW & SBD */ /* DM tune init gain */
604 #define rOFDM0_RxDetector2 0xc34 /* SBD & Fame Sync. */
605 #define rOFDM0_RxDetector3 0xc38 /* Frame Sync. */
606 #define rOFDM0_RxDetector4 0xc3c /* PD, SBD, Frame Sync & Short-GI */
608 #define rOFDM0_RxDSP 0xc40 /* Rx Sync Path */
609 #define rOFDM0_CFOandDAGC 0xc44 /* CFO & DAGC */
610 #define rOFDM0_CCADropThreshold 0xc48 /* CCA Drop threshold */
611 #define rOFDM0_ECCAThreshold 0xc4c /* energy CCA */
613 #define rOFDM0_XAAGCCore1 0xc50 /* DIG */
614 #define rOFDM0_XAAGCCore2 0xc54
615 #define rOFDM0_XBAGCCore1 0xc58
616 #define rOFDM0_XBAGCCore2 0xc5c
617 #define rOFDM0_XCAGCCore1 0xc60
618 #define rOFDM0_XCAGCCore2 0xc64
619 #define rOFDM0_XDAGCCore1 0xc68
620 #define rOFDM0_XDAGCCore2 0xc6c
622 #define rOFDM0_AGCParameter1 0xc70
623 #define rOFDM0_AGCParameter2 0xc74
624 #define rOFDM0_AGCRSSITable 0xc78
625 #define rOFDM0_HTSTFAGC 0xc7c
627 #define rOFDM0_XATxIQImbalance 0xc80 /* TX PWR TRACK and DIG */
628 #define rOFDM0_XATxAFE 0xc84
629 #define rOFDM0_XBTxIQImbalance 0xc88
630 #define rOFDM0_XBTxAFE 0xc8c
631 #define rOFDM0_XCTxIQImbalance 0xc90
632 #define rOFDM0_XCTxAFE 0xc94
633 #define rOFDM0_XDTxIQImbalance 0xc98
634 #define rOFDM0_XDTxAFE 0xc9c
636 #define rOFDM0_RxIQExtAnta 0xca0
637 #define rOFDM0_TxCoeff1 0xca4
638 #define rOFDM0_TxCoeff2 0xca8
639 #define rOFDM0_TxCoeff3 0xcac
640 #define rOFDM0_TxCoeff4 0xcb0
641 #define rOFDM0_TxCoeff5 0xcb4
642 #define rOFDM0_TxCoeff6 0xcb8
643 #define rOFDM0_RxHPParameter 0xce0
644 #define rOFDM0_TxPseudoNoiseWgt 0xce4
645 #define rOFDM0_FrameSync 0xcf0
646 #define rOFDM0_DFSReport 0xcf4
651 #define rOFDM1_LSTF 0xd00
652 #define rOFDM1_TRxPathEnable 0xd04
657 #define rTxAGC_A_Rate18_06 0xe00
658 #define rTxAGC_A_Rate54_24 0xe04
659 #define rTxAGC_A_CCK1_Mcs32 0xe08
660 #define rTxAGC_A_Mcs03_Mcs00 0xe10
661 #define rTxAGC_A_Mcs07_Mcs04 0xe14
662 #define rTxAGC_A_Mcs11_Mcs08 0xe18
663 #define rTxAGC_A_Mcs15_Mcs12 0xe1c
665 #define rTxAGC_B_Rate18_06 0x830
666 #define rTxAGC_B_Rate54_24 0x834
667 #define rTxAGC_B_CCK1_55_Mcs32 0x838
668 #define rTxAGC_B_Mcs03_Mcs00 0x83c
669 #define rTxAGC_B_Mcs07_Mcs04 0x848
670 #define rTxAGC_B_Mcs11_Mcs08 0x84c
671 #define rTxAGC_B_Mcs15_Mcs12 0x868
672 #define rTxAGC_B_CCK11_A_CCK2_11 0x86c
674 #define rFPGA0_IQK 0xe28
675 #define rTx_IQK_Tone_A 0xe30
676 #define rRx_IQK_Tone_A 0xe34
677 #define rTx_IQK_PI_A 0xe38
678 #define rRx_IQK_PI_A 0xe3c
680 #define rTx_IQK 0xe40
681 #define rRx_IQK 0xe44
682 #define rIQK_AGC_Pts 0xe48
683 #define rIQK_AGC_Rsp 0xe4c
684 #define rTx_IQK_Tone_B 0xe50
685 #define rRx_IQK_Tone_B 0xe54
686 #define rTx_IQK_PI_B 0xe58
687 #define rRx_IQK_PI_B 0xe5c
688 #define rIQK_AGC_Cont 0xe60
690 #define rBlue_Tooth 0xe6c
691 #define rRx_Wait_CCA 0xe70
692 #define rTx_CCK_RFON 0xe74
693 #define rTx_CCK_BBON 0xe78
694 #define rTx_OFDM_RFON 0xe7c
695 #define rTx_OFDM_BBON 0xe80
696 #define rTx_To_Rx 0xe84
697 #define rTx_To_Tx 0xe88
698 #define rRx_CCK 0xe8c
700 #define rTx_Power_Before_IQK_A 0xe94
701 #define rTx_Power_After_IQK_A 0xe9c
703 #define rRx_Power_Before_IQK_A 0xea0
704 #define rRx_Power_Before_IQK_A_2 0xea4
705 #define rRx_Power_After_IQK_A 0xea8
706 #define rRx_Power_After_IQK_A_2 0xeac
708 #define rTx_Power_Before_IQK_B 0xeb4
709 #define rTx_Power_After_IQK_B 0xebc
711 #define rRx_Power_Before_IQK_B 0xec0
712 #define rRx_Power_Before_IQK_B_2 0xec4
713 #define rRx_Power_After_IQK_B 0xec8
714 #define rRx_Power_After_IQK_B_2 0xecc
716 #define rRx_OFDM 0xed0
717 #define rRx_Wait_RIFS 0xed4
718 #define rRx_TO_Rx 0xed8
719 #define rStandby 0xedc
721 #define rPMPD_ANAEN 0xeec
724 /* 2. Page8(0x800) */
725 #define bRFMOD 0x1 /* Reg 0x800 rFPGA0_RFMOD */
726 #define bJapanMode 0x2
727 #define bCCKTxSC 0x30
728 #define bCCKEn 0x1000000
729 #define bOFDMEn 0x2000000
730 #define bXBTxAGC 0xf00 /* Reg 80c rFPGA0_TxGainStage */
731 #define bXCTxAGC 0xf000
732 #define bXDTxAGC 0xf0000
734 /* 4. PageA(0xA00) */
735 #define bCCKBBMode 0x3 /* Useless */
736 #define bCCKTxPowerSaving 0x80
737 #define bCCKRxPowerSaving 0x40
739 #define bCCKSideBand 0x10 /* Reg 0xa00 rCCK0_System 20/40 switch */
741 #define bCCKScramble 0x8 /* Useless */
742 #define bCCKAntDiversity 0x8000
743 #define bCCKCarrierRecovery 0x4000
744 #define bCCKTxRate 0x3000
745 #define bCCKDCCancel 0x0800
746 #define bCCKISICancel 0x0400
747 #define bCCKMatchFilter 0x0200
748 #define bCCKEqualizer 0x0100
749 #define bCCKPreambleDetect 0x800000
750 #define bCCKFastFalseCCA 0x400000
751 #define bCCKChEstStart 0x300000
752 #define bCCKCCACount 0x080000
753 #define bCCKcs_lim 0x070000
754 #define bCCKBistMode 0x80000000
755 #define bCCKCCAMask 0x40000000
756 #define bCCKTxDACPhase 0x4
757 #define bCCKRxADCPhase 0x20000000 /* r_rx_clk */
758 #define bCCKr_cp_mode0 0x0100
759 #define bCCKTxDCOffset 0xf0
760 #define bCCKRxDCOffset 0xf
761 #define bCCKCCAMode 0xc000
762 #define bCCKFalseCS_lim 0x3f00
763 #define bCCKCS_ratio 0xc00000
764 #define bCCKCorgBit_sel 0x300000
765 #define bCCKPD_lim 0x0f0000
766 #define bCCKNewCCA 0x80000000
767 #define bCCKRxHPofIG 0x8000
768 #define bCCKRxIG 0x7f00
769 #define bCCKLNAPolarity 0x800000
770 #define bCCKRx1stGain 0x7f0000
771 #define bCCKRFExtend 0x20000000 /* CCK Rx Iinital gain polarity */
772 #define bCCKRxAGCSatLevel 0x1f000000
773 #define bCCKRxAGCSatCount 0xe0
774 #define bCCKRxRFSettle 0x1f /* AGCsamp_dly */
775 #define bCCKFixedRxAGC 0x8000
776 /* #define bCCKRxAGCFormat 0x4000 */ /* remove to HSSI register 0x824 */
777 #define bCCKAntennaPolarity 0x2000
778 #define bCCKTxFilterType 0x0c00
779 #define bCCKRxAGCReportType 0x0300
780 #define bCCKRxDAGCEn 0x80000000
781 #define bCCKRxDAGCPeriod 0x20000000
782 #define bCCKRxDAGCSatLevel 0x1f000000
783 #define bCCKTimingRecovery 0x800000
784 #define bCCKTxC0 0x3f0000
785 #define bCCKTxC1 0x3f000000
786 #define bCCKTxC2 0x3f
787 #define bCCKTxC3 0x3f00
788 #define bCCKTxC4 0x3f0000
789 #define bCCKTxC5 0x3f000000
790 #define bCCKTxC6 0x3f
791 #define bCCKTxC7 0x3f00
792 #define bCCKDebugPort 0xff0000
793 #define bCCKDACDebug 0x0f000000
794 #define bCCKFalseAlarmEnable 0x8000
795 #define bCCKFalseAlarmRead 0x4000
796 #define bCCKTRSSI 0x7f
797 #define bCCKRxAGCReport 0xfe
798 #define bCCKRxReport_AntSel 0x80000000
799 #define bCCKRxReport_MFOff 0x40000000
800 #define bCCKRxRxReport_SQLoss 0x20000000
801 #define bCCKRxReport_Pktloss 0x10000000
802 #define bCCKRxReport_Lockedbit 0x08000000
803 #define bCCKRxReport_RateError 0x04000000
804 #define bCCKRxReport_RxRate 0x03000000
805 #define bCCKRxFACounterLower 0xff
806 #define bCCKRxFACounterUpper 0xff000000
807 #define bCCKRxHPAGCStart 0xe000
808 #define bCCKRxHPAGCFinal 0x1c00
809 #define bCCKRxFalseAlarmEnable 0x8000
810 #define bCCKFACounterFreeze 0x4000
811 #define bCCKTxPathSel 0x10000000
812 #define bCCKDefaultRxPath 0xc000000
813 #define bCCKOptionRxPath 0x3000000
815 #define RF_T_METER_88E 0x42
817 /* 6. PageE(0xE00) */
818 #define bSTBCEn 0x4 /* Useless */
819 #define bAntennaMapping 0x10
821 #define bCFOAntSumD 0x200
822 #define bPHYCounterReset 0x8000000
823 #define bCFOReportGet 0x4000000
824 #define bOFDMContinueTx 0x10000000
825 #define bOFDMSingleCarrier 0x20000000
826 #define bOFDMSingleTone 0x40000000
833 #define bEnable 0x1 /* Useless */
836 /* byte endable for srwrite */
837 #define bByte0 0x1 /* Useless */
845 /* for PutRegsetting & GetRegSetting BitMask */
846 #define bMaskByte0 0xff /* Reg 0xc50 rOFDM0_XAAGCCore~0xC6f */
847 #define bMaskByte1 0xff00
848 #define bMaskByte2 0xff0000
849 #define bMaskByte3 0xff000000
850 #define bMaskHWord 0xffff0000
851 #define bMaskLWord 0x0000ffff
852 #define bMaskDWord 0xffffffff
853 #define bMaskH3Bytes 0xffffff00
854 #define bMask12Bits 0xfff
855 #define bMaskH4Bits 0xf0000000
856 #define bMaskOFDM_D 0xffc00000
857 #define bMaskCCK 0x3f3f3f3f
858 #define bMask7bits 0x7f
859 #define bMaskByte2HighNibble 0x00f00000
860 #define bMaskByte3LowNibble 0x0f000000
861 #define bMaskL3Bytes 0x00ffffff
863 /*--------------------------Define Parameters-------------------------------*/